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( h t
(chapters 10
10.4,
4 10
10.5,
5 10
10.6,
6 start
t t off chapter
h t 11 DData
t converter
t
fundamentals)
Tuesday
uesday 23rd
3 d of
o February,
eb ua y, 2010,
0 0, 9:15-12:00
9 5 00
10.1
10 1 Switched Capacitor Circuits
10.2 Basic Operation and Analysis
Today:
10 3 Fi
10.3 First-order
t d filt filters
10.4 Biquad filters (high-Q)
10.5 Chargeg injection
j
10.7 Correlated double sampling techniques
11.1 Ideal D/A converter
11 2 Ideal A/D converter
11.2
11.3 quantization noise
11.4 signed codes
Signal-flow-graph analysis (p. 407)
Vin(s) Vout(s)
-
v 1 nonlinear
element
2 3 4
vn1 = k 1v1 + k2v 1 k 3v1 + k4v 1 +
C
3 1
2 C
2 A 2
+
C2
1 1 +
Vi(z) Vo(z)
1 1 -
C
- 2
C
2 2 A 2
C3
1
C
1
First
Fi order
d fully
f ll differential
diff i l fil
filter alternative
l i to
single-ended version in fig. 10.16
Example:
p Fully
y differential SC-sigma-delta
g ADC p
published May
y 2007
Q 2
5
C
1
C
A
1 1a
C
2
1
Vi(z)
Q
1
Q
4
Vo(z)
2 Q Q 2a
2 3
TTo reduce
d th effects
the ff t off charge
h injection
i j ti in i SC circuits,
i it realize
li
all switches connected to ground or virtual ground as n-
channel switches only,y, and turn off the switches connected to
ground or virtual ground first. Such an approach will minimize
distortion and gain error as well as keeping DC offset low.
In this case 1a and 2a are turned off first to prevent other
switches affecting the output voltage of the circuit.
25. februar 2010 21
Ex. 10.6 (1/2)
C2
2 1 2 1
C1 1
v in
vout
1 2 1 C2
For the amplifier: During 2 the error is sampled and stored across C1
and C2
The stored error is then subtracted during 1
For the integrator: During 1 the error is sampled and stored across C2
The stored error is then subtracted during 2
25. februar 2010 27
25. februar 2010 28
SC-integrator with CDS (J & M page 434)
1
C
2
1 2
C1 1
vin
v out
2
2
2 2
C C
1 2
1 1 1
Nyquist-rate converters:
E
Eachh value
l h has a one-to-one correspondencewith
d i h a single
i l
input
The sample-rate
p must be at least equal
q to twice the signal
g
frequency (Typically somewhat higher)
Oversampled converters:
The sample-rate
sample rate is much higher than the signal frequency
frequency,
typically 20 512 times.
The extra samples are used to increase the SNR
Often combined with noise shaping
Flash ADC from 1926 (Analog Digital
Conversion handbook
handbook, Analog Devices)
11.1 Ideal D/A converter
D/A Vout
B
in
V
ref
1 2 N
Bin = b 12 + b22 + + bN2
1 2 N
Vout = Vref b 12 + b22 + + b N2
Example 11.1 : 8-bit D/A converter
Vref
An ideal D/A converter has VLSB ---------
N
-
2
Vref = 5 V
Find Vout when 1
1 LSB = -----N-
Bin = 10110100 2
1 3 4 6
B in = 2 + 2 + 2 + 2 = 0,703125
V
out
-------------
Vref
Vout = VrefB in = 3,516 V
1 2-bit DAC
3/4
Find
1/2
VLSB VLSB 1
---------------- = --- = 1 LSB
V 4
1/4 ref
Bout
Vin A/D
Vref
1 2 N
Vref b12 + b22 + + bN2 = Vin Vx
where
1 1
--- VLSB Vx --- VLSB
2 2
Ideal transfer curve for a 2-bit A/D converter ( Fig.
g 11.4 )
VLSB
B ---------------- = 1/4 = 1 LSB
out V
reff
11
10
01
Vin
00 -----------
3/4 1 Vref
0 1/4 1/2
V01 Vref V11 Vref
A range of input values produce the same output value (QA range of input
values produce the same output value (Quantization error)
Different from the D/A case
11.3 Quantization noise
B V1
Vin A/D D/A
+
VQ
Quantization
noise
i
VQ
Vin
1
--- VLSB
V1 2
t
(Time)
1
--- VLSB
t 2
(Time) T
VQ = V 1 Vin
Quantization noise model
VQ
Vin V1
Vin V1
V1 = Vin + VQ
Quantizer Model
The
The model is exact as long as VQ is properly defined
VQ is most often assumed to be white and uniformely distributed between +/- Vlsb/2
Quantization noise
The rms-value of the quantization noise can be shown to be:
VLSB
VQrms = ------------
-
12
Vinrms Vref 2 2
SNR = 20 log ------------
------- = 20 log --------------------------------
V
Q rms VL SB 12
SNR = 6,02N
6 02N + 1,76 1 76 dB
Quantization noise (SNR as a function of Vin)
60 10-bit
SNR
50 Best possible SNR
(dB)
40
30
20
Vpp = Vref
10
0 Vin dB
60 50 40 30 20 10 0
- 510 : (0101) +1
1 = 1010 + 1 =
1011