Professional Documents
Culture Documents
Keywords System on chip (SoC), Network on Chip (NoC), Router, II. LITERATURE OVERVIEW
Buffers, FIFO, Crossbar, LUTs.
A new pipelined router design by Anoni Roca et al [10], have
I. INTRODUCTION focused in minimizing the router latency. Primarily those
router components have identified which bounds the router
NoC is a technology that is preconceived to remove the short frequency by taking critical paths. Limitations put on the
comings of the buses. It is a perspective to design the Performance of the router by a component called, arbiter. So
communication subsystem between IP cores in a SoC design the designer has made multiple smaller arbiters. L. benini et al
[1-2]. System on chips use dedicated buses for the [11] has given solution for the critical communication
communication among various IP cores. These buses do not problem between multiple IP cores. The original router
provide enough flexibility for the communication. NoC is an architecture was embedded in the System on chip interconnect
alternative paradigm to remove problems related to the buses network NoC. System on chip interconnect network has a
by using a communication network of switches/routers parametric router architecture. Noopur Sharma et al [12] have
connecting the IP cores [3-4]. Although, the system on chips compared the packet delay and outcomes of XY routing
designed using NoCs are getting popular these days and algorithm and OE routing algorithm. Pan Hao1 et al [13]
providing solutions to the problem related to the bus based solved the Problem of hampered communication and clock in
designs and considered as the future of the ASIC design [5-6], the architecture. Debora Matos et al [14] has designed the
these designs faces several design problems. First is the architecture, in which buffer size is reconfigurable. By this
suitable topology for the target NoCs such that the design method the excessive latency, power dissipation can be
constraints and performance needs are satisfied. Second is, the reduced. Along with that the architecture is area efficient. Phi
network interfaces design to access the on chip network and Hung et al [15] has described that various components has
routers provide the physical interconnection channel to been integrated on the NoC architecture and also the modeling
transport data between processing devices. Third is, the choice of reconfigurable components such as IP cores and fixed IPs.
of communication protocols which are suitable for on chip In this work a fresh design approach is presented to customize
interconnection networks. Finally, as technology scaled and the routers in a network-on chip for reconfigurable systems.
1601
International Conference on Computing, Communication and Automation (ICCCA2016)
A. Fixed-Priority Arbiter
We have designed NoC router architecture by using the Fixed
Priority Arbiter technique. We have also increased buffer
depth with using 8:1 multiplexer and a control register. In a
router, mediating access to a shared resource between multiple
agents is one of the fundamental operations performed by the
control logic. Fig. 3. Fixed priority arbiter
1602
International Conference on Computing, Communication and Automation (ICCCA2016)
B. Fixed-Priority Arbiter: RTL Schematic View
Fig. 5. South Channel: Simulation Waveform Fig. 7. RTL Schematic View of South Channel
1603
International Conference on Computing, Communication and Automation (ICCCA2016)
Table.1 Comparison of LUTs between Original Router and
Proposed Router Architecture.
Original Router Proposed Router
Resources
Architecture Architecture
Slices 92 92
LUTs 235 204
Flip Flops 92 92
Bonded IOBs 201 89
V. CONCLUSION
The main focus of the current work is aimed at an area
efficient design of a router for NoC applications. The router is
an important component of NoC design because it determines
Fig. 8. RTL Schematic View of complete Router Architecture
various network parameters like latency, throughput and
delay. In the proposed work baseline router architecture is
used and the router is designed for five inputs and five
outputs.
The simulation has been done using Modelsim Version 10.4a
and synthesis has been done by using the XILINX ISE Design
Suit Version 14.7 Tool. After comparing the proposed
architecture with base line architecture, it has been found that
the proposed architecture performs better than the baseline
architecture. It has constant delay, constant latency, and high
throughput. In addition, it has concurrent transmission which
gives it more flexibility over the baseline architecture and is
less error prone. Proposed architecture occupies lesser area
than the baseline architecture.
REFERENCES
Fig. 9 Complete Router: Simulation Waveform
[1] A. Bhanwal, M. kumar, Y. kumar, FPGA based Design of Low Power
Reconfigurable Router for Network on Chip (NoC), IEEE,International
Conference on Computing, Communication and Automation
C. Area calculation (ICCCA2015), pp 1320 1326, 2015.
[2] B. Attia, W. Chouchene, A. Zitouni, N. Abid,and R. Tourki ,
For obtaining the area efficient architecture for NoC router, A Modular Router Architecture Desgin For Network on Chip 8th
the target device is same i.e. XC6SLX4-3TQG144 on the IEEE, International Multi-Conference on Systems,
Xilinx ISE design suit ver.14.7. All the result are synthesized Signals & Devices, PP. 493-495, 2011.
on the same target device, We have to calculate the number of [3] International Technology Roadmap for Semiconductors, report 2012.
Online Available: http://www.itrs.net/ .
LUTs of original routers crossbar [19] and our proposed
[4] R. Saleh, S. Mirabbasi, AlanHu, M. Greenstreet, G. Lemieux, P. P.
routers crossbar. If a chip has less number of LUTs than it Pande, C. Grecu, and A. Ivanov, System-on-Chip: Reuse and
would takes less space to implement. Table 1 shows, the Integration, Proceedings of the IEEE, vol. 94, no. 6, pp. 1050 1069,
LUTs representation of original crossbar and Fixed-priority Jun. 2006.
arbiter, where original crossbar takes 35 LUTs to implement [5] T. Bjerregaard and S. Mahadevan, A Survey of Research and
and our Fixed-priority arbiter takes 5 LUTs to implement, Practices of Network-on-Chip, ACM Computing Surveys, vol. 38,
no. 1, pp. 1-51, 2006.
Here, there is reduction of 30 LUTs if we use Fixed-priority
[6] L. Benini and G. D. Micheli, Networks on chips: a new SoC
arbiter. paradigm, Comput., vol. 35, no. 1, pp. 70-78, 2002.
1604
International Conference on Computing, Communication and Automation (ICCCA2016)
[7] R. Holsmark and M. Hgberg, Modelling and Prototyping of a Network
on Chip, Master of Science Thesis, 2002 Electronics, online Available:
http://hem.fyristorg.com/.
[8] M. Ali, M. Welzl, and M. Zwicknagl, Networks on Chips: Scalable
Interconnects for Future Systems on Chips, 4th IEEE European
Conference on Circuits and Systems for Communications, pp. 240-245,
2008.
[9] M. Pirretti, G. M. Link, R. R. Brooks, N. Vijaykrishnan, M. Kandemir,
and M. J. Irwin, Fault tolerant algorithms for network- on-chip
interconnect, Proceedings. IEEE Computer society Annual Symposium
on VLSI, pp.46-51, Feb. 2004.
[10] A. Roca, J. Flich, F. Sil la, J. Duato, A Latency- Efficient Router
Architecture for CMP Systems, 2010 13th Euromicro Conference on
Digital System Design: Architectures, methods and Tools. pp. 165-172,
2010.
[11] L. Benini and G.D. Micheli, Network on chips: a new SoCs
paradigm,IEEE Computer, vol. 35, no. 1, pp. 7078, Jan. 2002.
[12] N. Sharma, S. Gadag, An Efficient Way to Increase Performance by
Using Low Power Reconfigurable Routers,IOSR Journal of
Electronics and Communication Engineering (IOSR JECE), Volume 8,
Issue 6, pp. 39-44, (Nov. - Dec. 2013).
[13] P. Hao1, H. QiI, D. Jiaqin, P. Pan, Comparison of 2D MESH Routing
Algorithm in NoC, IEEE 9th International Conference, pp. 791-795,
2011
[14] D. Matos, C. Concatto, M. Kreutz, F. Kastensmidt, L. Carro, and A.
Susin, Reconfigurable Routers for Low Power and High Performance,
ieee transactions on very large scale integration (vlsi) systems, vol. 19,
no. 11, pp.2045-2057, , November, 2011.
[15] P. H. Pham, P. Mau and C. Kim, A 64-PE Folded-Torus Intra-chip
Communication Fabric for Guaranteed Throughput in Network-on-Chip
Based Applications, IEEE Custom Integrated Circuit conference
(CICC) pp. 645 648, 2009.
[16] M. Vestias and H. Neto,Router design for application specificnetwork-
on-chip on reconfigurable systems, Field Program. Logic Appl, vol. 1,
pp. 389394, 2007.
[17] D. Bertozzi, A. Jalabert, M. Srinivasan, R. Tamhankar, S.Stergiou,L.
Benini, and G.D. Micheli, NoCs synthesis flow for customized domain
specific multiprocessor systems-on-chip, IEEE Trans. Parallel Distrib.
Syst., vol. 16, no. 2, pp. 113129, Feb. 2005.
[18] M. Ahn and E. Jung Kim.,Pseudo-Circuit: Accelerating
Communication for On-Chip Interconnection Networks, In
Proceedings of the 43rd Annual IEEE/ACM International Symposium
on Microarchitecture, pp. 399 408, 2010.
[19] D. Matos, C. Concatto, M. Kreutz, F. Kastensmidt, L. Carro and A.
Susin, Reconfigurable routers for low power and high performance,
IEEE Transaction on Very Large Scale Integration (VLSI) System, vol.
19, no. 11, pp. 2045-2057, Nov. 2011
1605