ACTIVIDAD PRCTICA

----------COMPUERTA OR(ALGORITMO) S <= '0';

ELSE
ENTITY COR IS
s <= '1';
PORT (a,b,c,d: IN BIT;
END IF;
s :OUT BIT);
END PROCESS;
END COR;
END PRONOT;
ARCHITECTURE PROOR OF COR IS
BEGIN ....... MUX(ALGORITMO)
PROCESS(a,b,c,d) ENTITY CMUX IS
BEGIN PORT (a,b,c,d,e,f,g,h,sel: IN BIT;
IF a='1' OR b = '1' OR c= '1' OR d='1' THEN s :OUT BIT);
S <= '1'; END CMUX
ELSE ARCHITECTURE PROMUX OF CMUX IS
s <= '0'; BEGIN
END IF; PROCESS(a,b,c,d,e,f,g,h,sel)
END PROCESS; BEGIN
END PROOR; CASE sel IS
WHEN "000" =>s<= 'a';
---------COMPUERTA NAND(ALGORITMO)
WHEN "001" =>s<= 'b';
ENTITY CNAND IS WHEN "010" =>s<= 'c';
PORT (a,b,c,: IN BIT; WHEN "011" =>s<= 'd';
s :OUT BIT); WHEN "100" =>s<= 'e';
END CNAND WHEN "101" =>s<= 'f';
ARCHITECTURE PRONAND OF CNAND IS WHEN "110" =>s<= 'g';
BEGIN WHEN "111" =>s<= 'h';
PROCESS(a,b,c) END CASE
BEGIN END PROCESS;
IF a='1' AND b = '1' AND c= '1' THEN END PROMUX;
S <= '0';
..........DECO (ALGORITMO)
ELSE
ENTITY CDECO IS
s <= '1';
PORT (entrada : IN BIT_VECTOR (3
END IF;
DOWNTO 0);
END PROCESS;
s :OUT BIT_VECTOR (15 DOWNTO 0));
END PRONAND;
END CDECO;
...... COMPUERTA NOT (ALGORITMO) ARCHITECTURE PRODECO OF CDECO IS
ENTITY CNOT IS BEGIN
PORT (a: IN BIT; PROCESS (entrada)
s :OUT BIT); BEGIN
END CNAND CASE entrada IS
ARCHITECTURE PRONOT OF CNOT IS WHEN "0000" => s<=
BEGIN "0000000000000001";
PROCESS(a) WHEN "0001" => s<=
BEGIN "0000000000000010";
IF a='1' THEN WHEN "0010" => s<=
"0000000000000100";
WHEN "0011" => s<=
"0000000000001000";
WHEN "0100" => s<=
"0000000000010000";
WHEN "0101" => s<=
"0000000000100000";
WHEN "0110" => s<=
"0000000001000000";
WHEN "0111" => s<=
"0000000010000000";
WHEN "1000" => s<=
"0000000100000000";
WHEN "1001" => s<=
"0000001000000000";
WHEN "1010" => s<=
"0000010000000000";
WHEN "1011" => s<=
"0000100000000000";
WHEN "1100" => s<=
"0001000000000000";
WHEN "1101" => s<=
"0010000000000000";
WHEN "1110" => s<=
"0100000000000000";
WHEN "1111" => s<=
"1000000000000000";
END CASE;
END PROCESS;
END PRODECO;
..........GRAY A BCD (ALGORITMO)
ENTITY CGRAY IS
PORT (entrada : IN BIT_VECTOR (3
DOWNTO 0);
s :OUT BIT_VECTOR (7 DOWNTO 0));
END CGRAY;
ARCHITECTURE PROGRAY OF CGRAY IS
BEGIN
PROCESS (entrada)
BEGIN
CASE entrada IS
WHEN "0000" => s<= "00000000";
WHEN "0001" => s<= "00000001";
WHEN "0010" => s<= "00000011";
WHEN "0011" => s<= "00000010";
WHEN "0100" => s<= "00000111";
WHEN "0101" => s<= "00000110";
WHEN "0110" => s<= "00000100";
WHEN "0111" => s<= "00000101";
WHEN "1000" => s<= "00010101";
WHEN "1001" => s<= "00010100";
WHEN "1010" => s<= "00010010";
WHEN "1011" => s<= "00010011";
WHEN "1100" => s<= "00001000";
WHEN "1101" => s<= "00001001";
WHEN "1110" => s<= "00010001";
WHEN "1111" => s<= "00010000";
END CASE;
END PROCESS;
END PROGRAY;
.......... SUMADOR COMPLETO DE 4 BITS
(ALGORITMO)
ENTITY CSUMADOR IS
PORT (A,B: IN BIT_VECTOR (3 DOWNTO 0);
s :OUT BIT_VECTOR (3 DOWNTO 0));
END CSUMADOR;
ARCHITECTURE PROSUMADOR OF
CSUMADOR IS
SIGNAL C: bit_vector ( 3 DOWNTO 0);
BEGIN
PROCESS (a,b)
BEGIN
s(0) <= A(0) XOR B(0) XOR '0';
C(0) <= (A(0) AND B(0)) OR (A(0) AND '0')
OR (B(0) AND '0');
s(1) <= A(1) XOR B(1) XOR C(0);
C(1) <= (A(1) AND B(1)) OR (A(1) AND C(0) )
OR ( B(1) AND C(0));
s(2) <= A(2) XOR B(2) XOR C(1);
C(2) <= (A(2) AND B(2)) OR (A(2) AND C(1) )
OR ( B(2) AND C(1));
s(3) <= A(3) XOR B(3) XOR C(2);
C(3) <= (A(3) AND B(3)) OR (A(3) AND C(2) )
OR ( B(3) AND C(2));
END POCESS;
END PROSUMADOR;
..........MAYOR ENTRADA (ALGORITMO)
ENTITY CMAYOR IS
PORT (a,b,c: IN BIT_VECTOR(2 DOWNTO 0);
s :OUT BIT_VECTOR(2 DOWNTO 0));
END CMAYOR
ARCHITECTURE PROMAYOR OF CMAYOR IS
BEGIN s<= '1' WHEN a='0' ELSE '1';
PROCESS(a,b,c) END PRONOT;
BEGIN
.. MUX (RTL)
IF a > b AND a > c THEN
ENTITY CMUX IS
S <= 'a';
PORT (a,b,c,d,e,f,g,h,sel: IN BIT;
ELSIF b > a AND b > c THEN
s :OUT BIT);
s <= 'b';
END CMUX
ELSIF c > a AND c > b THEN
ARCHITECTURE PROMUX OF CMUX IS
s <= 'c';
BEGIN
else
WITH sel SELECT
s <= "000";
S <= 'a' WHEN "000",
END IF;
'b' WHEB "001",
END PROCESS;
'c' WHEB "010",
END PROMAYOR;
'd' WHEB "011",
-.................................. 'e' WHEB "100",
AHORA EN RTL 'f' WHEB "101",
................COMPUERTA OR(RTL) 'g' WHEB "110",
ENTITY COR IS 'h' WHEB "111";
PORT (a,b,c,d: IN BIT; END PROMUX;
s :OUT BIT);
........ DECO (RTL)
END COR;
ARCHITECTURE PROOR OF COR IS ENTITY CDECO IS
BEGIN PORT (entrada : IN BIT_VECTOR (3
S <= '1' WHEN a='1' OR b = '1' OR c= '1' OR DOWNTO 0);
d='1' ELSE '0'; s :OUT BIT_VECTOR (15 DOWNTO 0));
END PROOR; END CDECO;
ARCHITECTURE PRODECO OF CDECO IS
......... COMPUERTA NAND(RTL)
BEGIN
ENTITY CNAND IS
WITH entrada SELECT
PORT (a,b,c: IN BIT;
s :OUT BIT); s<= "0000000000000001" WHEN "0000",
END CNAND "0000000000000010" WHEN "0001",
ARCHITECTURE PRONAND OF CNAND IS "0000000000000100" WHEN "0010",
BEGIN "0000000000001000" WHEN "0011",
S <= '0' WHEN a='1' AND b = '1' AND c= '1' "0000000000010000" WHEN "0100",
AND d='1' ELSE '1'; "0000000000100000" WHEN "0101",
END PRONAND; "0000000001000000" WHEN "0110",
"0000000010000000" WHEN "0111",
"0000000100000000" WHEN "1000",
"0000001000000000" WHEN "1001",
"0000010000000000" WHEN "1010",
...........COMPUERTA NOT (RTL)
"0000100000000000" WHEN "1011",
ENTITY CNOT IS
"0001000000000000" WHEN "1100",
PORT (a: IN BIT;
"0010000000000000" WHEN "1101",
s :OUT BIT);
"0100000000000000" WHEN "1110",
END CNOT
"1000000000000000" WHEN "1111";
ARCHITECTURE PRONOT OF CNOT IS
END PRODECO
BEGIN
...................... GRAY A BCD (RTL) OR ( B(2) AND C(1));
s(3) <= A(3) XOR B(3) XOR C(2);
ENTITY CGRAY IS
C(3) <= (A(3) AND B(3)) OR (A(3) AND C(2) )
PORT (entrada : IN BIT_VECTOR (3
OR ( B(3) AND C(2));
DOWNTO 0);
END PROSUMADOR;
s :OUT BIT_VECTOR (7 DOWNTO 0));
END CGRAY;

ARCHITECTURE PROGRAY OF CGRAY IS

BEGIN

WITH entrada SELECT

s<= "00000000" WHEN "0000",

"00000001" WHEN "0001",
"00000011" WHEN "0010",
"00000010" WHEN "0011",
"00000111" WHEN "0100",
"00000110" WHEN "0101",
"00000100" WHEN "0110",
"00000101" WHEN "0111",
"00010101" WHEN "1000",
"00010100" WHEN "1001",
"00010010" WHEN "1010",
"00010011" WHEN "1011",
"00001000" WHEN "1100",
"00001001" WHEN "1101",
"00010001" WHEN "1110",
"00010000" WHEN "1111";
END PROGRAY;

---------- SUMADOR COMPLETO 4BITS (RTL)

ENTITY CSUMADOR IS
PORT (A,B: IN BIT_VECTOR (3 DOWNTO 0);
s :OUT BIT_VECTOR (3 DOWNTO 0));
END CSUMADOR;
ARCHITECTURE PROSUMADOR OF
CSUMADOR IS
SIGNAL C: bit_vector ( 3 DOWNTO 0);
BEGIN
s(0) <= A(0) XOR B(0) XOR '0';
C(0) <= (A(0) AND B(0)) OR (A(0) AND '0')
OR (B(0) AND '0');
s(1) <= A(1) XOR B(1) XOR C(0);
C(1) <= (A(1) AND B(1)) OR (A(1) AND C(0) )
OR ( B(1) AND C(0));
s(2) <= A(2) XOR B(2) XOR C(1);
C(2) <= (A(2) AND B(2)) OR (A(2) AND C(1) )