Ideal Tx-Line Reflection

Rm. 340, Department of Electrical Engineering

E-mail: rbwu@ew.ee.ntu.edu.tw
google: rbwu

S. H. Hall et al., High-Speed Digital Design, Chap.3

1
N. N. Rao, Elements of Engineering Electromagnetics, Chap. 6
 What will you learn?
How to solve circuits with ideal lossless tx-line?
Is there easier analytic equ. circuit model.
How to solve analytically tx-line circuits with R,
L, and C loading/discontinuities?
How does reflection come from? How to deal with
multiple reflection phenomenon?
How to measure? Operation principle of TDR.
How to extract tx-line parameters & discontinuities
from TDR measurement?
How to mitigate reflection?
R. B. Wu 2
 Contents
Analytic Tx-Line Analysis
Reflections from Resistive Loads
Reflection from Reactive Loads
Time Domain Reflectometry
Termination Designs

R. B. Wu 3
Analytic Tx-Line Analysis

4
 Distributed Element

Tx-line is also called vS(t) vA(t) i(z,t) vB(t)

a distributed element +
iA(t) v(z,t) iB(t)
_
i(z,t)

vs. lumped elements ZS, ZL.

Note the reference of V(z,t).
Where is the ground of tx-line? GROUND
I(z,t) must accompany the return-path current.
How to interpret a negative I(z,t)?
How to solve circuits with a distributed circuit element?
R. B. Wu 5
 Eq. Circuit Model for SPICE Simulation

Rule of Thumb:

1. Decide # of segments 10
tr v p

2. Choose R, L, C, G segment R, L, C, G *
#
t max freq.
Note: TDsegment r
10 # 10 R. B. Wu
 Equivalent Circuit Seen from Both Ends

V ( z, t ) V t vzp V t vzp
VA (t ) V (0, t ) V t V t
I ( z, t )
1
Z0
V (t ) V (, t ) V
V t vzp V t vzp B

t T V t T

I A (t ) I (0, t )
1

V t V t
I B (t ) I (, t )
1
Z0

V t T V t T
Z0

VB (t ) Z 0 I B (t )
VA (t ) Z 0 I A (t )
2V ( z , t )
2V ( z 0, t )
2V ( z 0, t T )
2V ( z , t T )

V VB V ; V VA V
R. B.
Ref.: F. H. Branin, Jr., Transient analysis of lossless transmission lines, Proc. Wu
IEEE, vol. 55,7 pp.
2012-2013, Nov. 1967.
 Circuit Modeling

A B
Z0 ; T
Z0 Z0 VB
VA

EA EB

Equivalent circuit
Time delay
Impedance
* voltage controlled voltage source
E A ( t ) 2v B ( t T ) E B ( t T )
Rem: Only 4 lumped E B ( t ) 2v A ( t T ) E A ( t T )
elements, even for very
long tx-line.
R. B. Wu 8
 Time Marching
At source end At load end
Zs Z0 Z0

Vs (t) VA (t) EA (t) EB (t) VB (t) ZL

VS (t ) VA(t) E A(t) V ( 0,t) V ( ,t) EB (t) VB (t)

t
x x 0 x 0 0 0
x x 0 x 0 0 0
x x 0 x 0 0 0
T x x 0 x x x x
x x 0 x x x x
x x 0 x x x x
2T x x x x x x x
x x x x x x x
3T x x x x x x x

R. B. Wu 9
Reflections from Resistive Loads

10
 Time-Domain Sol. w/o Simulator

1. Determine launch voltage & final DC or t =0

voltage
2. Calculate load reflection coefficient and voltage
delivered to the load
3. Calculate source reflection coefficient and
resultant source voltage

R. B. Wu 11
 Determine Launch Voltage
TD
I+ Rs A B
Vs
Zo
Rg 0 Vs Rt
V +

V0

Z=0 (initial voltage)

I+ t=0, V=Vi

Rg
Z0 Rt
Z0 V+ Vi = VS Vf = VS
V0 Z0 + RS Rt + RS
Z=0

Step 1: determine launch voltage

Simply a voltage divider!
R. B. Wu 12
 Voltage Delivered to Load
TD
Rs A B VB
Vs Z0
Vs Zo Rt
0
2Ei RL

(initial voltage)
t=0, V=Vi

(signal is reflected) for t d

t=TD, V=Vi +rB (Vi ) RL
VB 2V
rB Rt Zo
;
Vreflected = rB (Vincident)
Z 0 RL
V VB V
Rt Zo VB = Vincident + Vreflected I V Z 0

Step 2: determine VB at t = TD
Tx-line delays the arrival of launched voltage until t = TD.
VB for 0 < t < TD is at quiescent voltage (0 in this case)
Voltage wavefront will be reflected at tx-line end
VB = Vincident + Vreflected at t = TD R. B. Wu 13
 Voltage Reflected back to Source

Rs A B
Vs
Zo
0 Vs rA rB Rt

TD
IA VA (initial voltage)
Z0

t=0, V=Vi
Rg
2Er

V0

Z=0 t=2TD, (signal is reflected)

V=Vi + rB (Vi) + rAr B )(Vi ) t=TD, V=Vi + rB (Vi )

R. B. Wu 14
 Voltage Reflected Back to Source
Rs Zo Vreflected = rA (Vincident)
rA
Rs Zo VA = Vlaunch + Vincident + Vreflected

Step 3: Determine VA at t = 2TD

Tx-line delays the arrival of voltage reflected from load
until t = 2TD.
VA at time 0 < t < 2TD is at launch voltage
Voltage wavefront will be reflected at source
VA = Vlaunch + Vincident + Vreflected at t = 2TD

In steady state, sol. converges to VB = VS [Rt/(Rt + Rs)]

R. B. Wu 15
Lattice (Bounce) Diagram

R. B. Wu 16
 1st Reflection vs. 1st Incident Switching
Open-circuited line R 1 (VB 2V )
Termination by Z 0 R 0 (VB V )
Applications

First reflection switching First incident switching

R. B. Wu 17
 Over Driven Tx-Line (Under Damped)
V(source) Zo V(load) Assume Zs=25 ohms
2v Zs Zo =50ohms
TD = 250 ps Vs=0-2 volts
0 Vs Zo 50
Vinitial Vs (2) 1.3333
Zs Zo 25 50
rsource 0. 3333 rload 1

Time V(source) V(load) rsource Zs Zo 25 50 0.33333
0 Zs Zo 25 50
1.33v
0v 50
rload Zl Zo 1
500 ps 1.33v Zl Zo 50
1.33v
Response from lattice diagram

1000 ps 2.66v
-0.443v 3
2.5
1500 ps 2.22v 2
-0.443v Volts
1.5

1.77v 1 Source
2000 ps 0.5
0.148v Load
0
0 250 500 750 1000 1250 1500 1750 2000 2250
2500 ps 1.92
0.148v Time, ps

2.07
R. B. Wu 18
 Under Driven Tx-Line (Over Damped)
V(source) Zo V(load) Assume Zs=75 ohms
2v Zs Zo=50ohms
0 TD = 250 ps Vs=0-2 volts
Vs
Zo 50
Vinitial Vs (2) 0.8
r source 0 . 2 r load 1 Zs Zo 75 50
Time V(source) V(load) Zs Zo 75 50
r source 0.2
0 0.8v Zs Zo 75 50
0v
Zl Zo 50
rload 1
500 ps 0.8v Zl Zo 50
0.8v

1000 ps 1.6v Response fr om lattice diagram

0.16v
2.5
1500 ps 1.76v 2
0.16v
1.5
V olt s

1.92v 1 Sour ce
2000 ps
0.032v 0.5
Load

0
2500 ps 0 2 50 500 750 1000 1250

Tim e , ps

R. B. Wu 19
Effects of Rise Time overdriven case

R. B. Wu 20
Effects of Rise Time underdriven case

R. B. Wu 21
 Reflection and Transmission
Incident 1r Transmitted

r Reflected

Reflection Coefficient Transmission Coefficient

Zt Z0 Zt Z0
r =1+r 1
Zt Z0 Zt Z0
2Zt

Zt Z0
R. B. Wu 22
Multiple line impedance

R. B. Wu 23
R. B. Wu 24
 Multi Receivers Topology
l2
Receiver 1
Rs=Zs l1 Z0 Z 0 Rs 50
l1 l3 250 ps;
Z0 l3 > l2
l2 125 ps;
Receiver 2
0-2V Z0

Z0 2 Z0
2 13
Z0 2 Z0
T2 1 2 2
3

3 13 ; T3 2
3

4 1; 5 1
Eig 3-35 v 4

vA
3 4
v 8
9
3

v 52 vB 20
9
27

R. B. Wu 25
 Effects of Non-symmetry
l2
Receiver 1
Rs=Zs l1 Z0

Z0 l3 > l2
Receiver 2
0-2V Z0

R. B. Wu 26
 Ringing Noise on Address Lines of DDR
v p 3 108 / 2.5; Rs 3.27 104 s m1
tanD 0.02; TD3 L3 / v p 100ps
Tt Lt / v p 214ps; t l / v p

Z0 L1=(Lt-l)/2 Short End

L3
0-1.5V L2=(Lt+l)/2 Long End
Tr=200ps Z0, vp, Rs, tanD

Ringing Effect Ringing Effect

2 2

1.5 1.5

l/Lt=0 l/Lt=0.6, Short End

Voltage(V)

Voltage(V)
1 1
l/Lt=0.2, Short End l/Lt=0.6, Long End
0.5 l/Lt=0.2, Long End 0.5 l/Lt=0.8, Short End

l/Lt=0.4, Short End l/Lt=0.8, Long End

0 0
l/Lt=0.4, Long End

-0.5
0 0.5 1 1.5 2 2.5 3
-0.5
0 0.5 1 R.
1.5B. Wu
2 27
2.5 3
time(ns) time(ns)
 RLC Resonance Model of Ringing Noise
The total response can be divided into the balanced response and the ringing
noise response.
The ringing noise response can be fitted as a RLC resonance response
l l
sin sin 2
0
Tt
A 2 Lt
l
b
2 Lt v Step Response, l/Lt=0.12
0 Lt
0 p
sin 2 2 Tt
2 Lt
2
j 0 0 0.884m1
Z0 v0 1.5
Z0, L3 Z0/2
0-1.5V
Balanced
Tr=200ps
v0
veq Voltage(V) 1 Precise, short end
vstep(t-TD) L
vn
Model, short end
0-1.5V Avn Precise, long end
Tr=200ps 0.5 Model, long end
TD=L3/vp
Ringing
0
veq v0 vn -0.5
0 0.5 1 1.5 2 2.5 3
Equivalent Balanced Ringing noise time(ns)
R. B. Wu 28
response response response
 Eye Height Bit rate Influence
Worst case occurs at UI/Tt is odd.

UI/Tt=4, l/Lt=0.12 Eye Height/Vh

7 0.8

65% 0.8

0.8
6
0.8
0.6
5 0.6

0.6
0.6
UI/Tt

4 0.6 0.6
UI/Tt=3, l/Lt=0.12 0.4
0.4 0.2
3 0
0.6

0.2

0.6
0.4
0.4
2 00.4.2
0.6
0.4
0%
0.2
0 0.4 0.6
0

0 0.2 0.6
1
0 0.1 0.2 0.3 0.4 0.5 0.6
l/Lt

R. B. Wu 29
 Eye Height Leg Difference Influence
Worst case occurs Eye Height/Vh
at where the max 7 0.8
of A occurs. 0.8

0.8
6
0.8
l 2
0 Lt 0.12 5 0.6
0.6
L
0.6
0.6
UI/Tt

4 0.6 0.6
0.4 0.2 0.4
3 0
0.6

0.2

0.6
0.4
0.4
2 00.4.2
0.6
0.4
0.2
0 0.4 0.6
0

0 0.2 0.6
1
UI/Tt=3, l/Lt=0.12 0 0.1 0.2 0.3 0.4 0.5 0.6
l/Lt UI/Tt=3, l/Lt=0.6

Ref: K.-Y. Yang, et al., Modeling and

0% fast eye- diagram estimation of ringing 62%
effects on branch line structures, IEEE
T-CPMT, Apr. 2014.
R. B. Wu 30
Effect of a Long Stub

R. B. Wu 31
Reflections from Reactive Loads

32
 Inductive Termination
t=0
for t T l u
diL
LL R0 iL 2v V0
R0 V0 / 2
R0 LL
dt

V0
iL (t ) VR0 1 e ( t T )R0 LL
0

( t T )R0 LL
vL (t ) v(l , t ) V0e
z=0 z = z1 z=l

iL(t)
v (l , t ) v(l , t ) V0 2
v (0, t ) V0 2
R0
for t 0
v(l,t) LL
for 2T t T
v(l,t)
z1 l u t T
2v+(0, t-T)
v(l,t)
V0
V0
V0 / 2

z = z1 z=l z
T LL
R0
t R. B. Wu
 Capacitive Termination
t=0
for t T
R0
R0
v (l , t ) v(l , t ) V0 2
CL

z1 l u t1 T
V0
v(z,t1)

V0
z=0 z = z1 z=l

iL(t) V0 / 2
v (0, t ) V0 2
R0
for t 0 z = z1 z=l z
v(l,t) CL v(z1,t)
v(l,t) 2v+(0, t-T)
V0

V0
V0 / 2

0 T t1 t
t R. B. Wu
T
Time Domain Reflectometry

36
 Time-Domain Reflectometry
Key advantages over frequency measurement
Ability to extract electrical data relevant to digital systems
Can extract impedance, velocity, tx-line parameters, and model
parameters of discontinuities.
Basic theory

1 r
Z DUT Z o ;
1 r
Vreflected Z DUT Z o
r
Vincident Z DUT Z o

R. B. Wu 37
 Impedance & Velocity
at node A

R. B. Wu 38
 Peeling Idea for Reflections
Multiple reflections.
Need minimize reflections prior to DUT & TDR
Use a controlled-impedance, low-loss cable btw TDR & probe
Use a low-loop-inductance, controlled-impedance probe

J. M. Jong and V. K.
Tripathi, IEEE T-CHMT,
pp. 497-504, Aug .
1992
J. M. Jong, B. Janko
and V. K. Tripathi,
IEEE T-CHMT, pp.
119-126, Feb. 1993

R. B. Wu 41
Inductive Load in Middle of a Line
L 0r
2Z t
r max 1 e
L

2tr Z 0

vs

vs L
Aind ;
4Z0
vs: excitation voltage

R. B. Wu 42
Capacitive Load in Middle of a Line

CD

VB-Ei

Tw,50
Vr

vs Z 0C
Acap ;
4

R. B. Wu 43
Discontinuity Loading

R. B. Wu 44
Equally Spaced Capacitive Loads

Z 0 49.7
d 0.573ns
C L 2 pF
t r 0.35ns

R. B. Wu 45
 FLY-BY Topology in DIM and Modeling

B C
Simulation Model thin trace (trace width: 4mil)

f= 800 MHz + Package

A thick trace (10mil)
Tr=125 ps
+ +
_Microstrip (10 mil) Stripline (10 mil)
R1= 40 ohm
C
stripline (4 mil)
Voltage = 1.5v B R R R R R R R R

_ L L L L
_
L L L L
R2= 40 ohm

C C C C C C C C

TDR at A and TDT at B will be considered under DDR3 to discuss

effects of FLY-BY trace design (width 10mil vs. 4mil).
R. B. Wu 46
 Simulation A trace width

R1= 40 ohm stripline (4 mil)

Results
Microstrip (10 mil) Stripline (10 mil)
R R

f= 800 MHz L L
+ R2= 40 ohm

Tr=125 ps
B C C

_
1

TDR
1

VA TDT
VB
0.8
0.8

0.6

Voltage (V)
0.6
Voltage (V)

0.4 0.4

0.2 0.2

Trace W idth = 4 m il Trace W idth = 4 m il

Trace Width = 10 mil Trace Width = 10 mil
0 0

0 1 2 3 4 5 6 0 1 2 3 4 5 6
Time (nSec) Time (nSec)

Suitable trace width (thin trace) improves impedance match.

H.-H. Chuang, et al., Signal/power integrity modeling of high-speed memory
modules using chip-package-board co-analysis, IEEE T-EMC, May 2010. R. B. Wu 47
Inductance Measurement by TDR
Z0

Z0
L
Voc
0
vs ,DUT (t ) vs ,ref (t ) dt

Rem.:
different formula
if matched at
right end

R. B. Wu 48
Capacitance Measurement by TDR
Z0

1
C
Z 0Voc
0
vo,ref (t ) vo,DUT (t ) dt

R. B. Wu 49
Termination Design

50
 Termination Schemes to minimize reflection noise
Decrease system frequency
Shorten PCB traces
Termination with matched impedance
Source termination
On-die source termination
Series source termination
Parallel termination (Load termination)
Load termination with a resistive load
AC load termination
Active termination
Ref.: H. Johnson & M. Graham, High-Speed Digital Design, Sec.6.1-4 R. B. Wu 51
 Source Termination
On-die source termination

Difficult to guarantee matched buffer impedance!

Series source termination

Add cost to board, and consumes board area!

R. B. Wu 52
SI is about Finding & Fixing Problems

3 inch long PCB Trace 3 inch long PCB Trace

Series termination (~40 Ohms)

R. B. Wu 53
Source Termination
suggested :
Rs Rop Z 0
overshoot

T10-90 2.2 RC 2.2Z 0C

2
VDD 1
E 2 f
2 R
(Pulse Freq.) f VDD
2

Power
2R
R. B. Wu 54
 Load Termination
Load termination with a resistive load

Power delivery and thermal problems!

AC load termination

Capacitor value need be optimized for specific design

Capacitive loading increases signal delay! R. B. Wu 55
 Load Termination

Eq. ckt
Tterm. 2.2 RC
2.2 C ( RL // Z 0 ) 1.1Z 0C
CD
2
net risetime : Tterm tr2

Too much power consumption! R. B. Wu 56

 Split Termination

match R1 // R2 Z 0

(VHI VEE ) 2 (VLO VEE ) 2

Pload 2 R2
(VCC VHI ) 2 (VCC VLO ) 2
2 R1
( V ) 2
2Z 0
R. B. Wu 57
 Load Termination for Multiple Lines

Bifurcated line
with matched
trace impedance

Daisy-chain configuration

Cap. of each
short stub adds
to cap. load of
receiver End termination
R. B. Wu 58
 AC Load Termination

R1C clock time

Power saving (in DC-balanced circuit)

( V / 2 ) 2 ( V ) 2
PR1 Z0 4Z0

R. B. Wu 59
Match by Series/Parallel Termination

Parallel
termination

R. B. Wu 60
 Active Termination
V L H
25
V H L

25 2/3
1

TTL / CMOS
50

Clamp to -1V on HIGH-

to-LOW (limit signal
undershoot)
L L L

R0 Suitable for any Z0

L L L
Power saving
Voo 0.1 F
ECL Vbb
R. B. Wu 61
 Comparisons
Rise time of an end-terminated circuit, when capacitively
loaded, is half of a series-terminated line driving same load.
Most TTL or CMOS gates cant source enough current to
drive end terminators. Split termination or capacitive
termination can be a remedy.
One can daisy-chain receivers on an end-terminated line.
At low-pulse repetition rates, source terminations dissipates
little power.
V 1
2

Peak drive power for source-terminated line is 2 R

same as end-terminated line (biased at halfway point)

R. B. Wu 62
 Did you learn?
Whats diff. of distributed from lumped circuits?
How to solve analytically tx-line circuits with R,
L, and C loading/discontinuities?
Load & source reflection coeff. & bounce diagram.
Operation principle of time domain reflectometry.
How to extract tx-line parameters & discontinuities
from TDR measurement?
How to mitigate reflection?

R. B. Wu 63
 References & Further Reading
F. H. Breanin, Jr., Transient analysis of lossless transmission lines,
IEEE Proc. Lett., pp.2012-2013, 1967.
J. M. Jong, B. Janko, and V. K. Tripathi, Equivalent circuit modeling of
interconnects from time-domain measurements, IEEE T-CHMT, vol. 16,
pp. 119-126, Feb. 1993.
M.-H. Wang and R.-B. Wu, Measuring method for equivalent
circuitry, USA Patent 6,137,293, Oct. 2000.
H.-H. Chuang, et al., Signal/power integrity modeling of high-speed
memory modules using chip-package-board coanalysis, IEEE T-EMC,
vol. 52, pp. 381-391, May 2010.
K.-Y. Yang, et al., Modeling and fast eye-diagram estimation of ringing
effects on branch line structures, IEEE T-CPMT, Apr. 2014.
A. Boutar, et al., "An efficient analytical method for electromagnetic
field to transmission line coupling into a rectangular enclosure excited by
an internal source", IEEE T-EMC, pp. 1-9, 2015.
R. B. Wu 64
 References & Further Reading
A. Beygi and A. Dounavis, "Analysis of excited multi-conductor
transmission lines based on the passive method of characteristics
macro-model," IEEE T-EMC, vol. 54, pp. 1281 - 1288 , Dec. 2012.
F. Capolino, et al., "Equivalent transmission line model with a lumped
X-circuit for a meta-layer made of pairs of planar conductors, IEEE
T-AP, vol. 61, pp. 852-861, Feb. 2013.
G. Lugrin, et al., "High-frequency electromagnetic coupling to multi-
conductor transmission lines of finite length, IEEE T-EMC, vol. 57,
pp. 1714-1723, Dec. 2015.
M. Chernobryvko, D. De Zutter, and D. Vande Ginste, "Nonuniform
multi-conductor transmission line analysis by a two-step perturbation
technique", IEEE T-CPMT, vol. 4, pp. 1838-1846, Nov. 2014.
G. Antonini, et al., "Review of Clayton R. Paul studies on multi-
conductor transmission lines", IEEE T-EMC, vol. 55, pp. 639-647,
Aug. 2013.
R. B. Wu 65