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Colossus 15/17 D

DIS_OPT Schematic
IVY Bridge (rPGA989)
C
Intel PCH (Panther Point) C

REV:-1
B 2012-01-05. B

DY:No stuff
DIS_OPT:DISCRTE OPTIMUS installed
DY_35W:No stuff on 35W CPU <Core Design>

DY_45W:No stuff on 45W CPU


Wistron Corporation
A CR_Balen17:Stuff for 17" 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.
CR_Goya:Stuff for 15"
Title

Cover Page
Size Document Number Rev
A4 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 1 of 103
5 4 3 2 1
5 4 3 2 1

SYSTEM DC/DC CPU DC/DC


COLOSSUS Block Diagram INPUTS
TPS51461
OUTPUTS
48 VT1323
INPUTS OUTPUTS
42~44

5V_S5 VCCSA=0D85V_S0 DCBATOUT(5V_S5) VCC_CORE

SYSTEM DC/DC
VRAM/DDR3 VRAM/DDR3 SN1003055RUWR 45

D
64MBx16 4 64MBx16 4 Project code : 91.4ST01.001 INPUTS OUTPUTS D
88,89,90,91 88,89,90,91 5V_S5/3D3V_S5 1D05V_S0
PCB P/N : 11254
Revision : -1 SYSTEM DC/DC
DDR3 RT8223M_5V/3D3V 41
Intel CPU INPUTS OUTPUTS
DDRIII 1600/1333 Channel A 5V_AUX_S5
DDRIII Slot 0 3D3V_AUX_S5
Nvidia N13P IVY Bridge-M 1600/1333 14 DCBATOUT 5V_S5
3D3V_S5
GL PCIe x8
DDRIII 1600/1333 Channel B DDRIII Slot 1 SYSTEM DC/DC
1600/1333 15 RT8207MZ 46

83,84,85,86,87
INPUTS OUTPUTS
1D5V_S3
4,5,6,7,8,9,10 DCBATOUT 0D75V_S0
DDR_VREF_S3

GFX DC/DC
VT1323 42~44
FDIx2 DMI2.0x4
C C
2.7GT/s 5GT/s INPUTS OUTPUTS
DCBATOUT(5V_S5) VCC_GFXCORE

LED Panel LVDS(Dual Channel) VGA


49
NCP3218G 92
Intel
INPUTS OUTPUTS
CRT RGB CRT PCH
50 DCBATOUT VGA_CORE

Panther Point-M Finger Printer CHARGER


HDMI BQ24738 40
HDMI 1.4 51 AES2665 64
USB 3.0/2.0 ports (14) INPUTS OUTPUTS
ETHERNET (10/100/1000Mb) AD+
Cardreader WEBCAM 49 BT+ DCBATOUT
SD/MMC Realtek PCIE High Definition Audio 26
CONN 74
RTS5229 32 SATA ports (6) USB 2.0
SYSTEM DC/DC
USB 2.0 82 RT8068A 47
PCIE ports (8) CONN x1
Gigabit NIC INPUTS OUTPUTS
RJ45 LPC I/F
Realtek PCIE
B CONN ACPI 1.1 USB 3.0 3D3V_S5 1D8V_S0 B
59
RTL8111F 31 USB3.0 62
CONN x3 SYSTEM DC/DC
VT385FCX 93
MIC IN 17,18,19,20,21,22,23,24,25
INPUTS
26 OUTPUTS
SPI
PCIE+USB2.0
Mini-Card 65 3D3V_S0 3D3V_VGA_S0
802.11a/b/g/n 1D5V_S0 1D5V_VGA_S0
AUDIO CODEC Bluetooth combo 1D5V_S3 1V05_VGA_S0
SM Bus

Internal Digital MIC Switches 36


HP IDT HD Audio SATA HDD1 56 INPUTS OUTPUTS
92HD91 1D5V_S3 1D5V_S0
AMP 5V_S5 5V_S0
HPA0929RTJR 29 3D3V_S5 3D3V_S0
Accelerometer LPC Bus LPC debug port HDD2 56
71
HP3DC2 79 PCB LAYER
58
(DISCRETE)
L1:Top L5:VCC
2nd SPEAKE KBC ODD 56 L2:GND L6:Signa
D/A
2nd AMP TPA2012D2R SPI Flash60 L3:Signal L7:GND
A 8MB ENE L4:Signal L8::Bottom
A
KB9016QF A/D mSATA
Woofer 30 27 103 <Core Design>

Subwoofer AMP TPA3111D1 58 PWM FAN Wistron Corporation


21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
28 Taipei Hsien 221, Taiwan, R.O.C.
Main SPEAKER
Title
Touch Int.
Thermal
Block Diagram
Size Document Number Rev
PAD69 KB69 A3 1
G709/P2800 28 Colossus
25 Date: W ednesday, January 04, 2012 Sheet 2 of 103
5 4 3 2 1
5 4 3 2 1

PCH Strapping Chief River Schematic Checklist Rev0.72 Processor Strapping Chief River Schematic Checklist Rev0.72
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k CFG[2] PCI-Express Static 1: Normal Operation.
- 10-k weak pull-up resistor. Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
Lane Reversal 0:
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
Disabled - No Physical Display Port attached to
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. CFG[4] 1: Embedded DisplayPort.
D GNT2#/GPIO53 Mobile: Used as GPIO only 0 D

GNT1#/GPIO51 Pull-up resistors are not required on these signals. Enabled - An external Display Port device is
0: connectd to the EMBEDDED display Port
If pull-ups are used, they should be tied to the Vcc3_3power rail.
CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
SPI_MOSI function 2 disabled
Straps 11
Disable Danbury:Left floating, no pull-down required. 01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm enabled
weak pull-up resistor [CRB has it pulled up
NV_ALE with 1-kohm no-stuff resistor] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training 1
Disable Danbury: Leave floating (internal pull-down)

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. Voltage Rails
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. POWER PLANE VOLTAGE DESCRIPTION
Platform design should provide appropriate pull-up or pull-down depending on ACTIVE IN
C
/GPIO[33] 5V_S0 5V C
the desired settings. If a jumper option is used to tie this signal to GND as 3D3V_S0 3.3V
required by the functional strap, the signal should be pulled low through a weak 1D8V_S0 1.8V
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. 1D5V_S0 1.5V
1D05V_S0 1.05V
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal VCCSA_OD85V 0.9 - 0.675V S0 CPU Core Rail
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for 0D75V_S0 0.75V Graphics Core Rail
strapping functions. VCC_CORE 0.35V to 1.5V
VCC_GFXCORE 0.4 to 1.25V
3D3V_VGA_S0 3.3V
1D5V_VGA_S0 1D5V
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 1D05V_VGA_S0 1D05V

HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low(0) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no
GPIO15 5V_USBX_S3 5V
confidentiality. High(1) - Intel ME Crypto Transport Layer Security (TLS) cipher 1D5V_S3 1.5V S3
suite with confidentiality. DDR_VREF_S3 0.75V
Note : This is an un-muxed signal.
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. BT+ 6V-14.1V
Sampled at rising edge of RSMRST#. DCBATOUT 6V-14.1V
CRB has a 1-kohm pull-up on this signal to +3.3VA rail. 5V_S5 5V
5V_AUX_S5 5V All S states AC Brick Mode only
3D3V_S5 3.3V
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down 3D3V_AUX_S5 3.3V
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled. 1D05V_LAN 1.05V S0/M0, SX/M3 ON whenever iAMT is active
B B

Default = Do not connect (floating)


3D3V_M 3.3V
High(1) = Enables the internal VccVRM to have a clean supply for 1D05V_M 1.05V S0/M0, SX/M3, WOL_EN ON for iAMTLegacy WOL
GPIO27 analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails. 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
SATA Table
3D3V_AUX_S5 3.3V G3, Sx Powered by Li Coin Cell in G3 SATA
USB2.0 Table and 3D3V_S5 in Sx
Pair Device
PCIe Routing Pair Device
SMBus ADDRESSES
0 USB 3.0 I/O CONN. 1 0 HDD1
LANE1 N/A 1 N/A 1 mSATA
I 2 C / SMBus Addresses Ref Des Chief River CRV
2 USB 3.0 I/O CONN. 2 2 HDD2
LANE2 17"Card Reader 3 USB 3.0 I/O CONN. 3
USB3.0 Table Device Address Hex Bus
3 N/A
4 FREE USB EC SMBus 1 BAT_SCL/BAT_SDA 4 ODD
LANE3 15"Card Reader Pair Device Battery BAT_SCL/BAT_SDA
CHARGER BAT_SCL/BAT_SDA
5 BT WLAN combo 5 N/A
LANE4 Mini Card1(WLAN) 1 I/O CONN. 1
6 FREE
2 FREE EC SMBus 2 SML1_CLK/SML1_DATA
A
LANE5 N/A 7 FREE PCH SML1_CLK/SML1_DATA
<Core Design> A
3 I/O CONN. 2 eDP SML1_CLK/SML1_DATA
8 Fingerprint
LANE6 Intel GBE LAN / LAN USB 2.0 I/O CONN.
4 I/O CONN. 3 Wistron Corporation
9 PCH SMBus PCH_SMBDATA/PCH_SMBCLK 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SO-DIMMA (SPD) PCH_SMBDATA/PCH_SMBCLK Taipei Hsien 221, Taiwan, R.O.C.
LANE7 N/A 10 Camera SO-DIMMB (SPD) PCH_SMBDATA/PCH_SMBCLK
Digital Pot PCH_SMBDATA/PCH_SMBCLK Title
11 FREE G-Sensor PCH_SMBDATA/PCH_SMBCLK
LANE8 N/A 12 FREE
MINI PCH_SMBDATA/PCH_SMBCLK Table of Content
Size Document Number Rev
A3 1
13 FREE Colossus
Date: Monday, December 26, 2011 Sheet 3 of 103
5 4 3 2 1
5 4 3 2 1

CPU(1/7)
IVY BRIDGE PROCESSOR (DMI,DP,PEG,FDI)
PEG Compensation
D D
1D05V_S0
CPU1A 1 OF 9
J22 PEG_COMP 1 2 NOTE.
IVY-BRIDGE PEG_ICOMPI R401 24D9R2F-L-GP
19 DMI_TXN[3:0] PEG_ICOMPO J21 If PEG is not implemented, the RX&TX pairs can be left as No Connect
DMI_TXN0 B27 H22
DMI_TXN1 DMI_RX#0 PEG_RCOMPO
Note: B25 DMI_RX#1
Intel DMI supports both Lane DMI_TXN2 A25
DMI_TXN3 DMI_RX#2 PEG_RXN0 PEG_RXN[0..7] 83
B24 K33
Reversal and polarity inversion DMI_RX#3 PEG_RX#0
M35 PEG_RXN1
but only at PCH side. This is 19 DMI_TXP[3:0] PEG_RX#1
DMI_TXP0 B28 L34 PEG_RXN2
DMI_TXP1 DMI_RX0 PEG_RX#2 PEG_RXN3
enabled via a soft strap. B26 DMI_RX1 PEG_RX#3 J35

DMI
DMI_TXP2 A24 J32 PEG_RXN4
DMI_TXP3 DMI_RX2 PEG_RX#4 PEG_RXN5
B23 DMI_RX3 PEG_RX#5 H34
H31 PEG_RXN6
19 DMI_RXN[3:0] DMI_RXN0 PEG_RX#6 PEG_RXN7
G21 DMI_TX#0 PEG_RX#7 G33 Signal Routing Guideline:
DMI_RXN1 E22 G30 PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
DMI_RXN2 DMI_TX#1 PEG_RX#8
F21 F35
DMI_RXN3 D21
DMI_TX#2 PEG_RX#9
E34
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
DMI_TX#3 PEG_RX#10
19 DMI_RXP[3:0] PEG_RX#11 E32
DMI_RXP0 G22 D33
DMI_RXP1 DMI_TX0 PEG_RX#12
D22 DMI_TX1 PEG_RX#13 D31

PCI EXPRESS* - GRAPHICS


DMI_RXP2 F20 B33
DMI_RXP3 DMI_TX2 PEG_RX#14
C21 DMI_TX3 PEG_RX#15 C32 PEG_RXP[0..7] 83
J33 PEG_RXP0
PEG_RX0 PEG_RXP1
PEG_RX1 L35
K34 PEG_RXP2
19 FDI_TX_N[7:0] PEG_RX2
C Note:
FDI_TX_N0
FDI_TX_N1
A21
H19
FDI0_TX#0 PEG_RX3 H35
H32
PEG_RXP3
PEG_RXP4 C
FDI_TX_N2 FDI0_TX#1 PEG_RX4 PEG_RXP5
Intel FDI supports both Lane E19 FDI0_TX#2 PEG_RX5 G34
FDI_TX_N3 F18 G31 PEG_RXP6

Intel(R) FDI
Reversal and polarity inversion FDI_TX_N4 B21
FDI0_TX#3 PEG_RX6
F33 PEG_RXP7
but only at PCH side. This is FDI_TX_N5 FDI1_TX#0 PEG_RX7
C20 FDI1_TX#1 PEG_RX8 F30
enabled via a soft strap. FDI_TX_N6 D18 E35
FDI_TX_N7 FDI1_TX#2 PEG_RX9
E17 FDI1_TX#3 PEG_RX10 E33
PEG_RX11 F32
19 FDI_TX_P[7:0] PEG_RX12 D34
FDI_TX_P0 A22 E31
FDI_TX_P1 FDI0_TX0 PEG_RX13
G19 FDI0_TX1 PEG_RX14 C33
FDI_TX_P2 E20 B32
FDI_TX_P3 FDI0_TX2 PEG_RX15
G18 FDI0_TX3 PEG_TXN[0..7] 83
FDI_TX_P4 B20 M29 PEG_C_TXN0 C416
C
DIS_OPT 416 1 2SCD22U10V2KX-1GP PEG_TXN0
FDI_TX_P5 FDI1_TX0 PEG_TX#0 PEG_C_TXN1 C415
C 415
C19 FDI1_TX1 PEG_TX#1 M32 DIS_OPT 1 2SCD22U10V2KX-1GP PEG_TXN1
FDI_TX_P6 D19 M31 PEG_C_TXN2 C414
C
DIS_OPT 414 1 2SCD22U10V2KX-1GP PEG_TXN2
FDI_TX_P7 FDI1_TX2 PEG_TX#2 PEG_C_TXN3
F17 FDI1_TX3 PEG_TX#3 L32 DIS_OPT413
C413
C 1 2SCD22U10V2KX-1GP PEG_TXN3
L29 PEG_C_TXN4 C412
C
DIS_OPT 412 1 2SCD22U10V2KX-1GP PEG_TXN4
PEG_TX#4 PEG_C_TXN5 C411
C 411
Note: 19 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#5 K31 DIS_OPT 1 2SCD22U10V2KX-1GP PEG_TXN5
Lane reversal does not apply to J17 K28 PEG_C_TXN6 C410
C
DIS_OPT 410 1 2SCD22U10V2KX-1GP PEG_TXN6
19 FDI_FSYNC1 FDI1_FSYNC PEG_TX#6 PEG_C_TXN7
FDI sideband signals. PEG_TX#7 J30 DIS_OPT409
C409
C 1 2SCD22U10V2KX-1GP PEG_TXN7
19 FDI_INT H20 FDI_INT PEG_TX#8 J28
PEG_TX#9 H29
DP Compensation, within 500mil 19 FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#10 G27
19 FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#11 E29
PEG_TX#12 F27
PEG_TX#13 D28
1D05V_S0 F26
PEG_TX#14
B 4mil PEG_TX#15 E25
B
R4021 2 24D9R2F-L-GP DP_COMP A18 EDP_COMPIO PEG_C_TXP0 C432
C 432 PEG_TXP[0..7] 83
12mil A17 EDP_ICOMPO PEG_TX0 M28 DIS_OPT 1 2SCD22U10V2KX-1GP PEG_TXP0
B16 M33 PEG_C_TXP1 C431
C
DIS_OPT 431 1 2SCD22U10V2KX-1GP PEG_TXP1
EDP_HPD PEG_TX1 PEG_C_TXP2 C430
C 430
PEG_TX2 M30 DIS_OPT 1 2SCD22U10V2KX-1GP PEG_TXP2
NOTE: EDP_HPD L31 PEG_C_TXP3 C429
C
DIS_OPT 429 1 2SCD22U10V2KX-1GP PEG_TXP3
PEG_TX3 PEG_C_TXP4 C428
C 428
C15 L28 DIS_OPT 1 2SCD22U10V2KX-1GP PEG_TXP4
Select a Fast FET similar to 2N7002E whose rise/ D15
EDP_AUX PEG_TX4
K30 PEG_C_TXP5 DIS_OPT427
C427
C 1 2SCD22U10V2KX-1GP PEG_TXP5
EDP_AUX# PEG_TX5
eDP

fall time is less than 6 ns. PEG_TX6 K27 PEG_C_TXP6 C425


C
DIS_OPT 425 1 2SCD22U10V2KX-1GP PEG_TXP6
J29 PEG_C_TXP7 C426
C
DIS_OPT 426 1 2SCD22U10V2KX-1GP PEG_TXP7
If HPD on eDP interface is PEG_TX7
C17 EDP_TX0 PEG_TX8 J27
disabled, connect it to CPU VCCIO via a 10-k pull-Up F16 H28
EDP_TX1 PEG_TX9
resistor on the motherboard. C16 EDP_TX2 PEG_TX10 G28
G15 E28
This signal can be left as no connect if entire eDP interface is disabled. EDP_TX3 PEG_TX11
F28
PEG_TX12
C18 EDP_TX#0 PEG_TX13 D27
E16 EDP_TX#1 PEG_TX14 E26
D16 EDP_TX#2 PEG_TX15 D25
F15 EDP_TX#3
Signal Routing Guideline:
EDP_ICOMPO keep W/S=12/15 mils and routing
length less than 500 mils.
EDP_COMPIO keep W/S=4/15 mils and routing 633996-302
length less than 500 mils. Hand control CPU1 P/N
2ND = 62.10055.321
NOTE. 3RD = 62.10055.551 1st 633996-302
A Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort. 2nd 633996-501 <Core Design>
A
3rd 633996-301
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(1/7): DMI/PEG/FDI
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 4 of 103
5 4 3 2 1
CPU(2/7)
IVY BRIDGE PROCESSOR (CLK,MISC,JTAG)
CPU1B 2 OF 9
1D05V_S0
IVY-BRIDGE

A28 CPU_BCLK_P 1 4 RN501

MISC
CLKOUT_DMI_P 18

CLOCKS
BCLK CPU_BCLK_N 2
C26 A27 3 SRN0J-6-GP CLKOUT_DMI_N 18

1
22 H_SNB_IVB# PROC_SELECT# BCLK#
1D05V_S0
D R501
62R2F-GP TPAD14-OP-GP TP501 1 TP_SKTOCC#_R AN34
SKTOCC#
A16 CLK_DP_P_R 2 3
D
DPLL_REF_CLK
Q501 A15 CLK_DP_N_R 1 4 SRN1KJ-7-GP

2
DPLL_REF_CLK# RN504
27 PROCHOT_EC G
TPAD14-OP-GP
D TP502 1 H_CATERR# AL33
H_PROCHOT# 42 CATERR#

1
S

THERMAL
R525
100KR2J-1-GP 2N7002K-2-GP AN33 R8 CPUDRAMRST#
22,27 H_PECI PECI SM_DRAMRST#
84.2N702.J31

DDR3
MISC
2nd = 84.2N702.W31

2
H_PROCHOT# 1 2 H_PROCHOT#_D AL32 AK1 SM_RCOMP_0
R508 56R2F-1-GP PROCHOT# SM_RCOMP0 SM_RCOMP_1
A5
SM_RCOMP1 SM_RCOMP_2
A4
SM_RCOMP2
AN32
22,36 H_THRMTRIP# THERMTRIP#

1 2 H_CPUPWRGD_R
PM_DRAM_PWRGD Traces impedance= 50 ohm
3D3V_S0
R518 10KR2J-3-GP
PRDY#
AP29 XDP_PRDY# 1 TP503 TPAD14-OP-GP
AP27 XDP_PREQ#
3D3V_S5 PREQ#
AR26 XDP_TCK
1

PWR MANAGEMENT
1D5V_S0 TCK

JTAG & BPM


R519 AR27 XDP_TMS
R523 H_PM_SYNC_R TMS XDP_TRST#
19 H_PM_SYNC 1 2 AM34 AP30

1
200R2F-L-GP 0R0402-PAD-1-GP PM_SYNC TRST#
C503 AR28 XDP_TDI

1
SCD1U10V2KX-5GP R520 TDI XDP_TDO TP509 TPAD14-OP-GP
U501 AP26 1
2

2
R524 C502 H_CPUPWRGD_R TDO
19 PM_DRAM_PWRGD 1 5 22 H_CPUPWRGD 1 2 AP33
IN B VCC 200R2F-L-GP SC1U6D3V2KX-GP 0R0402-PAD-1-GP UNCOREPWRGOOD

2
45,48 0D85V_EN 1 R532 2 0R2J-2-GP 2 R516
IN A H_DBR#_R
AL35 2 1

2
PM_DRAM_PWRGD_M PM_DRAM_PWRGD_R DBR# XDP_DBRESET# 19
36,46,47 RUNPWROK 1 R531 2 0R2J-2-GP 3 4 1 2 V8 0R0402-PAD
GND OUT Y R512 130R2F-1-GP SM_DRAMPWROK
DY
74VHC1G09DFT2G-GP AT28
BPM#0
AR29
BPM#1
AR30
73.01G09.AAH BUF_CPU_RST# AR33
BPM#2
AT30
C S0_PWR_GOOD0D85V_EN(Follow Gable1.1)
RESET# BPM#3
BPM#4
BPM#5
AP32
AR31
C
AT31
DY R531 and stuff R532 BPM#6
AR32
1D05V_S0 BPM#7
-1 1220 3D3V_S0
1

R526 DY
75R2J-1-GP
1 DY
C504
2

U502 SCD1U10V2KX-5GP 3D3V_S0 1D05V_S0


2

1 5
DDR3 Compensation Signals

2
NC#1 VCC

2
R530 SM_RCOMP_0
21,27,31,32,36,65,71,82,83,103 PLT_RST# 2
A DY SM_RCOMP_1
51R2J-2-GP
BUF_CPU_RST#_R 1 1D5V_S3 R529 SM_RCOMP_2
3
GND Y
4 DY 2
S3 Power Reduction Circuit 1KR2J-1-GP

1
1

1
R517
SM_DRAMRST#

1
74LVC1G07GW-GP R521 R510 R504 R503

1
43R2J-GP 750R2F-GP XDP_TDO
Buffered reset to CPU DY

200R2F-L-GP

25D5R2F-GP

140R2F-GP
R522 R513
73.01G07.0HG 2
CPUDRAMRST# 1 2CPUDRAMRST#_R 1KR2F-3-GP XDP_DBRESET#

2
2ND = 73.01G07.CHH 0R2J-2-GP

2
1 2

2
3RD = 73.17S07.0AG Q502
R527 DMN5L06K-7-GP
R514
1K5R2F-2-GP
S D 1 2 DDR3_DRAMRST# 14,15
84.05067.031

1
R515 2ND = 84.00138.H31 1KR2J-1-GP
4K99R2F-L-GP 3RD = 84.2N702.W31 1D05V_S0
PU/PD for JTAG signals

G
2
PCH_DDR_RST# 8,18
XDP_TMS R506 1 2 51R2J-2-GP

1
C501 XDP_TDI R509 1 2 51R2J-2-GP
B B

SCD047U25V2KX-GP
2
XDP_PREQ# R505 1 2 51R2J-2-GP
DY

RN505
XDP_TCK 1 4
XDP_TRST# 2 3

SRN51J-GP

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(2/7): CLK/MISC/JTAG
Size Document Number Rev
A2 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 5 of 103

5 4 3 2 1
5 4 3 2 1

CPU(3/7)
D
IVY BRIDGE PROCESSOR (DDR3) D

CPU1C 3 OF 9 CPU1D 4 OF 9

IVY-BRIDGE IVY-BRIDGE
SA_CK0 AB6 SB_CK0 AE2
14 M_A_DQ[63:0] M_A_DIM0_CLK_DDR0 14 15 M_B_DQ[63:0] M_B_DIM0_CLK_DDR0 15
AA6 AD2
M_A_DQ0 SA_CLK#0 M_A_DIM0_CLK_DDR#0 14 M_B_DQ0 SB_CLK#0 M_B_DIM0_CLK_DDR#0 15
C5 V9 C9 R9
M_A_DQ1 SA_DQ0 SA_CKE0 M_A_DIM0_CKE0 14 M_B_DQ1 SB_DQ0 SB_CKE0 M_B_DIM0_CKE0 15
D5 A7
M_A_DQ2 SA_DQ1 M_B_DQ2 SB_DQ1
D3 SA_DQ2 D10 SB_DQ2
M_A_DQ3 D2 M_B_DQ3 C8
M_A_DQ4 SA_DQ3 M_B_DQ4 SB_DQ3
D6 SA_DQ4 SA_CK1 AA5 A9 SB_DQ4 SB_CK1 AE1
M_A_DQ5 M_A_DIM0_CLK_DDR1 14 M_B_DQ5 M_B_DIM0_CLK_DDR1 15
C6 AB5 A8 AD1
M_A_DQ6 SA_DQ5 SA_CLK#1 M_A_DIM0_CLK_DDR#1 14 M_B_DQ6 SB_DQ5 SB_CLK#1 M_B_DIM0_CLK_DDR#1 15
C2 V10 D9 R10
M_A_DQ7 SA_DQ6 SA_CKE1 M_A_DIM0_CKE1 14 M_B_DQ7 SB_DQ6 SB_CKE1 M_B_DIM0_CKE1 15
C3 D8
M_A_DQ8 SA_DQ7 M_B_DQ8 SB_DQ7
F10 SA_DQ8 G4 SB_DQ8
M_A_DQ9 F8 M_B_DQ9 F4
M_A_DQ10 SA_DQ9 M_B_DQ10 SB_DQ9
G10 AB4 F1 AB2
M_A_DQ11 SA_DQ10 SA_CK2 M_B_DQ11 SB_DQ10 SB_CK2
G9 SA_DQ11 SA_CLK#2 AA4 G1 SB_DQ11 SB_CLK#2 AA2
M_A_DQ12 F9 W9 M_B_DQ12 G5 T9
M_A_DQ13 SA_DQ12 SA_CKE2 M_B_DQ13 SB_DQ12 SB_CKE2
F7 F5
M_A_DQ14 SA_DQ13 M_B_DQ14 SB_DQ13
G8 SA_DQ14 F2 SB_DQ14
M_A_DQ15 G7 M_B_DQ15 G2
M_A_DQ16 SA_DQ15 M_B_DQ16 SB_DQ15
K4 AB3 J7 AA1
M_A_DQ17 SA_DQ16 SA_CK3 M_B_DQ17 SB_DQ16 SB_CK3
K5 AA3 J8 AB1
C M_A_DQ18 SA_DQ17 SA_CLK#3 M_B_DQ18 SB_DQ17 SB_CLK#3 C
K1 SA_DQ18 SA_CKE3 W10 K10 SB_DQ18 SB_CKE3 T10
M_A_DQ19 J1 M_B_DQ19 K9
M_A_DQ20 SA_DQ19 M_B_DQ20 SB_DQ19
J5 J9
M_A_DQ21 SA_DQ20 M_B_DQ21 SB_DQ20
J4 SA_DQ21 J10 SB_DQ21
M_A_DQ22 J2 AK3 M_B_DQ22 K8 AD3
M_A_DQ23 SA_DQ22 SA_CS#0 M_A_DIM0_CS#0 14 M_B_DQ23 SB_DQ22 SB_CS#0 M_B_DIM0_CS#0 15
K2 AL3 K7 AE3
M_A_DQ24 SA_DQ23 SA_CS#1 M_A_DIM0_CS#1 14 M_B_DQ24 SB_DQ23 SB_CS#1 M_B_DIM0_CS#1 15
M8 SA_DQ24 SA_CS#2 AG1 M5 SB_DQ24 SB_CS#2 AD6
M_A_DQ25 N10 AH1 M_B_DQ25 N4 AE6
M_A_DQ26 SA_DQ25 SA_CS#3 M_B_DQ26 SB_DQ25 SB_CS#3
N8 SA_DQ26 N2 SB_DQ26
M_A_DQ27 N7 M_B_DQ27 N1
M_A_DQ28 SA_DQ27 M_B_DQ28 SB_DQ27
M10 SA_DQ28 M4 SB_DQ28
M_A_DQ29 M9 AH3 M_B_DQ29 N5 AE4
SA_DQ29 SA_ODT0 M_A_DIM0_ODT0 14 SB_DQ29 SB_ODT0 M_B_DIM0_ODT0 15

DDR SYSTEM MEMORY B


M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4
DDR SYSTEM MEMORY A

M_A_DQ31 SA_DQ30 SA_ODT1 M_A_DIM0_ODT1 14 M_B_DQ31 SB_DQ30 SB_ODT1 M_B_DIM0_ODT1 15


M7 AG2 M1 AD5
M_A_DQ32 SA_DQ31 SA_ODT2 M_B_DQ32 SB_DQ31 SB_ODT2
AG6 AH2 AM5 AE5
M_A_DQ33 SA_DQ32 SA_ODT3 M_B_DQ33 SB_DQ32 SB_ODT3
AG5 AM6
M_A_DQ34 SA_DQ33 M_B_DQ34 SB_DQ33
AK6 AR3
M_A_DQ35 SA_DQ34 M_B_DQ35 SB_DQ34
AK5 AP3
M_A_DQ36 SA_DQ35 M_B_DQ36 SB_DQ35
AH5 M_A_DQS#[7:0] 14 AN3 M_B_DQS#[7:0] 15
M_A_DQ37 SA_DQ36 M_A_DQS#0 M_B_DQ37 SB_DQ36 M_B_DQS#0
AH6 SA_DQ37 SA_DQS#0 C4 AN2 SB_DQ37 SB_DQS#0 D7
M_A_DQ38 AJ5 G6 M_A_DQS#1 M_B_DQ38 AN1 F3 M_B_DQS#1
M_A_DQ39 SA_DQ38 SA_DQS#1 M_A_DQS#2 M_B_DQ39 SB_DQ38 SB_DQS#1 M_B_DQS#2
AJ6 J3 AP2 K6
M_A_DQ40 SA_DQ39 SA_DQS#2 M_A_DQS#3 M_B_DQ40 SB_DQ39 SB_DQS#2 M_B_DQS#3
AJ8 M6 AP5 N3
M_A_DQ41 SA_DQ40 SA_DQS#3 M_A_DQS#4 M_B_DQ41 SB_DQ40 SB_DQS#3 M_B_DQS#4
AK8 AL6 AN9 AN5
M_A_DQ42 SA_DQ41 SA_DQS#4 M_A_DQS#5 M_B_DQ42 SB_DQ41 SB_DQS#4 M_B_DQS#5
AJ9 AM8 AT5 AP9
M_A_DQ43 SA_DQ42 SA_DQS#5 M_A_DQS#6 M_B_DQ43 SB_DQ42 SB_DQS#5 M_B_DQS#6
AK9 AR12 AT6 AK12
M_A_DQ44 SA_DQ43 SA_DQS#6 M_A_DQS#7 M_B_DQ44 SB_DQ43 SB_DQS#6 M_B_DQS#7
AH8 SA_DQ44 SA_DQS#7 AM15 AP6 SB_DQ44 SB_DQS#7 AP15
M_A_DQ45 AH9 M_B_DQ45 AN8
M_A_DQ46 SA_DQ45 M_B_DQ46 SB_DQ45
AL9 AR6
M_A_DQ47 SA_DQ46 M_B_DQ47 SB_DQ46
AL8 AR5
M_A_DQ48 SA_DQ47 M_B_DQ48 SB_DQ47
AP11 M_A_DQS[7:0] 14 AR9 M_B_DQS[7:0] 15
M_A_DQ49 SA_DQ48 M_A_DQS0 M_B_DQ49 SB_DQ48 M_B_DQS0
AN11 D4 AJ11 C7
B M_A_DQ50 SA_DQ49 SA_DQS0 M_A_DQS1 M_B_DQ50 SB_DQ49 SB_DQS0 M_B_DQS1 B
AL12 SA_DQ50 SA_DQS1 F6 AT8 SB_DQ50 SB_DQS1 G3
M_A_DQ51 AM12 K3 M_A_DQS2 M_B_DQ51 AT9 J6 M_B_DQS2
M_A_DQ52 SA_DQ51 SA_DQS2 M_A_DQS3 M_B_DQ52 SB_DQ51 SB_DQS2 M_B_DQS3
AM11 N6 AH11 M3
M_A_DQ53 SA_DQ52 SA_DQS3 M_A_DQS4 M_B_DQ53 SB_DQ52 SB_DQS3 M_B_DQS4
AL11 SA_DQ53 SA_DQS4 AL5 AR8 SB_DQ53 SB_DQS4 AN6
M_A_DQ54 AP12 AM9 M_A_DQS5 M_B_DQ54 AJ12 AP8 M_B_DQS5
M_A_DQ55 SA_DQ54 SA_DQS5 M_A_DQS6 M_B_DQ55 SB_DQ54 SB_DQS5 M_B_DQS6
AN12 AR11 AH12 AK11
M_A_DQ56 SA_DQ55 SA_DQS6 M_A_DQS7 M_B_DQ56 SB_DQ55 SB_DQS6 M_B_DQS7
AJ14 AM14 AT11 AP14
M_A_DQ57 SA_DQ56 SA_DQS7 M_B_DQ57 SB_DQ56 SB_DQS7
AH14 AN14
M_A_DQ58 SA_DQ57 M_B_DQ58 SB_DQ57
AL15 AR14
M_A_DQ59 SA_DQ58 M_B_DQ59 SB_DQ58
AK15 SA_DQ59 AT14 SB_DQ59
M_A_DQ60 AL14 M_B_DQ60 AT12
M_A_DQ61 SA_DQ60 M_A_A0 M_A_A[15:0] 14 M_B_DQ61 SB_DQ60 M_B_A0 M_B_A[15:0] 15
AK14 AD10 AN15 AA8
M_A_DQ62 SA_DQ61 SA_MA0 M_A_A1 M_B_DQ62 SB_DQ61 SB_MA0 M_B_A1
AJ15 SA_DQ62 SA_MA1 W1 AR15 SB_DQ62 SB_MA1 T7
M_A_DQ63 AH15 W2 M_A_A2 M_B_DQ63 AT15 R7 M_B_A2
SA_DQ63 SA_MA2 M_A_A3 SB_DQ63 SB_MA2 M_B_A3
SA_MA3 W7 SB_MA3 T6
V3 M_A_A4 T2 M_B_A4
SA_MA4 M_A_A5 SB_MA4 M_B_A5
V2 T4
SA_MA5 M_A_A6 SB_MA5 M_B_A6
W3 T3
SA_MA6 M_A_A7 SB_MA6 M_B_A7
AE10 W6 AA9 R2
14 M_A_BS0 SA_BS0 SA_MA7 M_A_A8 15 M_B_BS0 SB_BS0 SB_MA7 M_B_A8
AF10 V1 AA7 T5
14 M_A_BS1 SA_BS1 SA_MA8 M_A_A9 15 M_B_BS1 SB_BS1 SB_MA8 M_B_A9
V6 W5 R6 R3
14 M_A_BS2 SA_BS2 SA_MA9 M_A_A10 15 M_B_BS2 SB_BS2 SB_MA9 M_B_A10
SA_MA10 AD8 SB_MA10 AB7
V4 M_A_A11 R1 M_B_A11
SA_MA11 M_A_A12 SB_MA11 M_B_A12
SA_MA12 W4 SB_MA12 T1
AE8 AF8 M_A_A13 AA10 AB10 M_B_A13
14 M_A_CAS# SA_CAS# SA_MA13 M_A_A14 15 M_B_CAS# SB_CAS# SB_MA13 M_B_A14
AD9 V5 AB8 R5
14 M_A_RAS# SA_RAS# SA_MA14 M_A_A15 15 M_B_RAS# SB_RAS# SB_MA14 M_B_A15
14 M_A_WE# AF9 SA_WE# SA_MA15 V7 15 M_B_WE# AB9 SB_WE# SB_MA15 R4

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(3/7): DDR3
Size Document Number Rev
Custom 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 6 of 103
5 4 3 2 1
5 4 3 2 1

CPU(4/7)
CPU1F POWER 6 OF 9 IVY BRIDGE PROCESSOR (POWER)
8.5A
IVY-BRIDGE

53A PROCESSOR UNCORE POWER 1D05V_S0

PROCESSOR CORE VCC_CORE

D POWER AG35 VCC1


D
AG34 VCC2 VCCIO1 AH13
AG33 VCC3 VCCIO2 AH10
AG32 AG10
VCC4 VCCIO3
AG31 AC10
VCC5 VCCIO4 C729 C730 C731 C732 C715 C716 C717 C718 C733 C734 C719 C720
AG30 VCC6 VCCIO5 Y10

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
C713 C722 C727 C736 C714 AG29 U10
VCC7 VCCIO6
1

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC10U10V5KX-2GP
AG28 VCC8 VCCIO7 P10

SC10U6D3V5KX-1GP
AG27 L10

2
VCC9 VCCIO8
AG26 J14
2

2
VCC10 VCCIO9
AF35 VCC11 VCCIO10 J13
AF34 J12
Place Bottom AF33
AF32
VCC12
VCC13
VCC14
VCCIO11
VCCIO12
VCCIO13
J11
H14
AF31 H12
VCC15 VCCIO14
AF30 H11
VCC16 VCCIO15
AF29 VCC17 VCCIO16 G14
AF28 G13
VCC18 VCCIO17

PEG AND DDR


C735 C721 C726 C728 C723 AF27 G12
VCC19 VCCIO18
1

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP
AF26 F14
VCC20 VCCIO19 C725 C737 C705 C724
AD35 F13
VCC21 VCCIO20

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
AD34 F12
2

2
VCC22 VCCIO21
AD33 VCC23 VCCIO22 F11 DY DY DY DY
AD32 E14

2
VCC24 VCCIO23
AD31 E12
VCC25 VCCIO24
AD30 VCC26
AD29 E11
VCC27 VCCIO25
AD28 D14
VCC28 VCCIO26
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
AC35 D11
VCC31 VCCIO29
AC34 C14
C VCC32 VCCIO30 C
AC33 VCC33 VCCIO31 C13
AC32 C12
VCC34 VCCIO32
AC31 C11
VCC35 VCCIO33
AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
AC28 A14
VCC38 VCCIO36
AC27 VCC39 VCCIO37 A13
AC26 A12
VCC40 VCCIO38
AA35 VCC41 VCCIO39 A11
AA34
Place Top C742 C701 C741 C703 C709 AA33
VCC42
VCC43 VCCIO40 J23
1

1
SC22U6D3V5MX-2GP

SC10U10V5KX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

AA32
VCC44
AA31 VCC45
AA30
2

VCC46
AA29
VCC47 1D05V_S0
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
Y34
Y33
VCC51
VCC52 CORE SUPPLY
VCC53

2
Y32
C738 C702 C706 C707 C708 VCC54 R709
Y31
VCC55
1

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

Y30 75R2F-2-GP
VCC56
DY Y29
VCC57
Y28
2

1
VCC58
Y27 VCC59
Y26
VCC60
V35
VCC61
SVID
V34 AJ29 VIDALERT# R705 1 43R2J-GP
2
VCC62 VIDALERT# VR_SVID_ALERT# 42
V33 AJ30
VCC63 VIDSCLK H_CPU_SVIDCLK 42
V32 AJ28 H_CPU_SVIDDAT 42
B VCC64 VIDSOUT B
V31 VCC65
V30 VCC66
C740 C739 C704 C712 C710 C711 V29 1 2 1D05V_S0
VCC67
1

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

V28 R703 130R2F-1-GP


VCC68
DY DY DY V27
VCC69
V26
2

VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32 VCC74
U31 VCC75
U30
VCC76
U29 VCC77
U28
VCC78
U27 VCC79
Power 78.22610.51L U26
VCC80 VCC_CORE
R35
VCC81
R34
C746 C745 C744 C743 C752 C751 VCC82
R33
VCC83
1

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

R32
VCC84
DY DY DY R31
VCC85
SC10U6D3V5KX-1GP

R30 R706
2

VCC86
R29 100R2F-L1-GP-U
VCC87
SENSE LINES

R28

2
VCC88 VCC_SENSE_R R702 2
R27 AJ35 1
VCC89 VCC_SENSE VSS_SENSE_R R701 2 0R0402-PAD VCCSENSE 42
R26 AJ34 1
VCC90 VSS_SENSE 0R0402-PAD VSSSENSE 42
P35 VCC91
P34
VCC92

1
P33
VCC93
P32 B10
VCC94 VCCIO_SENSE VTT_SENSE 45 R704
P31 A10
VCC95 VSS_SENSE_VCCIO VSSP_SENSE 45
P30 VCC96 100R2F-L1-GP-U
A A
P29

2
VCC97
P28 VCC98 <Core Design>
1

C748 C749 C747 P27 VCC99


1

1D05V_S0
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

P26 R707 R708


VCC100
10R2F-L-GP
10R2F-L-GP

DY DY C750DY Differential Sense feedback


Wistron Corporation
SC10U6D3V5KX-1GP
2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


2

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(4/7): PWR
Size Document Number Rev
Custom 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 7 of 103
5 4 3 2 1
5 4 3 2 1

CPU(5/7) M3 - Processor Generated SO-DIMM VREF_DQ


IVY BRIDGE PROCESSOR (GRAPHICS POWER) DDR_VREF_S3

33A 84.05067.031

1
VCC_GFXCORE
470U*2 22U*6 POWER R808
0R2J-2-GP
2ND = 84.00138.H31
3RD = 84.2N702.W31

S
CPU1G 7 OF 9
DY Q802
14 M_VREF_DQ_DIMM0

2
PCH_DDR_RST#
Under Socket and Closed to CPU G DMN5L06K-7-GP

SENSE
LINES
AT24 IVY-BRIDGE AK35 R810
VAXG1 VAXG_SENSE VCC_AXG_SENSE 42

1
D D
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE 42 0R2J-2-GP
AT21 R809
AT20
VAXG3
0R2J-2-GP DY

1
D
VAXG4
AT18
VAXG5 DY
AT17 0R2J-2-GP

2
VAXG6
1

1
C820 C821 C822 C823 C824 C825 AR24 R812 1 2 M_VREF_DQ_DIMM0_R DDR_VREF_S3_B4
VAXG7 M_VREF_DQ_DIMM1_R DDR_VREF_S3_D1
AR23
VAXG8
CAD Note: +V_SM_VREF should 15 M_VREF_DQ_DIMM1 R813 1 2
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
AR21 have 10 mil trace width 0R2J-2-GP
2

2
VAXG9
AR20 VAXG10
AR18 AL1 +V_SM_VREF_CNT 3RD = 84.2N702.W31

D
VAXG11 SM_VREF 2ND = 84.00138.H31
AR17 VAXG12

VREF

2
AP24
VAXG13 B4:VREF_DQ CHA 84.05067.031

1
AP23 D1:VREF_DQ CHB C801 C802 R814
VAXG14
AP21
VAXG15 DY DY 5,18 PCH_DDR_RST# G 0R2J-2-GP
DMN5L06K-7-GP

SCD1U16V2ZY-2GP

SC2D2U10V3ZY-1GP
AP20 B4 DDR_VREF_S3_B4
DY

2
VAXG16 SA_DIMM_VREFDQ DDR_VREF_S3_D1 Q803
AP18 D1

1
VAXG17 SB_DIMM_VREFDQ
AP17

S
VAXG18

1
AN24
VAXG19 R815 R816
AN23
AN21
VAXG20
VAXG21
1KR2F-3-GP 1KR2F-3-GP 12~16A
AN20
VAXG22 DY DY 1D5V_S0

DDR3 -1.5V RAILS


AN18

2
VAXG23
AN17 VAXG24 33OU*1 10U*6 -1 1221

GRAPHICS
VCC_GFXCORE
22U*6 AM24
AM23
VAXG25 VDDQ1 AF7
AF4 C805 C806 C807
VAXG26 VDDQ2

1
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
AM21 AF1 C803 C804 C808
VAXG27 VDDQ3 TC801
AM20 AC7
VAXG28 VDDQ4

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC10U10V5KX-2GP
ST330U2D5VDM-9GP
Closed to CPU Socket AM18 AC4

2
VAXG29 VDDQ5
AM17 VAXG30 VDDQ6 AC1
AL24 VAXG31 VDDQ7 Y7 DY DY
AL23 Y4 77.23371.13L
VAXG32 VDDQ8 2nd = 79.33719.L01
AL21 Y1
C VAXG33 VDDQ9 C
AL20 VAXG34 VDDQ10 U7
AL18 U4
VAXG35 VDDQ11
1

C826 C827 C828 C829 C830 C831 AL17 U1


VAXG36 VDDQ12
DY DY AK24 VAXG37 VDDQ13 P7
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

AK23 P4
2

VAXG38 VDDQ14
AK21 P1
VAXG39 VDDQ15
AK20 VAXG40
AK18
VAXG41
AK17
AJ24
VAXG42
VAXG43
6A
AJ23 VAXG44
AJ21 0D85V_S0
VAXG45
AJ20 VAXG46
AJ18
Power 78.22610.51L VAXG47
AJ17 M27

SA RAIL
VAXG48 VCCSA1
AH24 M26
VAXG49 VCCSA2 C813 C814 C815
AH23 L26
VAXG50 VCCSA3
1

1
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
C837 C836 C835 C834 C833 C832 AH21 J26
VAXG51 VCCSA4
AH20 J25
VAXG52 VCCSA5 0D85V_S0
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

DY AH18 J24
2

2
VAXG53 VCCSA6
SC10U6D3V5KX-1GP

AH17 H26
VAXG54 VCCSA7
H25
1.5A VCCSA8

1
DY R801
100R2J-2-GP
1D8V_S0
1.8V RAIL

2
H23 VCCUSA_SENSE
VCCSA_SENSE VCCUSA_SENSE 48

B6
VCCPLL1
MISC

A6 C22 H_FC_C22
B C819 C816 C817 C818 VCCPLL2 VCCSA_VID0 VCCSA_SEL H_FC_C22 48 B
A2 VCCPLL3 VCCSA_VID1 C24
VCCSA_SEL 48
1

3
4
RN801
2

A19 H_VCCP_SEL SRN1KJ-11-GP-U


VCCIO_SEL
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

2
1
SNB: No Connect
IVB: VSS R817
0R2J-2-GP
2 1 H_SNB_IVB#_PWRCTRL 1 TP801 TPAD14-OP-GP
DY
H_VCCP_SEL Voltage

2
1 1.05V R818
DY 0R2J-2-GP

0 1.0V
1

S3 Power Reduction Circuit Processor VREF_DQ Implementation


DDR_VREF_S3
R811DY
R807
1 2
1 2 0R2J-2-GP
A A
0R2J-2-GP <Core Design>
Q801
DMN5L06K-7-GP
R805
14 M_VREF_DQ_DIMM0
1 2 +V_SM_VREF D S +V_SM_VREF_CNT Wistron Corporation
DY 84.05067.031 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
0R2J-2-GP Taipei Hsien 221, Taiwan, R.O.C.
1

2ND = 84.00138.H31
3RD = 84.2N702.W31 R803 Title
G

R802DY
100KR2J-1-GP
CPU(5/7): GFX/PWR
1 2 Size Document Number Rev
2

5,18 PCH_DDR_RST# Custom


0R2J-2-GP
Colossus 1
19,27,36,46,47,92 PM_SLP_S3# Date: Wednesday, January 04, 2012 Sheet 8 of 103
5 4 3 2 1
5 4 3 2 1

CPU(6/7)
IVY BRIDGE PROCESSOR (GND)
CPU1H 8 OF 9 CPU1I 9 OF 9
D D
AT35 VSS1 VSS81 AJ22
AT32 VSS2 VSS82 AJ19
AT29 IVY-BRIDGE AJ16 T35 IVY-BRIDGE F22
VSS3 VSS83 VSS161 VSS234
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
AT22 VSS6 VSS86 AJ7 T32 VSS164 VSS237 E27
AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24
AT16 VSS8 VSS88 AJ3 T30 VSS166 VSS239 E21
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18
AT10 VSS10 VSS90 AJ1 T28 VSS168 VSS241 E15
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6
AR16 VSS17 VSS98 AH25 P3 VSS175 VSS248 E5
AR13 VSS18 VSS99 AH22 P2 VSS176 VSS249 E4
AR10 VSS19 VSS100 AH19 N35 VSS177 VSS250 E3
AR7 VSS20 VSS101 AH16 N34 VSS178 VSS251 E2
AR4 VSS21 VSS102 AH7 N33 VSS179 VSS252 E1
AR2 VSS22 VSS103 AH4 N32 VSS180 VSS253 D35
AP34 VSS23 VSS104 AG9 N31 VSS181 VSS254 D32
AP31 VSS24 VSS105 AG8 N30 VSS182 VSS255 D29
AP28 VSS25 VSS106 AG4 N29 VSS183 VSS256 D26
AP25 VSS26 VSS107 AF6 N28 VSS184 VSS257 D20
AP22 VSS27 VSS108 AF5 N27 VSS185 VSS258 D17
AP19 VSS28 VSS109 AF3 N26 VSS186 VSS259 C34
C AP16 AF2 M34 C31 C
VSS29 VSS110 VSS187 VSS260
AP13 VSS30 VSS111 AE35 L33 VSS188 VSS261 C28
AP10 VSS31 VSS112 AE34 L30 VSS189 VSS262 C27
AP7 VSS32 VSS113 AE33 L27 VSS190 VSS263 C25
AP4 VSS33 VSS114 AE32 L9 VSS191 VSS264 C23
AP1 VSS34 VSS115 AE31 L8 VSS192 VSS265 C10
AN30 VSS35 VSS116 AE30 L6 VSS193 VSS266 C1
AN27 VSS36 VSS117 AE29 L5 VSS194 VSS267 B22
AN25 AE28 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 VSS40 VSS121 AE9 L1 VSS198 VSS271 B13
AN13 VSS41 VSS122 AD7 K35 VSS199 VSS272 B11
AN10 VSS42 VSS123 AC9 K32 VSS200 VSS273 B9
AN7 VSS43 VSS124 AC8 K29 VSS201 VSS274 B8
AN4 VSS44 VSS125 AC6 K26 VSS202 VSS275 B7
AM29 VSS45 VSS126 AC5 J34 VSS203 VSS276 B5
AM25 VSS46 VSS127 AC3 J31 VSS204 VSS277 B3
AM22 VSS47 VSS128 AC2 H33 VSS205 VSS278 B2
AM19 VSS48 VSS129 AB35 H30 VSS206 VSS279 A35
AM16 VSS49 VSS130 AB34 H27 VSS207 VSS280 A32
AM13 VSS50 VSS131 AB33 H24 VSS208 VSS281 A29
AM10 VSS51 VSS132 AB32 H21 VSS209 VSS282 A26
AM7 VSS52 VSS133 AB31 H18 VSS210 VSS283 A23
AM4 VSS53 VSS134 AB30 H15 VSS211 VSS284 A20
AM3 VSS54 VSS135 AB29 H13 VSS212 VSS285 A3
AM2 VSS55 VSS136 AB28 H10 VSS213
AM1 VSS56 VSS137 AB27 H9 VSS214
AL34 VSS57 VSS138 AB26 H8 VSS215
B B
AL31 VSS58 VSS139 Y9 H7 VSS216
AL28 VSS59 VSS140 Y8 H6 VSS217
AL25 VSS60 VSS141 Y6 H5 VSS218
AL22 VSS61 VSS142 Y5 H4 VSS219
AL19 VSS62 VSS143 Y3 H3 VSS220
AL16 VSS63 VSS144 Y2 H2 VSS221
AL13 VSS64 VSS145 W35 H1 VSS222
AL10 VSS65 VSS146 W34 G35 VSS223
AL7 VSS66 VSS147 W33 G32 VSS224
AL4 VSS67 VSS148 W32 G29 VSS225
AL2 VSS68 VSS149 W31 G26 VSS226
AK33 VSS69 VSS150 W30 G23 VSS227
AK30 VSS70 VSS151 W29 G20 VSS228
AK27 VSS71 VSS152 W28 G17 VSS229
AK25 VSS72 VSS153 W27 G11 VSS230
AK22 VSS73 VSS154 W26 F34 VSS231
AK19 VSS74 VSS155 U9 F31 VSS232
AK16 VSS75 VSS156 U8 F29 VSS233
AK13 VSS76 VSS157 U6
AK10 VSS77 VSS158 U5
AK7 VSS78 VSS159 U3
AK4 VSS79 VSS160 U2
AJ25 VSS80

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (6/7):GND
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 9 of 103
5 4 3 2 1
5 4 3 2 1

CPU(7/7)
D
IVY BRIDGE PROCESSOR (RESERVED) CFG4
D

Display Port Presence Strap 0:Enable eDP

1
DY R1006
1KR2J-1-GP CFG4 1:(Default) Disabled; No Physical Display Port
attached to Embedded Display Port

2
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
CPU1E 5 OF 9

IVY-BRIDGE
CFG7
AH27 VCC_DIE_SENSE 1 TP1004 TPAD14-OP-GP
VCC_DIE_SENSE

1
AK28 CFG0 VSS_DIE_SENSE AH26
AK29 DY R1009
CFG2 CFG1
AL26 CFG2 1KR2J-1-GP
AL27 CFG3
CFG4 AK26 L7

2
CFG5 CFG4 RSVD#L7
AL29 CFG5 RSVD#AG7 AG7
CFG6 AL30 AE7
CFG7 CFG6 RSVD#AE7
AM31 CFG7 RSVD#AK2 AK2
AM32 CFG8

CFG
AM30 CFG9 RSVD#W8 W8
AM28 CFG10
AM26 CFG11 PEG DEFER TRAINING
C AN28 AT26 C
CFG12 RSVD#AT26
AN31 CFG13 RSVD#AM33 AM33
AN26 CFG14 RSVD#AJ27 AJ27 CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion
AM27 CFG15 0: PEG Wait for BIOS for training
AK31 CFG16
AN29 CFG17

VCC_GFXCORE T8
RSVD#T8
VCC_CORE 49D9R2F-GP
DY R1001 VAXG_VAL_SENSE RSVD#J16 J16

49D9R2F-GP
1 DY 2
R1002 VSSAXG_VAL_SENSE
AJ31 VAXG_VAL_SENSE RSVD#H16 H16
1 2 AH31 VSSAXG_VAL_SENSE RSVD#G16 G16
49D9R2F-GP 1 DY 2 R1003 VCC_VAL_SENSE AJ33
49D9R2F-GP R1004 VSS_VAL_SENSE VCC_VAL_SENSE
1 DY 2 AH33 VSS_VAL_SENSE

AJ26 RSVD#AJ26 RSVD_NCTF#AR35 AR35

RESERVED
RSVD_NCTF#AT34 AT34
AT33 CFG2
RSVD_NCTF#AT33
RSVD_NCTF#AP35 AP35 PEG Static Lane Reversal

1
RSVD_NCTF#AR34 AR34
R1005 1:(Default) Normal Operation; Lane #
DY 1KR2J-1-GP CFG2 definition matches socket pin map definition
F25 RSVD#F25
F24 0:Lane Reversed

2
RSVD#F24
F23 RSVD#F23
D24 RSVD#D24 RSVD_NCTF#B34 B34
G25 RSVD#G25 RSVD_NCTF#A33 A33
G24 RSVD#G24 RSVD_NCTF#A34 A34
B B
E23 RSVD#E23 RSVD_NCTF#B35 B35
D23 C35 CFG6 CFG5
RSVD#D23 RSVD_NCTF#C35
C30 RSVD#C30

1
A31 RSVD#A31
B30 DY R1007 R1008
RSVD#B30
B29 RSVD#B29 1KR2J-1-GP 1KR2J-1-GP
D30 RSVD#D30 RSVD#AJ32 AJ32
B31 AK32

2
RSVD#B31 RSVD#AK32
A30 RSVD#A30
C29 RSVD#C29

BCLK_ITP AN35
J20 RSVD#J20 BCLK_ITP# AM35
B18 RSVD#B18
PCIE Port Bifurcation Straps

J15 RSVD#J15 RSVD_NCTF#AT2 AT2 CFG[6:5] 11: (Default) x16 - Device 1 functions 1 and 2 disabled
RSVD_NCTF#AT1 AT1 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
RSVD_NCTF#AR1 AR1
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(7/7): CFG/RSVD/DDR3_VRE
Size Document Number Rev
A3 1
Colossus
Date: Tuesday, December 27, 2011 Sheet 10 of 103
5 4 3 2 1
5 4 3 2 1

D D

(Blanking)

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_XDP
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 11 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 12 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

AOAC
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 13 of 103
5 4 3 2 1
5 4 3 2 1

DIMM1 REVERSED M_A_DQS#[7:0]

M_A_DQS[7:0] 6
6

DIM1 M_A_A[15:0] 6
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 A1 NP2 NP2
M_A_A2 96
M_A_A3 A2
95 A3 RAS# 110 M_A_RAS# 6
M_A_A4 92 113 M_A_WE# 6
M_A_A5 A4 WE#
91 A5 CAS# 115 M_A_CAS# 6
M_A_A6 90
M_A_A7 A6
86 A7 CS0# 114 M_A_DIM0_CS#0 6
D M_A_A8 89 121 Note: D
A8 CS1# M_A_DIM0_CS#1 6
M_A_A9 85
M_A_A10 107
A9
73 M_A_DIM0_CKE0 6 SA0_DIM0 If SA0 DIM0 = 0, SA1_DIM0 = 0
M_A_A11 A10/AP CKE0
M_A_A12
84 A11 CKE1 74 M_A_DIM0_CKE1 6
SA1_DIM0
SO-DIMMA SPD Address is 0xA0
83 A12
M_A_A13 119 101 M_A_DIM0_CLK_DDR0 6
SO-DIMMA TS Address is 0x30
A13 CK0

4
3
M_A_A14 80 103 M_A_DIM0_CLK_DDR#0 6
M_A_A15 A14 CK0# RN1401
78 A15
6 M_A_BS2 79 A16/BA2 CK1 102 M_A_DIM0_CLK_DDR1 6 SRN10KJ-5-GP If SA0 DIM0 = 1, SA1_DIM0 = 0
CK1# 104 M_A_DIM0_CLK_DDR#1 6 SO-DIMMA SPD Address is 0xA2
109 BA0
6 M_A_BS0 SO-DIMMA TS Address is 0x32
108 11

1
2
6 M_A_BS1 BA1 DM0
6 M_A_DQ[63:0] DM1 28
M_A_DQ0 5 46
M_A_DQ1 DQ0 DM2
7 DQ1 DM3 63
M_A_DQ2 15 136
M_A_DQ3 DQ2 DM4
17 DQ3 DM5 153
M_A_DQ4 4 170
M_A_DQ5 DQ4 DM6
6 DQ5 DM7 187
M_A_DQ6 16
M_A_DQ7 DQ6 SODIMM1_1_SMB_DATA_R R1409 1
18 DQ7 SDA 200 2 0R0402-PAD-1-GP PCH_SMBDATA 15,18,103
M_A_DQ8 21 202 SODIMM1_1_SMB_CLK_R R1401 1 2 0R0402-PAD-1-GP
DQ8 SCL PCH_SMBCLK 15,18,103
M_A_DQ9 23
M_A_DQ10 DQ9
33 DQ10 EVENT# 198 TS#_DIMM0_1 15
M_A_DQ11 35
M_A_DQ12 DQ11
22 DQ12 VDDSPD 199 3D3V_S0
M_A_DQ13 24 3D3V_S0
DQ13

1
M_A_DQ14 34 197 SA0_DIM0 C1401 C1402
M_A_DQ15 DQ14 SA0 SA1_DIM0
36 DQ15 SA1 201

SCD1U16V2ZY-2GP

SC2D2U6D3V3KX-GP
M_A_DQ16 39

2
DQ16

1
M_A_DQ17 41 77
M_A_DQ18 DQ17 NC#77 R1402
51 DQ18 NC#122 122
M_A_DQ19 53 125 1D5V_S3 10KR2J-3-GP
M_A_DQ20 DQ19 NC#125/TEST
40
C
M_A_DQ21 42
DQ20
75 Thermal EVENT C

2
M_A_DQ22 DQ21 VDD
50 DQ22 VDD 76 DY
M_A_DQ23 52 81
M_A_DQ24 DQ23 VDD
57 DQ24 VDD 82
M_A_DQ25 59 87
M_A_DQ26 DQ25 VDD TS#_DIMM0_1
67 DQ26 VDD 88
M_A_DQ27 69 93
1D5V_S3 M_A_DQ28 DQ27 VDD
56 DQ28 VDD 94
M_A_DQ29 58 99
M_A_DQ30 DQ29 VDD
M_A_DQ31
68 DQ30 VDD 100 SODIMM A DECOUPLING
70 DQ31 VDD 105
1

R1403 M_A_DQ32 129 106 1D5V_S3


1KR2F-3-GP M_A_DQ33 DQ32 VDD
131 DQ33 VDD 111
M_A_DQ34 141 112
M_A_DQ35 DQ34 VDD
143 DQ35 VDD 117
M_A_DQ36 130 118
2

M_VREF_CA_DIMM0 M_A_DQ37 DQ36 VDD


132 DQ37 VDD 123
M_A_DQ38 140 124 C1407 C1408 C1409 C1410 C1411 C1412
DQ38 VDD
1

1
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
M_A_DQ39 142 DY DY DY
DQ39
1

SC10U10V5KX-2GP
R1405 C1403 C1404 M_A_DQ40 147 2 DY
1KR2F-3-GP SCD1U10V2KX-4GP SC2D2U6D3V3KX-GP M_A_DQ41 DQ40 VSS
149 3
2

2
M_A_DQ42 DQ41 VSS
157 DQ42 VSS 8
M_A_DQ43 159 9
M_A_DQ44 DQ43 VSS
DY 146 13
2

M_A_DQ45 DQ44 VSS


148 DQ45 VSS 14
M_A_DQ46 158 19
M_A_DQ47 DQ46 VSS
160 DQ47 VSS 20
M_A_DQ48 163 25
1D5V_S3 M_A_DQ49 DQ48 VSS
165 DQ49 VSS 26
M_A_DQ50 175 31
DQ50 VSS

1
M_A_DQ51 177 32 C1413 C1414 C1415 C1416 C1417 C1418
M_A_DQ52 DQ51 VSS C1419
164 DQ52 VSS 37
1

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
B R1406 M_A_DQ53 166 38 SC1U10V2KX-1GP B

2
1KR2F-3-GP M_A_DQ54 DQ53 VSS
M_A_DQ55
174 DQ54 VSS 43 DY DY DY DY
M_A_DQ56
176 DQ55 VSS 44 Layout Note:
181 DQ56 VSS 48
M_A_DQ57 183 49 Place these Caps near
2

M_A_DQ58 DQ57 VSS


M_VREF_DQ_DIMM0 M_A_DQ59
191 DQ58 VSS 54 SO-DIMMA.
193 DQ59 VSS 55
M_A_DQ60 180 60
DQ60 VSS
1

R1407 M_A_DQ61 182 61


1KR2F-3-GP C1405 C1406 M_A_DQ62 DQ61 VSS
192 DQ62 VSS 65
SCD1U10V2KX-4GP SC2D2U10V3ZY-1GP M_A_DQ63 194 66
2

DQ63 VSS
VSS 71
M_A_DQS#0 10 72
2

M_A_DQS#1 DQS0# VSS


DY M_A_DQS#2
27 DQS1# VSS 127
45 DQS2# VSS 128
M_A_DQS#3 62 133
M_A_DQS#4 DQS3# VSS
135 DQS4# VSS 134
M_A_DQS#5 152 138
M_A_DQS#6 DQS5# VSS
169 DQS6# VSS 139
M_A_DQS#7 186 144
DQS7# VSS
VSS 145
M_A_DQS0 12 150
M_A_DQS1 DQS0 VSS
29 DQS1 VSS 151
0D75V_S0 M_A_DQS2
Place these caps M_A_DQS3
47 DQS2 VSS 155
64 DQS3 VSS 156
close to VTT1 and M_A_DQS4 137 161
M_A_DQS5 DQS4 VSS
VTT2. M_A_DQS6
154 DQS5 VSS 162
171 DQS6 VSS 167
1

C1420 C1421 C1422 C1423 M_A_DQS7 188 168


DQS7 VSS
VSS 172
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

116 173
2

6 M_A_DIM0_ODT0 ODT0 VSS


6 M_A_DIM0_ODT1
120 ODT1 VSS 178
VSS 179
A M_VREF_CA_DIMM0 126 184 A
VREF_CA VSS
1 VREF_DQ VSS 185
8 M_VREF_DQ_DIMM0
VSS 189 <Core Design>
5,15 DDR3_DRAMRST#
30 RESET# VSS 190
VSS 195
0D75V_S0
1st 661448-307 203
VSS
VTT1 661448-307VSS
196
205 Wistron Corporation
DY DY 2nd 661448-306 204 206 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VTT2 VSS Taipei Hsien 221, Taiwan, R.O.C.
3rd 661448-304
DDR3-204P-86-GP-U Title
010412 Update connetor HP P/N, H=9.2mm 62.10017.U01
hanle control but not change library Size Document Number
DDR3 SO-DIMM1 Rev
2nd = 62.10017.U01 Custom
3rd = 62.10024.H81 Colossus 1
Date: Wednesday, January 04, 2012 Sheet 14 of 103
5 4 3 2 1
5 4 3 2 1

6 M_B_A[15:0]
M_B_A0
M_B_A1
98
97
DIM2

A0 NP1
NP1
NP2
DIMM2 REVERSED
M_B_A2 A1 NP2 3D3V_S0
96
M_B_A3 A2
6 M_B_DQS#[7:0] 95 110 M_B_RAS# 6
M_B_A4 A3 RAS#
92 113 M_B_WE# 6
M_B_A5 A4 WE#
6 M_B_DQS[7:0] 91 115 M_B_CAS# 6
M_B_A6 A5 CAS#
90
M_B_A7 A6
86 114 M_B_DIM0_CS#0 6
M_B_A8 A7 CS0#
89 121 M_B_DIM0_CS#1 6
M_B_A9 A8 CS1#
85
M_B_A10 A9
107 73 M_B_DIM0_CKE0 6
M_B_A11 A10/AP CKE0
84 74 M_B_DIM0_CKE1 6 RN1501
M_B_A12 A11 CKE1 SB1_DIM0
D 83 1 4 D
M_B_A13 A12 SB0_DIM0
119 101 M_B_DIM0_CLK_DDR0 6 2 3
M_B_A14 A13 CK0
80 103 M_B_DIM0_CLK_DDR#0 6
M_B_A15 A14 CK0# SRN10KJ-5-GP
78
A15 Note:
6 M_B_BS2 79 102 M_B_DIM0_CLK_DDR1 6
A16/BA2 CK1
CK1#
104 M_B_DIM0_CLK_DDR#1 6 SO-DIMMB SPD Address is 0xA4
6 M_B_BS0 109 SO-DIMMB TS Address is 0x34
BA0
6 M_B_BS1
108 11
BA1 DM0
6 M_B_DQ[63:0] 28
M_B_DQ0 DM1
5 46
M_B_DQ1 DQ0 DM2
7 63
M_B_DQ2 DQ1 DM3
15 136
M_B_DQ3 DQ2 DM4
17 153
M_B_DQ4 DQ3 DM5
4 170
M_B_DQ5 DQ4 DM6
6 187
M_B_DQ6 DQ5 DM7
16
DQ6 R1504 1
M_B_DQ7 18 200 SODIMM0_1_SMB_DATA_R 2 0R0402-PAD-1-GP PCH_SMBDATA 14,18,103
M_B_DQ8 DQ7 SDA SODIMM0_1_SMB_CLK_R R1505 1
21 202 2 0R0402-PAD-1-GP PCH_SMBCLK 14,18,103
M_B_DQ9 DQ8 SCL
23
M_B_DQ10 DQ9 3D3V_S0
33 198 TS#_DIMM0_1 14
M_B_DQ11 DQ10 EVENT#
35
M_B_DQ12 DQ11
22 199
M_B_DQ13 DQ12 VDDSPD
24

1
M_B_DQ14 DQ13 SB0_DIM0 C1504
M_B_DQ15
34
DQ14 SA0
197
SB1_DIM0
DY C1505
36 201
DQ15 SA1

SCD1U16V2ZY-2GP
M_B_DQ16 39 SC2D2U10V3ZY-1GP

2
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1
51 122
M_B_DQ19 DQ18 NC#2 1D5V_S3
53 125
M_B_DQ20 DQ19 NC#/TEST
40
M_B_DQ21 DQ20
42 75
M_B_DQ22 DQ21 VDD1
50 76
M_B_DQ23 DQ22 VDD2
52 81
M_B_DQ24 DQ23 VDD3
C 57 82 C
M_B_DQ25 DQ24 VDD4
59 87
M_B_DQ26 DQ25 VDD5
67 88
M_B_DQ27 DQ26 VDD6
69 93
M_B_DQ28 DQ27 VDD7
56 94
M_B_DQ29 DQ28 VDD8
58 99
M_B_DQ30 DQ29 VDD9
68 100
M_B_DQ31 DQ30 VDD10
70 105
M_B_DQ32 DQ31 VDD11
129 106
1D5V_S3 M_B_DQ33 DQ32 VDD12
131 111
M_B_DQ34 DQ33 VDD13
141 112
M_B_DQ35 DQ34 VDD14
143 117
M_B_DQ36 DQ35 VDD15
130 118 SODIMM B DECOUPLING
1

R1506 M_B_DQ37 DQ36 VDD16


132 123
1KR2F-3-GP M_B_DQ38 DQ37 VDD17 1D5V_S3
140 124
M_B_DQ39 DQ38 VDD18
142
M_B_DQ40 DQ39
147 2
M_B_DQ41 DQ40 VSS
149 3
2

M_B_DQ42 DQ41 VSS


157 8
M_VREF_CA_DIMM1 M_B_DQ43 DQ42 VSS
159 9
M_B_DQ44 DQ43 VSS TC1501 C1508 C1509 C1510 C1511 C1512 C1513
146 13
1

1
DQ44 VSS

ST330U2D5VDM-9GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
M_B_DQ45 148 14 DY DY DY
1

DQ45 VSS

SC10U10V5KX-2GP
R1507 C1506 C1507 M_B_DQ46 158 19
1KR2F-3-GP SCD1U10V2KX-4GP SC2D2U6D3V3KX-GP M_B_DQ47 DQ46 VSS
160 20
2

2
M_B_DQ48 DQ47 VSS
163 25
M_B_DQ49 DQ48 VSS 77.23371.13L
165 26
M_B_DQ50 DQ49 VSS 2nd = 79.33719.L01
DY 175 31
2

M_B_DQ51 DQ50 VSS


177 32
M_B_DQ52 DQ51 VSS
164 37
M_B_DQ53 DQ52 VSS
166 38
M_B_DQ54 DQ53 VSS
174 43
M_B_DQ55 DQ54 VSS
176 44
1D5V_S3 M_B_DQ56 DQ55 VSS
181 48

1
M_B_DQ57 DQ56 VSS C1516 C1517 C1518 C1519 C1521 C1520 C1522
B
M_B_DQ58
183
DQ57 VSS
49 Layout Note: B
191 54
DQ58 VSS Place these Caps near

SC1U10V2KX-1GP
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
M_B_DQ59 193 55

2
1

DQ59 VSS

SCD1U10V2KX-5GP
R1508 M_B_DQ60 180 60
1KR2F-3-GP M_B_DQ61 DQ60 VSS SO-DIMMB.
182 61
M_B_DQ62 DQ61 VSS
192 65
M_B_DQ63 DQ62 VSS
194 66
DQ63 VSS
71
2

M_VREF_DQ_DIMM1 M_B_DQS#0 VSS


10 72
M_B_DQS#1 DQS0# VSS
27 127
1

M_B_DQS#2 DQS1# VSS


45 128
1

R1509 C1514 C1515 M_B_DQS#3 DQS2# VSS


1KR2F-3-GP SCD1U10V2KX-4GP SC2D2U10V3ZY-1GP M_B_DQS#4
62
DQS3# VSS
133 DY DY DY DY
135 134
2

M_B_DQS#5 DQS4# VSS


152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
DY 186 144
2

DQS7# VSS
145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
M_B_DQS2 DQS1 VSS
47 155
M_B_DQS3 DQS2 VSS
64 156
M_B_DQS4 DQS3 VSS
137 161
M_B_DQS5 DQS4 VSS
154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
6 M_B_DIM0_ODT0 116 173
ODT0 VSS
6 M_B_DIM0_ODT1 120 178
ODT1 VSS
179
M_VREF_CA_DIMM1 VSS
126 184
VREF_CA VSS
8 M_VREF_DQ_DIMM1 1 185
VREF_DQ VSS
189
VSS
Place these caps 0D75V_S0 5,14 DDR3_DRAMRST# 30
RESET# VSS
190
A 195 A
close to VTT1 and VSS
196
VSS
VTT2. 203 205 <Core Design>
VTT1 VSS
204
VTT2 661447-301VSS
206

C1523 C1501 C1502 C1503 Wistron Corporation


1

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DDR3-204P-85-GP-U
1st 661447-301 Taipei Hsien 221, Taiwan, R.O.C.
DY DY
2nd 661447-306 62.10017.U21
2

Title
3rd 661447-304 2ND = 62.10017.T91
3rd = 62.10024.I61
Size Document Number
DDR3 SO-DIMM2 Rev
010412 Update connetor HP P/N, H=5.2mm Custom
hanle control but not change library Colossus 1
Date: Wednesday, January 04, 2012 Sheet 15 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 16 of 103
5 4 3 2 1
A B C D E

RTC_X1
RTC_AUX_S5

1
R1705

2
PCH(1/9)
27,71 LPC_AD[0..3]
20KR2J-L2-GP INTVRMEN- Integrated

1
C1701 SUS 1.05V VRM Enable
R1706 SC1U10V2KX-1GP 1 DY 2 PCH_INTVRMEN High - Enable internal VRs

2
1 2 RTC_X2 R1707 330KR2J-L1-GP
10MR2J-L-GP RN1705
PCH1A 1 OF 10 SRN47J-8-GP
RTC_AUX_S5 LPC_AD3_L 1 8 LPC_AD3 27,71
R1708 RTC_X1 A20 C38 LPC_AD0_L LPC_AD2_L 2 7
RTCX1 FWH0/LAD0 LPC_AD2 27,71
4 X1701 1 2 A38 LPC_AD1_L LPC_AD0_L 3 6 4
FWH1/LAD1 LPC_AD0 27,71

LPC
RTC_X2 C20 B37 LPC_AD2_L LPC_AD1_L 4 5
RTCX2 FWH2/LAD2 LPC_AD1 27,71

2
1 4 20KR2J-L2-GP C37 LPC_AD3_L
FWH3/LAD3

1
G1701 RTC_RST# D20 RTCRST#
1

C1704 SRTC_RST# D36 LPC_FRAME#_R 2 R1726 1 33R2J-2-GP


C1702 C1703 SC1U10V2KX-1GP GAP-OPEN FWH4/LFRAME# LPC_FRAME# 27,71
G22

2
SRTCRST#
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP

2 3 E36
2

1
LDRQ0#

RTC
R1709
1 2 1MR2J-1-GP INTRUDER# K22 K36
7pF20PPM RTC_AUX_S5 INTRUDER# LDRQ1#/GPIO23 PCH_GPIO23 1 TP1701 TPAD14-OP-GP
82.30001.661 R1710
1 2 330KR2J-L1-GP PCH_INTVRMEN C17 V5
INTVRMEN SERIRQ INT_SERIRQ 27
RN1701
X-32D768KHZ-34GPU 29 HDA_SDOUT_CODEC 29 HDA_RST#_CODEC 1 8
29 HDA_SYNC_CODEC 2 7 SATA0RXN AM3 SATA_RXN0 56
3 6 HDA_BIT_CLK N34 AM1
29 HDA_BITCLK_CODEC HDA_BCLK SATA0RXP SATA_RXP0 56
2ND = 82.30001.B21 HDD1

SATA 6G
4 5 SATA0TXN AP7 SATA_TXN0 56
HDA_SYNC L34 AP5
SRN33J-7-GP HDA_SYNC SATA0TXP SATA_TXP0 56
R1711 1 2 PCH_HDA_SPKR T10 AM10
29 HDA_SPKR SPKR SATA1RXN SATA_RXN1 103

1
0R0402-PAD-1-GP AM8
SATA1RXP SATA_RXP1 103
EC1701 EC1702 PCH_HDA_RST# K34
HDA_RST# SATA1TXN AP11 SATA_TXN1 103 mSATA

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP
-1 1220 AP10
2

2
HDA_SYNC_C SATA1TXP SATA_TXP1 103
E34 HDA_SDIN0 SATA2RXN AD7 SATA_RXN2 56
SATA2RXP AD5 SATA_RXP2 56
G34 HDA_SDIN1 SATA2TXN AH5
AH4
SATA_TXN2 56 HDD2
SATA2TXP SATA_TXP2 56
C34 HDA_SDIN2

IHDA
DY_RF DY_RF 29 HDA_SDIN0_CODEC SATA3RXN AB8
A34 HDA_SDIN3 SATA3RXP AB10
3 AF3 3
SATA3TXN
SATA3TXP AF1
HDA_SDO A36
RN1704 HDA_SDO

SATA
SATA4RXN Y7 SATA_RXN4 56
27 ME_UNLOCK 1 4 SATA4RXP Y5 SATA_RXP4 56
HDD_HALTLED_R
82 HDD_HALTLED 2 3 C36 HDA_DOCK_EN#/GPIO33 SATA4TXN AD3
AD1
SATA_TXN4 56 ODD
ISO_PREP# SATA4TXP SATA_TXP4 56
SRN1KJ-11-GP-U N32 HDA_DOCK_RST#/GPIO13
Q1701 Y3
SATA5RXN
27 RTCRST_ON G SATA5RXP Y1
SATA5TXN AB3
D RTC_RST# PCH_JTAG_TCK_BUF J3 AB1
JTAG_TCK SATA5TXP
S PCH_JTAG_TMS H7 Y11 1D05V_S0
JTAG_TMS SATAICOMPO

JTAG
2N7002K-2-GP PCH_JTAG_TDI K5 Y10 SATA_COMP R1713 1 2 37D4R2F-GP
JTAG_TDI SATAICOMPI
1

R1737 R1736 PCH_JTAG_TDO H1


100KR2J-1-GP 2K2R2J-2-GP JTAG_TDO 1D05V_S0
SATA3RCOMPO AB12

AB13 SATA3_COMP R1714 1 2 49D9R2F-GP 5V_S0


2

SATA3COMPI

1
T3 AH1 RBIAS_SATA3 1 2
60 PCH_SPI_CLK SPI_CLK SATA3RBIAS R1715 750R2F-GP
60 PCH_SPI_CS#0 Y14 SPI_CS0# NEED TO PLACE CLOSE TO PCH DY R1716
10KR2J-3-GP
TPAD14-OP-GP TP1702 1 SPI_CS1# T1

2
SPI_CS1#

SPI
P3 SATA_LED#
2 SATALED# SATA_LED# 82 2

60 PCH_SPI_MOSI V4 SPI_MOSI SATA0GP/GPIO21 V14 SATA0GP_GPIO21 22


3D3V_S0
U3 P1 PCH_GPIO19 2 1 R1731
60 PCH_SPI_MISO SPI_MISO SATA1GP/GPIO19 10KR2J-3-GP

PANTHER-GP-NF
3D3V_S5

R1724 1 2 1KR2J-1-GP HDA_SYNC

R1729 1
RTC Battery 3D3V_AUX_S5
2 10KR2J-3-GP ISO_PREP#
RTC_AUX_S5

U1701
2
3D3V_S5 RTC1 +RTC_VCC
3
PCHXDP R1717 1 2 210R2F-L-GP PCH_JTAG_TMS 3
PCHXDP R1718 1 2 210R2F-L-GP PCH_JTAG_TDO 1 +RTC_VCC 1 2 RTC PW R 1

1
PCHXDP R1719 1 2 210R2F-L-GP PCH_JTAG_TDI R1720 1KR2J-1-GP
5V_S0 C1705
NO REBOOT STRAP 2 CH715FPT-GP
SC1U10V3ZY-6GP
RN1703 4

2
No Reboot Strap R1722 1 8 PCH_JTAG_TMS
DY_PCHXDP 2 7 PCH_JTAG_TDI 83.R0304.B81
1

Low = Default 3 6 PCH_JTAG_TDO ACES-CON2-18-GP


HDA_SPKR High = No Reboot R1730 4 5 20.F1637.002
10KR2J-3-GP
2ND = 83.R2004.C81
3D3V_S0 SRN100F-GP
1 <Core Design> 1
PCHXDP R1721 1 2 51R2J-2-GP PCH_JTAG_TCK_BUF
2

HDA_SDO_G R1727 1 DY 2 1KR2J-1-GP HDD_HALTLED_R 2ND = 20.F1864.002


1 DY HDA_SPKR R1728 1 DY 2 20KR2J-L2-GP HDA_SDO
R1722
2
10KR2J-3-GP 84.05067.031 Wistron Corporation
G

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


2ND = 84.00138.H31 Taipei Hsien 221, Taiwan, R.O.C.
3RD = 84.2N702.W 31 LAYOUT NOTE:
HDA_SYNC_C S D HDA_SYNC JTAG_TMS TERMINATIONS NEED TO BE PLACED NEAR PCH Title

1 2 INT_SERIRQ
DMN5L06K-7-GP
JTAG_TDI TERMINATIONS
JTAG_TDO TERMINATIONS
NEED
NEED
TO
TO
BE
BE
PLACED
PLACED
NEAR
NEAR
PCH
XDP
PCH(1/9): HDA/JTAG/SATA
R1723 10KR2J-3-GP Size Document Number Rev
U1703 JTAG_TCK TERMINATIONS NEED TO BE PLACED NEAR PCH A3
Colossus 1
Date: W ednesday, January 04, 2012 Sheet 17 of 103
A B C D E
A B C D E

PCH1B PCH(2/9) 2 OF 10
2 1
3D3V_S5 3D3V_S0

4
3
BG34 R1806 10KR2J-3-GP
PERN1 RN1803
BJ34 PERP1 SMBALERT#/GPIO11 E12 EC_SW I# 27
AV32 PETN1 SRN2K2J-1-GP
PCH_SMB_CLK 3D3V_S0
15DY_17UP AU32 PETP1 SMBCLK H14 PCH_SMB_CLK 69 3D3V_S5
15DY_17UP PCH_SMB_DATA
BE34 C9 PCH_SMB_DATA 69

1
2
82 PCIE_RXN2_MEDIA17 PERN2 SMBDATA
82 PCIE_RXP2_MEDIA17 BF34 PERP2
C1808 1 2 SCD1U10V2KX-5GP PCIE_TXN2_C BB32 R1807 1 2
17"Card Read 82 PCIE_TXN2_MEDIA17
C1812 1 2 SCD1U10V2KX-5GP PCIE_TXP2_C AY32
PETN2 1KR2J-1-GP
82 PCIE_TXP2_MEDIA17 PETP2

SMBUS
4
SML0ALERT#/GPIO60 A12 PCH_DDR_RST# 5,8 4
BG36 U1801
32 PCIE_RXN3_MEDIA PERN3 PCH_SML0_CLK TP1803 TPAD14-OP-GP PCH_SMB_DATA
15"Card Read
32 PCIE_RXP3_MEDIA BJ36 PERP3 SML0CLK C8 1 14,15,103 PCH_SMBDATA 1 6
32 PCIE_TXN3_MEDIA C1805 1 2 SCD1U10V2KX-5GP PCIE_TXN3_C AV34
C1806 1 PETN3
32 PCIE_TXP3_MEDIA 2 SCD1U10V2KX-5GP PCIE_TXP3_C AU34 PETP3 SML0DATA G12 PCH_SML0_DATA 1 TP1805 TPAD14-OP-GP 2 5
15UP_17DY PCH_SMB_CLK
65 PCIE_RXN4_W LAN 15UP_17DY BF36 PERN4 3 4 PCH_SMBCLK 14,15,103
WLAN 65 PCIE_RXP4_W LAN BE36 PERP4
65 PCIE_TXN4_W LAN C1809 1 2 SCD1U10V2KX-5GP PCIE_TXN4_C AY34 C13 PCH_GPIO74 DMN66D0LDW -7-GP
C1807 1 PETN4 SML1ALERT#/PCHHOT#/GPIO74
65 PCIE_TXP4_W LAN 2 SCD1U10V2KX-5GP PCIE_TXP4_C BB34 PETP4
E14 PCH_SML1CLK
SML1CLK/GPIO58 84.DMN66.03F

PCI-E*
BG37 PERN5
BH37 M16 PCH_SML1DATA
PERP5 SML1DATA/GPIO75 C1801
AY36 PETN5
BB36 XTAL25_IN 1 2
PETP5

31 PCIE_RXN6_LAN BJ38 PERN6 SC15P50V2JN-2-GP


LAN 31 PCIE_RXP6_LAN BG38 PERP6

3
C1810 1 2 SCD1U10V2KX-5GP PCIE_TXN6_C

Controller
31 PCIE_TXN6_LAN AU36 PETN6 CL_CLK1 M7
31 PCIE_TXP6_LAN C1811 1 2 SCD1U10V2KX-5GP PCIE_TXP6_C AV36 R1805 X1801
PETP6 1MR2J-1-GP XTAL-25MHZ-155-GP

Link
BG40 PERN7 CL_DATA1 T11 3D3V_AUX_S5 3D3V_S5
3D3V_S0_W LAN BJ40 12pF30PPM

2
PERP7

4
3
2
1
AY40

2
PETN7 RN1802
BB40 PETP7 CL_RST1# P10 C1802
SRN2K2J-4-GP
2

BE38 XTAL25_OUT 1 2
R1808 PERN8
BC38 PERP8 82.30020.D41
2ND = 82.30020.G71
1KR2J-1-GP AW38 -1 1220

5
6
7
8
3 PETN8 3RD = 82.30020.G61 SC15P50V2JN-2-GP PCH_SML1CLK 3
AY38 PETP8
Q1801 R1804 PCH_SML1DATA
1

G M10 CLKREQ_PEG_A#_C 1 2
PEG_A_CLKRQ#/GPIO47 0R0402-PAD-1-GP CLKREQ_PEG_A# 83 3D3V_S5
Y40 CLKOUT_PCIE0N
D CLKRQ_W LAN# Y39 CLKOUT_PCIE0P CLKOUT_PEG_A_N
CLKOUT_PEG_A_N AB37 1 4 RN1810 CLK_PCIE_VGA# 83
GPIO73 CLKOUT_PEG_A_P 3 SRN0J-6-GP

CLOCKS
65 CLKRQ_W LAN#_C S J2 PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P AB38 2 CLK_PCIE_VGA 83 U1802
2N7002K-2-GP PCH_SML1DATA 1 6
R1809 AB49 AV22 SML1_DATA 27,29,79,86
CLKOUT_PCIE1N CLKOUT_DMI_N CLKOUT_DMI_N 5
1 2 AB47 CLKOUT_PCIE1P CLKOUT_DMI_P AU22 CLKOUT_DMI_P 5 2 5
0R2J-2-GP
GPIO18 M1 3 4 PCH_SML1CLK
PCIECLKRQ1#/GPIO18 27,29,79,86 SML1_CLK
AM12
DY CLKOUT_DP_N
AM13 DMN66D0LDW -7-GP
CLKOUT_DP_P
82 CLK_PCIE_MEDIA17# AA48 CLKOUT_PCIE2N
17"Card Read 82 CLK_PCIE_MEDIA17 AA47 CLKOUT_PCIE2P
RN1806 CLOCK TERMINATION FOR FCIM 84.DMN66.03F
BF18 CLK_BUF_EXP_N 1 4
CLKIN_DMI_N CLK_BUF_EXP_P
82 CLKREQ_MEDIA#17 V10 PCIECLKRQ2#/GPIO20 CLKIN_DMI_P BE18 2 3 SRN10KJ-5-GP

RN1807
Y37 BJ30 CLK_BUF_CPYCLK_N 1 4
32 CLK_PCIE_MEDIA# CLKOUT_PCIE3N CLKIN_GND1_N CLK_BUF_CPYCLK_P
15"Card Read 32 CLK_PCIE_MEDIA Y36 CLKOUT_PCIE3P CLKIN_GND1_P BG30 2 3 SRN10KJ-5-GP 3D3V_S5

32 CLKREQ_MEDIA# A8 RN1808
PCIECLKRQ3#/GPIO25

4
3
G24 CLK_BUF_DOT96_N 1 4
CLKIN_DOT_96N CLK_BUF_DOT96_P
CLKIN_DOT_96P E24 2 3 SRN10KJ-5-GP RN1801
65 CLK_PCIE_W LAN# Y43 CLKOUT_PCIE4N SRN2K2J-1-GP
WLAN Y45 RN1809
2 65 CLK_PCIE_W LAN CLKOUT_PCIE4P CLK_BUF_CKSSCD_N 2
CLKIN_SATA_N AK7 1 4
CLKRQ_W LAN# L12 AK5 CLK_BUF_CKSSCD_P 2 3 SRN10KJ-5-GP

1
2
PCIECLKRQ4#/GPIO26 CLKIN_SATA_P

V45 K45 CLK_BUF_REF14 R1802 1 2 10KR2J-3-GP


CLKOUT_PCIE5N REFCLK14IN PCH_SMB_CLK
V46 CLKOUT_PCIE5P
All resistors need very close to PCH PCH_SMB_DATA
GPIO44 L14 H45
PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK
CLK_PCI_FB 21
AB42 V47 XTAL25_IN
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49

GPIO56 E6 1D05V_S0
PEG_B_CLKRQ#/GPIO56
Y47 XCLK_RCOMP 1 2 CLK_14M_KBC_P
XCLK_RCOMP R1803 90D9R2F-1-GP
31 CLK_PCIE_LAN# V40 CLKOUT_PCIE6N
LAN 31 CLK_PCIE_LAN V42 CLKOUT_PCIE6P
DY

1
31 CLKREQ_LAN# T13 PCIECLKRQ6#/GPIO45 C1803
V38 K43 CLK_48_USB30 1 TP1801 TPAD14-OP-GP
FLEX CLOCKS

2
CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64 SC68P50V2JN-1GP
V37 CLKOUT_PCIE7P
F47 CLK_27_NSSC 1 TP1802 TPAD14-OP-GP
CLKRQ_W W AN# CLKOUTFLEX1/GPIO65
K12 PCIECLKRQ7#/GPIO46
CLKOUTFLEX2/GPIO66 H47
AK14 CLK_27M_VGA 86
CLKOUT_ITPXDP_N CLK_14M_KBC_P TP1804 TPAD14-OP-GP
AK13 CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 K49 1
1 <Core Design> 1

PANTHER-GP-NF
RN1804
CLKREQ_LAN# 1 10
3D3V_S5 3D3V_S0 Wistron Corporation
PCH_GPIO74 2 9 CLKRQ_W LAN# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
CLKRQ_W W AN# 3 8 GPIO56 Taipei Hsien 221, Taiwan, R.O.C.
GPIO44 4 7 CLKREQ_MEDIA#
5 6 GPIO73 RN1805 Title
1 4 GPIO18
3D3V_S5
SRN10KJ-L3-GP 2 3 CLKREQ_MEDIA#17 PCH(2/9): PCIE/SMBUS/CLK
Size Document Number Rev
SRN10KJ-5-GP A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 18 of 103
A B C D E
A B C D E

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)


(R1917 STUFFED,
PCH(3/9) R1901 UNSTUFFED

LOW Disabled
(R1917 UNSTUFFED,
3 OF 10
R1901 STUFFED
4 DMI_RXN[3:0] PCH1C
FDI_TX_N[7:0] 4
DMI_RXN0 BC24 BJ14 FDI_TX_N0
DMI_RXN1 DMI0RXN FDI_RXN0 FDI_TX_N1
4 BE20 DMI1RXN FDI_RXN1 AY14 4
DMI_RXN2 BG18 BE14 FDI_TX_N2
DMI_RXN3 DMI2RXN FDI_RXN2 FDI_TX_N3
4 DMI_RXP[3:0] BG20 DMI3RXN FDI_RXN3 BH13
BC12 FDI_TX_N4 RTC_AUX_S5
DMI_RXP0 FDI_RXN4 FDI_TX_N5
BE24 DMI0RXP FDI_RXN5 BJ12
DMI_RXP1 BC20 BG10 FDI_TX_N6
DMI_RXP2 DMI1RXP FDI_RXN6 FDI_TX_N7 R1917 1
BJ18 DMI2RXP FDI_RXN7 BG9 2 330KR2J-L1-GP
DMI_RXP3 BJ20 FDI_TX_P[7:0] 4
4 DMI_TXN[3:0] DMI3RXP FDI_TX_P0 DSW ODVREN R1901 1
FDI_RXP0 BG14 2 330KR2J-L1-GP
DMI_TXN0 AW24 BB14 FDI_TX_P1 DY
DMI_TXN1 DMI0TXN FDI_RXP1 FDI_TX_P2
AW20 DMI1TXN FDI_RXP2 BF14
DMI_TXN2 BB18 BG13 FDI_TX_P3
DMI_TXN3 DMI2TXN FDI_RXP3 FDI_TX_P4
4 DMI_TXP[3:0] AV18 DMI3TXN FDI_RXP4 BE12

DMI
FDI
BG12 FDI_TX_P5
DMI_TXP0 FDI_RXP5 FDI_TX_P6
AY24 DMI0TXP FDI_RXP6 BJ10
DMI_TXP1 AY20 BH9 FDI_TX_P7
DMI_TXP2 DMI1TXP FDI_RXP7
AY18 DMI2TXP
1D05V_S0 DMI_TXP3 AU18 DMI3TXP
FDI_INT AW16 FDI_INT 4
R1902 1 2 49D9R2F-GP DMI_COMP_R BJ24 AV12 FDI_FSYNC0 4
DMI_ZCOMP FDI_FSYNC0
BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 4

1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 4


R1903 750R2F-GP DMI2RBIAS FDI_LSYNC0

FDI_LSYNC1 BB10 FDI_LSYNC1 4

3 3D3V_S0 3
TPAD14-OP-GP TP1903 1 SUSACK#_R A18 DSW ODVREN -1 1220
DSWVRMEN
1 R1904 20R0402-PAD-1-GP RSMRST#

System Power Management


C12 E22 PCH_DPW ROK R1905 1 DY 2 10KR2J-3-GP
SUSACK# DPWROK

R1906 1 2 0R0402-PAD-1-GP PM_SYSRST#_R K3 B9


5 XDP_DBRESET# SYS_RESET# WAKE# PCIE_W AKE# 27,31

R1907 1 2 0R0402-PAD-1-GP SYS_PW ROK_R P12 N3


36 SYS_PW ROK SYS_PWROK CLKRUN#/GPIO32 PM_CLKRUN# 27

R1908 1 2 0R0402-PAD-1-GP PM_PCH_PW ROK L22 G8 PCH_GPIO61 1 TP1901 TPAD14-OP-GP


27,36 S0_PW R_GOOD PWROK SUS_STAT#/GPIO61 3D3V_S5
R1909 1 2 0R0402-PAD-1-GP
RN1901
APW ROK L10 N14 AC_PRESENT 1 8
APWROK SUSCLK/GPIO62 PCH_SUSCLK_KBC 27
2 7
PM_RI# 3 6
B13 D10 PCH_GPIO63 1 TP1904 TPAD14-OP-GP PCIE_W AKE# 4 5
5 PM_DRAM_PW RGD DRAMPWROK SLP_S5#/GPIO63
-1 1220
SRN10KJ-6-GP
C21 H4 SLP_S4#_R R1911 1 0R0402-PAD-1-GP
2
41 RSMRST# RSMRST# SLP_S4# PM_SLP_S4# 27,46
2 R1920 1
K16 F4 SLP_S3#_R R1912 1 0R0402-PAD-1-GP
2
27 SUS_PW R_ACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# R1910 1 PM_SLP_S3# 8,27,36,46,47,92 3D3V_S0
100KR2J-1-GP DY 2 0R2J-2-GP

E20 G10 PM_SLP_A#_R R1913 1 0R0402-PAD-1-GP


2 PM_SLP_A# 1 TP1905 TPAD14-OP-GP
2 27 PM_PW RBTN# PWRBTN# SLP_A# 2
PM_CLKRUN# 1 2
R1915 8K2R2J-3-GP
H20 G16 SLP_SUS# 1 TP1908 TPAD14-OP-GP
27,86 AC_PRESENT ACPRESENT/GPIO31 SLP_SUS#

PCH_GPIO72 E10 AP14


BATLOW#/GPIO72 PMSYNCH H_PM_SYNC 5

PM_RI# A10 K14 SLP_LAN#


RI# SLP_LAN#/GPIO29

PANTHER-GP-NF 3D3V_S5
SRN10KJ-5-GP
R1914
SUS_PW R_ACK 2 3
RSMRST# 1 2 PCH_GPIO72 1 4
Intel ME-EC Interaction Signal List with and without M3 support RSMRST#_KBC 27

1KR2F-3-GP RN1902
Platform With M3 Support
Signal Name (e.g., Intel AMT) Platform Without M3 Support 3D3V_S5

SLP_LAN# 1 2
SUSPWRDNACK(GPIO30) Required Required R1919 10KR2J-3-GP

ACPRESENT(GPIO31) Required Required


1 <Core Design> 1

(Tie to SLP_S3#)
SLP_A# Required Note: If SLP_S3# is not Wistron Corporation
routed from PCH to EC, then 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SLP_A# becomes required
from Intel ME-EC Title
prespecrive. PCH(3/9): DMI/FDI/PM
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 19 of 103
A B C D E
A B C D E

PCH(4/9)
4
3D3V_S0 4

PCH1D 4 OF 10
27 L_BKLT_EN J47 L_BKLTEN SDVO_TVCLKINN AP43

2
1
49 LCDVDD_EN M45 L_VDD_EN SDVO_TVCLKINP AP45

RN2002 P45 AM42


SRN2K2J-1-GP 49 BKLT_CTL L_BKLTCTL SDVO_STALLN
SDVO_STALLP AM40
49 LCD_SMBCLK T40 L_DDC_CLK
49 LCD_SMBDATA K47 AP39

3
4
L_DDC_DATA SDVO_INTN
SDVO_INTP AP40
L_CTRL_CLK T45
L_CTRL_DATA L_CTRL_CLK
P39 L_CTRL_DATA
1 2 LVD_IBG AF37 LVD_IBG SDVO_CTRLCLK P38
R2005 2K37R2F-GP AF36 M39
LVD_VBG SDVO_CTRLDATA
AE48 LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
DDPB_AUXP AT47
DDPB_HPD AT40
49 TXCLKA_L- AK39 LVDSA_CLK#

LVDS
49 TXCLKA_L+ AK40 LVDSA_CLK DDPB_0N AV42
DDPB_0P AV40
49 TXOUTA_L0- AN48 LVDSA_DATA#0 DDPB_1N AV45
49 TXOUTA_L1- AM47 LVDSA_DATA#1 DDPB_1P AV46

Digital Display Interface


49 TXOUTA_L2- AK47 LVDSA_DATA#2 DDPB_2N AU48
AJ48 LVDSA_DATA#3 DDPB_2P AU47
3 AV47 3
DDPB_3N
49 TXOUTA_L0+ AN47 LVDSA_DATA0 DDPB_3P AV49
49 TXOUTA_L1+ AM49 LVDSA_DATA1
49 TXOUTA_L2+ AK49 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
3D3V_S0

49 TXCLKB_L- AF40 LVDSB_CLK#


49 TXCLKB_L+ AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
49 TXOUTB_L0- AH45 LVDSB_DATA#0 DDPC_HPD AT38
49 TXOUTB_L1- AH47 LVDSB_DATA#1
49 TXOUTB_L2- AF49 LVDSB_DATA#2 DDPC_0N AY47

4
3
AF45 LVDSB_DATA#3 DDPC_0P AY49
AY43 RN2001
DDPC_1N
49 TXOUTB_L0+ AH43 LVDSB_DATA0 DDPC_1P AY45 SRN2K2J-1-GP
49 TXOUTB_L1+ AH49 LVDSB_DATA1 DDPC_2N BA47
49 TXOUTB_L2+ AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 BB47

1
2
LVDSB_DATA3 DDPC_3N
BB49
CLOSED IN PCH1 DDPC_3P

50 PCH_BLUE N48 CRT_BLUE DDPD_CTRLCLK M43 PCH_HDMI_CLK 51


50 PCH_GREEN P49 CRT_GREEN DDPD_CTRLDATA M36 PCH_HDMI_DATA 51
PCH_RED T49
PCH_GREEN 50 PCH_RED CRT_RED
PCH_BLUE AT45 DPD_AUXN 1 TP2002 TPAD14-OP-GP
DDPD_AUXN

CRT
50 CRT_DDC_CLK T39 AT43 DPD_AUXP 1 TP2001 TPAD14-OP-GP
CRT_DDC_CLK DDPD_AUXP
50 CRT_DDC_DATA M40 CRT_DDC_DATA DDPD_HPD BH41 HDMI_PCH_DET 51
8
7
6
5

2 2
RN2003 BB43 HDMI_DATA2_R# 51
SRN150F-1-GP DDPD_0N
50 CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45 HDMI_DATA2_R 51
50 CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44 HDMI_DATA1_R# 51
DDPD_1P BE44 HDMI_DATA1_R 51
BF42 HDMI_DATA0_R# 51
1
2
3
4

DAC_IREF DDPD_2N
T43 DAC_IREF DDPD_2P BE42 HDMI_DATA0_R 51
T42 CRT_IRTN DDPD_3N BJ42 HDMI_CLK_R# 51
1

DDPD_3P BG42 HDMI_CLK_R 51


R2003
1KR2D-1-GP PANTHER-GP-NF
2

1 <Core Design> 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH(4/9): LVDS/CRT/DDI
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 20 of 103
A B C D E
A B C D E

3D3V_S0 PCH1E PCH(5/9) 5 OF 10


AY7

R2113 1 2 PCH_GPIO51 BG26 TP1


RSVD1
RSVD2
RSVD3
AV7
AU3
USB2.0 Table
10KR2J-3-GP BJ26 BG4
TP2 RSVD4
BH25
BJ16
TP3
TP4 RSVD5 AT10 USB
BG16
AH38
TP5 RSVD6 BC8 Pair Device
TP6
AH37 TP7 RSVD7 AU2 0 USB 3.0 I/O CONN.
4 AK43 AT4 4
USB3.0 Table AK45
C18
TP8
TP9
TP10
RSVD8
RSVD9
RSVD10
AT3
AT1
1 N/A
USB N30 TP11 RSVD11 AY3 2 USB 3.0 I/O CONN.
H3 TP12 RSVD12 AT5
Pair Device AH12 TP13 RSVD13 AV3 3 USB 3.0 I/O CONN.
AM4 TP14 RSVD14 AV1
1 I/O CONN. 1 LEFT_DOWN AM5
Y13
TP15 RSVD15 BB1
BA3
4 FREE
TP16 RSVD16
2 FREE K24
L24
TP17 RSVD17 BB5
BB3
5 BT WLAN combo
TP18 RSVD18
3 I/O CONN. 2 LEFT_UP AB46
AB45
TP19 RSVD19 BB7
BE8
6 FREE
TP20 RSVD20

RSVD
4 I/O CONN. 3 RIGHT_UP RSVD21 BD4
BF6
7 FREE
RSVD22
1
DY
2 PE_GPIO0 B21 AV5
8 Fingerprint
10KR2J-3-GP TP21 RSVD23
M20 TP22 RSVD24 AV10 9 USB 2.0 CONN(Debug)
R2111 AY16 TP23
BG46 TP24 RSVD25 AT8 10 Camera
RSVD26 AY5
BA2
11 FREE
RSVD27
3D3V_S0 62 USB3_RXN1 BE28
BC30
USB3RN1
AT12
12 FREE
USB3RN2 RSVD28
R2110 62 USB3_RXN3 BE32
BJ32
USB3RN3 RSVD29 BF3 13 FREE
82 USB3_RXN4 USB3RN4
1 DY 2 CAMERA_ON 62 USB3_RXP1 BC28
10KR2J-3-GP USB3RP1
BE30 USB3RP2
3 BF32 3
SRN8K2J-3-GP 62 USB3_RXP3 USB3RP3
82 USB3_RXP4 BG32 USB3RP4 USBP0N C24 USB_PN0 62
2 3 ACCEL_INT# 62 USB3_TXN1 AV26 USB3TN1 USBP0P A24 USB_PP0 62 USB 3.0 Conn. 1
1 4 NMI_SMI_DBG# BB26 USB3TN2 USBP1N C25
62 USB3_TXN3 AU28 USB3TN3 USBP1P B25
82 USB3_TXN4 AY30 USB3TN4 USBP2N C26 USB_PN2 62
RN2101 AU26 A26 RN2106
62 USB3_TXP1
AY26
USB3TP1 USBP2P
K28 USB_PN3 1 4
USB_PP2 62 USB 3.0 Conn. 2
USB3TP2 USBP3N USB_PN3_1 82
AV28 H28 USB_PP3 2 3
62 USB3_TXP3
AW30
USB3TP3 USBP3P
E28
USB_PP3_1 82 USB 3.0 Conn. 3 (UB1)
82 USB3_TXP4 USB3TP4 USBP4N
D28 SRN0J-6-GP
USBP4P
3D3V_S0 USBP5N C28 15UP_17DY USB_PN5 65
RN2102 3D3V_S0 A28 USB_PP5 65 BT WLAN combo
INT_PIRQA# USBP5P
1 10 RN2105 C29
INT_PIRQD# DGPU_HOLD_RST# USBP6N
2 9 1 4 USBP6P B29
INT_PIRQB# 3 8 PCH_GPIO5 2 3 DGPU_PW R_EN# INT_PIRQA# K40 N28
INT_PIRQC# PCH_GPIO52 INT_PIRQB# PIRQA# USBP7N
4 7 K38 PIRQB# USBP7P M28

PCI
3D3V_S0 5 6 SRN8K2J-3-GP INT_PIRQC# H38 L30
PIRQC# USBP8N USB_PN8 64
INT_PIRQD# G38 K30 RN2107
SRN8K2J-2-GP-U
PIRQD# USBP8P
G30 USB_PN9 USB_PP9 1 4
USB_PP8 64 Fingerprint
USBP9N USB_PP9_1 82
83 DGPU_HOLD_RST# C46 REQ1#/GPIO50 USBP9P E30 USB_PP9 USB_PN9 2 3 USB_PN9_1 82 USB 2.0 Conn. 1 (UB1)

USB
1 PCH_GPIO52 C44 C30
REQ2#/GPIO52 USBP10N USB_PN10 49
TPAD14-OP-GP TP2102 E40 A30 SRN0J-6-GP
93 DGPU_PW R_EN# REQ3#/GPIO54 USBP10P USB_PP10 49 Camera
TPAD14-OP-GP TP2107 PCH_GPIO51 USBP11N L32 15UP_17DY
1 D47 GNT1#/GPIO51 USBP11P K32
CAMERA_ON E42 G32 -1 12/15
TPAD14-OP-GP TP2103 PE_GPIO0 GNT2#/GPIO53 USBP12N
1 F46 GNT3#/GPIO55 USBP12P E32
USBP13N C32
USBP13P A32
2 2
79 ACCEL_INT# G42 PIRQE#/GPIO2
3D3V_S5 G40
56 SATA_ODD_DA# PIRQF#/GPIO3
NMI_SMI_DBG# C42 C33 USB_BIAS R2101 1 2 22D6R2F-L1-GP
27 NMI_SMI_DBG# PIRQG#/GPIO4 USBRBIAS#
PCH_GPIO5 D44 PIRQH#/GPIO5
R2102 B33
PCI_PME# USBRBIAS
1 2 K10 PME#
10KR2J-3-GP
PCI_PLTRST# C6 A14
PLTRST# OC0#/GPIO59 3D3V_S5
OC1#/GPIO40 K20
OC2#/GPIO41 B17
R2103 1 2 22R2J-2-GP CLK_PCI_SIO_R H49 C16
27 CLK_PCI_KBC R2105 1 CLKOUT_PCI0 OC3#/GPIO42
18 CLK_PCI_FB 2 22R2J-2-GP CLK_PCI_FB_R H43 CLKOUT_PCI1 OC4#/GPIO43 L16
TPAD14-OP-GP TP2108 1 CLK_OUT_PCI2 J48 A16
TPAD14-OP-GP TP2106 CLK_OUT_PCI3 CLKOUT_PCI2 OC5#/GPIO9 R2104
1 K42 CLKOUT_PCI3 OC6#/GPIO10 D14
R2107 1 2 22R2J-2-GP CLK_PCI_KBC_R H40 C14 OC# 1 2
CLK_PCI_KBC 71,103 CLK_PCI_DEBUG CLKOUT_PCI4 OC7#/GPIO14 10KR2J-3-GP

CLK_PCI_DEBUG PANTHER-GP-NF
3D3V_S5
1

RN2108
EC2101 EC2102 USB_PP3 1 4 USB_PP3_2 82
SC12P50V2JN-3GP
SC12P50V2JN-3GP

DY_RF DY_RF USB_PN3 2 3 USB_PN3_2 82 (UB2)


2

15DY_17UP
SRN0J-6-GP
RN2109
U2101 AND GATE USB_PP9 1 4
1 USB_PN9 2 3
USB_PP9_2 82 (UB2)
B USB_PN9_2 82
1 VCC 5 <Core Design> 1
PCI_PLTRST# 2 SRN0J-6-GP
A PLT_RST#
Y 4 PLT_RST# 5,27,31,32,36,65,71,82,83,103 15DY_17UP
3 GND
-1 12/15 Wistron Corporation
1

74LVC1G08GW -1-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


R2108 Taipei Hsien 221, Taiwan, R.O.C.
73.01G08.L04 100KR2J-1-GP
2ND = 73.7SZ08.EAH DY Title
3RD = 73.7SZ08.DAH
PCH(5/9): PCI/USB/NVM
2

Size Document Number Rev


A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 21 of 103
A B C D E
A B C D E

RP2201
3D3V_S0
PCH(6/9) 3D3V_S0

1 10 H_A20GATE R2207 1 2 10KR2J-3-GP


2 9 H_RCIN# R2208 1 2 10KR2J-3-GP
PCH_TEMP_ALERT# 3 8 GPIO34 PCH1F 6 OF 10
SATA_ODD_PW R_EN 4 7
3D3V_S0 5 6 EC_SCI# TPAD14-OP-GP TP2222 1 CRD_REQ#_R_R T7 BMBUSY#/GPIO0 TACH4/GPIO68 C40 SATA_ODD_PW R_EN 56
SRN10KJ-L3-GP PCH_GPIO1 A42 B41 UMA_DIS#
TACH1/GPIO1 TACH5/GPIO69
PCH_GPIO6 H36 C41 DGPU_PRSNT#
3D3V_S0 TACH2/GPIO6 TACH6/GPIO70
4 4
3D3V_S5 EC_SCI# E38 A40
27 EC_SCI# TACH3/GPIO7 TACH7/GPIO71
R2204 1
DY
2 10KR2J-3-GP PCH_GPIO24 TPAD14-OP-GP TP2229 1 PCH_GPIO8 C10 GPIO8
SRN10KJ-5-GP
RN2204 2 3 PCH_GPIO38 TPAD14-OP-GP TP2202 1 LAN_DIS# C4 LAN_PHY_PWR_CTRL/GPIO12
1 4 mSATA_DET# 1 4 PCH_GPIO39 1D05V_S0
2 3 LAN_DIS# TLS_ENcrytion G2 P4 H_A20GATE 27
RN2205 GPIO15 A20GATE

1
SRN10KJ-5-GP AU16 H_PECI_R 1 DY 0R2J-2-GP
2
PECI H_PECI 5,27
1 2 DGPU_PW ROK 56 SATA_ODD_DET# U2 SATA4GP/GPIO16
R2209 DY R2222
R2218 10KR2J-3-GP P5 56R2J-4-GP
RCIN# H_RCIN# 27

GPIO
93 DGPU_PW ROK D40 AY11

2
TACH0/GPIO17 PROCPWRGD H_CPUPW RGD 5

CPU/MISC
PCH_GPIO22 T5 AY10 PCH_THRMTRIP#_R 1 2
SCLOCK/GPIO22 THRMTRIP# H_THRMTRIP# 5,36
R2210 390R2F-2GP
3D3V_S0 PCH_GPIO24 E8 T14 INIT3_3V# 1 TP2203 TPAD14-OP-GP
GPIO24 INIT3_3V#
E16 AY1 DF_TVS
103 mSATA_DET# GPIO27 DF_TVS
TPAD14-OP-GP TP2230 1PCH_GPIO28 P8 PROC_SELECT
3D3V_S0 GPIO28
TS_VSS1 AH8
GPIO34 K1 1D8V_S0
STP_PCI#/GPIO34
GPIO69_DIS TS_VSS2 AK11
GPIO6_FF GPIO22_45W GPIO1_Balen17 K4 GPIO35
2

1
TS_VSS3 AH10
R2211 R2206 R2205 R2231 SATA2GP_GPIO36 V8 R2201
SATA2GP/GPIO36 2K2R2J-2-GP
10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP TS_VSS4 AK10


3 SATA3GP_GPIO37 M5 3
SATA3GP/GPIO37
1

2
PCH_GPIO6 PCH_GPIO38 N2 P37
PCH_GPIO22 UMA_DIS# SLOAD/GPIO38 NC_1
1 2 H_SNB_IVB# 5
PCH_GPIO1 PCH_GPIO39 M3 R2202 1KR2J-1-GP
SDATAOUT0/GPIO39
2

V13 SDATAOUT1/GPIO48 VSS_NCTF_15#BG2 BG2


R2212 R2215 R2216 R2230 DMI & FDI Termination Voltage
10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP 27 PCH_TEMP_ALERT# V3 SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16#BG48 BG48

DY D6 BH3 SNB: "1"


1

GPIO57 VSS_NCTF_17#BH3 DF_TVS IVB: "0"


VSS_NCTF_18#BH47 BH47

GPIO6_DF_DY GPIO22_35W GPIO1_Goya15 A4 VSS_NCTF_1#A4 VSS_NCTF_19#BJ4 BJ4

NCTF
A44 VSS_NCTF_2#A44 VSS_NCTF_20#BJ44 BJ44

A45 VSS_NCTF_3#A45 VSS_NCTF_21#BJ45 BJ45


3D3V_S0
A46 VSS_NCTF_4#A46 VSS_NCTF_22#BJ46 BJ46

A5 VSS_NCTF_5#A5 VSS_NCTF_23#BJ5 BJ5

2
A6 BJ6 R2233
VSS_NCTF_6#A6 VSS_NCTF_24#BJ6

A4,A44,A45,A46,A5,A6,B3,B47,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
DY

BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
10KR2J-3-GP
B3 VSS_NCTF_7#B3 VSS_NCTF_25#C2 C2

1
B47 VSS_NCTF_8#B47 VSS_NCTF_26#C48 C48
2 DGPU_PRSNT# 2

D49,E1,E49,F1,F49
BD1 VSS_NCTF_9#BD1 VSS_NCTF_27#D1 D1

NCTF TEST PIN:

2
BD49 VSS_NCTF_10#BD49 VSS_NCTF_28#D49 D49
R2232
BE1 VSS_NCTF_11#BE1 VSS_NCTF_29#E1 E1 10KR2J-3-GP

BE49 E49 "H"GDDR5 DDR3

1
VSS_NCTF_12#BE49 VSS_NCTF_30#E49
VRAM "L"DDR3
BF1 VSS_NCTF_13#BF1 VSS_NCTF_31#F1 F1

BF49 VSS_NCTF_14#BF49 VSS_NCTF_32#F49 F49

PANTHER-GP-NF

3D3V_S0

3D3V_S0 3D3V_S0 SATA0GP_GPIO21 17


RN2202
1 4
2 3 SATA_ODD_DET#
1 2 SATA3GP_GPIO37 1 2 SATA2GP_GPIO36
R2217 DY 200KR2J-L1-GP R2213 DY 200KR2J-L1-GP SRN10KJ-5-GP
1 2 1 2
1 R2226 10KR2J-3-GP R2227 10KR2J-3-GP <Core Design> 1
3D3V_S5

FDI TERMINATION VOLTAGE OVERRIDE DMI TERMINATION VOLTAGE OVERRIDE Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1 2 TLS_ENcrytion
GPIO37 LOW - Tx, Rx terminated to same voltage GPIO36 LOW - Tx, Rx terminated to same voltage R2214 1KR2J-1-GP Title
(FDI_OVRVLTG) (DC Coupling Model DEFAULT) (DC Coupling Model DEFAULT) PCH(6/9): GPIO/NTCF/RSVD
Size Document Number Rev
A3 1
Colossus
Date: Thursday, January 05, 2012 Sheet 22 of 103
A B C D E
5 4 3 2 1

3D3V_S0

DY
PCH(7/9)

2
R2307 3D3V_DAC_S0 5V_S0
VCC_PCH: 6A 0R3J-0-U-GP
U2301
1mA

1
5 1
1.3A PCH1G POWER 7 OF 10 VOUT VIN
GND 2

1
1D05V_S0

SCD01U16V2KX-3GP

SCD1U10V2KX-4GP
D 4 3 C2308 D
NC#4 EN

SC1U10V2KX-1GP
C2312
AA23 U48 C2322 C2323 SC1U10V2KX-1GP

2
VCCCORE1 VCCADAC
AC23 G9090-330T11U-GP

2
VCCCORE2

SC10U6D3V3MX-GP

SC1U10V2KX-1GP
AD21

CRT
VCCCORE3

1
C2313 C2314 C2315 C2316 AD23 U47
VCCCORE4 VSSADAC
AF21 74.09090.D3F

VCC CORE
VCCCORE5

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
AF23

2
VCCCORE6 3D3V_S0
DY DY AG21 VCCCORE7 2nd = 74.70233.03F
AG23 VCCCORE8 1mA
AG24 VCCCORE9 VCCALVDS AK36
AG26 VCCCORE10
AG27 VCCCORE11 VSSALVDS AK37
AG29 VCCCORE12
AJ23 VCCCORE13 1D8V_S0

LVDS
AJ26 VCCCORE14 VCCTX_LVDS1 AM37
AJ27 VCCCORE15 60mA
AJ29 VCCCORE16 VCCTX_LVDS2 AM38
1D05V_S0 AJ31 VCCCORE17

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SC10U6D3V5KX-1GP
2.925A VCCTX_LVDS3 AP36

1
AP37 C2306 C2307 C2309
VCCTX_LVDS4
L2301 AN19

2
1D05V_S0 VCCIO28
DY
1 2 +V1.05S_VCCAPLL_EXP BJ22
IND-1UH-100-GP VCCAPLLEXP 266mA 3D3V_S0

VCC3_3_6 V33

SCD1U10V2KX-4GP
HVCMOS
AN16 VCCIO15

1
SC10U6D3V3MX-GP
C C

1
C2317 AN17 C2318
VCCIO16
DY V34

2
VCC3_3_7

2
AN21 VCCIO17
AN26 VCCIO18
1D05V_S0 AN27 AT16 +VCCAFDI_VRM
160mA
VCCIO19 VCCVRM3
SC: decap +V1.05S_VCC_DMI 1D05V_S0
AP21 VCCIO20 R2301
AP23 AT20 1 2
42mA
VCCIO21 VCCDMI1
1

1
C2310 C2311 C2321 C2320 C2301 0R0402-PAD

1
DMI
AP24 C2319
VCCIO22
SC1U10V3KX-3GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

VCCIO
SC1U10V2KX-1GP
2

AP26 AB36 VCCCLKDMI

2
VCCIO23 VCCCLKDMI 1D05V_S0

1
AT24 C2302
VCCIO24
1 R2306 2
20mA
SC1U10V2KX-1GP

2
AN33 0R0603-PAD-1-GP
VCCIO25
AN34 VCCIO26 VCCDFTERM1 AG16
3D3V_S0 -1 1220

SCD1U10V2KX-4GP
1
BH29 AG17 1D8V_S0
VCC3_3_3 VCCDFTERM2 C2303

DFT / SPI
190mA
1

C2304

2
B SCD1U10V2KX-4GP B
VCCDFTERM3 AJ16
1D05V_S0
2

+VCCAFDI_VRM AP16 VCCVRM2


VCCDFTERM4 AJ17

1 DY 2 +V1.05S_VCCAPLL_FDI BG6
R2302 0R3J-0-U-GP VCCAFDIPLL
3D3V_S5
1 R2303 2 +V1.05S_VCCDPLL_FDI AP17 VCCIO27 20mA
V1
FDI

0R0603-PAD-1-GP +V1.05S_VCC_DMI VCCSPI

1
SC1U10V2KX-1GP
AU20 C2305
VCCDMI2
-1 1220

2
PANTHER-GP-NF

+VCCAFDI_VRM

1D5V_S0 1 2
R2304 0R3J-0-U-GP

1D8V_S0 1
R2305
DY 2
0R3J-0-U-GP
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH(7/9): PWR1
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 23 of 103
5 4 3 2 1
A B C D E

1D05V_S0
PCH(8/9)
1
R2405
DY 2
0R3J-0-U-GP
2.925A
3D3V_S5
PCH1J POWER 10 OF 10 1D05V_S0
2mA +VCCACLK AD49 N26
VCCACLK VCCIO29
1 R2401 2

1
P26 C2402
0R0603-PAD-1-GP +VCCPDSW VCCIO30
T16 VCCDSW3_3
3D3V_S0

SC1U6D3V2KX-GP
P28

2
VCCIO31

1
L2401 C2403
4 1 2 +V3.3S_VCC_CLKF33 -1 1220 SCD1U10V2KX-4GP PCH_VCCDSW V12 T27 4
IND-10UH-215-GP C2401 DCPSUSBYP VCCIO32

1
68.1001D.10E SCD1U10V2KX-4GP T29
1D05V_S0 +V3.3S_VCC_CLKF33 VCCIO33 3D3V_S5
DY T38 VCC3_3_5 97mA
2ND = 68.1001E.10N DY

2
L2405 T23
VCCSUS3_3_7
SC10U6D3V3MX-GP

SC1U10V2KX-1GP
2 1 +VCCAPLL_CPY_PCH BH23
1 VCCAPLLDMI2

1
IND-10UH-193-GP T24 C2406
VCCSUS3_3_8

1
C2404 C2405 C2439 AL29 3D3V_S5 SCD1U10V2KX-4GP
1D05V_S0 VCCIO14
SC10U6D3V3MX-GP DY V23
2

2
VCCSUS3_3_9 3D3V_S5 5V_S5

USB
2
+VCCSUS1 AL24 V24

CH751H-40-1-GP
DCPSUS3 VCCSUS3_3_10

1
C2407
P24 SCD1U10V2KX-4GP
1mA
1mA

A
VCCSUS3_3_6

1
C2408 1D05V_S0

2
SC1U10V2KX-1GP AA19 D2401 R2402
VCCASW1 10R2J-2-GP
DY T26

2
VCCIO34
AA21 VCCASW2 83.R0304.D8F

2
K
1D05V_S0 AA24 M26 +V5A_PCH_VCC5REFSUS
1.01A VCCASW3 V5REF_SUS 3D3V_S0

1
AA26 C2409 5V_S0

CH751H-40-1-GP
Clock and Miscellaneous
VCCASW4 +VCCA_USBSUS SCD1U10V2KX-4GP
DCPSUS4 AN23 1mA
AA27 C2415

A
VCCASW5

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC1U10V2KX-1GP
VCCSUS3_3_1 AN24
1

1
C2410 C2411 C2412 C2413 C2414 AA29 DY D2402 R2403
VCCASW6 2ND = 83.R2004.B8F 10R2J-2-GP

2
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
AA31 3RD = 83.R3004.A8F 83.R0304.D8F
2

2
VCCASW7

2
K
3 AC26 P34 +V5S_PCH_VCC5REF 3
VCCASW8 V5REF C2416

1
AC27 VCCASW9
N20 3D3V_S5 SC1U10V2KX-1GP
VCCSUS3_3_2

PCI/GPIO/LPC
AC29

2
VCCASW10
VCCSUS3_3_3 N22
AC31 VCCASW11

1
2ND = 68.1001E.10N P20 C2417 2ND = 83.R2004.B8F
VCCSUS3_3_4 SC1U10V2KX-1GP 3RD = 83.R3004.A8F
AD29 VCCASW12
1D05V_S0
68.1001D.10E 80mA P22

2
L2402 VCCSUS3_3_5 3D3V_S0
AD31 VCCASW13
1 2 +V1.05S_VCCA_A_DPL
IND-10UH-215-GP W21 AA16
VCCASW14 VCC3_3_1

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
80mA

1
L2403 W23 W16 C2418 C2419
1 2 +V1.05S_VCCA_B_DPL VCCASW15 VCC3_3_8 266mA
IND-10UH-215-GP W24 T34

2
VCCASW16 VCC3_3_4 3D3V_S0
68.1001D.10E
W26 VCCASW17
1

1
SC22U6D3V5MX-2GP
TC2401

SC1U10V2KX-1GP
C2420

SC22U6D3V5MX-2GP
TC2402

SC1U10V2KX-1GP
C2421

2ND = 68.1001E.10N
W29 VCCASW18

1
DY C2422
2

DY W31 AJ2 SCD1U10V2KX-4GP


VCCASW19 VCC3_3_2

2
W33 1D05V_S0
VCCASW20
VCCIO5 AF13

SC1U6D3V2KX-GP
+VCCRTCEXT N16 DCPRTC

1
AH13 C2423
VCCIO12
1

2 C2424 +VCCAFDI_VRM 2
SCD1U10V2KX-4GP Y49 AH14 1D05V_S0

2
VCCVRM4 VCCIO13
160mA
2

+V1.05S_VCCA_A_DPL VCCIO6 AF14 DY


AF33, AF34 and AG34 should be VCCDIFFCLKN[3:1] BD47 VCCADPLLA

SATA
AK1 +V1.05S_VCCAPLL_SATA3 1 2 L2404
1D05V_S0 +V1.05S_VCCA_B_DPL VCCAPLLSATA IND-10UH-193-GP
BF47 VCCADPLLB

1
C2425
AF11 +VCCAFDI_VRM DY SC10U6D3V3MX-GP
VCCVRM1
AF17

2
VCCIO7
1D05V_S0 AF33 VCCDIFFCLKN1
1

1D05V_S0
SC1U6D3V2KX-GP

C2427 AF34 AC16


VCCDIFFCLKN2 VCCIO2
1
SC1U6D3V2KX-GP

C2426 AG34
55mA 1D05V_S0 VCCDIFFCLKN3
AC17
95mA
2

VCCIO3
2

1
AG33 AD17 C2428
VCCSSC VCCIO4
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
1

C2429 C2430

2
1 2PCH_DCPSST V16 DCPSST
1D05V_S0 SCD1U10V2KX-4GP 1D05V_S0
2

1 DY 2 +V1.05M_VCCSUS T17 T21


R2404 0R3J-0-U-GP C2431 DCPSUS1 VCCASW22
V19 DCPSUS2
1

SC1U10V2KX-1GP
MISC

1D05V_S0
DY VCCASW23 V21
2

CPU

1mA BJ8 V_PROC_IO


1 VCCASW21 T19 <Core Design> 1
1

C2432 C2433 C2434


RTC_AUX_S5 3D3V_S5
SC1U10V3KX-3GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

6uA
10mA Wistron Corporation
2

HDA

A22 P32
RTC

VCCRTC VCCSUSHDA
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC1U10V2KX-1GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


1

C2435 C2436 C2437 C2438 Taipei Hsien 221, Taiwan, R.O.C.


PANTHER-GP-NF SCD1U10V2KX-4GP
Title
DY DY
2

PCH(8/9): PWR2
Size Document Number Rev
A3 1
Colossus
Date: Tuesday, December 27, 2011 Sheet 24 of 103
A B C D E
A B C D E

PCH1I 9 OF 10

AY4
AY42
AY46
VSS159
VSS160
VSS259
VSS260
H46
K18
K26
PCH(9/9)
VSS161 VSS261
AY8 VSS162 VSS262 K39
B11 K46 PCH1H 8 OF 10
VSS163 VSS263
B15 VSS164 VSS264 K7 H5 VSS0
B19 VSS165 VSS265 L18
4 B23 VSS166 VSS266 L2 AA17 VSS1 VSS80 AK38 4
B27 VSS167 VSS267 L20 AA2 VSS2 VSS81 AK4
B31 VSS168 VSS268 L26 AA3 VSS3 VSS82 AK42
B35 VSS169 VSS269 L28 AA33 VSS4 VSS83 AK46
B39 VSS170 VSS270 L36 AA34 VSS5 VSS84 AK8
B7 VSS171 VSS271 L48 AB11 VSS6 VSS85 AL16
F45 VSS172 VSS272 M12 AB14 VSS7 VSS86 AL17
BB12 VSS173 VSS273 P16 AB39 VSS8 VSS87 AL19
BB16 VSS174 VSS274 M18 AB4 VSS9 VSS88 AL2
BB20 VSS175 VSS275 M22 AB43 VSS10 VSS89 AL21
BB22 VSS176 VSS276 M24 AB5 VSS11 VSS90 AL23
BB24 VSS177 VSS277 M30 AB7 VSS12 VSS91 AL26
BB28 VSS178 VSS278 M32 AC19 VSS13 VSS92 AL27
BB30 VSS179 VSS279 M34 AC2 VSS14 VSS93 AL31
BB38 VSS180 VSS280 M38 AC21 VSS15 VSS94 AL33
BB4 VSS181 VSS281 M4 AC24 VSS16 VSS95 AL34
BB46 VSS182 VSS282 M42 AC33 VSS17 VSS96 AL48
BC14 VSS183 VSS283 M46 AC34 VSS18 VSS97 AM11
BC18 VSS184 VSS284 M8 AC48 VSS19 VSS98 AM14
BC2 VSS185 VSS285 N18 AD10 VSS20 VSS99 AM36
BC22 VSS186 VSS286 P30 AD11 VSS21 VSS100 AM39
BC26 VSS187 VSS287 N47 AD12 VSS22 VSS101 AM43
BC32 VSS188 VSS288 P11 AD13 VSS23 VSS102 AM45
BC34 VSS189 VSS289 P18 AD19 VSS24 VSS103 AM46
BC36 VSS190 VSS290 T33 AD24 VSS25 VSS104 AM7
BC40 VSS191 VSS291 P40 AD26 VSS26 VSS105 AN2
BC42 VSS192 VSS292 P43 AD27 VSS27 VSS106 AN29
BC48 VSS193 VSS293 P47 AD33 VSS28 VSS107 AN3
BD46 VSS194 VSS294 P7 AD34 VSS29 VSS108 AN31
3 BD5 R2 AD36 AP12 3
VSS195 VSS295 VSS30 VSS109
BE22 VSS196 VSS296 R48 AD37 VSS31 VSS110 AP19
BE26 VSS197 VSS297 T12 AD38 VSS32 VSS111 AP28
BE40 VSS198 VSS298 T31 AD39 VSS33 VSS112 AP30
BF10 VSS199 VSS299 T37 AD4 VSS34 VSS113 AP32
BF12 VSS200 VSS300 T4 AD40 VSS35 VSS114 AP38
BF16 VSS201 VSS301 W34 AD42 VSS36 VSS115 AP4
BF20 VSS202 VSS302 T46 AD43 VSS37 VSS116 AP42
BF22 VSS203 VSS303 T47 AD45 VSS38 VSS117 AP46
BF24 VSS204 VSS304 T8 AD46 VSS39 VSS118 AP8
BF26 VSS205 VSS305 V11 AD8 VSS40 VSS119 AR2
BF28 VSS206 VSS306 V17 AE2 VSS41 VSS120 AR48
BD3 VSS207 VSS307 V26 AE3 VSS42 VSS121 AT11
BF30 VSS208 VSS308 V27 AF10 VSS43 VSS122 AT13
BF38 VSS209 VSS309 V29 AF12 VSS44 VSS123 AT18
BF40 VSS210 VSS310 V31 AD14 VSS45 VSS124 AT22
BF8 VSS211 VSS311 V36 AD16 VSS46 VSS125 AT26
BG17 VSS212 VSS312 V39 AF16 VSS47 VSS126 AT28
BG21 VSS213 VSS313 V43 AF19 VSS48 VSS127 AT30
BG33 VSS214 VSS314 V7 AF24 VSS49 VSS128 AT32
BG44 VSS215 VSS315 W17 AF26 VSS50 VSS129 AT34
BG8 VSS216 VSS316 W19 AF27 VSS51 VSS130 AT39
BH11 VSS217 VSS317 W2 AF29 VSS52 VSS131 AT42
BH15 VSS218 VSS318 W27 AF31 VSS53 VSS132 AT46
BH17 VSS219 VSS319 W48 AF38 VSS54 VSS133 AT7
BH19 VSS220 VSS320 Y12 AF4 VSS55 VSS134 AU24
H10 VSS221 VSS321 Y38 AF42 VSS56 VSS135 AU30
BH27 VSS222 VSS322 Y4 AF46 VSS57 VSS136 AV16
BH31 VSS223 VSS323 Y42 AF5 VSS58 VSS137 AV20
2 2
BH33 VSS224 VSS324 Y46 AF7 VSS59 VSS138 AV24
BH35 VSS225 VSS325 Y8 AF8 VSS60 VSS139 AV30
BH39 VSS226 VSS328 BG29 AG19 VSS61 VSS140 AV38
BH43 VSS227 VSS329 N24 AG2 VSS62 VSS141 AV4
BH7 VSS228 VSS330 AJ3 AG31 VSS63 VSS142 AV43
D3 VSS229 VSS331 AD47 AG48 VSS64 VSS143 AV8
D12 VSS230 VSS333 B43 AH11 VSS65 VSS144 AW14
D16 VSS231 VSS334 BE10 AH3 VSS66 VSS145 AW18
D18 VSS232 VSS335 BG41 AH36 VSS67 VSS146 AW2
D22 VSS233 VSS337 G14 AH39 VSS68 VSS147 AW22
D24 VSS234 VSS338 H16 AH40 VSS69 VSS148 AW26
D26 VSS235 VSS340 T36 AH42 VSS70 VSS149 AW28
D30 VSS236 VSS342 BG22 AH46 VSS71 VSS150 AW32
D32 VSS237 VSS343 BG24 AH7 VSS72 VSS151 AW34
D34 VSS238 VSS344 C22 AJ19 VSS73 VSS152 AW36
D38 VSS239 VSS345 AP13 AJ21 VSS74 VSS153 AW40
D42 VSS240 VSS346 M14 AJ24 VSS75 VSS154 AW48
D8 VSS241 VSS347 AP3 AJ33 VSS76 VSS155 AV11
E18 VSS242 VSS348 AP1 AJ34 VSS77 VSS156 AY12
E26 VSS243 VSS349 BE16 AK12 VSS78 VSS157 AY22
G18 VSS244 VSS350 BC16 AK3 VSS79 VSS158 AY28
G20 VSS245 VSS351 BG28
G26 BJ28 PANTHER-GP-NF
VSS246 VSS352
G28 VSS247
G36 VSS248
G48 VSS249
H12 VSS250
H18 VSS251
1 H22 VSS252 <Core Design> 1
H24 VSS253
H26 VSS254
H30
H32
VSS255
VSS256
Wistron Corporation
H34 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
VSS257 Taipei Hsien 221, Taiwan, R.O.C.
F3 VSS258
Title

PANTHER-GP-NF PCH(9/9): GND


Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 25 of 103
A B C D E
5 4 3 2 1

D D

(Blanking)

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH_XDP
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 26 of 103
5 4 3 2 1
5 4 3 2 1

SSID = KBC U2701


3D3V_AUX_KBC
3D3V_AUX_KBC
For EC power consumption reserver
12 125 VBAT 2 R2702 1
21 CLK_PCI_KBC PCICLK VCC
4 22 0R0402-PAD
17,71 LPC_FRAME# LPC_AD0 LFRAME# VCC
10 33
LPC_AD1 LAD0 VCC 3D3V_AUX_KBC 3D3V_AUX_S5
17,71 LPC_AD[0..3] 8 111
LPC_AD2 LAD1 VCC R2703
7 96
LPC_AD3 LAD2 VCC
5 9 1 2
LAD3 VCC VBAT 0R0603-PAD-1-GP
17 INT_SERIRQ 3 67
SERIRQ AVCC
22 H_A20GATE 1
H_RCIN# GA20
22 H_RCIN# 2 69 EC_AGND

1
KBRST# AGND C2710 C2709 C2708 C2707 C2706 C2705 C2704 C2701
5,21,31,32,36,65,71,82,83,103 PLT_RST# 13 11
ECSCI#_KBC PCIRST# GND
20
SCI# GND
24 DY DY

SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
19 PM_CLKRUN# 38 35

2
ECRST# CLKRUN# GND
37 94
ECRST# GND
113
GND
D TPAD14-OP-GP TP2745 1 FPR_OFF 21 D
PWM0
68 TOUCHPAD_LED 23
KB_BL_ON PWM1 V18R EC_AGND
25 124 1 2
PWM2 V18R C2711 SC4D7U6D3V3KX-GP
28 FAN1_PWM 26
FANPWM0 FAN1_DAC TP2742 TPAD14-OP-GP
68 CAP_LED 27 68 1
FANPWM1 DA0
28 FAN_TACH1 28 70 QUICKWEB_BTN# 82
FANFB0 DA1 PROCHOT_EC
65 AOAC_EN# 29 71 PROCHOT_EC 5
FANFB1 DA2
72 WLAN_PME_DIS_C 65
DA3 3D3V_AUX_KBC
69 KCOL[0..17] AD_IA 40
KCOL0 39
KCOL1 KSO0 SCD1U10V2KX-5GP 1DY
40 63 2 C2714 EC_AGND

1
KCOL2 KSO1 AD0 PCB_VER_AD
20110608 for vendor debug 41
KSO2 AD1
64
KCOL3 42 65 ADT_TYPE R2736
KCOL4 KSO3 AD2 CPU_THRM TP2748 TPAD14-OP-GP 10KR2J-3-GP
43 66 1
KROW4 TP2735 KROW4 KCOL5 KSO4 AD3 SYS_THRM TP2749 TPAD14-OP-GP
1 2 44 75 1
GAP-CLOSE-PWR KCOL6 KSO5 AD4 MODEL_ID
45 76

2
KROW5 TP2737 KROW5 KCOL7 KSO6 AD5 AIRLINE_VOLT_RC WLAN_PME_DIS_C
1 2 46 73
GAP-CLOSE-PWR KCOL8 KSO7 AD6
47 74
KROW6 TP2738 KROW6 KCOL9 KSO8 AD7
1 2 48
GAP-CLOSE-PWR KCOL10 KSO9
49
KROW7 TP2740 KROW7 KCOL11 KSO10
1 2 50 97 PCIE_WAKE# 19,31 PCB VERSION
GAP-CLOSE-PWR KCOL12 KSO11 GPXIOA0 PCH_SUSCLK_KBC
51 98 BLON_OUT 49
KCOL13 KSO12 GPXIOA1 3D3V_AUX_KBC
52 99 USB_PWR_EN# 61,62
KCOL14 KSO13 GPXIOA2
53 100 A_SD# 29
KCOL15 KSO14 GPXIOA3
54 101 S5_ENABLE 36

1
KCOL16 KSO15 GPXIOA4
81 102 PM_PWRBTN# 19 01/05/12

1
KCOL17 KSO16 GPXIOA5 R2735 R2727
69 KROW[0..7] 82 103 RSMRST#_KBC 19
KROW0 KSO17 GPXIOA6 C2712 100KR2F-L1-GP 64K9R2F-1-GP
KROW1
55
KSI0 GPXIOA7
104 AD_OFF 38
SC20P50V2JN-1GP
PCB_1
56 105 NMI_SMI_DBG# 21

2
KROW2 KSI1 GPXIOA8
57 106 S0_PWR_GOOD 19,36

2
KROW3 KSI2 GPXIOA9
58 107 RTCRST_ON 17
KROW4 KSI3 GPXIOA10 PCB_VER_AD
59 108 AC_PRESENT 19,86
KROW5 KSI4 GPXIOA11
60

1
KROW6 KSI5
61 109 BAT_IN# 39
KROW7 KSI6 GPXIOD0 EC_GPIO70 R2728
62 110
KSI7 GPXIOD1 EC_ENABLE# TP2747 TPAD14-OP-GP 100KR2F-L1-GP
112 1
GPXIOD2 KBC_PWRBTN#_R
114 MODEL ID
GPXIOD3
78 115 D85V_PWRGD 42,48

2
39,40 BAT_SDA SDA0 GPXIOD4
77 116 PCH_TEMP_ALERT# 22
39,40 BAT_SCL SCL0 GPXIOD5 3D3V_AUX_KBC
80 117 SUS_PWR_ACK 19
18,29,79,86 SML1_DATA SDA1 GPXIOD6 H_PECI_R1
C 79 118 1 R2745 2 H_PECI 5,22 EC_AGND C
18,29,79,86 SML1_CLK SCL1 GPXIOD7

2
43R2J-GP
69 KBC_CLK1 83 36 WLAN_LED# 65 R2724
PSCLK1 GPIO1A 10KR2F-2-GP
69 KBC_DATA1 84
PSDAT1 GPIO53
91 EC_WLAN_LED# 68 MODEL_ID
38 AD_DETECT 85 93 PWRLED 82
PSCLK2 GPIO55
86 GPU_PROTECT# 86

1
PSDAT2
69 TPCLK 87
PSCLK3 MODEL_ID
69 TPDATA 88
PSDAT3

1
122 SLP_A# 1 TP2739 TPAD14-OP-GP
GPIO5D R2726
69 LOGO_BL_ON 17
KB_BL_DETECT GPIO0B 100KR2F-L1-GP
18 123 PCH_SUSCLK_KBC 19
GPIO0C GPIO5E

2
127 3D3V_AUX_S5
GPIO59 CHG_ON# 40 3D3V_AUX_KBC
82 LID_CLOSE# 16 121 BLUETOOTH_EN 65
GPIO0A GPIO57 KBC_ECWP_C R2744 2 KBC_ECWP#
20 L_BKLT_EN 19 89 1 0R2J-2-GP EC_AGND
GPIO0D GPIO50 ECSWI#_KBC
32
GPIO18
15 PM_SLP_S4# 19,46

2
GPIO8
38 DC_BATFULL 34 14 STOP_CHG# 40

2
GPIO19 GPIO7 R2729
6 PM_SLP_S3# 8,19,36,46,47,92
GPIO4 R2733 10KR2F-2-GP
65 E51_TXD 30
GPIO16 10KR2F-2-GP
65 E51_RXD 31
GPIO17 EC_SPI_CS#_C1 R2737 33R2J-2-GP
DY
17 ME_UNLOCK 90 128 2 1

1
GPIO52 GPIO5A EC_SPI_DO_C1 EC_SPI_CS#_C 60
38 CHARGE_LED 92 120 R2743 2 1 33R2J-2-GP

1
GPIO54 GPIO5C EC_SPI_DI_C1 EC_SPI_DO_C 60
65 WIFI_RF_EN 95 119 R2742 2 1 0R2J-2-GP
GPIO56 GPIO5B EC_SPI_DI_C 60
126 EC_SPI_CLK_C1 R2719 2 1 33R2J-2-GP
GPIO58 EC_SPI_CLK_C 60
TPAD14-OP-GP TP2750 1 PM_PWRBTN#
TPAD14-OP-GP TP2751 1 D2702
R2731 KB9016QF-A3-GP KBC_ECWP# K A SPI_WP#_C 60
1 2 KB_BL_DETECT 71.09016.B0G
69 KB_BL_DETECT_C
2 R2711 1 1SS355GP-GP
51KR2J-1-GP 0R0402-PAD 2 R2715 1 ECSWI#_KBC
18 EC_SWI#
0R0402-PAD
83.00355.F1F
1

R2730 EC_AGND 2 R2712 1 ECSCI#_KBC


22 EC_SCI#
100KR2J-1-GP 0R0402-PAD

3RD = 84.2N702.W31
2

2ND = 84.07002.I31 ECRST#


B 3D3V_AUX_KBC 84.2N702.J31
Prevent BIOS data loss solution B
Q2701 3D3V_AUX_S5
R2732 Q2703
MMBT3906-4-GP
BAT_IN# 1 2 G KB_BL_ON 84.T3906.A11

1
2nd = 84.03906.F11

E
69 KB_BL_ON_R# D R2705
100KR2J-1-GP PURE_HW_SHUTDOWN#_B 10KR2J-3-GP
28,36,86 PURE_HW_SHUTDOWN# 2 1 B
S R2723
10KR2J-3-GP GPIO06-->PWRBTN

2
C
AD_OFF 2 1
R2770 2N7002K-2-GP
1KR2J-1-GP PURE_HW_SHUTDOWN#

HP Limit Signal Detect EC GPIO standard PH/PL


SRN4K7J-8-GP 3D3V_AUX_KBC 3D3V_AUX_KBC
BAT_SCL 4 1
3D3V_AUX_KBC BAT_SDA 3 2

2
RN2701 R2706
10KR2J-3-GP

1
2

KBC_PWRBTN#_R1 2 KBC_PWRBTN# 82
R2757
470R2J-2-GP
BAV99PT-GP-U

1
D2701 C2717
R2716 DY SC220P50V2KX-3GP
3

R2738
ECRST# 1 2

2
1 2 ADT_TYPE
LIMIT_SIGNAL
83.00099.K11 10KR2J-3-GP
1KR2F-3-GP 2ND = 83.00099.M11
1

3RD = 83.00099.T11 C2715


1

SCD1U10V2KX-5GP GPIO70-->PWR_CHG_ACOK# LOW active


R2734
2

A 12K4R2F-GP R2725 A
R2768
L_BKLT_EN 1 2 3D3V_S0 EC_GPIO70 1 2 PWR_CHG_ACOK# 40
2

100KR2J-1-GP 0R0201-PAD-GP

1
28 FAN_TACH1 1 2 C2713
EC_AGND R2714 SCD1U10V2KX-5GP
<Core Design>
10KR2J-3-GP
2
Wistron Corporation
C2718 SCD1U16V2KX-3GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
AIRLINE_VOLT_RC 1 2 BLUETOOTH_EN 1 DY 2 Taipei Hsien 221, Taiwan, R.O.C.
S5_ENABLE R2740 1 2 R2713
40 AIRLINE_VOLT R2739 1 2 10KR2J-3-GP 10KR2J-3-GP Title
10KR2J-3-GP
RN2713 pull-Low 10K Resistor to DY EC CONTROLLER
Size Document Number Rev
HP AIRLINE COMBO on BLUETOOTH_EN. A2
Colossus 1
Date: Thursday, January 05, 2012 Sheet 27 of 103
5 4 3 2 1
5 4 3 2 1

3D3V_S0

2 R2813 1

1
0R0402-PAD
R2809
Q2802 100KR2J-1-GP
DY

2
S THERM_SYS_SHDN#
D D
27,36,86 PURE_HW_SHUTDOWN# D

G IMVP_PWRGD 36,42

1
R2812 C2811 2N7002K-2-GP
10KR2J-3-GP DY DY SCD1U10V2KX-5GP 84.2N702.J31
2ND = 84.07002.I31

2
3RD = 84.2N702.W31

2
DY

90 C
3D3V_S0
U2803
R2806 R2801
1 222K1R2F-L-GP SET 1 5 VCC 2 1

1
SET VCC 150R2F-1-GP
2
THERM_SYS_SHDN# GND
3 4
OUT# HYST

HYST
C2817

2
SCD1U10V2KX-5GP
G709T1UF-GP 3D3V_S0
R2810
74.00709.A7F 2 1

R2811
DY 0R2J-2-GP
2 1
0R2J-2-GP

-1 1226

C C

B B

5V_S0
1

0R2J-2-GP
R2807 R2805
1 DY 2 10KR2J-3-GP
2

27 FAN_TACH1 A K FAN_TACH1_C

D2801

CH551H-30GP-GP
83.R5003.J8F FOR PWM FAN
2ND = 83.R5003.H8H

-1 0102

20 mil
5V_S0 5V_S0_FAN
5

FAN1
R2814 5V_S0_FAN
1 2 1
0R0402-PAD
R2815 1 2 FAN1_PWM_R 2
27 FAN1_PWM
1KR2J-1-GP 3
K
SC4D7U6D3V3KX-GP

FAN_TACH1_C 4
1

C2440 D2802
A AFTE14P-GP AFTP49 5V_S0_FAN A
1 CH551H-30GP-GP
1

ACES-CON4-19-GP
83.R5003.J8F
6

AFTE14P-GP AFTP46 1 FAN1_PWM_R DY L2801


A

MLVS0402M04-GP 2ND = 83.R5003.H8H


AFTE14P-GP AFTP45 1 FAN_TACH1_C

AFTE14P-GP AFTP47 1 <Core Design>


2

-1 1226
-1 0104
20.F1637.004 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2nd = 20.F1808.004 Taipei Hsien 221, Taiwan, R.O.C.
3rd = 20.F1579.004
Title

Thermal/FAN
Size Document Number Rev
A2 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 28 of 103
5 4 3 2 1
5 4 3 2 1

AVDD_CODEC 5V_S0

3D3V_S0
DVDD_CORE
AUDIO CODEC(92HD91) 5V_S0

3D3V_S0 3D3V_S0 C2905


1

2
SC10U10V5KX-2GP
C2907 Q2901

1
R2902 C2908 C2910 C2911 R2919 Vout = 4.75 V

1
SC1U10V2KX-1GP
4K7R2J-2-GP C2909 10KR2J-3-GP HPA01085DBVR-GP

SCD1U10V2KX-5GP
AVDD_CODEC

2
1

SCD1U10V2KX-5GP

SC1U10V2KX-1GP

SC10U10V5KX-2GP
C2903 C2904 AVDD_CODEC_EN 3 4
2

1
1

1
C2902 U2901 EN NR
2
GND

SCD1U10V2KX-5GP
SC1U10V2KX-1GP
HDA_RST#_CODEC 1 5

2
IN OUT

SCD1U10V2KX-5GP
1 27

2
DVDD_CORE AVDD1 AUD_AGND
38
1

AVDD2

1
C2901 3 45 C2914 74.01085.03FC2915

1
SCD01U16V2KX-3GP DVDD_IO PVDD C2916
39
2

PVDD

SCD1U10V2KX-5GP
SC2D2U6D3V3KX-GP

SCD01U16V2KX-3GP
9 13 SENSE_A

2
DVDD SENSE_A SENSE_B
D 14 D
SENSE_B
28 MIC_L C2913 1 2SC1U16V3KX-5GP MIC_L0
PORTA_L MIC_R
29 C2917 1 2 SC1U16V3KX-5GP MIC_R0 AUD_AGND
PORTA_R
23
VREFOUT_A +VREFOUT_A
6
17 HDA_BITCLK_CODEC BITCLK HP_OUT_L
31
17 HDA_SDOUT_CODEC
5
SDATA_OUT
PORTB_L
PORTB_R
32 HP_OUT_R Port Arrangement
10 19
17 HDA_SYNC_CODEC SYNC PORTC_L
PORTC_R
20 Port A---> Mic In
R2903 1 2 33R2J-2-GP HDA_SDIN0_CODEC_C 8 24
17 HDA_SDIN0_CODEC
R2903 Need close to Codec SDATA_IN VREFOUT_C/GPIO4 Port B---> HeadPhone
11 15

DMIC_CLK_R
17 HDA_RST#_CODEC RESET# PORTE_L
PORTE_R
16 Port C---> x
DMIC_DATA_RF1
PORTF_L
17
FSPK_L 58 Port D--->Main SPKR
DY_RF DY_RF 18
1

PORTF_R FSPK_R 58
EC2906 EC2905
MUTE# 47
EAPD
40
Port E---> x
PORTD_+L SPKR_L+ 58
SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

R2913 1 2100R2F-L1-GP-U DMIC_CLK_R 2 41


49 DMIC_CLK Port F---> 2ND SPKR
2

DMIC_DATA_RF1 DMIC_CLK/GPIO1 PORTD_-L SPKR_L- 58


49 DMIC_DATA 2 1 4
R2926 0R0402-PAD DMIC_0/GPIO2
44 SPKR_R+ 58
PORTD_+R
48 43 SPKR_R- 58
SPDIFOUT0/GPIO3 PORTD_-R
68 MUTE_LED_CTRL 46
DMIC1/GPIO0/SPDIFOUT1
25
MONO_OUT MONO_OUT 30
3D3V_S0 1 2 CAP+ 36 12 AUO_BEEP
CAP+ PCBEEP
C2906
CAP CLOSED IN CODEC
1

SC4D7U6D3V3KX-GP 21 AUD_VREFFILT C2918 1 2 SC10U10V5KX-2GP


R2901 VREFFILT AUD_CAP2 C2919 1 SCD1U10V2KX-5GP
22 2
CAP- CAP2 AUD_V- C2920 1 SC4D7U6D3V3KX-GP
10KR2J-3-GP 35 34 2
CAP- V- AUD_VREG C2921 1 SC4D7U6D3V3KX-GP
37 2
VREG(+2.5V)
D2901
2

7
DVSS Place close to codec
K A
27 A_SD#
42 26
PVSS AVSS1
30
1SS355GP-GP AVSS2 AUD_AGND
1 DY 2 49 33
R2927 GND AVSS2
C 0R2J-2-GP C
83.00355.F1F 92HD91B2X5NLGXYAX-GP
2ND = 83.00355.D1F
AUD_AGND
3D3V_S0
30,58 MUTE# R2904
1 DY 2 MUTE_LED_CTRL

10KR2J-3-GP

SENSE Detect Headphone Trace = 15mil Digital GND & AUD_AGND PC BEEP AVDD_CODEC
C2927 MIC IN ME update MIC1 Jack
+VREFOUT_A 1 2
MIC1
AVDD_CODEC Tie Analog GND and Digital GND AUDIO-JK306-GP

1
SC1U6D3V2KX-GP
under codec by a single point R2909 R2922 R2923 AUD_AGND
9
8
Close to Pin13
1

10KR2J-3-GP 4K7R2J-2-GP 7
R2906 4K7R2J-2-GP
2K49R2F-GP 0818 IDT request 100KR2J-1-GP BLM18PG600SN-2GP 5

2
R2924
C2924 R2910 C2926
Place under U2901 MONO_L 2 1 MONO_L_0 1 2 MONO_L_1 2 1 AUO_BEEP MIC_L0 1 2 MIC_L0_jack 4
2

SENSE_A SCD1U16V2KX-3GP SCD1U16V2KX-3GP 3


R2925
G2901 BLM18PG600SN-2GP 6
1 2 MIC_R0 1 2 MIC_R0_jack 2
1

2
C2922 1

1
SC1KP50V2KX-1GP If sense A total length is greater than 6 inches. GAP-CLOSE-PWR-3-GP R2911 C2925

D
G2902 10KR2J-3-GP EC2901 EC2902 22.10270.E11
2

SC220P50V2KX-3GP

SC220P50V2KX-3GP
Change C2922 to 0.1uF 1 2 Q2902 SCD01U16V2KX-3GP

2
2N7002K-2-GP

1
AUD_AGND GAP-CLOSE-PWR-3-GP 84.2N702.J31
G2903 2ND = 84.07002.I31 2ND = 22.10270.F61
AVDD_CODEC 1 2 3RD = 84.2N702.W31
GAP-CLOSE-PWR-3-GP
G2904 AUD_AGND

S
1

Close to Pin14 1 2
R2908 GAP-CLOSE-PWR-3-GP
100KR2F-L1-GP G2905 17 HDA_SPKR AUD_AGND AUD_AGND
B R2918 B
1 2
SENSE_A 1 2 SENSE_A_jack
2

SENSE_B GAP-CLOSE-PWR-3-GP AUD_AGND


AUD_AGND
39K2R2F-L-GP
DY
1

C2923 audio ground must be connect to


SC1KP50V2KX-1GP AUD_AGND
digital ground with an 80 mil copper ADD TEST PAD AUD_AGND 1 AFTP31 AFTE14P-GP
2

SENSE_A_jack 1 AFTP30 AFTE14P-GP


bridge located directly under codec MIC_L0_jack 1 AFTP21 AFTE14P-GP
AUD_AGND -1 12/15 Add AFTP 30 & 31 MIC_R0_jack 1 AFTP27 AFTE14P-GP
to prevent ESD latch up.

HeadPhone 5V_S0
3D3V_S0

C2930 5V_S0

1
C2935

ME update HP1 Jack

1
SC1U10V2KX-1GP

SCD1U10V2KX-5GP
2

4
3
R2917
U2902 10KR2J-3-GP
HP1 RN2901
AUDIO-JK306-GP 12 6 SD# SRN2K2J-1-GP

2
VDD SD#
9 20
VDD HP_DATA
8 7

1
2
SDA PQ2903
7 CPN 17 8 HP_CLK
CPN SCL
C2929 1 2CPP 18 HP_CLK 1 6 SML1_CLK 18,27,79,86
BLM18PG600SN-2GP AUD_AGND SC1U10V2KX-1GP CPP
EL2901 5
2 5
HPA_OUT_L 1 EL2902 2 HPA_OUT_L_jack 4 HP_OUT_L C2931
1 2 LEFTINM 1 15 CPVSS
BLM18PG600SN-2GP LEFTINP LEFTINM CPVSS
3 2 16 3 4

1
HPA_OUT_R HPA_OUT_R_jack SC1U10V2KX-1GP LEFTINP CPVSS
1 2 6
2 HP_OUT_R C2932
1 2 RIGHTINM 5 3 C2928
RIGHTINP RIGHTINM GND 2N7002KDW-GP
1 4 9

2
SML1_DATA 18,27,79,86
1

SC1U10V2KX-1GP RIGHTINP GND SC2D2U10V3KX-1GP 84.2N702.A3F


10
EC2904 EC2903 R2915 GND HP_DATA
13
GND
SC220P50V2KX-3GP

SC220P50V2KX-3GP

A HPA_OUT_L HPA_OUT_L1 A
1 2 30R3F-GP 14 19 2nd = 84.2N702.E3F
2

HPA_OUT_R HPA_OUT_R1 HPLEFT GND 3RD = 84.2N702.F3F


1 2 11 21
22.10270.E11 R2916 HPRIGHT GND
2ND = 22.10270.F61 30R3F-GP
1
1

C2933 C2934
<Core Design>
SC1U10V2KX-1GP

SC1U10V2KX-1GP

AUD_AGND HPA00929RTJR-GP
2
2

AUD_AGND AUD_AGND AUD_AGND HPA_OUT_L_jack 1 AFTP16 AFTE14P-GP AUD_AGND


SENSE_A 1 2 SENSE_JACK Wistron Corporation
R2914 HPA_OUT_R_jack 1 AFTP22 AFTE14P-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
20KR2F-L-GP
Title
SENSE_JACK 1 AFTP35 AFTE14P-GP
AUD_AGND Audio Codec 92HD91/HeadphoneAMP
AUD_AGND 1 AFTP36 AFTE14P-GP Size Document Number Rev
A2 1
-1 12/15 Add AFTP 35 & 36 Colossus
Date: Wednesday, January 04, 2012 Sheet 29 of 103

5 4 3 2 1
5 4 3 2 1

PVCC DCBATOUT
R3001
D D
2 1

WOOFER AMP 0R0603-PAD-1-GP

1
C3004 C3003
C3002 C3001

SC1KP50V2KX-1GP

SCD1U25V3KX-GP

SC4D7U25V5KX-GP

SC4D7U25V5KX-GP
2

2
WOOFER
WOOFER U3001
WOOFER 29 W OOFER_- 1 AFTP29 AFTE14P-GP
GND
1 28 W OOFER_+ 1 AFTP28 AFTE14P-GP
29,58 MUTE# SD# PVCC
WOOFER
WOOFER 2 FAULT# PVCC 27
WOOFER C3005 68.00206.051 1 AFTP48 AFTE14P-GP
3 26 BSNL 1 2 2ND = 68.00216.031
5V_S0 NC#3 BSN#26 WOOFER
4 25 W OOFER_OUTN L3001 1 2 W OOFER_-
NC#4 OUTN#25 SCD47U25V3KX-1GP PBY201209T-800Y-N-1GP
R3004
1 2 100KR2J-1-GP G0 5 24
GAIN0 PGND C3007

2
R3002
R3005 2 100KR2J-1-GP G1 BSNL_R_G C3006 W OOFER1
1 DY 6 GAIN1 OUTN#23 23 1 DY 2 2 1
GAIN 26dB DY SC1000P50V3JN-GP-U 3

1
R3008 1 2 10R5J-GP 7 22 10R5J-GP SC1000P50V3JN-GP-U 1
AVCC BSN#22
G1 G0 GAIN 2 1 C3014 SC1U25V3KX-1-GP
1

R3006 R3007 8 21 2
AGND BSP#21 C3008
0 0 20 R3003 4
DY C3015
1 2 9 20 1 DY 2 BSPL_R_G 2 DY
1
R3009 GVDD OUTP#20 ACES-CON2-18-GP
0 1 26 1 2
C 49K9R2F-L-GP 10 19 10R5J-GP SC1000P50V3JN-GP-U 2ND = 20.F1864.002 C
2

100KR2J-1-GP
100KR2J-1-GP SC1U16V3KX-5GP PLIMIT PGND
1 0 32 20.F1637.002
11 18 W OOFER_OUTP L3002 1 2 W OOFER_+
INN OUTP#18 PBY201209T-800Y-N-1GP
1 1 36 WOOFER
12 17 BSPL 1 2 68.00206.051
INP BSP#17

1
C3009 SCD47U25V3KX-1GP 2ND = 68.00216.031
13 16 PVCC C3010
NC#13 PVCC W OOFER
SC1000P50V3JN-GP-U
G1=0 G0=0 GAIN=6dB

2
PVCC 1R3010 WOOFER
210KR2J-3-GP 14 15
AVCC PVCC G1=0 G0=1 GAIN=12dB

1
C3016 C3013 C3012 C3011 G1=1 G0=0 GAIN=18dB
1

SC1U25V3KX-1-GP

SCD1U25V3KX-GP
TPA3111D1-GP
R3011 74.00836.01G SC10U25V5KX-GP G1=1 G0=1 GAIN=24dB
SC1U16V3KX-5GP

2
2

28K7R2F-GP HPF=275Hz GAIN=16dB


WOOFER WOOFER
2

WOOFER WOOFER WOOFER


WOOFER WOOFER
2

WOOFER R312 R3013


0R0603-PAD 0R0603-PAD
1

C3017 C3018
1

1
SC1U16V3KX-5GP

SC1U16V3KX-5GP
2

B B

WOOFERWOOFER
Woofer use in AUD_AGND ground
MONO_OUT 29

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio AMP_SPK/WOOFER
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 30 of 103
5 4 3 2 1
5 4 3 2 1

Regout power plane(1D05V)


USE EFuse No ASF LAN CHIP-RTL8111F
EVDD10
R3117
VDD33 3D3V_S5 VDD33 1 2
R3130 40 mils R3131 0R0603-PAD

1
LAN_GPO R3106 1 2 1KR2J-1-GP 1 2 1 2 VDDREG C3112 C3109
0R0603-PAD 0R0603-PAD Put cap near pin21

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP
2

2
1

1
C3124 C3122 C3103 C3117 C3118 C3114 C3119 C3106 Place
D LAN_SMBDATA R3118 1 2 10KR2J-3-GP D
closed to

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC4D7U10V3KX-GP
SCD1U16V2KX-3GP
2

2
DY DY Pin 34,35

RN3101
EEDI 3 2
EECS 4 1 VDD10

SRN10KJ-5-GP
cap near pin12,27,39,42,47,48 <200mils

1
C3123 C3120 C3107 C3121 C3135 C3116 C3115

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
2

2
DY DY DY
Avoid Leakage
AMBER_LED# 59 EEPROM LED OPTION USE '00'
R3104 => LED0 : ACT (Amber)
1 2 RSET => LED1 : LINK (White)
LAN_GPO
2K49R2F-GP VDD33 VDD33 VDD33 (BOTH 10/100 & GIGA CHIP)
W HITE_LED# 59 cap near pin3,6,9,13,29,41,45
(Power down => Kept high)

LANXOUT
LANXIN
VDD10

VDD10
C C

60 mils L3101

48
47
46
45
44
43
42
41
40
39
38
37
U3101 REGOUT 1 2
49 IND-4D7UH-192-GP

AVDD33
AVDD33

AVDD10
CKXTAL2
CKXTAL1
AVDD33
DVDD10
LED0
DVDD3

LED1/EESK
RSET

GPO/SMBALERT
GND

1
68.4R750.20C C3101 C3113

SCD1U10V2KX-5GP
SC4D7U10V3KX-GP
2

2
Lan Power Inductance Spec
1 36 REGOUT (1) IDC >= 600mA DY
59 MDIP0 MDIP0 REGOUT VDDREG
59 MDIN0 2 MDIN0 VDDREG 35 (2) Tolerance < 20%
VDD10 3 34
AVDD10 VDDREG ENSW REG (3) RDC <= 0.8ohms(Max)
59 MDIP1 4 MDIP1 ENSWREG 33
5 32 EEDI (4) Efficiency >= 80%
59 MDIN1 VDD10 MDIN1 EEDI/SDA
6 AVDD10 LED3/EEDO 31
7 30 EECS
59 MDIP2 MDIP2 EECS/SCL VDD10
59 MDIN2 8 MDIN2 DVDD10 29
VDD10 9 28
LanChip Power 59 MDIP3 10
11
AVDD10
MDIP3
LANWAKE#
DVDD33 27
26 ISOLATE#
VDD33
PCIE_W AKE# 19,27
Put 4D7U L + 22U cap near pin36 <200mils
+3.3V_LAN_S5 Rising time (10%~90%) 59 MDIN3
12
MDIN3 ISOLATE#
25
(2nd = 78.22610.81L)
VDD33 AVDD33 PERST# PLT_RST# 5,21,27,32,36,65,71,82,83,103
Spec >1mS and <100mS 71.08111.N03

REFCLK_N
REFCLK_P
SMBDATA
CLKREQ#
SMBCLK
DVDD10

EVDD10
Regout Switch

HSON
HSOP
HSIN
HSIP

GND
RTL8111F-CGT-GP
13
14
15
16
17
18
19
20
EVDD10 21
22
23
24
B VDD33 B
VDD10

ENSW REG 1 R3119 2


Close to LanChip 0R0402-PAD
Using Efuse
Without ASF PCIE_RXN6_R 1 2 C3111
SCD1U10V2KX-5GP
PCIE_RXN6_LAN 18
LAN_SMBDATA PCIE_RXP6_R 1 2 C3110 PCIE_RXP6_LAN 18
SCD1U10V2KX-5GP

CLK_PCIE_LAN# 18 ENSWREG (REGOUT 1D05V)


18 CLKREQ_LAN# CLK_PCIE_LAN 18 PH = Enable
PCIE_TXN6_LAN 18 PL = Disable
PCIE_TXP6_LAN 18

25MHz Crystal KBC Reserved Pin Isolate Strap Pin


C3104 Isolate# => Low , Isolate LanChip
1 2 LANXOUT GPO => EFuse Strap Pin 3D3V_S0

SC18P50V2JN-1-GP

1
A <Core Design> A
4

R3111
X3101 1KR2J-1-GP
XTAL-25MHZ-155-GP
3RD = 82.30020.G61 Wistron Corporation

2
2ND = 82.30020.G71 ISOLATE# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
82.30020.D41
1

1
C3105 Title
R3114
1 2 LANXIN 15KR2F-GP
LAN_RTL8111F
Size Document Number Rev

2
SC18P50V2JN-1-GP A3
Colossus 1
Crystal +/- 20 ppm
Date: W ednesday, January 04, 2012 Sheet 31 of 103
5 4 3 2 1
5 4 3 2 1

RTS5229 -1 12/15 0201 0 Ohm change to short pad

SP5 R3201 1 2 0R0201-PAD-GP SD_D1 74


SP7 R3202 1 2 0R0201-PAD-GP
15UP_17DY SD_D0 74
SP9 R3203 1
15UP_17DY
0R0201-PAD-GP
CLKREQ_MEDIA# 18 2 SD_CLK 74
PLT_RST# 5,21,27,31,36,65,71,82,83,103 SP10 R3204 1 2 0R0201-PAD-GP
15UP_17DY SD_CMD 74
3D3V_S0 15UP_17DY
D
SD_CD#_C
15UP_17DY SP12 R3205 1
D
2 0R0201-PAD-GP SD_D3 74
SD_W P_C R3211 1 2 100KR2J-1-GP SP14 R3206 1 2 0R0201-PAD-GP
15UP_17DY SD_D2 74
3D3V_S0_L R3207 1 2 15UP_17DY
10KR2J-3-GP
SD_CD#_C R3209 1 2 0R0201-PAD-GP SD_CD# 74
15UP_17DY SD_W P_C R3210 1 2 0R0201-PAD-GP
15UP_17DY SD_W P 74
15UP_17DY

Vendor info update design issue (RTS5229)U3201 closed near

24
23
22
21
20
19
U3201

CLKREQ#
PERST#
MS_INS#
SD_CD#

GPIO
SD_WP
1 18 SP14
18 PCIE_TXP3_MEDIA HSIP SP6 SP12
18 PCIE_TXN3_MEDIA 2 HSIN SP5 17
3 16 SP10
18 CLK_PCIE_MEDIA SCD1U16V2KX-3GP REFCLKP SP4 DV33_18
18 CLK_PCIE_MEDIA# 4 REFCLKN DV33_18 15
18 PCIE_RXP3_MEDIA C3209 1 2PCIE_RXP3_MEDIA_C 5 14 SP9
C3210 1 HSOP SP3
18 PCIE_RXN3_MEDIA 2PCIE_RXN3_MEDIA_C 6 HSON SP2 13 SP7
SCD1U16V2KX-3GP

CARD_3V3
15UP_17DY

DV12_S
3V3_IN

2
RREF
AV12
15UP_17DY 25

SP1
C GND C3216 C

SC5P50V2CN-2GP
RTS5229-GR-1-GP

7
8
9
10
11
12
AV12
RREF

DV33_18

1
15UP_17DY C3201
15UP_17DY

SC1U6D3V2KX-GP
15UP_17DY
SP5

2
CARD_DV12_S
RREF 1 2
CARD1_3V3 R3208
1

6K2R2F-GP
C3206
SCD1U16V2KX-3GP C3205 15UP_17DY
2

SC4D7U10V5ZY-3GP 3D3V_S0 CARD_DV12_S


1

1
15UP_17DY C3207 C3208 C3204
15UP_17DY SC4D7U10V5ZY-3GP C3203
SCD1U16V2KX-3GP

SC10U6D3V5KX-1GP

SCD1U16V2KX-3GP
2

2
15UP_17DY
15UP_17DY
B B

15UP_17DY
15UP_17DY

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Card Reader-RTS5229
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 32 of 103
5 4 3 2 1
5 4 3 2 1

D D

C
(Blanking) C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
1394
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 33 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 34 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 35 of 103
5 4 3 2 1
5 4 3 2 1

R3614
CRB : 1K
Power Sequence
R3623
28,42 IMVP_PW RGD 1 R3614 2 SYS_PW ROK 2 1
0R0201-PAD-GP 0R0402-PAD

3D3V_S5
D3603 U3608
1 SYS_PW ROK 19 5,46,47 RUNPW ROK 1 B
VCC 5
D 19,27 S0_PW R_GOOD 3 8,19,27,46,47,92 PM_SLP_S3# 2 A D

1
C3612 4 PW R_1D05V_1V_EN 45
SCD01U50V2KX-1GP Y
2 3 GND
BAS16-6-GP DY

2
83.00016.K11 74LVC1G08GW -1-GP
2ND = 83.00016.F11 73.01G08.L04
2ND = 73.7SZ08.DAH

DY

5V_S0 5V_S5

ANNIE Run Power


Run power follow TOP-1
DCBATOUT

C3607
U3604
1 S
2 S
D
D
8
7
5V_S0 5V_S5

2
1 2 3 S D 6
R3619 D
DY 5

1
330KR2J-L1-GP G C3613 C3614
SCD1U25V2KX-GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP

4
RUN_ENABLE QM3004M3-GP

2
C R3622 C3608 C
2 1 1 2
0R0402-PAD DY
84.30043.037

K
SCD1U25V2KX-GP

1
2nd = 84.02657.037
R3618 D3602
470R2J-2-GP MMPZ5239BPT-GP
83.9R103.D3F
2ND = 83.9R103.F3F 3D3V_S0 3D3V_S5 5V_S0

A
U3607
RUN_PW R_ON_G 1 S D 8

1
C3616 2 S D 7

1
3D3V_AUX_S5 C3615 1 2 3 S D 6 R3624
SCD01U50V2KX-1GP D 5 1KR2J-1-GP
2 78.10324.2FL DY SCD1U25V2KX-GP G
1

2
Q3603 R3612 QM3004M3-GP
6 1 100KR2J-1-GP C3609
1 2 1D5V_S0
5 2 DY

D
2

8,19,27,46,47,92 PM_SLP_S3# 84.30043.037


SCD1U25V2KX-GP MAX Current 3000 mA
4 3 PS_S3CNTRL 2nd = 84.02657.037 Q3605
PS_S3CNTRL Design Current 2100 mA 2N7002K-2-GP
DMN66D0LDW -7-GP 1D5V_S0 1D5V_S3
84.DMN66.03F R3621 U3605
0D75V_S0 Q3604 1 S D 8
1 2 22R2J-2-GP 6 1 C3611 2 S D 7 Total= 11.39A
1 2 3 S D 6

S
5 2 4 G D 5
B R3620 1D5V_S0 B
DY SCD1U25V2KX-GP
TPCA8062-H-GP PS_S3CNTRL
4 3 1 2
C3610
DMN66D0LDW -7-GP 1 2
220R2F-GP 84.08062.037
84.DMN66.03F DY
2ND = 84.00460.037
SCD1U25V2KX-GP

-1 0103 check Power list


H_THRMTRIP# 5,22
E

H_PW RGD_R B MMBT2222ALT1G-GP


Q3601
1

C3602 84.02222.X11
C

SCD1U10V2KX-5GP 2ND = 84.02222.V11


2

5,21,27,31,32,65,71,82,83,103 PLT_RST# R3616 2 1 4K7R2J-2-GP


1

R3632
2K2R2J-2-GP
2

83.R0304.D8F
A 2ND = 83.R2004.B8F <Core Design> A
D3601
3RD = 83.R3004.A8F
41 3V_5V_EN A K PURE_HW _SHUTDOW N# 27,28,86
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
CH751H-40-1-GP
1

R3603 2 1 2KR2F-3-GP Taipei Hsien 221, Taiwan, R.O.C.


S5_ENABLE 27
R3602
200KR2J-L1-GP Title
DY
Power Plane Enable
2

Size Document Number Rev


A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 36 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ADAPTER
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 37 of 103
5 4 3 2 1
5 4 3 2 1
Adaptor in to generate DCBATOUT
AD+
LIMIT_SIGNAL AD_JK
PU3802
SI7121DN-T1-GE3-GP
1 S D 8
2 S D 7
3 S D 6
D PWR_AD+_2 4 G D 5 D

2
PD3802 PC3807 DY

K
1

2
PC3808 SM24DTCT-GP-U SCD1U50V3KX-GP 84.07121.037

1
SC1KP50V2KX-1GP PD3803 PC3806 2ND = 84.06675.030

SCD1U50V3KX-GP
P6SMB27A-1-GP PR3807 1 2

200KR2F-L-GP

2
DY PC3805 SC1KP50V2KX-1GP

1
PQ3802 EC3801
DY

SCD1U25V2KX-GP
R2
DCIN1 E DY
DC_PIN2 2 1 DC_PIN1 83.P6SMB.KAG PWR_ADJK_EN B

2
R1
2ND = 83.P6SBM.DAG DY C
4 3 LIMIT_SIGNAL 83.0SM24.A11

1
6 5 2ND = 83.0024V.0A1 PQ3801 PDTA124EU-1-GP AD_JK AD+
8 7 C 84.00124.K1K DY DY PR3808 PG3801
10 9 B R1 100KR2J-1-GP 1 2
AD_JK 27 AD_OFF PWR_ADJK_EN 40
E
ACES-CONN10D-4-GP R2 GAP-CLOSE-PWR

2
PG3802
PDTC124EU-1-GP 2ND = 84.00024.01K
20.81633.010 1Pin=3A 84.00124.H1K
1 2

2nd = 20.81772.010
DY
C 2ND = 84.05124.011 GAP-CLOSE-PWR C
PG3803
-1 1222 PR3802 to save 100mW when battery full. 1 2

GAP-CLOSE-PWR
DC_PIN2 PG3804
PL3801 1 2
PQ3803_C 1 2 1 DY 2
PR3802 MLVS0402M04-GP GAP-CLOSE-PWR
510R2J-1-GP PG3805
PU3801 1 2

4 3 GAP-CLOSE-PWR
PG3806
27 DC_BATFULL 5 2 CHARGE_LED 27
ADD TEST PAD 1 2

6 1 GAP-CLOSE-PWR
PG3807
1 2
5V_AUX_S5 84.DM601.03F
DMN601DWK-7-GP PL3802 GAP-CLOSE-PWR
B 1 2 1 DY 2 LIMIT_SIGNAL 1 AFTP32 AFTE14P-GP B
PR3811 2nd = 84.2N702.E3F MLVS0402M04-GP
510R2J-1-GP DC_PIN2 1 AFTP33 AFTE14P-GP
DC_PIN1 DC_PIN1 1 AFTP34 AFTE14P-GP
AD_JK AD_JK
AC Present = White
200KR2F-L-GP

Standby = White pulsing 1 AFTP20 AFTE14P-GP


2
PR3809

1 AFTP23 AFTE14P-GP
Charging = Amber 1 AFTP24 AFTE14P-GP

*LEDs are off if no AC jack pluged in 1 AFTP25 AFTE14P-GP


1 AFTP26 AFTE14P-GP
1

-1 1222 PR3802 to save 100mW when battery full. 1 AFTP50 AFTE14P-GP


AD_DETECT 27 5V_AUX_S5
1
PR3810
34K8R2F-1-GP

PC3809 <Core Design>


SCD1U50V3KX-GP

PQ3804
2

CHARGE_LED G PR3803
E

D 1 2 B MMBT3906-4-GP Wistron Corporation


A A
1

PQ3803 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


84.T3906.A11 Taipei Hsien 221, Taiwan, R.O.C.
S
C

10KR2J-3-GP 2nd = 84.C3906.A11


2N7002K-2-GP 3rd = 84.03906.R11 Title
84.2N702.J31
2nd = 84.2N702.W31 PQ3803_C DCIN JACK
Size Document Number Rev
A4 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 38 of 103
5 4 3 2 1

D
BATT Connector D

BT+
close to conn. BATT EMI
BT+ EC3901 1 2 SCD1U50V3KX-GP
DY

K
1
PC3902 PD3911
SC2200P50V2KX-2GP P4SSMJ27APT-GP
DY Battry conn direction

A
1
AFTE14P-GP AFTP89 BAT1
9
1
C SRN33J-7-GP BT+ C

27 BAT_IN# 4 5 2
3 6 BAT_TH# 3
27,40 BAT_SDA 2 7 BAT_SDA0 4
27,40 BAT_SCL 1 8 BAT_SCL0 BAT_SCL0 5
BAT_SDA0 6
1

PC3905 PN3901 BAT_TH# 7


DY SCD1U50V3ZY-1-GP BT+ 8
10
2

1
EC3902 EC3903 EC3904
PD3901 SYN-CON8-23-GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP
MMPZ5232BPT-GP-U

2
83.5R603.D3F
2ND = 83.5R603.K3F DY DY DY 20.81713.008

A
3rd = 83.5R603.Q3F
2nd = 20.81717.008

3rd = 20.81761.008

-1 1226

Close to Batt Connector 3D3V_AUX_KBC

3D3V_AUX_KBC
D3902 D3901
B B

2 1 6 BAT_SCL0

BAT_TH# 3
2 5
1

BAV99PT-GP-U BAT_SDA0 3 4

83.00099.K11
BAV99S-GP
2ND = 83.00099.M11
83.00099.AAE
3RD = 83.00099.T11 2ND = 83.BAV99.AAE

ADD TEST PAD

BT+ 1 AFTP8 AFTE14P-GP


1 AFTP7 AFTE14P-GP
1 AFTP2 AFTE14P-GP
BAT_TH# 1 AFTP3 AFTE14P-GP
A BAT_SCL0 1 AFTP4 AFTE14P-GP <Core Design> A
BAT_SDA0 1 AFTP5 AFTE14P-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

BATT CONN
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 39 of 103
5 4 3 2 1
5 4 3 2 1

AD+_IN_P

PQ4009
2N7002A-7-GP AD+_IN_G

D
84.2N702.E31
2ND = 84.07002.I31
G
AD+ 84.30043.037 2ND = 84.02657.037 BT+
D D
QM3004M3-GP 84.30043.037 2ND = 84.02657.037 84.30043.037

S
PU4006 QM3004M3-GP 2ND = 84.02657.037 AD+_IN DCBATOUT QM3004M3-GP
PU4004 PR4001 PU4005
PR4031 PR4030 8 D S 1
1 2 1 2 7 D S 2 1 S D 8 1 2 8 D S 1
1MR2F-GP 3D3MR2J-GP 6 D S 3 2 S D 7 7 D S 2

1
510KR2F-GP
5 D PC4024 3 S D 6 PC4001 D01R3721F-GP-U 6 D S 3

SCD1U25V2KX-GP

SCD1U25V2KX-GP
G AD+_IN_P D 5 PR4004 5 D

1
G +VBAT_DEBUG G
DY DY

2
PC4023

SCD01U50V2KX-1GP
PC4025

2
1

1
1 2
PR4005 PR4006

1
SC2200P50V2KX-2GP AD+ GAP-CLOSE-PWR GAP-CLOSE-PWR PWR_CHG_BAT_BATDRV_R
PR4013 SC2200P50V2KX-2GP

2
2D2R5J-1-GP PC4002 1 2

1
DY

1
PR4003 PR4017 DCBATOUT
1 2 PR4009 PR4007 1 DY 2 20R5F-1GP
20R5F-1GP
430KR2F-GP 100KR2J-1-GP

2
PC4010 PC4005

2
SC2D2U25V5KX-1GP SCD1U25V2KX-GP PR4008
2

2
PR4033
4K02R2F-GP

2
2 1

1
38 PWR_ADJK_EN 0R0402-PAD-1-GP PC4008 PC4009

1
PC4007

SC1U25V3KX-1-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
PR4010 PR4011 PC4006 BQ24738_AGND 2 1

2
SCD1U25V2KX-GP
68KR2F-GP

PC4011
4K02R2F-GP PC4003

PWR_CHG_BAT_VCC
PC4004 1 2 SC1U16V3KX-5GP
PU4002
DY

5
6
7
8
SC1U16V3KX-5GP
SCD1U25V2KX-GP

D
D
D
D

QM3004M3-GP
-1 1220

A
PD4005 84.30043.037
BQ24738_AGND PU4001 BQ24738_AGND SD103AWS-1-GP

G
4

S
S
S
BQ24738_AGND PWR_CHG_BAT_ACN 1 20 83.1R504.A8F

K
3D3V_AUX_S5 ACN VCC
2ND = 83.1R004.H8F

3
2
1
11 PWR_CHG_BAT_BATDRV 3.3uH, 10*10*4
PWR_CHG_BAT_ACP BATDRV
2
C
ACP
16 PWR_CHG_BAT_REGN Rdc: C
PC4012

1
PWR_CHG_BAT_CMSRC REGN
AD+_IN_G 1 2 3
CMSRC TYP=10.8mohm MAX=11.8mohm
PR4015 PR4014 17 PWR_CHG_BAT_BTST 1 2
100KR2F-L1-GP 4K02R2F-GP PWR_CHG_BAT_ACDRV 4
BTST Idc=10A, Isat=16A
ACDRV PWR_CHG_BAT_HIDRV SCD047U25V3KX-3-GP BT+
18
PWR_CHG_BAT_ACDET HIDRV
6
2

ACDET
PWR_CHG_BAT_ILIM PL4001 PR4002
10
PC4013 ILIM PWR_CHG_BAT_PHASE PWR_CHG_BAT_PHASE_R 1
19 1 2 2
1

PHASE
SCD01U50V2KX-1GP

1
PR4018 PG4002 15 PWR_CHG_BAT_LODRV IND-3D3UH-57GP D01R3721F-GP-U
59KR2F-GP PWR_CHG_BAT_SDA 8 LODRV 68.3R310.20A
27,39 BAT_SDA 2 1

1
GAP-CLOSE-PWR-3-GP SDA 2ND = 68.3R31C.10P PC4017
14
2

5
6
7
8

1
PWR_CHG_BAT_SCL 9 GND PU4003 PC4015 PC4014 PC4016
27,39 BAT_SCL 2 1
2

2
D
D
D
D
SCL

SC10U25V5KX-GP
GAP-CLOSE-PWR-3-GP 13 PWR_CHG_BAT_SRP PG4003 PG4004 DY DY

2
SRP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
QM3004M3-GP
PG4001 PWR_CHG_BAT_ACOK 5

2
ACPRES PWR_CHG_BAT_SRN

GAP-CLOSE-PWR

GAP-CLOSE-PWR
12
27 AD_IA SRN
2 PR4022 1 PWR_CHG_BAT_IOUT 7 84.30043.037

GND

1
IOUT

G
BQ24738_AGNDBQ24738_AGND 0R0402-PAD-1-GP 4

S
S
S
PC4019

SC100P50V2JN-3GP
PWR_CHG_BAT_REGN BQ24738RGRR-GP

21

3
2
1
3D3V_AUX_S5
PR4021

1
PWR_CHG_BAT_REGN 74.24738.073 PC4020
R1 2 1 1 2
1

2
1
PR4019 90W_R1 3D3V_AUX_S5 SCD1U25V2KX-GP
10KR2F-2-GP 0R0402-PAD-1-GP PR4024 0R0402-PAD-1-GP
1

PR4029 2 1 PWR_CHG_BAT_SRP_R
PR4020 121KR2F-L-GP BQ24738_AGND
2

1
10KR2F-2-GP PR4025 0R0402-PAD-1-GP
2
27 PWR_CHG_ACOK# PR4016
R2 PR4035 2 1 PWR_CHG_BAT_SRN_R
1 2 100KR2J-1-GP
2

PQ4003 STOP_CHG# to KBC GPIO24


D

2N7002-7F-GP

2
23K7R2F-GP
2 PR4012 1 STOP_CHG# 27

1
BQ24738_AGND 0R0402-PAD-1-GP PC4021 PC4022

1
G PC4018 SCD1U25V2KX-GP SCD1U25V2KX-GP
5V_AUX_S5
-1 12/20

2
SC100P50V2JN-3GP
DY
S

2
Power request short pad
PC4027
5
6
7
8

B 1 2 B
PU4007 BQ24738_AGND
2IN-
2IN+

2OUT
VCC

SC100P50V2JN-3GP LM393DR-GP
BQ24738_AGND
84.27002.N31
2ND = 84.2N702.X31
BQ24738_AGND BQ24738_AGND
1OUT
GND
1IN+
1IN-
4
3
2
1

1129_PU4007 Phase in 1st 74.00393.H21

BQ24738_AGND
74.00393.H21
2ND = 74.10393.A21
3RD = 74.00393.S21

3D3V_AUX_S5
PWR_CHG_BAT_ILIM
1

PR4032 HP AIRLINE COMBO PD4004


100KR2J-1-GP
3D3V_AUX_KBC
1 2 2
D

PQ4007 PC4026 SCD1U50V3KX-GP


2

A 2N7002A-7-GP A
3
1
PR4026
2 AIRLINE_VOLT 27 DY
G CHG_ON# 27 1
1

15K4R2F-GP AD<=17V, disable


PR4027
100KR2F-L1-GP charger function BAV99W-1-GP <Core Design>
S

AD+ Wistron Corporation


21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
84.2N702.E31
2ND = 84.07002.I31 Title

Charger_BQ24738
Size Document Number Rev
A2 1
Colossus
Date: Thursday, January 05, 2012 Sheet 40 of 103
5 4 3 2 1
5 4 3 2 1

3V_PW R 3D3V_S5 DCBATOUT DCBATOUT_5V


PG4119 DCBATOUT
1 2 PG4102
+VBAT_DEBUG 1 2
GAP-CLOSE-PW R RT8223_PW R

1
PG4120 AD+ GAP-CLOSE-PW R
PD4101
1 2 PR4122 PR4124 PW R_3V_ENTIP PC4126 PG4103
+VBAT_DEBUG_R ST15U25VM-1-GP
A K 1 DY 2 1 2 DCBATOUT 1 2

2
GAP-CLOSE-PW R 0R0603-PAD 77.C1561.02L

1
PG4121 1SS355GP-GP 33R5J-2-GP GAP-CLOSE-PW R

1
1 2 83.00355.F1F PR4123 PC4106 PR4101 PG4104

1
86K6R2F-GP
2ND = 83.00355.D1F DY PC4105 1 2 SC18P50V2JN-1-GP DY 1 2

SCD1U25V3KX-GP

K
D GAP-CLOSE-PW R BT+ 0R0603-PAD DCBATOUT_5V Acoustic 1125 D

2
PG4122 GAP-CLOSE-PW R
PD4103

2
1 2 PG4105
A K DY PD4104 1 2
GAP-CLOSE-PW R PDZ27B-3-GP

A
PG4123 1SS355GP-GP 83.27R03.E3F PW R_5V_ENTIP 45WUP_35WDY GAP-CLOSE-PW R
1 2 83.00355.F1F 2nd = 83.27R03.C3F PG4106

1
2ND = 83.00355.D1F PC4120 PC4122 PC4123 1 2

1
GAP-CLOSE-PW R

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
PG4124 PR4102 PC4107 GAP-CLOSE-PW R

2
1 2 51KR2F-L-GP DY SC18P50V2JN-1-GP

1
2
GAP-CLOSE-PW R PC4125

2
PG4125 ST15U25VM-1-GP

2
1 2 77.C1561.02L
GAP-CLOSE-PW R

DCBATOUT
RT8223M for 3V5V DCBATOUT_5V
-1 1220
RT8223_PW R

PU4102 PU4104

D 2 2
1

1
PC4108 PU4101 3 3
8
7
6
5

TPCC8067-H-GP PC4109 1 4 1 4
SC10U25V5KX-GP

D
D
D
D

SCD1U25V3KX-GP
84.08067.A37 45WUP_35WDY_65BOM 10 10
2

2
9 9
C
7 7 -1 1226 C
4
G 8 6
5
8 6
5
G

16
1 S
2 S
3 S

PU4103

VIN
PC4113 FDMS3600-02-RJK0215-COLAY-GP FDMS3600-02-RJK0215-COLAY-GP
S PC4112 SCD1U25V3KX-GP
Iomax=5A SCD1U25V3KX-GP
PR4103 PR4104 84.03664.037 84.03664.037
OCP>9A 2 1PW R_3V_BOOT_R1 2PW R_3V_BOOT9
4D7R3J-L1-GP BOOT2 BOOT1 22 PW R_5V_BOOT1 2PW R_5V_BOOT1_R
1 2
3V_PW R PW R_3V_HG 10 21 PW R_5V_HG 1R3J-L1-GP 5V_S5
UGATE2 UGATE1 PL4102
PL4101 1 2 PW R_3V_PH 11 20 PW R_5V_PH 1 2
IND-2D2UH-46-GP-U PHASE2 PHASE1 Iomax=20A
68.2R210.20B PW R_3V_LG 12 LGATE2 LGATE1 19 PW R_5V_LG
IND-D88UH-GP 45WUP_35WDY OCP>30A
1

PU4105
D
8
7
6
5

1
PC4119 2ND = 68.2R21A.20I TPCC8065-H-GP PT4101 PT4102 PT4103

ST330U6D3VDM-29-GP

ST330U6D3VDM-29-GP
D
D
D
D

ST220U6D3VDM-15GP PW R_3V_VO PW R_5V_VO PG4127


84.08065.B37 7 24
2

VOUT2 VOUT1 68.R8810.201

SE220U6D3VM-30-GP
PG4126

2
1

GAP-CLOSE-PWR-3-GP
PW R_3V_FB 5 2 PW R_5V_FB 2ND = 68.R8810.10G
FB2 FB1
GAP-CLOSE-PWR-3-GP

G RT8223_PW R 1 PR4105 2
77.C2271.00L 4 249KR2F-GP PR4111
G

2
2ND = 77.22271.27L 1 2PW R_5V3V_EN13 23 PW R_5V_PGD 1 2
1 S
2 S
3 S

RSMRST# 19
2

PR4106 100KR2F-L1-GP EN PGOOD 0R0402-PAD-1-GP


S PW R_3V_ENTIP6 1 PW R_5V_ENTIP
2VREF ENTRIP2 ENTRIP1
-1 0102 with power check 2VREF 3 REF PGND 15 77.52271.09L
1

PC4114 PW R_5V3V_TON 4 25 2ND = 77.92271.03L


B TONSEL GND B
SCD22U10V2KX-1GP

77.C3371.15L 77.C3371.15L

1
2ND = 77.23371.11L 2ND = 77.23371.11L
2
1

84.07692.A37 PW R_5V3V_SKIP 14 18 PW R_5V3V_ENC PR4107


SKIPSEL ENC
1

1
PR4109 0R2J-2-GP DY
PR4108 0R2J-2-GP FDMC7692 PR4110
DY
VREG3

VREG5

6K8R2F-2-GP Rdson=9.5~11.5mohm, 31K6R2F-GP

1 2
51125_FB1_R
Idc=10.6A, Qg=10~20nc
1 2

51125_FB2_R PC4115
2

2
DY PC4116 RT8223MZQW -GP-U SC18P50V2JN-1-GPDY
8

17

SC18P50V2JN-1-GP

2
3D3V_AUX_S5 5V_AUX_S5
3D3V_AUX_S5_5_51123

PG4128
2

PG4129

1
5V_AUX_S5_51123

1 2 1 2
1

PR4113
PR4112 PR4114 GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP 20KR2F-L-GP
10KR2F-2-GP 2VREF 2 1 PR4121
0R0402-PAD-1-GP

2
1 2
2

PR4115 3V_5V_EN 36
DY 0R0402-PAD-1-GP
3D3V_AUX_S5 1 2
0R2J-2-GP
1

DY PR4116 PC4117 PC4118


SC22U6D3V5MX-2GP

2 1
2

2
SC10U6D3V5KX-1GP

0R2J-2-GP
Vout=2*(1+R1/R2)
DY PR4117
Close to VFB Pin (pin5) 2VREF 2 1
A 0R2J-2-GP GND VREF VREG3 VREG5 <Core Design> A

2 PR4118 1
3D3V_AUX_S5
0R0402-PAD-1-GP SKIPSEL DEM PWM Ultrasonic Ultrasonic Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
PR4119 Taipei Hsien 221, Taiwan, R.O.C.
DY
2 1
0R2J-2-GP TONSEL 200k/CH1 300k/CH1 400k/CH1 400k/CH1 Title
250k/CH2 375k/CH2 500k/CH2 500k/CH2
RT8223M_5V/3D3V
Size Document Number Rev
A3 1
Colossus
Date: Thursday, January 05, 2012 Sheet 41 of 103
5 4 3 2 1
5 4 3 2 1

2 PR4266 1
28,36 IMVP_PWRGD 0R0402-PAD-1-GP
SSID = CPU.Regulator 5 H_PROCHOT#
2 PR4253 1
0R0402-PAD-1-GP PR4224 75R2F-2-GP
1D05V_S0

1 DY 2
7 VR_SVID_ALERT# Volterra's suggestion:
PR4225 130R2F-1-GP
7 H_CPU_SVIDDAT
1 2 The total output MLCC is 30x22uF for 3-PHASE VCC
PR4226 54D9R2F-L1-GP The total output MLCC is 20x22uF+4x10uF for 2-PHASE VCCAXG
1 2
7 H_CPU_SVIDCLK

45WUP_35W21.5R

45WUP_35W75KR

45WUP_35W706R
5V_S5
27,48 D85V_PWRGD

PR4204

PR4211

PR4205

PR4265

PR4207

PR4208

PR4209

PR4210
Boot Voltage PR4265 PR4204
PR4260 1D8V_S0 3D3V_S5

1
D 866KR2F-GP D

1
PR4262
0V 887ohm 825ohm

PR4201

825R2F-GP

0R0402-PAD-1-GP

100KR2J-1-GP

887R2F-L-GP

475R2F-L1-GP

147R2F-GP

20KR2F-L-GP

402R2F-GP
2

1
PR4231
PWR_VCORE_VIN_UVLO_R PC4211 10R2F-L-GP

2
SC1U16V2KX-GP

PWR_VCORE_VR_ENABLE
1V 215ohm 191ohm

2
1

2
1

115R2F-1-GP

45WUP_35W0R

45WUP_35W191R

45WUP_35W475R
PR4263 PC4214

442R2F-GP
PWR_VCORE_R_OSC
100KR2F-L1-GP

PWR_VCORE_R_SEL0

PWR_VCORE_R_SEL1
SCD1U10V2KX-5GP

PWR_VCORE_R_SEL6
PWR_VCORE_VR_READY2
PWR_VCORE_VR_READY1
PWR_VCORE_VR_TT#
PWR_VCORE_R_SEL4
1 2

2
2
PC4237 SCD1U10V2KX-5GP
PR4223
GND_1318
1 2

0R0402-PAD-1-GP

GND_1318

49

48
47
46
45
44
43
42
41
40
39
38
37
PWR_AXG_IPH2_2_R 44
PU4201
43 PWR_VCORE_IPH1_3_L

R_SEL6
VR_READY2
VR_READY1
VR_TT#
R_SEL4
ALERT#
VDIO
VCLK
VR_ENABLE

R_SEL0
R_SEL1
GND

R_OSC
PWR_AXG_IPH2_1_R 44
43 PWR_VCORE_IPH1_2_L 1D8V_S0
43 PWR_VCORE_IPH1_1_L
PWR_VCORE_VDD3 1 36 PWR_VCORE_R_SEL2 PR4230
VDD3 R_SEL2 PWR_VCORE_R_SEL3 1K96R2F-1-GP
2 35
VDD R_SEL3 PWR_VCORE_R_REF PR4247
PWR_VCORE_VIN_UVLO
3
VDD R_REF
34
PWR_AXG_IPH2_2
45WUP_35WDY
45WUP_35WDY PWR_VCORE__PWM3
4
VIN_UVLO IPH2_2
33
PWR_VCORE_R_SEL5
1 2 1 2
5 32
PR4220 43 PWR_VCORE__PWM3 PWR_VCORE__PWM2 PWM1_3 R_SEL5 PWR_AXG_PWM2_2 499R2F-2-GP
43 PWR_VCORE__PWM2 PWR_VCORE__PWM1
6
PWM1_2 PWM2_2
31
PWR_AXG_PWM2_1 PWR_AXG_PWM2_2 44 45WUP_35WDY
PR4241 1K96R2F-1-GP 7 30
499R2F-2-GP 43 PWR_VCORE__PWM1 PWR_VCORE__TP_FAULT#1 PWM1_1 PWM2_1 PWR_AXG_TS_FAULT#2 PWR_AXG_PWM2_1 44 PR4246
45WUP_35WDY 43 PWR_VCORE__TP_FAULT#1 PWR_VCORE_IPH1_3
8
TS_FAULT#1 TS_FAULT#2
29
PWR_AXG_IPH2_1 PWR_AXG_TS_FAULT#2 44
1 2 1 2 9 28 1 2 1 2
PR4232 1 PR4217 1 PWR_VCORE_IPH1_2 IPH1_3 IPH2_1 PWR_AXG_MRAMP2
2 21K96R2F-1-GP 10 27
PR4256 1 PWR_VCORE_IPH1_1 IPH1_2 MRAMP2
2499R2F-2-GP 1 2 11 26 PR4229 499R2F-2-GP

1
IPH1_1 SENSE2+

PR4257

PC4201

PC4202
499R2F-2-GP PWR_VCORE_MRAMP1 1K96R2F-1-GP 45WUP_35W1KR

SENSE1+
12 25

A2_OUT1

A3_OUT1
A3_OUT2

A2_OUT2
SENSE1-
MRAMP1 SENSE2-

A_ERR1

A_ERR2
PR4216 PR4218 PR4212

A2_IN1

A3_IN1

A3_IN2

A2_IN2

45WUP_35W15.4KR
1K96R2F-1-GP
PC4229 PC4228 PC4230 0R2J-2-GP 0R2J-2-GP
C
DY C

2
DY

DY
1

1
SC10P50V2JN-4GP

SC10P50V2JN-4GP

SC10P50V2JN-4GP

25K5R2F-GP

SC10P50V2JN-4GP

SC10P50V2JN-4GP
2

2
PR4261 PR4219 PR4258 VT1318MFQX-2-GP
PR4215 45WDY_35W0R

13
14
15
16
17
18
19
20
21
22
23
24
0R2J-2-GP0R2J-2-GP 14K3R2F-GP
DY DY 0R2J-2-GP
2

2
45WUP_35W15.8K

PWR_VCORE_A_ERR1
PWR_VCORE_A2_IN1
PWR_VCORE_A2_OUT1
PWR_VCORE_A3_IN1
PWR_VCORE_A3_OUT1
PWR_AXG_A3_OUT2
PWR_AXG_A3_IN2
PWR_AXG_A2_OUT2
PWR_AXG_A2_IN2
PWR_AXG_A_ERR2
2

2
DY DY DY
45WDY_35W0R 74.01318.B73 GND_1318

-1 1228 by power

PWR_AXG_SENSE2_P 2 PR4252 1 VCC_AXG_SENSE 8


PC4231 0R0402-PAD-1-GP
SC22P50V2JN-4GP GND_1318 PWR_AXG_SENSE2_N 2 PR4254 1
PC4236 VSS_AXG_SENSE 8
PR4251 0R0402-PAD-1-GP
2 1 2 1 45WUP_35W56PF 7 VCCSENSE 1 2 PWR_VCORE_SENSE_P
0R0402-PAD-1-GP

PC4232 PR4234 SC33P50V2JN-3GP


PR4235
PC4238
2 1VCORE_IN1_R0 VCORE_IN1_L0
DY 2
DY 1 1 2 2 1
PR4250
SC22P50V2JN-4GP 6K81R2F-1-GP
SC330P50V2JC-2-GP
7 VSSSENSE 1 2 PWR_VCORE_SENSE_N
30K1R2F-L-GP 0R0402-PAD-1-GP
PR4237 PR4236 PR4264
45WUP_35W220PF
1 2 1 2VCORE_IN1_R1 2 1 2 1

523R2F-GP 0R2J-2-GP 13K3R2F-L1-GP PR4233 PC4235 SC22P50V2JN-4GP PC4233 SC22P50V2JN-4GP


45WUP_35W845R 45WUP_35W1D78K 45WUP_35W20K 10KR2F-2-GP
1 2 1 2

PC4234
PR4255
PC4218 PR4244
1 2 AXG_IN2_L1 2 1 1 AXG_IN2_R0
DY 2 1
DY2
48D7KR2F-GP SC56P50V2JN-2GP 6K81R2F-1-GP SC22P50V2JN-4GP

B
45WUP_35W30.1K 45WUP_35W1KpF B

PR4249 PR4239
PR4240
PR4238 PC4213
1 2 1 2AXG_IN2_R1 1 2 1 2
1 2 VCORE_IPH1_R0 1 2 PR4245 10KR2F-2-GP
698R2F-GP 953R2F-GP
1K02R2F-1-GP 10K7R2F-GP
SCD01U16V2KX-3GP
45WUP_35W7.87K 45WUP_35W0R 45WUP_35W665R
45WUP_35W1.3K 45WUP_35W4.7nF
1 2
PG4201
GAP-CLOSE-PWR
PC4219
PR4243
GND_1318 1 2 AXG_IPH2_R0 1 2

SC2200P50V2KX-2GP 1K27R2F-L-GP

45WUP_35W10nF 45WUP_35W3.24KR
3D3V_S0
VCC_CORE
PR4222 SRN10KJ-5-GP
1 2 PWR_VCORE_MRAMP1 2 3 PWR_VCORE_VR_READY1
44K2R2F-1-GP 1 4 PWR_VCORE_VR_READY2

45WUP_35W60.4K RN4201

VCC_GFXCORE
PR4227
2 1 PWR_AXG_MRAMP2
45WDY_35W56.2K
56KR2F-GP

A A

1D05V_S0
<Core Design>
PR4206
1 2 PWR_VCORE_VR_TT#

62R2J-GP Wistron Corporation


1

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


PC4203 Taipei Hsien 221, Taiwan, R.O.C.
DY SC47P50V2JN-3GP
2

Title

DY VT1318_CPUCORE(1/3)
Size Document Number Rev
A2 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 42 of 103

5 4 3 2 1
5 4 3 2 1

5V_S5
5V_S5
Small caps close to slave for placement
Small caps close to slave for placement

PC4304

PC4305

PC4306

PC4307

PC4308

PC4309
SC1U10V2KX-1GP

SC1U10V2KX-1GP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

PC4330

PC4323

PC4321

PC4322

PC4326

PC4327
SC1U10V2KX-1GP

SC1U10V2KX-1GP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
1

1
D D

1
PC4310
SCD1U10V2KX-5GP PC4325

2
SCD1U10V2KX-5GP

2
45WUP_35WDY

C1

C2

C3

C4
1D8V_S0

C1

C2

C3

C4
PR4305 PU4301
0R0402-PAD-1-GP 1D8V_S0 PR4307 PU4303 45WUP_35WDY

VDDH

VDDH

VDDH

VDDH
1 2 TS_FAULT#_DR1 A1 B4 PWR_CORE_BT1 0R0402-PAD-1-GP 45WUP_35WDY
45WUP_35WDY
45WUP_35WDY 45WUP_35WDY

VDDH

VDDH

VDDH

VDDH
42 PWR_VCORE__TP_FAULT#1 TS_FAULT# BST TS_FAULT#_DR3 PWR_CORE_BT3
42 PWR_VCORE__TP_FAULT#1 1 2 A1
TS_FAULT# BST
B4 45WUP_35WDY

1
A4

1
VCC PC4301
H4 A4
VX#H4 SCD22U10V3KX-2GP VCC PC4329
H3 H4

2
1

1
PC4302 VX#H3 PC4328 VX#H4 SCD22U10V3KX-2GP
H2 H3

2
PWR_VCORE_PU4301_VDD VX#H2 VX#H3
SC4D7U10V3KX-GP B1
VDD VX#H1
H1 SC4D7U10V3KX-GP
PWR_VCORE_PU4303_VDD VX#H2
H2 45WUP_35WDY
F4 B1 H1
2

2
VX#F4 PWR_CORE_VX1 VDD VX#H1
F3 F4
VX#F3 VX#F4 PWR_CORE_VX3
F2 F3
VX#F2 VX#F3
42 PWR_VCORE_IPH1_1_L B2
ISENSE VX#F1
F1 45WUP_35WDY VX#F2
F2
D4 42 PWR_VCORE_IPH1_3_L B2 F1
1D8V_S0 VX#D4 ISENSE VX#F1
42 PWR_VCORE__PWM1 B3 D3 D4
PWM VX#D3 VX#D4
D2 42 PWR_VCORE__PWM3 B3 D3
VX#D2 1D8V_S0 PWM VX#D3
D1 D2
VX#D1 VX#D2
PR4301 D1
PC4303 74.01323.A7Z 74.01323.A7Z VX#D1
PR4304
1 2 1 2 A2 PC4324
GND
1 2 1 2 A2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCD1U25V2KX-GP GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
10R2F-L-GP SCD1U25V2KX-GP
VT1323SFCX-1-GP 10R2F-L-GP
E1 45WUP_35WDY
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
VT1323SFCX-1-GP

E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
45WUP_35WDY 45WUP_35WDY
PG4301
PG4303
1 2
1 2
C GAP-CLOSE-PWR C
GAP-CLOSE-PWR
GND_1323S_1
GND_1323S_3

5V_S5
Small caps close to slave for placement
PC4311

PC4314

PC4312

PC4313

PC4320

PC4319
SC1U10V2KX-1GP

SC1U10V2KX-1GP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
DY-35W
1

1
PC4318
SCD1U10V2KX-5GP
2

2
Iomax=94A
Itdc=56A
VCC_CORE
C1

C2

C3

C4

1D8V_S0 PR4306 PU4302


0R0402-PAD-1-GP
VDDH

VDDH

VDDH

VDDH

1 2 TS_FAULT#_DR2 A1 B4 PWR_CORE_BT2
42 PWR_VCORE__TP_FAULT#1 TS_FAULT# BST

45WUP_35WDY
1

A4
VCC 2ND = 68.5001N.10T
H4 PC4316
PL4301
1

1
PC4315 VX#H4 SCD22U10V3KX-2GP
H3 68.5001N.10Q
2

VX#H3
SC4D7U10V3KX-GP H2
PWR_VCORE_PU4302_VDD VX#H2 PR4303
B1 H1 5 6
2

VDD VX#H1
F4 100R2F-L1-GP-U
VX#F4 PWR_CORE_VX2
F3 3 4

2
VX#F3
F2
VX#F2
42 PWR_VCORE_IPH1_2_L B2 F1 1 2
ISENSE VX#F1
D4
VX#D4
42 PWR_VCORE__PWM2 B3 D3
1D8V_S0 PWM VX#D3 IND-50NH-21-GP
D2
VX#D2
VX#D1
D1 PL4301 and PL4302 Colay
B PR4302 B
PC4317 74.01323.A7Z
1 2 1 2 A2
GND 35WUP_45WDY
IND-50NH-16-GP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SCD1U25V2KX-GP
10R2F-L-GP
1 2
VT1323SFCX-1-GP
E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4

3 4

PG4302 PL4302

1 2

GAP-CLOSE-PWR
68.5001N.10M
GND_1323S_2
DY-45W
2nd = 68.5001N.10U

CPU35W DY=BLUE
CPU45W DY=RED

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VT1323_CPUCORE(2/3)
Size Document Number Rev
A2 1
Colossus
Date: Thursday, January 05, 2012 Sheet 43 of 103
5 4 3 2 1
5 4 3 2 1

D D

5V_S5

Small caps close to slave for placement

PC4403

PC4404

PC4405

PC4406

PC4407
SC1U10V2KX-1GP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
1

1
PC4408

SCD1U10V2KX-5GP

2
Iomax=46A
Itdc=38A

C1

C2

C3

C4
1D8V_S0 PR4403 PU4401 VCC_GFXCORE
0R0402-PAD-1-GP

VDDH

VDDH

VDDH

VDDH
1 2 TS_FAULT#_DR4 A1 B4 PWR_AXG_BT1
42 PWR_AXG_TS_FAULT#2 TS_FAULT# BST DY-35W
PR4402

1
A4

1
VCC PC4409 100R2F-L1-GP-U
H4
1

PC4401 VX#H4 SCD22U10V3KX-2GP


H3

2
VX#H3
SC4D7U10V3KX-GP H2
PWR_AXG_PU4401_VDD VX#H2
B1 H1
2

VDD VX#H1 PL4401


F4

2
VX#F4 PWR_AVG_VX1
F3 1 4
VX#F3
F2
VX#F2
42 PWR_AXG_IPH2_1_R B2 F1
ISENSE VX#F1
D4
1D8V_S0 VX#D4
42 PWR_AXG_PWM2_1 B3 D3 2 3
PWM VX#D3
D2
VX#D2 IND-240NH-GP
D1
74.01323.A7Z VX#D1
PR4401 BPW10040
PC4402
1 2 1 2 A2 45WUP_35WDY
GND
C C

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCD1U25V2KX-GP
10R2F-L-GP 68.2415N.101
VT1323SFCX-1-GP 2ND = 68.CTX17.101

E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
PG4401

1 2

GAP-CLOSE-PWR

GND_1323S_4

PL4402
5V_S5
1 2
IND-D1UH-26-GP
Small caps close to slave for placement
35WUP_45WDY

PC4410

PC4413

PC4411

PC4412

PC4416
SC1U10V2KX-1GP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
1

1
PC4415
DY-45W
SCD1U10V2KX-5GP

2
45WUP_35WDY
C1

C2

C3

C4
1D8V_S0 PR4405 PU4402 45WUP_35WDY
0R0402-PAD-1-GP 45WUP_35WDY
45WUP_35WDY
45WUP_35WDY
45WUP_35WDY
VDDH

VDDH

VDDH

VDDH

1 2 TS_FAULT#_DR5 A1 B4 PWR_AXG_BT2
42 PWR_AXG_TS_FAULT#2 TS_FAULT# BST

1
A4
B VCC PC4418 B
H4
1

PC4417 VX#H4 SCD22U10V3KX-2GP


H3

2
VX#H3
SC4D7U10V3KX-GP H2
PWR_AXG_PU4402_VDD VX#H2
B1 H1
2

VDD VX#H1
VX#F4
F4 45WUP_35WDY PWR_AVG_VX2
F3
VX#F3
45WUP_35WDY VX#F2
F2
42 PWR_AXG_IPH2_2_R B2 F1
ISENSE VX#F1
D4
1D8V_S0 VX#D4
42 PWR_AXG_PWM2_2 B3 D3
PWM VX#D3
D2
VX#D2
D1
VX#D1
PR4404
PC4414 74.01323.A7Z
1 2 1 2 A2
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SCD1U25V2KX-GP
10R2F-L-GP
VT1323SFCX-1-GP
45WUP_35WDY
E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4

45WUP_35WDY 45WUP_35WDY

PG4402

1 2

GAP-CLOSE-PWR

GND_1323S_5

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

VT1323_CPUCORE(3/3)
Size Document Number Rev
A2 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 44 of 103

5 4 3 2 1
5 4 3 2 1

Iomax=16A
OCP>26A
D D

5V_S5 1D05V_S0
PL4501

1
PC4512 PC4513 PC4514 PC4515 PC4516 PC4517 1 2

1
PC4501 PC4502 PC4503 PC4504 PC4505 PC4506 PC4507 PC4508 PC4518 PC4519 PC4520 PC4521
IND-D42UH-6-GP

PWR_VCCP_SW

2
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
68.R4210.20C

1
PC4509
4D7R2J-2-GP

2
PC4510

2
SCD22U10V3KX-2GP

17

16
8

1
PU4501 PC4511

1
SC560P50V2KX-2GP

VIN#17

SW

VIN#16
PR4504
PR4525

2
3D3V_S5 2D2R3-1-U-GP
2 1 PW R_VCCP_VCCA 1 15 1 2 0D85V_EN 5,48
VCCA VBST PR4503

1
PR4528
0R0402-PAD-1-GP PC4525 2 14 PW R_VCCP_VBST 1 2 2 1 3D3V_S0
SC1U6D3V2KX-GP PW R_VCCP_COMP 3 GND PGOOD VCCP_RUN ON PR4501 1 0R0402-PAD
13 2

2
COMP EN 0R0402-PAD-1-GP PW R_1D05V_1V_EN 36
PW R_VCCP_VFB PW R_VCCP_FET 10KR2J-3-GP
4 12
SC1800P50V2KX-1GP

VFB FSET PW R_VCCP_MODE


5 VOUT MODE 11
C GND_1003055 6 10 PW R_VCCP_IMON C
SS IMON

1
PW R_VCCP_SS
PC4526 PR4524
1

1
PGND

PGND
PC4522 PC4529
2

2
PC4528 1 2 1 2 SC1U6D3V2KX-GP

2
PR4523 PR4527
2

22K1R2F-L-GP
2KR2F-3-GP SN1003055RUW R-GP DY 0R2J-2-GP

9
SCD01U16V2KX-3GP
SC680P50V2KX-2GP 5K6R2F-2-GP

2
1

1
2

PC4527

2
PR4521

1
0R0402-PAD-1-GP 1 2 PC4524 PR4526
0R0402-PAD-1-GP GND_1003055
74.10355.043
1

2
SC100P50V2JN-3GP

1
GND_1003055 PG4501
1 2

GAP-CLOSE-PW R
GND_1003055 GND_1003055

Close to pin4
1

PR4529 PR4522
3K09R2F-1-GP20KR2F-L-GP
2

B B

VSSP_SENSE 7

VTT_SENSE 7

Differential

<Variant Name>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SN1003055RUWR
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 45 of 103

5 4 3 2 1
5 4 3 2 1

SSID = PWR.Plane.Regulator_1p5v0p75v

D D

5
3D3V_S0

1D5V_S3 / 0D75V_S0

1
R3710
83.R0304.D8F 10KR2J-3-GP
2ND = 83.R2004.B8F
3RD = 83.R3004.A8F

2
D3705
K A 0D75V_EN PR4615
8,19,27,36,47,92 PM_SLP_S3#
0D75V_EN 2 1 PWR_0D75V_EN
0R0402-PAD-1-GP

2
CH751H-40-1-GP
C3705
SCD47U25V3KX-1GP

1
R&C delay

-1 0102 by Power
PR4604
PWR_1D5V_VCC5 2 1 5V_S5
5D1R2F-GP

1
PC4606 DCBATOUT
SC1U10V2KX-1GP
PR4603

2
1

1
SC1KP50V2KX-1GP
PC4602 10K7R2F-GP

1
PR4610 PC4607 PC4611
1 2 PWR_1D5V_EN

2
19,27 PM_SLP_S4#

SC10U25V5KX-GP

SC10U25V5KX-GP
0R0402-PAD-1-GP

2
PWR_1D5V_VDDP 1 PR4605 2 5V_S5

2
1

C PC4612 0R0603-PAD C

1
DY SCD1U10V2KX-5GP
PC4601
2

SC1U10V2KX-1GP PU4602

5
6
7
8
PWR_1D5V_CS

D
D
D
D
3D3V_S0 TPCC8067-H-GP

1
PR4602 84.08067.A37

13

11

12
100KR2J-1-GP

G
PU4601 4

S
S
S
74.08207.C73 PC4609

CS

VDDP
VDD
PR4606
Close to pin19
2

3
2
1
18 PWR_1D5V_BOOT
1 2 PWR_1D5V_PHASE_L 1 2
BOOT 2D2R3-1-U-GP
5,36,47 RUNPWROK 10 Iomax=13A, OCP>20A.
PR4616 PGOOD SCD1U25V3KX-GP
1 2 PWR_1D5V_TON 9 17 PWR_1D5V_UGATE
DCBATOUT TON UGATE
620KR2F-GP
PWR_1D5V_EN 8 1D5V_S3
S5 PL4601
PWR_0D75V_EN 7 16 PWR_1D5V_PHASE 1 2
S3 PHASE
PG4606
1 2 PWR_1D5V_VTTIN 19
1D5V_S3 VLDOIN COIL-D82UH-2-GP PC4613
1

GAP-CLOSE-PWR PC4603 15 PWR_1D5V_LGATE DY PT4601

1
SC10U6D3V3MX-GP LGATE
68.R8210.10V

SC1U16V3KX-5GP

ST330U2D5VDM-9GP
2

5
6
7
8
2nd = 68.R6810.10Z

2
D
D
D
D
1 14 PU4603
VTTGND PGND
TPCC8062-H-GP 77.23371.13L
5 PWR_1D5V_VDDQ 84.08062.A37 2nd = 79.33719.L01
VDDQ

G
4 -1 1220 3rd = 77.23371.13L

S
S
S
PWR_1D5V_FB
Close to pin19 0D75V_S0 20 6

1
VTT FB
DY

3
2
1
1
2 PR4608
VTTSNS
VTTREF

30K9R2F-GP PC4610
SC18P50V2JN-1-GP
R1
GND

GND

2
PG4608

2
1 2 PWR_1D5V_VDDQ
1D5V_S3
RT8207MZQW-GP-U
21

GAP-CLOSE-PWR

1
B B

R2 PR4609
30KR2F-GP
1PWR_1D5V_VTTREF

PR4607

2
1 2
+0.75VS 0R0402-PAD-1-GP
DDR_VREF_S3

Close to output cap pin1, not


Iomax: 1.2A PC4608 Close to PIN6 inside of the output cap
SCD033U16V2KX-GP
0D75V_S0
2

Vout=0.75*(1+R1/R2)
1

PC4604
SC10U6D3V3MX-GP
2

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8207MZ_1D5V & 0D75V


Size Document Number Rev
A2
Colossus 1
Date: Thursday, January 05, 2012 Sheet 46 of 103
5 4 3 2 1
5 4 3 2 1

RT8068A for 1D8V_S0


D D

3D3V_S5

PG4702
1 2

GAP-CLOSE-PW R-3-GP PU4701


Iomax=2.2A
PG4706
PW R_1D8V_PVDD
OCP>3.2A
1D8V_S0
1 2 10 PVIN LX#1 1 PL4701
PR4701
GAP-CLOSE-PW R-3-GP 1 2 9 2 PW R_1D8V_PHASE 1 2
PG4707 2D2R2F-GP PVIN LX#2 IND-2D2UH-207-GP

1
1 2 PW R_1D8V_SVIN 8 3 68.2R21D.10Y
SVIN LX#3

1
1 DY PC4703

1
GAP-CLOSE-PW R-3-GP PC4701 SC1U6D3V2KX-GP 7 2ND = 68.2R21A.201 PR4703 PC4705

2
NC#7

1
SC10U6D3V3MX-GP
PC4702 PW R_1D8V_S0_EN 5 20KR2F-L-GP
EN R1

1
SC10U6D3V3MX-GP
6 PC4706 PC4707
2

2
FB

SC100P50V2JN-3GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
5,36,46 RUNPW ROK 4

2
PGOOD
11

2
GND
RT8068AZQW ID-GP-U PW R_1D8V_FB

74.08068.A43

1
8,19,27,36,46,92 PM_SLP_S3# 1 PR4702 2 2ND = 74.05671.043
C 0R0402-PAD-1-GP PR4704 C
10KR2F-2-GP R2
Vo=0.6*(1+(R1/R2))

2
1
PC4704
SC22P50V2GN-GP

2
DY

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8068A_1D8V
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 47 of 103
5 4 3 2 1
5 4 3 2 1

TPS51461 for VCCSA


D D
3D3V_S0

1
5V_S5 PR4808
100KR2J-1-GP
VID0 VID1 VCCSA

2
1
PR4809

1
PR4806 PC4814 D85V_PW RGD_C 2 1 D85V_PW RGD 27,42 L L 0.9V
1R2F-GP SC1U10V2KX-1GP 0R0402-PAD-1-GP

2
PR4812 1 DY 2 1KR2F-3-GP L H 0.8V

2
PW R_VCCSA_VID1 2 PR4804 1 VCCSA_SEL 8
0R0402-PAD-1-GP H L 0.725V

1
PC4816 PW R_VCCSA_VID0 2 PR4805 1 H_FC_C22 8
SC2D2U10V3KX-1GP 0R0402-PAD-1-GP
H H 0.675V

2
PW R_VCCSA_EN 2 PR4801 1
0R0402-PAD-1-GP 0D85V_EN 5,45

1
PC4804
PWR_VCCSA_V5DRV DY SC1U6D3V2KX-GP

2
18
17
16
15
14
13
PU4801
C C

VID1
VID0
PGOOD

EN
V5DRV
V5FILT
SCD1U25V3KX-GP Design Current =6 A
19 PR4807 PC4805
5V_S5 20
PGND
12 PW R_VCCSA_BST 1 2 PW R_VCCSA_BST_R 1 2
6.6A<OCP< 7.8A
PG4801 PGND BST 0R0603-PAD-1-GP
21 PGND SW#11 11
1 2 PW R_VCCSA_VIN 22 10 0D85V_PW R
VIN SW#10 PL4801 0D85V_PW R 0D85V_S0
23 VIN SW#9 9
GAP-CLOSE-PW R-3-GP 24 8 PG4810
VIN SW#8
1

PG4802 PC4801 PC4813 PC4815 25 7 PW R_VCCSA_SW 1 2 1 2


GND SW#7
1 2

COMP

MODE
SLEW
SC10U10V3MX-GP

SC10U10V3MX-GP

SC10U10V3MX-GP

VOUT
0D85V_S0
VREF
GND GAP-CLOSE-PW R
2

GAP-CLOSE-PW R-3-GP COIL-D47UH-9-GP PG4811


74.51461.043

1
PG4809 PC4809 PC4808 PC4810 PC4807 1 2
1 2 TPS51461RGER-GP PR4811
68.R4710.20G
1
2
3
4
5
6

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
100R2F-L1-GP-U GAP-CLOSE-PW R

2
SC22U6D3V5MX-2GP
GAP-CLOSE-PW R-3-GP 2ND = 68.R4710.20D PG4812
PWR_VCCSA_VREF
PWR_VCCSA_COMP

1 2

1
VCCUSA_SENSE 8
PW R_VCCSA_SLEW GAP-CLOSE-PW R
PG4813
1 2

2 PC4806 GAP-CLOSE-PW R
SCD01U50V2KX-1GP PG4814
1 2
1
1

GAP-CLOSE-PW R
PR4802 PG4815
B 4K99R2F-L-GP B
1 2

GAP-CLOSE-PW R
2

PG4816
PWR_VCCSA_COMP_1

1 2

GAP-CLOSE-PW R
PG4817
1 2

GAP-CLOSE-PW R
1

PC4817
SC3300P50V3KX-1GP
2
2

PC4802
SCD22U10V2KX-1GP
1

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51461_VCCSA
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 48 of 103
5 4 3 2 1
5 4 3 2 1

LVDS CONNECTOR
D_MIC by EMI LVDS Impedance:90 ohm LVDS1 AUO B156HB01 V0
48
3D3V_S0 EL4901 DCBATOUT_LCD
41 50
DMIC_DATA_C 1 2 DMIC_DATA 29 1
SBY100505T-601Y-N-GP
D 2 D

2
1

1
3 SC1U6D3V2KX-GP

1
RN9401 EC4908 4 C4905 C4902 DY C4901 SC1U6D3V2KX-GP
SRN2K2J-1-GP SC22P50V2JN-4GP 5 5V_S0_LOGO_BL SCD1U10V2KX-5GP

2
42 6

2
7 LCDVDD
8 3D3V_S0

3
4
9
LCD_SMBCLK 10
EL4902
LCD_SMBDATA 11 USB_CAMERA
DMIC_CLK_C 1 2 12 USB_CAMERA#
WEBCAM -1 12/22
DMIC_CLK 29
SBY100505T-601Y-N-GP 43 13
14 DMIC_DATA_RF2 ER4901 2 10R0402-PAD DMIC_DATA_C DMIC

1
15 DMIC_CLK_RF2 ER4902 2 10R0402-PAD DMIC_CLK_C
EC4909 16 LCD_BRIGHTNESS R4903 1 2 1KR2J-1-GP BKLT_CTL 20
SC22P50V2JN-4GP 17 BLON_OUT_C

2
DCBATOUT_LCD DCBATOUT 18 LCD_SMBCLK 20
19 LCD_SMBDATA 20
F4901 44 20
2 1 21
POLYSW -1D1A24V-GP-U 22
2

C4907 FUSE 23
24 TXOUTA_L0- 20
Main:69.50007.A41 25
SCD1U50V3KX-GP

TXOUTA_L0+ 20
1

69.50007.A31
26 TXOUTA_L1- 20
2nd = 69.50007.A41 Second:69.50007.A31 45 27 TXOUTA_L1+ 20
28 TXOUTA_L2- 20
29 TXOUTA_L2+ 20
30 TXCLKA_L- 20
C 31 C
TXCLKA_L+ 20 DCBATOUT_LCD
WEBCAM 32
33 TXOUTB_L0- 20
46 34 TXOUTB_L0+ 20
R4905 2 1 USB_CAMERA 35 TXOUTB_L1- 20
21 USB_PP10

1
0R0402-PAD 36 TXOUTB_L1+ 20
R4906 2 1 USB_CAMERA# 37 TXOUTB_L2- 20 EC4902 EC4901
21 USB_PN10

SC5D6P50V2CN-1GP
0R0402-PAD 38 TXOUTB_L2+ 20 RF RF

2
SC5D6P50V2CN-1GP
LCDVDD 39 TXCLKB_L- 20
40 TXCLKB_L+ 20
47 51
U4902 3D3V_S0 -1 12/20 Delete TR4901
G5285T11U-GP 49
Layout 40 mil IPEX-CONN40-2R-GP-U
3 OUT IN#4 4
2 LCDVDD
GND
20 LCDVDD_EN 1 5
EN IN#5 20.F1093.040
2

1
R4907 C4903 74.05285.07F 2ND = 20.F1289.040
1
SC4D7U6D3V3KX-GP

C4906 EC4904 EC4903


100KR2J-1-GP

SC4D7U6D3V3KX-GP

2ND = 74.09724.09F RF RF
2

2
SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP
1

B 3D3V_S0 B

1
EC4906 EC4905
RF RF

2
SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP
27 BLON_OUT 1 R4901 2 BLON_OUT_C
1KR2J-1-GP DMIC_DATA_RF2
DMIC_CLK_RF2
2

R4904 C4904

1
EC4910 EC4907
100KR2J-1-GP

SC100P50V2JN-3GP
2

RF RF
1

2
SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP
CAP CLOSED IN LVDS1

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LCD Connector
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 49 of 103
5 4 3 2 1
5 4 3 2 1

CRT Connector CRT DDCDATA & DDCCLK level shift


Pull High 5V Design on CRT Board
CRT1 D-SUB-15-136-GP 5V_CRT_S0 3D3V_S0 500mA
4 9 5V_HDMI
NC#4 VCC_CRT

1
11 NC#11 R5004

A
1
DDCDATA_ID1 12 CRT_DDCDATA_CON C5012 0R0402-PAD 5V_CRT_S0
D 15 CRT_DDCCLK_CON SCD01U16V2KX-3GP D5001 83.R5003.J8F D
DDCCLK_ID3
5 CH551H-30GP-GP

2
GND CRT_R
6 GND CRT_RED 1
CRT_G
2ND = 83.R5003.H8H
7 2

K
GND CRT_GREEN CRT_B 3D3V_S0
8 GND CRT_BLUE 3 3D3V_S0 -1 0102

3D3V_S0_DDC
10 GND
16 14 CRT_VSYNC_CON
GND VSYNC

8
7
6
5
17 13 CRT_HSYNC_CON
GND HSYNC

2
1
RN5003
RN5002 SRN10KJ-6-GP
20.20961.015 -1 0102 by ME SRN2K2J-1-GP

2ND = 20.21019.015

1
2
3
4
Q5001

3
4
ADD TEST PAD CRT_DDCDATA_CON CRT_IN#_R
20 CRT_DDC_DATA 1 6

CRT_DDCDATA_CON 1 AFTP9 AFTE14P-GP 2 5


CRT_DDCCLK_CON 1 AFTP10 AFTE14P-GP
CRT_R 1 AFTP11 AFTE14P-GP 3 4
CRT_G 1 AFTP12 AFTE14P-GP
CRT_B 1 AFTP13 AFTE14P-GP
CRT_VSYNC_CON AFTP14 AFTE14P-GP 2N7002KDW -GP
1 20 CRT_DDC_CLK
CRT_HSYNC_CON 1 AFTP15 AFTE14P-GP 84.2N702.A3F
CRT_IN#_R 1 AFTP18 AFTE14P-GP 2nd = 84.2N702.E3F
1 AFTP19 AFTE14P-GP 3RD = 84.2N702.F3F CRT_DDCCLK_CON
5V_CRT_S0 1 AFTP17 AFTE14P-GP

C C
CRT RGB L5001 68.00084.A71
20 PCH_RED R5005 1 2 CRT_RED_RR 1 2 CRT_R
0R2J-2-GP BLM15BB470SN1D-2GP
68.00084.A71 CRT_DDCDATA_CON
L5002
CRT_HSYNC_CON
20 PCH_GREEN R5006 1 2 CRT_GREEN_RR 1 2 CRT_G CRT_VSYNC_CON
0R2J-2-GP BLM15BB470SN1D-2GP CRT_DDCCLK_CON
L5003 68.00084.A71

1
C5008 C5009 C5010 C5011
20 PCH_BLUE R5007 1 2 CRT_BLUE_RR 1 2 CRT_B DY DY DY DY

SC100P50V2JN-3GP

SC100P50V2JN-3GP
SC18P50V2JN-1-GP

SC18P50V2JN-1-GP
0R2J-2-GP BLM15BB470SN1D-2GP

2
8
7
6
5

1
C5001 C5002 C5003 C5004 C5005 C5006
RN5004
SC8P50V2CN-3GP

SC8P50V2CN-3GP

SC8P50V2CN-3GP

SC8P50V2CN-3GP

SC8P50V2CN-3GP

SC8P50V2CN-3GP
SRN150F-1-GP
2

2
-1 1220
1
2
3
4

D5003

1 6 CRT_VSYNC_CON
B CRT EMI B
CRT_IN#_R EC5001 2 1 SCD1U25V2KX-GP 5V_S0 2 5 5V_S0
EC5002 2
DY
5V_CRT_S0 1 SCD1U25V2KX-GP
DY CRT_HSYNC_CON 3 4

BAV99S-GP

83.00099.AAE
CRT Hsync & Vsync level shift 5V_CRT_S0
2ND = 83.BAV99.AAE
1

C5007
73.1G125.0JH
SCD1U10V2KX-5GP

2ND = 73.1G125.D0G U5001


2

3RD = 73.07125.0AG 1 5
OE# VCC

20 CRT_HSYNC 2 A
3 GND Y 4

74AHCT1G125GW -1-GP

73.1G125.0JH
2ND = 73.1G125.D0G U5002
A 3RD = 73.07125.0AG 1 5 <Core Design> A
OE# VCC

20 CRT_VSYNC 2 RN5005
A HSYNC_5 CRT_HSYNC_CON
3 GND Y 4 VSYNC_5
1
2
4
3 CRT_VSYNC_CON Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
74AHCT1G125GW -1-GP SRN33J-5-GP-U Taipei Hsien 221, Taiwan, R.O.C.

Title

CRT_CONN
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 50 of 103
5 4 3 2 1
5 4 3 2 1

1 AFTP95 AFTE14P-GP

HDMI Level Shifter & CONNECTOR 5V_HDMI


HDMI_DATA2_R_C_CON 1
1 AFTP94

AFTP41
AFTE14P-GP

AFTE14P-GP
HDMI_CLK_R_C HDMI_CLK_R_C_CON HDMI_DATA1_R_C HDMI_DATA1_R_C_CON
HDMI CONN HDMI_DATA2_R_C#_CON 1 AFTP42 AFTE14P-GP

3
HDMI1 HDMI_DATA1_R_C_CON 1 AFTP37 AFTE14P-GP
TR5101 TR5103
FILTER-4P-49-GP FILTER-4P-49-GP 20 HDMI_DATA1_R_C#_CON 1 AFTP38 AFTE14P-GP

1 HDMI_DATA2_R_C_CON HDMI_DATA0_R_C_CON 1 AFTP43 AFTE14P-GP


D D
2 HDMI_DATA0_R_C#_CON 1 AFTP44 AFTE14P-GP
3 HDMI_DATA2_R_C#_CON
2

4
4 HDMI_DATA1_R_C_CON HDMI_CLK_R_C_CON 1 AFTP72 AFTE14P-GP
HDMI_CLK_R_C# HDMI_CLK_R_C#_CON HDMI_DATA1_R_C# HDMI_DATA1_R_C#_CON 5
69.10118.111 69.10118.111 6 HDMI_DATA1_R_C#_CON HDMI_CLK_R_C#_CON 1 AFTP81 AFTE14P-GP
7 HDMI_DATA0_R_C_CON
8 DDC_CLK_HDMI 1 AFTP80 AFTE14P-GP
9 HDMI_DATA0_R_C#_CON
HDMI_DATA0_R_C HDMI_DATA0_R_C_CON HDMI_DATA2_R_C HDMI_DATA2_R_C_CON 10 HDMI_CLK_R_C_CON DDC_DATA_HDMI 1 AFTP93 AFTE14P-GP
11
12 HDMI_CLK_R_C#_CON HPD_HDMI_CON 1 AFTP130 AFTE14P-GP
1

3
13
TR5102 TR5104 14 5V_HDMI 5V_S0
FILTER-4P-49-GP FILTER-4P-49-GP 15 DDC_CLK_HDMI
16 DDC_DATA_HDMI
17 F5101
18 2 1
19
2

1
21 C5102 FUSE-1D1A6V-4GP-U

SCD1U10V2KX-5GP
HDMI_DATA0_R_C# HDMI_DATA0_R_C#_CON HDMI_DATA2_R_C# HDMI_DATA2_R_C#_CON 69.50007.691
69.10118.111 69.10118.111 2nd = 69.50007.771

2
SKT-HDMI21-4-GP 3RD = 69.50007.C21

HPD_HDMI_CON
Close to GPU 22.10296.711
HDMI DISCRETE/ UMA Co-lay
2ND = 22.10296.751
C C5103 1 2 SCD1U10V2KX-5GP HDMI_CLK_R_C# C
20 HDMI_CLK_R# C5104 SCD1U10V2KX-5GP HDMI_CLK_R_C 3D3V_S0
20 HDMI_CLK_R 1 2

C5105 1 2 SCD1U10V2KX-5GP HDMI_DATA0_R_C#


20 HDMI_DATA0_R# C5106 SCD1U10V2KX-5GP HDMI_DATA0_R_C
20 HDMI_DATA0_R 1 2

3
1 2HDMI_HPD_B 1 Q5102
R5111 150KR2J-L1-GP PMBS3904-1-GP

2
1
C5110 1 2 SCD1U10V2KX-5GP HDMI_DATA1_R_C#
20 HDMI_DATA1_R# C5107 1 2
66.68136.08L=>680ohm for UMA
SCD1U10V2KX-5GP HDMI_DATA1_R_C R5110 84.03904.L06 HDMI_HPD_E 1 2 HDMI_PCH_DET 20
20 HDMI_DATA1_R 2nd = 84.03904.P11 R5128
66.47136.A8L=>470ohm for GPU 200KR2J-L1-GP DY

1
C5108 1 2 SCD1U10V2KX-5GP HDMI_DATA2_R_C# 0R0402-PAD
20 HDMI_DATA2_R# C5109 SCD1U10V2KX-5GP HDMI_DATA2_R_C R5112
1 2

2
20 HDMI_DATA2_R 20KR2F-L-GP

5V_S0
Close to HDMI Connector

2
8
7
6
5

8
7
6
5
RN5106 RN5107

3
SRN470J-5-GP SRN470J-5-GP
D5102
BAW 56-5-GP
1 83.00056.Q11
2
3
4

1
2
3
4
HDMI_PLL_GND 2nd = 83.00056.G11

DDC_DATA_PH1 2
3RD = 83.00056.K11

DDC_CLK_PH1
B B
3D3V_S0

S
4
3
3D3V_S0
Q5106
RN5101
SRN2K2J-1-GP 2N7002K-2-GP

Q5104

1
2

D
DDC_CLK_Q 4 S1 D1 3 DDC_CLK_HDMI
84.2N702.J31
RN5117 2ND = 84.2N702.W 31

HDMI_PLL_GND
5 G1 G2 2
20 PCH_HDMI_CLK 2 3
20 PCH_HDMI_DATA 1 4 6 D2 S2 1

SRN0J-6-GP
DDC_DATA_Q ME2N7002DKW -G-GP
84.2N702.F3F DDC_DATA_HDMI

A 2ND = 84.2N702.E3F <Core Design> A

Routing Guidelines: Wistron Corporation


21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm). Taipei Hsien 221, Taiwan, R.O.C.
The total delay on CTRLDATA should be longer than CTRLCLK. Title

HDMI Level Shifter/Conn


Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 51 of 103
5 4 3 2 1
5 4 3 2 1

D D

(Blanking)

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Display Port
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 52 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 53 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 54 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 55 of 103
5 4 3 2 1
5 4 3 2 1

SATA HDD1 Connector SATA HDD2 Connector


CHECK HDD conn model pin define_ME wire
HDD2
HDD1 22 21
22 21 1 NP1 SATA_TXP2_C 1 AFTP107 AFTE14P-GP
1 NP1
D SCD01U16V2KX-3GP 2 1 C5614 SATA_TXP0_C 2
17 SATA_TXP2 SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
2
2
2
3
1 C5623
1 C5622
SATA_TXP2_C
SATA_TXN2_C
SATA_TXN2_C 1 AFTP106 AFTE14P-GP D
17 SATA_TXP0 17 SATA_TXN2
SCD01U16V2KX-3GP 2 1 C5613 SATA_TXN0_C 3 SATA_RXN2_C AFTP96 AFTE14P-GP
17 SATA_TXN0
4 C5618 1
15DY_17UP SATA_RXN2_C 45
2 SCD01U16V2KX-3GP
1

C5616 1 2 SCD01U16V2KX-3GP SATA_RXN0_C 5


17 SATA_RXN2
C5619 1 2
15DY_17UP
SCD01U16V2KX-3GP SATA_RXP2_C 6 SATA_RXP2_C 1 AFTP97 AFTE14P-GP
17 SATA_RXN0 17 SATA_RXP2
C5615 1 2 SCD01U16V2KX-3GP SATA_RXP0_C 6 7
17 SATA_RXP0
7
15DY_17UP 8
8
3D3V_S0 15DY_17UP 9 1 AFTP104 AFTE14P-GP
3D3V_S0 3D3V_S0

1
9 C5602 C5603 10
1

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP
C5604 C5601 AFTP103 AFTE14P-GP
10 DY DY 11 1
SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP

DY DY 11 12

2
12 13 5V_S0 1 AFTP182 AFTE14P-GP
2

13 5V_S0 14
5V_S0 14 15
15 16

1
16 C5621 C5620 17

SC10U10V5KX-2GP

SCD1U10V2KX-5GP
C5605 C5606 17 TP5602 1FFS_INT1 18

SC10U10V5KX-2GP

SCD1U10V2KX-5GP
TP5601 1FFS_INT0 18 19

2
2 19 SATA_TXP0_C 1 AFTP111 AFTE14P-GP TPAD14-OP-GP 20 NP2

2
TPAD14-OP-GP 20 NP2 24 23
24 23 SATA_TXN0_C 1 AFTP110 AFTE14P-GP
SATA_RX- and SATA_RX+ Trace FOX-CON20-1-GP-U
FOX-CON20-1-GP-U SATA_RXN0_C 1 AFTP109 AFTE14P-GP
Length match within 20 mil
SATA_RXP0_C 1 AFTP108 AFTE14P-GP 20.F1546.020
20.F1546.020 15DY_17UP 15DY_17UP 2nd = 20.F1473.020
2nd = 20.F1473.020 3D3V_S0 1 AFTP184 AFTE14P-GP

1 AFTP185 AFTE14P-GP 15DY_17UP


C 5V_S0 1 AFTP183 AFTE14P-GP C

ODD Connector
3D3V_S0
3D3V_S0
1

1
ODD1 R5606 DY R5602
21 22 10KR2J-3-GP 10KR2J-3-GP
NP1 1
SATA Zero Power ODD
2

2
2
3
4
5 SATA_ODD_DET# SATA_ODD_DET# 22
6 SATA_ODD_DA#_C 2 1 SATA_ODD_DA# 21
7 0R2J-2-GP R5601
8 DY
B 9 DY B
1

10 ODD_PW R_5V C5617


SCD1U10V2KX-5GP

11
12 ODD_PW R_5V
2
1

C5624 5V_S0 U5601


13 100 mil
14 SC10U6D3V5KX-1GP
15 SATA_RXP4_C C5608 1 2 SCD01U16V2KX-3GP SATA_RXP4 17 1 8 ODD_PW R_5V
2

SATA_RXN4_C C5607 1 GND OUT#8


16 2 SCD01U16V2KX-3GP SATA_RXN4 17 C5609 2 IN#2 OUT#7 7
17 2 1 3 IN#3 OUT#6 6
18 SATA_TXN4_C C5611 1 2 SCD01U16V2KX-3GP SATA_TXN4 17 22 SATA_ODD_PW R_EN 4 5
EN/EN# OCB

1
19 SATA_TXP4_C C5612 1 2 SCD01U16V2KX-3GP SATA_TXP4 17 SC10U6D3V5KX-1GP C5610
NP2 20 SC10U6D3V5KX-1GP
23 24
When the drive is powered on, the FET to the MD/DA pin drive is OFF. SY6288CCAC-GP

2
When the drive is powered off, the FET to the MD/DA pin is ON
74.06288.079
FOX-CON20-1-GP-U
5V_S0 2nd = 74.02001.079
20.F1546.020
Current limit
2

2nd = 20.F1473.020 R5603


100KR2J-1-GP Active High
typ =>2A
1

SATA_ODD_DA#_C
ODD_PWRGT#

SUPPORT ZERO SATA ODD

A <Core Design>
A
6

4
D2

G1

S1

SATA_TXP4_C 1 AFTP99 AFTE14P-GP Q5601


ME2N7002DKW -G-GP
SATA_TXN4_C 1 AFTP98 AFTE14P-GP
84.2N702.F3F Wistron Corporation
D1
S2

G2

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


1

SATA_RXN4_C 1 AFTP100 AFTE14P-GP 2ND = 84.2N702.E3F Taipei Hsien 221, Taiwan, R.O.C.

SATA_RXP4_C 1 AFTP101 AFTE14P-GP Title

ODD_PW R_5V 1 AFTP102 AFTE14P-GP HDD/ODD


SATA_ODD_PW R_EN SATA_ODD_DA# Size Document Number Rev
1 AFTP186 AFTE14P-GP A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 56 of 103
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ESATA
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 57 of 103
5 4 3 2 1
5 4 3 2 1

Main Speaker Connector 5


SPK1

29 SPKR_R+ L5801 1 2
SPK Trace = 40mil SPKR_R+_R 1 SPKR_R+_R 1 AFTP105 AFTE14P-GP
PBY160808T-121Y-GP
29 SPKR_R- L5802 1 2 SPKR_R-_R 2 SPKR_R-_R 1 AFTP113 AFTE14P-GP
29 SPKR_L+ L5803 1 2 PBY160808T-121Y-GP SPKR_L+_R 3
29 SPKR_L- L5804 1 2 PBY160808T-121Y-GP SPKR_L-_R 4 SPKR_L+_R 1 AFTP114 AFTE14P-GP
D PBY160808T-121Y-GP D
6 SPKR_L-_R 1 AFTP112 AFTE14P-GP

1
68.00206.021
C5801 C5802 C5803 C5804
ACES-CON4-17-GP-U1

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP
2

2
20.F1621.004
EC5805 EC5806 EC5807 EC5808
2ND = 20.F1937.004

1
SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP
SPKR_R+_C

SPKR_R-_C

SPKR_L+_C

SPKR_L-_C

2
1

1
Colse to Codec R5801 R5802 R5803 R5804
3D3R2F-GP 3D3R2F-GP 3D3R2F-GP 3D3R2F-GP
2

2
C C

GAIN 18dB 2ND Speaker Connector


5V_S0

R5805
DFDY dB_G1
1 2
100KR2J-1-GP
R5806
1 2 dB_G0
DY 100KR2J-1-GP
1

R5807 R5808
100KR2J-1-GP 100KR2J-1-GP
DY
2

DFDY
5V_S0
B B
29,30 MUTE#

C5806
1

C5805 C5807
1

1
SC10U6D3V3MX-GP

SC1U16V3KX-5GP

OUT_R+ 1 AFTP115 AFTE14P-GP


2

DFDY
2

DFDY DFDY SCD1U16V2KX-3GP OUT_R- 1 AFTP116 AFTE14P-GP

OUT_L+ 1 AFTP118 AFTE14P-GP


2nd Speaker AMP
OUT_L- 1 AFTP117 AFTE14P-GP
13

15
9

7
8

GND C5809 1 2 1 R5809 2 U5801


DFDY DFDY 1K96R2F-1-GP SPK2
SDL#
SDR#

G0
G1
AVDD

PVDD
PVDD

near by CODEC 5
SCD047U16V2KX-1-GP SPK Trace = 40mil
16 2 OUT_L+ 1
C5810 1 SCD047U16V2KX-1-GP
FSPK_R1 INR+ OUTL+
29 FSPK_R 2 1 R5810 2DFDYFSPK_R+ 17 INR- OUTL- 5 OUT_L-
C5808 1 DFDY
2 1 R5811 21K96R2F-1-GP 20 DFDY 14 OUT_R+ 2
SCD047U16V2KX-1-GP 1K96R2F-1-GP INL+ OUTR+
DFDY DFDY 19 INL- OUTR- 11
OUT_R-
3 DFDY
4
NC#10

AGND

PGND
PGND

EC5801

EC5802

EC5803

EC5804
NC#6

C5811 1 2 FSPK_L1 1 R5812 2 FSPK_L+


GND

29 FSPK_L
DFDY DFDY1K96R2F-1-GP 6
1

SCD047U16V2KX-1-GP
A TPA2012D2RTJR-GP A
<Core Design>
6
10

18

12
4

21

ACES-CON4-17-GP-U1
SC820P50V2KX-1GP

SC820P50V2KX-1GP

SC820P50V2KX-1GP

DFDY
DFDY
2

DFDY
SC820P50V2KX-1GP

DFDY 20.F1621.004 Wistron Corporation


21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
-1:12/09 R58010.R58011 Change into R5810 R5811 2ND = 20.F1937.004 Taipei Hsien 221, Taiwan, R.O.C.

Title

SPEAKER CONN
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 58 of 103
5 4 3 2 1
5 4 3 2 1

close to XF1

D close to XF1 D
XF5901

C5906
13 12 RJ45-8
31 MDIN3
2 1 XRF_RDC 15 10 MCT2 1 2 MCT2_C
14 11 RJ45-7 C5901 SCD01U50V2KX-1GP
31 MDIP3 1CT:1CT
SCD01U16V2KX-3GP RJ45-5 SRN75J-1-GP
31 MDIN2 16 9
18 7 MCT3 1 2 MCT3_C
17 8 RJ45-4 C5902 SCD01U50V2KX-1GP 1 8
31 MDIP2 1CT:1CT
2 7
19 6 RJ45-6 3 6
31 MDIN1
21 4 MCT0 1 2 MCT0_C 4 5
20 5 RJ45-3 C5907 SCD01U50V2KX-1GP
31 MDIP1 1CT:1CT
RN5901
22 3 RJ45-2
31 MDIN0
24 1 MCT1 1 2 MCT1_C
23 2 RJ45-1 C5908 SCD01U50V2KX-1GP
31 MDIP0 1CT:1CT

XFORM-24P-60-GP

68.IH160.30A

2ND = 68.89246.301
C C

AMBER = LAN ACK

RJ451

B RJ451 B
31 W HITE_LED#
13 CHASSIS

31 AMBER_LED# AMBER_LED# 1 2 AMBER_R_LED# 9


R5902 3D3V_S5 10 AMBER
470R2J-2-GP
1

C5905 C5903 RJ45-1 1


SCD1U16V2KX-3GPDY DY SCD1U16V2KX-3GP
RJ45-2 2
2

RJ45-3 3
RJ45-4 4
RJ45-5 5
RJ45-6 6
RJ45-7 7
RJ45-8 8

W HITE_LED# 1 2 W HITE_R_LED# 11 -1 1220


(1)route on bottom as differential pairs.
R5901 5V_S5 12 WHITE
470R2J-2-GP 14 CHASSIS
(2)Tx+/Tx- are pairs. Rx+/Rx- are pairs.
WHITE 10/100 WHITE 10/100 (3)No vias, No 90 degree bends.
RJ45-LED-12P-14-GP-U1
(4)pairs must be equal lengths.
20 mils 22.10277.W 71
(5)6mil trace width,12mil separation.
2nd = 22.10177.N81
(6)36mil between pairs and any other trace.
RJ45-1 1 AFTP120 AFTE14P-GP (7)Must not cross ground moat,
except RJ-45 moat.
1 AFTP128 AFTE14P-GP RJ45-2 1 AFTP121 AFTE14P-GP

A 3D3V_S5 1 AFTP127 AFTE14P-GP RJ45-3 1 AFTP122 AFTE14P-GP <Core Design> A

RJ45-4 1 AFTP119 AFTE14P-GP


AMBER_R_LED# AFTP169 AFTE14P-GP
1
RJ45-5 1 AFTP123 AFTE14P-GP Wistron Corporation
W HITE_R_LED# 1 AFTP168 AFTE14P-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
RJ45-6 1 AFTP124 AFTE14P-GP Taipei Hsien 221, Taiwan, R.O.C.
5V_S5 1 AFTP129 AFTE14P-GP
RJ45-7 1 AFTP125 AFTE14P-GP Title

RJ45-8 1 AFTP126 AFTE14P-GP RJ45+Transformer


Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 59 of 103
5 4 3 2 1
5 4 3 2 1

SSID = Flash.ROM
SPI FLASH ROM (8M byte) for PCH & KBC
3D3V_S5 3D3V_SPI 3D3V_SPI 3D3V_S5
Notes:
D D
The total SPI interface signal between EC and PCH
0R0402-PAD
cant not exceed 6500mil. The mismatch between

1
C6001 C6002 C6003 DY C6004 R6011
3D3V_SPI
DY SC10U6D3V5KX-1GP SCD1U10V2KX-5GP 1 2 SPI signal must be within 500mil

SC10U6D3V5KX-1GP
2

2
SCD1U10V2KX-5GP
8
7
6
5
RN6001
SRN4K7J-10-GP

1
2
3
4

PCH
3D3V_SPI
U6002
PCH
17 PCH_SPI_CS#0
1 CS# VCC 8
17 PCH_SPI_MISO 1 2 SPI_SO 2 DO/IO1 HOLD#/IO3 7 SPI_HOLD_0#
R6001 33R2J-2-GP SPI_W P#3 6 PCH_SPI_CLK 17
WP#/IO2 CLK
4 GND DI/IO0 5 PCH_SPI_MOSI 17
C C

W 25Q64FVSSIG-GP

72.25Q64.F01
KBC
2nd = 72.25640.D01
-1_ 0102 R6007 0R2J-2-GP
1 2 EC_SPI_CS#_C 27
1 R6008 2 0R2J-2-GP
EC_SPI_DO_C 27
1 R6009 2 0R2J-2-GP
1
DY
R6010 2 0R2J-2-GP
EC_SPI_DI_C 27
DY EC_SPI_CLK_C 27
R6012 DY
2 1
DY
27 SPI_W P#_C
1 1 TP6005 AFTE14P-GP
0R2J-2-GP AFTE14P-GP TP6001
1 1 TP6006 AFTE14P-GP
AFTE14P-GP TP6002
1 1 TP6007 AFTE14P-GP
AFTE14P-GP TP6003
1 1 TP6008 AFTE14P-GP
AFTE14P-GP TP6004

B B
-1 1223 Reversed TP6001~TP6008 / R6007~R6010 is DY
1, 14mil, 75mil
Top
2 .

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Flash
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 60 of 103
5 4 3 2 1
5 4 3 2 1

RESERVED USB 2.0/3.0 BD


Power switcher Low active
SSID = USB
D USB30_VCCB D
5V_S5 U6101
100 mil
2 IN OUT1 7
OUT2 6
1

1
C6103 8 C6102 C6101
SCD1U10V2KX-5GP FLT1# TC6101
5 FLT2# DY

SCD1U16V2KX-3GP

SC10U10V5KX-2GP
ST100U6D3VBM-24-GP
DY
2

2
3 EN1# GND 1 77.81071.06L
4 EN2# GND 9
DY
R6101 TPS2060C-GP
DY
27,62 USB_PW R_EN# 2 1USB30B_ON#0 74.02060.A79
0R0402-PAD 2ND = 74.02182.079
LOW ACTIVE TYPE!!

C C

B B

<Core Design>

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB Power SW_USB IO


Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 61 of 103

5 4 3 2 1
5 4 3 2 1

Power switcher Low active USB 3.0 Connector


Pin definition
74.02060.A79 1 POWER
USB30_VCCA
5V_S5 2ND = 74.02182.079 U6201 2 USB 2.0 D-
100 mil
2 IN OUT1 7 3 USB 2.0 D+
OUT2 6
D 4 GND D

1
C6203 8 C6202 C6201
SCD1U10V2KX-5GP FLT1# TC6201
5 FLT2# DY 5 StdA_SSRX- SuperSpeed RX

SCD1U16V2KX-3GP

SC10U10V5KX-2GP
ST100U6D3VBM-24-GP
DY

2
3 EN1# GND 1 77.81071.06L 6 StdA_SSRX+
4 EN2# GND 9
R6214 7 GND
27,61 USB_PW R_EN# 2 1USB30A_ON#0
TPS2060C-GP 8 StdA_SSTX- SuperSpeed TX
0R0402-PAD
LOW ACTIVE TYPE!! 9 StdA_SSTX+
USB30_VCCA

USB3_1 USB3_2 1 AFTP166 AFTE14P-GP

USB30_VCCA 1 AFTP240 AFTE14P-GP


EC3602
USB30_VCCA USB3_RXN3_R 1 AFTP150 AFTE14P-GP
EC3601 2 1
USB32 USB3_RXP3_R 1 AFTP152 AFTE14P-GP
2 1 SCD1U25V2KX-GP
USB31 1 5 USB3_RXN3_R USB3_TXN3_R 1 AFTP149 AFTE14P-GP
VBUS STDA_SSRX- USB3_RXP3_R
SCD1U25V2KX-GP STDA_SSRX+ 6
1 5 USB3_RXN1_R USB3_TXP3_R 1 AFTP151 AFTE14P-GP
VBUS STDA_SSRX- USB3_RXP1_R USB_PN2_R USB3_TXN3_R
STDA_SSRX+ 6 2 D- STDA_SSTX- 8
USB_PP2_R 3 9 USB3_TXP3_R USB_PN2_R 1 AFTP153 AFTE14P-GP
USB_PN0_R USB3_TXN1_R D+ STDA_SSTX+
2 D- STDA_SSTX- 8
C USB_PP0_R 3 9 USB3_TXP1_R 10 USB_PP2_R 1 AFTP155 AFTE14P-GP C
D+ STDA_SSTX+ CHASSIS#10
11 CHASSIS#11 GND 4
10 CHASSIS#10 12 CHASSIS#12
11 4 13 7 USB3_RXN1_R 1 AFTP157 AFTE14P-GP
CHASSIS#11 GND CHASSIS#13 GND_DRAIN
12 CHASSIS#12
13 7 USB3_RXP1_R 1 AFTP154 AFTE14P-GP
CHASSIS#13 GND_DRAIN SKT-USB13-52-GP
USB3_TXN1_R 1 AFTP156 AFTE14P-GP
SKT-USB13-52-GP
22.10339.F81 USB3_TXP1_R 1 AFTP158 AFTE14P-GP

22.10339.F81 2ND = 22.10339.H01 USB_PN0_R 1 AFTP160 AFTE14P-GP


2ND = 22.10339.H01 3rd = 22.10339.K21 USB_PP0_R 1 AFTP162 AFTE14P-GP
3rd = 22.10339.K21 69.10103.041
C6207
SCD1U16V2KX-3GP FILTER-4P-6-GP
21 USB3_TXN3 2 1USB3_TXN3_L 3 4 USB3_TXN3_R

69.10103.041 2 1USB3_TXP3_L 2 1 USB3_TXP3_R


21 USB3_TXP3
C6204
SCD1U16V2KX-3GP FILTER-4P-6-GP C6206 Ultra Low Capacitance TVS Arrays
21 USB3_TXN1 2 1 USB3_TXN1_L 3 4 USB3_TXN1_R SCD1U16V2KX-3GP
TR6205 (Pin5.6.7.8 No Internal Connection)
21 USB3_TXP1 2 1 USB3_TXP1_L 2 1 USB3_TXP1_R
U6202 DY
C6205 USB3_RXN1_R 1 8USB3_RXN1_R
SCD1U16V2KX-3GP TR6204 USB3_RXP1_R L1#1L1#8
2 L2#2L2#7 7USB3_RXP1_R
B B
G1 GNDGND G2
USB3_TXN1_R 3 6USB3_TXN1_R
USB3_TXP1_R L3#3L3#6
4 L4#4L4#5 5USB3_TXP1_R
69.10103.041
RCLAMP0524P-GP
FILTER-4P-6-GP
21 USB3_RXP3 2 1 USB3_RXP3_R
69.10103.041
21 USB3_RXN3 3 4 USB3_RXN3_R
FILTER-4P-6-GP
Ultra Low Capacitance TVS Arrays
21 USB3_RXP1 2 1 USB3_RXP1_R TR6206
(Pin5.6.7.8 No Internal Connection)
21 USB3_RXN1 3 4 USB3_RXN1_R
U6203 DY
USB3_RXN3_R 1 8USB3_RXN3_R
TR6203 USB3_RXP3_R L1#1L1#8
2 L2#2L2#7 7USB3_RXP3_R
G1 GNDGND G2
USB3_TXN3_R 3 6USB3_TXN3_R
USB3_TXP3_R L3#3L3#6
-1 0103 by EMI 4 L4#4L4#5 5USB3_TXP3_R

-1 0103 by EMI
RCLAMP0524P-GP

69.10103.041

69.10103.041 FILTER-4P-6-GP
A 21 USB_PN2 3 4 USB_PN2_R <Core Design> A
FILTER-4P-6-GP
21 USB_PN0 2 1 USB_PN0_R 21 USB_PP2 2 1 USB_PP2_R

21 USB_PP0 3 4 USB_PP0_R Wistron Corporation


TR6202 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
TR6201 Taipei Hsien 221, Taiwan, R.O.C.

SWAP 0105 Title

SWAP 0105 USB3.0


Size Document Number Rev
A3 1
Colossus
Date: Thursday, January 05, 2012 Sheet 62 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Variant Name> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Resered(Bluetooth)
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 63 of 103
5 4 3 2 1
5 4 3 2 1

Finger Printer
D D

3D3V_S0 1 AFTP165 AFTE14P-GP

USB_PN8 1 AFTP167 AFTE14P-GP

USB_PP8 1 AFTP164 AFTE14P-GP

1 AFTP159 AFTE14P-GP

C C

5V_S0 1 AFTP180 AFTE14P-GP

FP1 20.K0721.006
ACES-CON6-52-GP
2ND = 20.K0382.006

8
3D3V_S0
6
USB_PP8 5
USB_PN8 4
3
2
5V_S0
U6401 DY 1
B B
21 USB_PN8 1 ESD I/O1 ESD I/O4 6 USB_PP8 21 7
2 GND VP 5 3D3V_S0
3 ESD I/O2 ESD I/O3 4

DFDY
IP4220CZ6-GP

-1 12/23 FP1 change source

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

Finger Print Conn


Size Document Number Rev
A4 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 64 of 103
5 4 3 2 1
5 4 3 2 1

SSID = Wireless

3D3V_S0_WLAN
Mini-Card--WLAN
3D3V_S5
D Half minicard D

2
C6505 C6503 C6504
C6501
CLOSED IN WLAN1
DY Mini-Card--WLAN

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

SCD01U16V2KX-3GP
1 2

1
3D3V_S0_WLAN 1D5V_S0
DY
R6501
SCD1U10V2KX-5GP Half minicard

S
2 1AOAC_EN#_R G 3D3V_S0_WLAN 1D5V_S0
27 AOAC_EN#

1
10KR2J-3-GP
2

C6502 Q6501 EC6501 EC6502 EC6503 EC6504


DY

SC2200P50V2KX-2GP

SC68P50V2JN-1GP

SC2200P50V2KX-2GP

SC68P50V2JN-1GP
SCD01U16V2KX-3GP
DY DMP2305U-7-GP

2
84.02305.G31 WLAN1
DY
1

2ND = 84.03419.031 53
R6502 NP1
27 WLAN_PME_DIS_C 1 2
3D3V_S0_WLAN 1 2
3 4
20 mil 0R3J-0-U-GP 5 6 DY_RF DY_RF DY_RF DY_RF
C 7 8 C
3D3V_S0 18 CLKRQ_WLAN#_C
9 10
18 CLK_PCIE_WLAN# 11 12
18 CLK_PCIE_WLAN 13 14
15 16

27 E51_RXD 17 18
27 E51_TXD 19 20 WIFI_RF_EN 27
21 22 PLT_RST# 5,21,27,31,32,36,71,82,83,103
18 PCIE_RXN4_WLAN 23 24
18 PCIE_RXP4_WLAN 25 26
27 28
29 30
18 PCIE_TXN4_WLAN 31 32
18 PCIE_TXP4_WLAN 33 34
35 36 USB_PN5_RFEL6501 2 1 USB_PN5 21
37 38 USB_PP5_RF EL6502 2 0R0402-PAD
1 USB_PP5 21
39 40 0R0402-PAD
41 42
B 43 44 WLAN_LED# 27 B
Pin Active Function 5V_S0 1 R6503 2
DY 45 46

1
47 48
5 High(3V) GPIO/BT_WAKE 0R2J-2-GP 49 50 R6505
20 High(3V) WIFI_Enable 27 BLUETOOTH_EN 2 R6504 1 51 52 4K7R2J-2-GP
0R0402-PAD NP2
47 Reserved BT_PRISEL(coexistence) 54

2
51 Reserved BTCX_STAT(coexistence) 3D3V_S0
SKT-MINI52P-58-GP-U
1-1 1226 del TR6501
20.F1697.052

2ND = 20.F1697.052
3RD = Main:62.10043.F91 <Core Design>

A
677869-FM8 Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1st 677869-FM8 Title
2nd 677869-AM8 MINICARD(WLAN+Bluetooth)/CONN
3rd 677869-BM8 Size Document Number Rev
4th 677869-LM8 A4 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 65 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 66 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 67 of 103
5 4 3 2 1
5 4 3 2 1

5V_S0
SSID = User.Interface Touchpad LED (Amber)
DRC5143Z0L-GP TPLED1
C TP_PWRLED_L 1 2 TP_PWRLED_R K A
D
On Keyboard LEDs 27 TOUCHPAD_LED B R1
R2
Q6803
E
R6806
330R2J-3-GP LED-O-63-GP
83.00193.J70
D

84.05143.011 2ND = 83.19217.J70


2ND = 84.00043.011
Cap locks LED (White)

1
DY EC6801
DRC5143Z0L-GP SCD1U25V2KX-GP

2
C CAP_LED#_Q 1 2 CAP_LED#_R1 69
27 CAP_LED B R1 R6801
E 1KR2J-1-GP
R2
Q6801

84.05143.011
2ND = 84.00043.011

C DRC5143Z0L-GP C
Mute LED (Amber) C MUTE_LED#_Q 1 2 MUTE_LED#_R1 69
29 MUTE_LED_CTRL B R1 R6802
E 330R2J-3-GP
R2
Q6802

84.05143.011
2ND = 84.00043.011

Wireless LED (White-On, Amber-Off)


5V_S0
1

B R6803 B
330R2J-3-GP

L6801 3D3V_S0
2

69 WIRELESS_AMBER# 1 DY 2
1
MLVS0402M04-GP
R6805
U6801 DY 100KR2J-1-GP
5V_S0 4 3
2

5 2 EC_WLAN_LED# 27
1

R6804 6 1
1KR2J-1-GP

DMN601DWK-7-GP L6802 <Core Design>


2

69 WIRELESS_WHITE# 1 DY 2
MLVS0402M04-GP
84.DM601.03F
Wistron Corporation
A 2nd = 84.2N702.E3F 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

LED Bard/Power Button


Size Document Number Rev
A4 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 68 of 103
5 4 3 2 1

KROW [0..7] 27

SSID = KBC KCOL[0..17] 27

KB_BL_DETECT A Cover Logo Backlight


Internal KeyBoard Connector HIGH = BL SKU
KB1
LOW = NON-BL SKU
33 KCOL16 1 AFTP227 AFTE14P-GP R6904
1 2
KCOL17 1 AFTP228 AFTE14P-GP DFDY0R2J-2-GP
D 1 KROW 1 KCOL15 1 AFTP189 AFTE14P-GP
5V_S0 Q6902
LOGO BACKLIGHT(LVDS1) D
KCOL10 1 AFTP190 AFTE14P-GP
KROW 7 KCOL11 AFTP191 AFTE14P-GP DMP2305U-7-GP
2
KROW 6 KCOL14
1
AFTP197 AFTE14P-GP
2nd = 84.03419.031R6905
3 1
4 KCOL9 KCOL13 1 AFTP211 AFTE14P-GP S D 5V_S0_LOGO_BL_L 1 DFDY
2 5V_S0_LOGO_BL
5 KROW 4 KCOL12 1 AFTP193 AFTE14P-GP 510R2J-1-GP

1
6 KROW 5 KCOL3 1 AFTP194 AFTE14P-GP

1
7 KCOL0 KCOL6 1 AFTP196 AFTE14P-GP DY C6905

G
1
8 KROW 2 KCOL8 1 AFTP202 AFTE14P-GP C6904 R6902 SCD1U10V2KX-5GP

2
KROW 3 KCOL7 AFTP221 AFTE14P-GP 10KR2J-3-GP
9
KCOL5 KCOL4
1
AFTP198 AFTE14P-GP
DY DY
10 1 DY

SCD1U10V2KX-5GP
2
11 KCOL1 KCOL2 1 AFTP199 AFTE14P-GP

2
12 KROW 0 KROW 0 1 AFTP200 AFTE14P-GP 2 1
13 KCOL2 KCOL1 1 AFTP201 AFTE14P-GP DY
14 KCOL4 KCOL5 1 AFTP214 AFTE14P-GP C6906
15 KCOL7 KROW 3 1 AFTP203 AFTE14P-GP SCD1U10V2KX-5GP
16 KCOL8 KROW 2 1 AFTP204 AFTE14P-GP
17 KCOL6 KCOL0 1 AFTP205 AFTE14P-GP
18 KCOL3 KROW 5 1 AFTP206 AFTE14P-GP
19 KCOL12 KROW 4 1 AFTP207 AFTE14P-GP Q6903
20 KCOL13 KCOL9 1 AFTP208 AFTE14P-GP G LOGO_BL_ON 27
21 KCOL14 KROW 6 1 AFTP209 AFTE14P-GP
22 KCOL11 KROW 7 1 AFTP210 AFTE14P-GP LOGO_BL_C D
23 KCOL10 KROW 1 1 AFTP220 AFTE14P-GP
24 KCOL15 CAP_LED#_R1 1 AFTP212 AFTE14P-GP S
25 KCOL16 MUTE_LED#_R1 1 AFTP213 AFTE14P-GP
26 KCOL17 W IRELESS_W HITE#
1 AFTP219 AFTE14P-GP 2N7002K-2-GP DY
27 W IRELESS_W HITE# 68 W IRELESS_AMBER#
1 AFTP215 AFTE14P-GP 84.2N702.J31
28 W IRELESS_AMBER# 68 KB_BL_DETECT_C1 AFTP216 AFTE14P-GP 2nd = 84.2N702.W 31
C 29 MUTE_LED#_R1 68 5V_S0 1 AFTP217 AFTE14P-GP C
30 CAP_LED#_R1 68
31 5V_S0
32 KB_BL_DETECT_C 27
LTB1
34
AFTE14P-GP AFTP231 1 5V_S0_LOGO_BL 4
PTW O-CONN32-GP 5V_S0_LOGO_BL 2
1
AFTE14P-GP AFTP233 1
20.K0661.032 3

1
EC6905
2nd = 20.K0660.032
Touch Pad ACES-CON2-20-GP

SCD1U25V2KX-GP
3rd = 20.K0676.032 DY

2
15FFUP_17DY
20.F1639.002
3D3V_S5 2nd = 20.F1841.002

3D3V_S5

2
1
EC6901 EC6902
Internal KeyBoard Backlight Connector DY RN6905

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
SRN4K7J-8-GP

2
2
1
5V_S0_KB_BL RN6901 20.K0721.006
5V_S0 Q6901 SRN4K7J-8-GP
TPAD1

3
4
DMP2305U-7-GP 2ND = 20.K0382.006
B 2nd = 84.03419.031 B
7
S D

3
4
KBL1 1
1

5 SRN33J-5-GP-U
R6903
1

C6902 27 TPCLK 2 3 TP_CLK 2


G
1

C6901 R6901 SCD1U10V2KX-5GP5V_S0_KB_BL 1 25V_S0_KB_BL_C 1 27 TPDATA 1 4 TP_DATA 3


2

10KR2J-3-GP 0R3J-0-U-GP
DY AFTE14P-GP AFTP192 RN6904 2 RN6902 PCH_SML0_CLK_C
4
1 2 3 5
SCD1U10V2KX-5GP

18 PCH_SMB_CLK
2

3 18 PCH_SMB_DATA 1 4 PCH_SML0_DATA_C 6
2

2 1 1 4 EC6904
AFTE14P-GP AFTP195 SRN33J-5-GP-U 8

2
C6903 6 10/6 TP Vendor request EC6903

SC5P50V2CN-2GP
SCD1U10V2KX-5GP RN6903 DY DY ACES-CON6-52-GP
27 KBC_CLK1 1 DY 4

1
ACES-CON4-39-GP 2 3
27 KB_BL_ON_R# 27 KBC_DATA1

SC5P50V2CN-2GP
20.K0722.004 SRN33J-5-GP-U

2nd = 20.K0397.004
-1 12/23 TPAD1 change source
3rd = main: 20.K0722.004

-1 1223 KBL1 Change Source 3D3V_S5

1 AFTP223 AFTE14P-GP
A <Core Design> A
TP_DATA 1 AFTP187 AFTE14P-GP

TP_CLK 1 AFTP188 AFTE14P-GP Wistron Corporation


21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1 AFTP222 AFTE14P-GP Taipei Hsien 221, Taiwan, R.O.C.

Title
PCH_SML0_DATA_C1 AFTP229 AFTE14P-GP
Key Board/Touch Pad
Size Document Number Rev
PCH_SML0_CLK_C 1 AFTP230 AFTE14P-GP A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 69 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Hall sensor at Power BD )

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Hall Sensor
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 70 of 103
5 4 3 2 1
5 4 3 2 1

D D

DEBUG BD for Factory Test


3D3V_S0
DB1
11
1
RN7101
1 8 LPC_AD0_R 2
17,27 LPC_AD0 LPC_AD1_R
17,27 LPC_AD1 2 DY 7
LPC_AD2_R
3
17,27 LPC_AD2 3 6 4
4 5 LPC_AD3_R 5
17,27 LPC_AD3
17,27 LPC_FRAME# 6
SRN0J-5-GP 7
C
5,21,27,31,32,36,65,82,83,103 PLT_RST#
8 C

21,103 CLK_PCI_DEBUG 9
10
12

PAD-10P-177042-GP

ZZ.00PAD.Y41

-1 0102

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Dubug connector
Size Document Number Rev
A4 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 71 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 72 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 73 of 103
5 4 3 2 1
5 4 3 2 1

D D

2 IN1 CARD-READER (SD/MMC)

CARD1_3V3 CARD1_3V3_C
DY
F7401
1 2

FUSE-1D1A6V-4GP-U CARD1_3V3_C

F7402
1 2

1
C GAP-CLOSE-PWR C7401 C7402 C

SCD1U16V2KX-3GP

SC10U10V5ZY-1GP
15UP_17DY 15UP_17DY

2
CR1

Socket C7403~7406 pls close to chip 4 VDD CD_PIN 10 SD_CD# 32


WP_PIN 12 SD_WP 32

32 SD_D0 7 DAT0 NP1 NP1


32 SD_D1 8 DAT1 NP2 NP2
32 SD_D2 9 DAT2
32 SD_D3 1 CD/DAT3
DY DY DY DY VSS 3
VSS 6
C7406

C7405

C7404

C7403
32 SD_CLK 5 CLK
CD#_WP_PIN/GND 11
GND 13
32 SD_CMD 2 CMD GND 14
2

2
15UP_17DY
B B
SKT-SDCARD-24-GP-U1
1

SD_D0 1 AFTP170 AFTE14P-GP

62.10051.891
SC5P50V2CN-2GP

SC5P50V2CN-2GP

SC5P50V2CN-2GP

SC5P50V2CN-2GP

SD_D1 1 AFTP171 AFTE14P-GP

SD_D2 1 AFTP172 AFTE14P-GP

SD_D3 1 AFTP174 AFTE14P-GP

SD_CLK 1 AFTP173 AFTE14P-GP

SD_CMD 1 AFTP175 AFTE14P-GP

SD_CD# 1 AFTP177 AFTE14P-GP

SD_WP 1 AFTP176 AFTE14P-GP <Core Design>

CARD1_3V3_C 1 AFTP178 AFTE14P-GP

A 1 AFTP179 AFTE14P-GP
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CARD Reader CONN


Size Document Number Rev
A4 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 74 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Express Card
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 75 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 76 of 103
5 4 3 2 1
5 4 3 2 1

D D

(Blanking)
C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPM
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 77 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 78 of 103
5 4 3 2 1
5 4 3 2 1

D D

ACCELEROMETER
3D3V_S0_WLAN

1
C7901 C7902

SCD1U16V2ZY-2GP

SC4D7U6D3V3KX-GP
2

2
U7901
C C
R7903 1 10
VDD_IO RES#10
1 2 RES#13 13
0R2J-2-GP 14 15
VDD RES#15
D7901 RES#16 16

ADY K ACCEL_INT#_R 11 4 G_CLK


21 ACCEL_INT# INT1 SCL/SPC
9 6 G_DATA
INT2 SDA/SDI/SDO
1SS355GP-GP
1 R7901 2G_CS 8 CS SDO/SA0 7 G_SDO 1 DY 2
R7902 0R2J-2-GP
0R0402-PAD
2 NC#2 GND 5
3 NC#3 GND 12

3D3V_S0_WLAN
HP3DC2TR-GP
3D3V_S0_WLAN
74.HP3DC.ABZ
B B
Must be placed in the
center of the system
4
3

RN7901
SRN2K2J-1-GP

Q7901
1
2

G_CLK 1 6 SML1_CLK 18,27,29,86


2 5

3 4
<Core Design>
2N7002KDW-GP
SML1_DATA 18,27,29,86

A G_DATA
84.2N702.A3F Wistron Corporation A
2nd = 84.2N702.E3F 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
3RD = 84.2N702.F3F Taipei Hsien 221, Taiwan, R.O.C.

Title

ACCELEROMETER
Size Document Number Rev
A4 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 79 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 80 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 81 of 103
5 4 3 2 1
5 4 3 2 1

Card Reader BD 15"=DY 17"=PHASE IN USB BD(USB3.0*1+USB2.0*1)


CRBD1
13
3D3V_S0 USB3_TXN4 1 AFTP139 AFTE14P-GP
1
D 1 AFTP242 AFTE14P-GP USB30_VCCB UB1 USB3_TXP4 1 AFTP140 AFTE14P-GP D
3D3V_S0
2 21
3 PCIE_RXN2_MEDIA17 1 AFTP243 AFTE14P-GP USB3_RXP4 1 AFTP137 AFTE14P-GP
18 PCIE_RXN2_MEDIA17
18 PCIE_RXP2_MEDIA17 4 1
5 PCIE_RXP2_MEDIA17 1 AFTP244 AFTE14P-GP USB3_RXN4 1 AFTP138 AFTE14P-GP
18 PCIE_TXN2_MEDIA17 6 2
18 PCIE_TXP2_MEDIA17 7 PCIE_TXN2_MEDIA17 1 AFTP245 AFTE14P-GP 3 25 USB_PN3_1 1 AFTP142 AFTE14P-GP
18 CLK_PCIE_MEDIA17# 8 4
18 CLK_PCIE_MEDIA17 9 PCIE_TXP2_MEDIA17 1 AFTP246 AFTE14P-GP 5 USB_PP3_1 1 AFTP141 AFTE14P-GP
18 CLKREQ_MEDIA#17 10 21 USB3_TXN4 6
5,21,27,31,32,36,65,71,83,103 PLT_RST# 11 CLK_PCIE_MEDIA17# 1 AFTP247 AFTE14P-GP USB30 CONN 21 USB3_TXP4 7 USB_PN9_1 1 AFTP143 AFTE14P-GP
12 8
CLK_PCIE_MEDIA17 1 AFTP248 AFTE14P-GP 21 USB3_RXP4 9 USB_PP9_1 1 AFTP144 AFTE14P-GP
14 21 USB3_RXN4 10
CLKREQ_MEDIA#17 1 AFTP249 AFTE14P-GP 3D3V_S5 11 24 5V_S5 1 AFTP145 AFTE14P-GP
ACES-CON12-13-GP 21 USB_PN3_1 12
PLT_RST# 1 AFTP250 AFTE14P-GP 21 USB_PP3_1 13 USB30_VCCB 1 AFTP147 AFTE14P-GP
5V_S0 14
15DY_17UP 1 AFTP251 AFTE14P-GP 15 3D3V_S5 1 AFTP146 AFTE14P-GP
USB20 CONN 17 SATA_LED# 16
17 HDD_HALTLED 17 1 AFTP148 AFTE14P-GP
20.K0423.012 27 PW RLED
21 USB_PN9_1 18
21 USB_PP9_1 19 23 SATA_LED# 1 AFTP226 AFTE14P-GP
2nd = 20.K0426.012 5V_S5 20
HDD_HALTLED 1 AFTP252 AFTE14P-GP
22
PW RLED 1 AFTP225 AFTE14P-GP
FOX-CON20-3-GP
PW RLED 5V_S0 1 AFTP224 AFTE14P-GP
C C
HDD_HALTLED
20.F2030.020

SATA_LED# 2ND = 20.F2139.020


USB_PN3_2 1 AFTP234 AFTE14P-GP

1
USB_PP3_2 1 AFTP235 AFTE14P-GP
UB2
EC8202 EC8203 EC8204
7 USB_PN9_2 1 AFTP253 AFTE14P-GP

2
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
1
USB_PP9_2 1 AFTP254 AFTE14P-GP
2
POWER BUTTON BD 3D3V_AUX_KBC 21
21
USB_PN3_2
USB_PP3_2 3
4
15DY_17UP
21 USB_PN9_2 5
21 USB_PP9_2 6
1

8
3D3V_AUX_KBC 5V_S5 R8201
100KR2F-L1-GP
MLX-CON6-24-GP-U
1

C8201 C8202
2
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

20.F1352.006
2

LID_CLOSE#
For ESD 2nd = 20.F1804.006
-1 01/04
3RD = 20.F1639.006
EC8201
QUICKW EB_BTN# 1 2
B LID_CLOSE#
PW RLED
3
5
4
6
TOUCHPAD BD PAGE 69 B

KBC_PW RBTN# 7 8

QUICKW EB_BTN#_C 1 AFTP241 AFTE14P-GP SRC220P50VK-GP


-1 12/26
KBC_PW RBTN#_C 1 AFTP232 TPAD26-OP-GP ZZ.00PAD.0K1
PW R1
PW RLED_C 1 AFTP218 AFTE14P-GP ACES-CON8-40-GP
10
LID_CLOSE#_C 1 AFTP236 AFTE14P-GP 8 3D3V_AUX_KBC
7 5V_S5
3D3V_AUX_KBC 1 AFTP238 AFTE14P-GP 6 KBC_PW RBTN#_C 1 ER8201 20R0402-PAD-1-GP KBC_PW RBTN# 27
5 PW RLED_C 1 ER8202 20R0402-PAD-1-GP
AFTP237 AFTE14P-GP LID_CLOSE#_C PW RLED 27
5V_S5 1 4 1 ER8203 20R0402-PAD-1-GP LID_CLOSE# 27
3 QUICKW EB_BTN#_C 1ER8204 2 33R5J-2-GP QUICKW EB_BTN# 27
1 AFTP239 AFTE14P-GP 2 DY R8202
1 1 2 3D3V_AUX_KBC
9 DY
100KR2F-L1-GP

20.K0667.008
2ND = 20.K0665.008
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

IO Board Connector
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 82 of 103
5 4 3 2 1
5 4 3 2 1

1D05V_VGA_S0

D
dGPU Reset 3D3V_VGA_S0 1U Under GPU D
U8301 DIS_OPT
21 DGPU_HOLD_RST# 1 5
A VCC
DIS_OPTDIS_OPTDIS_OPTDIS_OPTDIS_OPT DIS_OPT DIS_OPT 4.7U NEAR TO GPU
5,21,27,31,32,36,65,71,82,103 PLT_RST# 2

1
B

SC10U6D3V5KX-1GP
3 4 C8332 C8331 C8319 C8321 C8322 C8334 C8335
GND Y

SC4D7U6D3V3KX-GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
10U mid TO GPU

2
SC10U6D3V5KX-1GP
U74LVC1G08G-AL5-R-GP-U

1
73.01G08.EHG 3D3V_VGA_S0 VGA1A 1 OF 17
2ND = 73.7SZ08.EAH R8309
3RD = 73.01G08.L04 100KR2F-L1-GP 1/17 PCI_EXPRESS
R8306 1 DY 2 0R2J-2-GP Q8301

2
DY G AJ11

2
R8310 PEX_WAKE#
AG19
VGA_RST# PEX_IOVDD_1
18 CLKREQ_PEG_A# D DY 10KR2J-3-GP AJ12
PEX_RST# PEX_IOVDD_2
AG21
DIS_OPT PEX_CLKREQ# PEX_IOVDD_3
AG22
S AK12 AG24

1
2
PEX_CLKREQ# PEX_IOVDD_4
SC PEX_IOVDD_5
AH21
R8311 2N7002K-2-GP AL13 AH25
18 CLK_PCIE_VGA PEX_REFCLK PEX_IOVDD_6
10KR2J-3-GP AK13
3D3V_S5 18 CLK_PCIE_VGA# PEX_REFCLK#
PEG_RXP0 C8301 SCD22U10V2KX-1GP PEG_C_RXP0 AK14
1
PEG_RXN0 C8302
DIS_OPT
1 2
SCD22U10V2KX-1GP PEG_C_RXN0 AJ14 PEX_TX0
1 2
R8307 PEX_TX0# 1D05V_VGA_S0
1 2 0R2J-2-GP
DIS_OPT DIS_OPT PEG_TXP0
DIS_OPT PEG_TXN0
AN12
PEX_RX0
AM12 AG13
PEX_RX0# PEX_IOVDDQ_1
PEG_RXP1 C8303
DIS_OPT
SCD22U10V2KX-1GP PEG_C_RXP1 AH14 PEX_IOVDDQ_2
AG15

PEG_RXN1 C8304
1 2
SCD22U10V2KX-1GP PEG_C_RXN1 AG14 PEX_TX1 PEX_IOVDDQ_3
AG16 1U Under GPU
1 2
PEX_TX1# PEX_IOVDDQ_4
AG18 DIS_OPTDIS_OPTDIS_OPTDIS_OPTDIS_OPT DIS_OPTDIS_OPT
DIS_OPT AG25

1
PEG_TXP1 PEX_IOVDDQ_5
AN14 AH15
PEX_RX1 PEX_IOVDDQ_6

SC10U6D3V5KX-1GP
PEG_TXN1 AM14 AH18 C8329 C8330 C8318 C8320 C8323 C8336 C8337
PEX_RX1# PEX_IOVDDQ_7 4.7U NEAR TO GPU

SC4D7U6D3V3KX-GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
DIS_OPT AH26

2
PEX_IOVDDQ_8

SC10U6D3V5KX-1GP
PEG_RXP2 C8305 SCD22U10V2KX-1GP
1 2 PEG_C_RXP2 AK15 AH27
PEG_RXN2 C8306 SCD22U10V2KX-1GP PEG_C_RXN2 AJ15 PEX_TX2 PEX_IOVDDQ_9
1 2 AJ27
PEX_TX2# PEX_IOVDDQ_10
DIS_OPT PEG_TXP2 PEX_IOVDDQ_11
AK27 10U mid TO GPU
AP14 AL27
PEG_TXN2 PEX_RX2 PEX_IOVDDQ_12
AP15 AM28
PEX_RX2# PEX_IOVDDQ_13
PEG_RXP3 C8307
DIS_OPT
SCD22U10V2KX-1GP PEG_C_RXP3 AL16 PEX_IOVDDQ_14
AN28
4 PEG_TXP[0..7] 1 2
PEG_RXN3 C8308 SCD22U10V2KX-1GP PEG_C_RXN3 AK16 PEX_TX3
C 1 2 C
PEX_TX3#
4 PEG_TXN[0..7] DIS_OPT PEG_TXP3 AN15
PEG_TXN3 PEX_RX3
AM15
PEX_RX3#
PEG_RXP4 C8309
DIS_OPT
SCD22U10V2KX-1GP PEG_C_RXP4 AK17
1 2
PEG_RXN4 C8310 SCD22U10V2KX-1GP PEG_C_RXN4 AJ17 PEX_TX4
1 2
PEX_TX4#
DIS_OPT PEG_TXP4
PEG_RXP[0..7] 4 AN17
PEG_TXN4 PEX_RX4
AM17
PEX_RX4#
PEG_RXN[0..7] 4
PEG_RXP5 C8311
DIS_OPT
SCD22U10V2KX-1GP PEG_C_RXP5 AH17
1 2
PEG_RXN5 C8312 SCD22U10V2KX-1GP PEG_C_RXN5 AG17 PEX_TX5
1 2
PEX_TX5#
DIS_OPT PEG_TXP5 PEX_PLL_HVDD
AH12 3D3V_VGA_S0
AP17
PEG_TXN5 PEX_RX5
AP18 AG12
PEX_RX5# PEX_SVDD_3V3
PEG_RXP6 C8313
DIS_OPT
SCD22U10V2KX-1GP PEG_C_RXP6
1 2 AK18
PEG_RXN6 C8314 SCD22U10V2KX-1GP PEG_C_RXN6 AJ18 PEX_TX6
1 2
3.3V +/- 5%

1
PEX_TX6#
DIS_OPT PEG_TXP6 C8325 C8324 C8333
AN18
PEX_RX6 120mA

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
PEG_TXN6 AM18 DIS_OPT

2
PEX_RX6#
PEG_RXP7 C8315
DIS_OPT
SCD22U10V2KX-1GP PEG_C_RXP7 AL19
DIS_OPT DIS_OPT (See NV DG)
1 2
PEG_RXN7 C8316 SCD22U10V2KX-1GP PEG_C_RXN7 AK19 PEX_TX7
1 2
PEX_TX7#
DIS_OPT PEG_TXP7 AN20
PEG_TXN7 PEX_RX7
AM20
PEX_RX7#
AK20
AJ20
PEX_TX8
PEX_TX8#
X7R, Under GPU.
L4 NV_VCCSENSE 92
VDD_SENSE
AP20
AP21
PEX_RX8
PEX_RX8#
POWER IC
L5 NV_VSSSENSE 92
GND_SENSE
AH20
PEX_TX9
AG20
PEX_TX9#
AN21
PEX_RX9
AM21
PEX_RX9#
B AK21 B
PEX_TX10
AJ21
PEX_TX10#
P8
NC_3V3AUX
AN23
PEX_RX10
AM23
PEX_RX10#
AL22
PEX_TX11
AK22
PEX_TX11#
AP23
PEX_RX11 DY 1.05V +/- 3%
AP24
PEX_RX11#
AJ26 PEXTSTCLK_OUT 1 R8304 2 100R2J-2-GP 120mA
PEX_TSTCLK_OUT
AK23 AK26 PEXTSTCLK_OUT#
PEX_TX12 PEX_TSTCLK_OUT#
AJ23
PEX_TX12# (See NV DG)
AN24
PEX_RX12 1D05V_VGA_S0
AM24
PEX_RX12#
R8308
AH23
PEX_TX13

SC4D7U6D3V3KX-GP
AG23 AG26 VCC1R05VIDEO_PEX_PLLVDD 1 2
PEX_TX13# PEX_PLLVDD

SCD1U10V2KX-5GP

SC1U10V2KX-1GP
AN26

1
PEX_RX13 HCB1608KF-121T20-GP
AM26

1
PEX_RX13# C8326
AK24 R8303 C8327 C8328

2
AJ24
PEX_TX14
AK11 TESTMODE
1 2 10KR2J-3-GP OPT

2
PEX_TX14# TESTMODE
AP26
PEX_RX14 DIS_OPT
AP27
PEX_RX14# DIS_OPT DIS_OPT DIS_OPT
AL25
PEX_TX15
AK25
PEX_TX15# R8301
AN27 AP29 PEX_TERMP
1 2 2K49R2F-GP
PEX_RX15 PEX_TERMP
AM27
PEX_RX15#
DIS_OPT
N13P-GS-A1-GP

71.0N13P.00U 669120-001
A A

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_PCIE/STRAPPING(1/5)
Size Document Number Rev
A2
Colossus 1
Date: Wednesday, January 04, 2012 Sheet 83 of 103
5 4 3 2 1
5 4 3 2 1

LVDS Interface
VGA1K 11 OF 17
VGA1J 10 OF 17 6/17 IFPC
5/17 IFPAB
ALL PINS NC FOR GF117
D D
ALL PINS NC FOR GF117
AF8
IFPC_RSET
AN6 DVI/HDMI DP
IFPA_TXC#
AM6
IFPA_TXC
AJ8
IFPAB_RSET
AF7 I2CW_SDA AG2
IFPC_PLLVDD IFPC_AUX_I2CW_SDA#
AN3 I2CW_SCL AG3
IFPA_TXD0# IFPC_AUX_I2CW_SCL
AP3
IFPA_TXD0
IFPAB_PLLVDD AH8 AG4
IFPAB_PLLVDD TXC IFPC_L3#
AM5 TXC AG5
IFPA_TXD1# IFPC_L3
AN5
IFPA_TXD1
TXD0 AH4
IFPC IFPC_L2#
TXD0 AH3
IFPC_L2
AK6
IFPA_TXD2#
AL6 TXD1 AJ2
IFPA_TXD2 IFPC_L1#
TXD1 AJ3
IFPC_L1
AH6 TXD2 AJ1
IFPA_TXD3# IFPC_L0#
AJ6 TXD2 AK1
IFPA_TXD3 IFPC_L0

AH9
IFPB_TXC#
AJ9 AF6 P2
IFPB_TXC IFPC_IOVDD GPIO15
AG8

4
3
IFPA_IOVDD N13P-GS-A1-GP
AP5
IFPB_TXD4# RN8401
AG9 AP6
IFPB_IOVDD IFPB_TXD4
SRN10KJ-5-GP
DIS_OPT DIS_OPT
AL7

4
3
IFPB_TXD5#
AM7

1
2
RN8402 IFPB_TXD5
SRN10KJ-5-GP
DIS_OPT IFPB_TXD6#
AM8
AN8
IFPB_TXD6
1
2
AL8
IFPB_TXD7# VGA1L 12 OF 17
AK8
IFPB_TXD7
C 7/17 IFPD C

ALL PINS NC FOR GF117

N4 AN2
GPIO14 IFPD_RSET
IFPAB DVI/HDMI DP

N13P-GS-A1-GP
AG7 I2CX_SDA AK2
IFPD_PLLVDD IFPD_AUX_I2CX_SDA#
71.0N13P.00U DIS_OPT I2CX_SCL IFPD_AUX_I2CX_SCL
AK3

TXC AK5
IFPD_L3#
TXC AK4
IFPD_L3

TXD0 AL4
IFPD IFPD_L2#
TXD0 AL3
VGA1M 13 OF 17 IFPD_L2
8/17 IFPEF TXD1 AM4
IFPD_L1#
TXD1 AM3
IFPD_L1
ALL PINS NC FOR GF117
TXD2 AM2
IFPD_L0#
TXD2 AM1
IFPD_L0
DVI-DL DVI-SL/HDMI DP

AG6 M6
IFPD_IOVDD GPIO17
I2CY_SDA I2CY_SDA AB4
IFPE_AUX_I2CY_SDA#
I2CY_SCL I2CY_SCL AB3

4
3
IFPE_AUX_I2CY_SCL N13P-GS-A1-GP
AB8
IFPEF_PLLVDD RN8404
TXC TXC IFPE_L3#
AC5 SRN10KJ-5-GP
71.0N13P.00U DIS_OPT
AD6
IFPEF_RSET TXC TXC IFPE_L3
AC4 DIS_OPT
AC3
HDMI Interface

1
2
TXD0 TXD0 IFPE_L2#
AC2
TXD0 TXD0 IFPE_L2

TXD1 TXD1 AC1


IFPE_L1#
AD1
IFPE TXD1 TXD1 IFPE_L1
B AD3 B
TXD2 TXD2 IFPE_L0#
AD2
TXD2 TXD2 IFPE_L0

HPD_E HPD_E R1
GPIO18

IFPDE_PLL_IO_VDD AC7
IFPE_IOVDD
I2CZ_SDA AF2
IFPF_AUX_I2CZ_SDA#
I2CZ_SCL AF3
IFPF_AUX_I2CZ_SCL
AC8
IFPF_IOVDD
TXC AF1
IFPF_L3#
TXC AG1
4
3

IFPF_L3
RN8403 TXD3 TXD0 AD5
IFPF_L2#
SRN10KJ-5-GP TXD3 TXD0 AD4
IFPF_L2
DIS_OPT
TXD4 TXD1 AF5
IFPF TXD4 TXD1
IFPF_L1#
AF4
1
2

IFPF_L1
TXD5 TXD2 AE4
IFPF_L0#
TXD5 TXD2 AE3
IFPF_L0

HPD_F P3
GPIO19

N13P-GS-A1-GP
A A
71.0N13P.00U
DIS_OPT

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU Memory(2/5)
Size Document Number Rev
A2
Colossus 1
Date: Monday, December 26, 2011 Sheet 84 of 103

5 4 3 2 1
5 4 3 2 1

VGA1B 2 OF 17
2/17 FBA
VGA1C 3 OF 17
88 FBA_D[0..7] 3/17 FBB

90 FBB_D[0..7]
FBA_D0 L28 E1
FBA_D1 FBA_D0 FB_CLAMP
M29
FBA_D2 FBA_D1 FBB_D0
L29 G9
FBA_D3 FBA_D2 FBB_D1 FBB_D0
M28 E9
FBA_D4 FBA_D3 FBB_D2 FBB_D1
N31 G8
FBA_D5 FBA_D4 FBA_PLL_AVDD FBB_D3 FBB_D2
P29 K27 F9
FBA_D6 FBA_D5 FB_DLL_AVDD FBB_D4 FBB_D3
R29 F11
FBA_D7 FBA_D6 FBB_D5 FBB_D4
P28 Layout note:FBA_PLL_AVDD=16mil G11

SCD1U10V2KX-5GP
D
88 FBA_D[8..15] FBA_D7 FBB_D5 D
FBA_D8 J28 FBB_D6 F12
FBA_D9 FBA_D8 FBB_D7 FBB_D6
H29
FBA_D9 X7R 90 FBB_D[8..15] G12
FBB_D7

1
FBA_D10 J29 FBB_D8 G6
FBA_D11 FBA_D10 C8509 FBB_D9 FBB_D8
H28 F5
FBA_D12 FBA_D11 FBB_D10 FBB_D9
G29 DIS_OPT E6

2
FBA_D13 FBA_D12 FBB_D11 FBB_D10
E31 F6
FBA_D14 FBA_D13 FBB_D12 FBB_D11
E32 F4
FBA_D15 FBA_D14 FBB_D13 FBB_D12
88 FBA_D[16..23] F30 G4
FBA_D16 FBA_D15 FBB_D14 FBB_D13
C34
FBA_D16 Place close to Ball E2
FBB_D14
FBA_D17 D32 90 FBB_D[16..23] FBB_D15 F3
FBA_D18 FBA_D17 FBB_D16 FBB_D15
B33 C2
FBA_D19 FBA_D18 FBB_D17 FBB_D16
C33 D4
FBA_D20 FBA_D19 FBB_D18 FBB_D17
F33 D3
FBA_D21 FBA_D20 FBB_D19 FBB_D18
F32 C1
FBA_D22 FBA_D21 FBB_D20 FBB_D19
H33 B3
FBA_D23 FBA_D22 FBB_D21 FBB_D20
88 FBA_D[24..31] H32 C4
FBA_D24 FBA_D23 FBB_D22 FBB_D21
P34 B5
FBA_D25 FBA_D24 FBB_D23 FBB_D22
P32 90 FBB_D[24..31] C5
FBA_D26 FBA_D25 FBB_D24 FBB_D23
P31 A11
FBA_D27 FBA_D26 FBB_D25 FBB_D24
P33 C11
FBA_D28 FBA_D27 FBB_D26 FBB_D25
L31 D11
FBA_D29 FBA_D28 FBB_D27 FBB_D26
L34 B11
FBA_D30 FBA_D29 FBB_D28 FBB_D27
L32 D8
FBA_D31 FBA_D30 FBB_D29 FBB_D28
89 FBA_D[32..39] L33 A8
FBA_D32 FBA_D31 FBB_D30 FBB_D29
AG28 C8
FBA_D33 FBA_D32 FBA_CMD0 FBB_D31 FBB_D30 FBA_CMD19 FBB_CMD19
AF29 U30 91 FBB_D[32..39] B8
FBA_D34 FBA_D33 FBA_CMD0 FBA_CMD1 FBA_CMD0 88 FBB_D32 FBB_D31
AG29 T31 1 F24
FBA_D35 FBA_D34 FBA_CMD1 FBA_CMD2 TP8505 TPAD14-OP-GP FBB_D33 FBB_D32
AF28 U29 G23 D13
FBA_D35 FBA_CMD2 FBB_D33 FBB_CMD0

2
FBA_D36 FBA_CMD3 FBA_CMD2 88 FBB_D34 FBB_CMD1 FBB_CMD0 90 TP8515 TPAD14-OP-GP
AD30 R34 E24 E14 1
FBA_D37 FBA_D36 FBA_CMD3 FBA_CMD3 88 FBB_D35 FBB_D34 FBB_CMD1 R8517 R8518
AD29 R33 G24 F14
FBA_D38 FBA_D37 FBA_CMD4 FBA_CMD4 88,89 FBB_D36 FBB_D35 FBB_CMD2 FBB_CMD2 90
AC29 U32 D21 A12 10KR2J-3-GP 10KR2J-3-GP
FBA_D39 FBA_D38 FBA_CMD5 FBA_CMD5 88,89 FBB_D37 FBB_D36 FBB_CMD3 FBB_CMD3 90
89 FBA_D[40..47] AD28 U33 E21 B12
FBA_D40 AJ29
FBA_D39 FBA_CMD6
U28
FBA_CMD6 88,89 FBB_D38 G21
FBB_D37 FBB_CMD4
C14
FBB_CMD4 90,91 OPT OPT

1
FBA_D41 FBA_D40 FBA_CMD7 FBA_CMD7 88,89 FBB_D39 FBB_D38 FBB_CMD5 FBB_CMD5 90,91
AK29 V28 91 FBB_D[40..47] F21 B14
FBA_D42 FBA_D41 FBA_CMD8 FBA_CMD8 88,89 FBB_D40 FBB_D39 FBB_CMD6 FBB_CMD6 90,91
AJ30 V29 G27 G15
FBA_D43 FBA_D42 FBA_CMD9 FBA_CMD9 88,89 FBB_D41 FBB_D40 FBB_CMD7 FBB_CMD7 90,91
AK28 V30 D27 F15
FBA_D44 FBA_D43 FBA_CMD10 FBA_CMD10 88,89 FBB_D42 FBB_D41 FBB_CMD8 FBB_CMD8 90,91
AM29 U34 G26 E15
FBA_D45 FBA_D44 FBA_CMD11 FBA_CMD11 88,89 FBB_D43 FBB_D42 FBB_CMD9 FBB_CMD9 90,91 FBB_CMD2
AM31 U31 E27 D15
FBA_D46 FBA_D45 FBA_CMD12 FBA_CMD12 88,89 FBB_D44 FBB_D43 FBB_CMD10 FBB_CMD10 90,91 FBB_CMD3
AN29 V34 E29 A14
FBA_D47 FBA_D46 FBA_CMD13 FBA_CMD13 88,89 FBB_D45 FBB_D44 FBB_CMD11 FBB_CMD11 90,91 FBA_CMD2 FBB_CMD5
89 FBA_D[48..55] AM30 V33 F29 D14
FBA_D48 FBA_D47 FBA_CMD14 FBA_CMD14 88,89 FBB_D46 FBB_D45 FBB_CMD12 FBB_CMD12 90,91 FBA_CMD3 FBB_CMD18
AN31 Y32 E30 A15
FBA_D49 FBA_D48 FBA_CMD15 FBA_CMD15 88,89 FBB_D47 FBB_D46 FBB_CMD13 FBB_CMD13 90,91 FBA_CMD5
AN32 AA31 91 FBB_D[48..55] D30 B15
FBA_D50 FBA_D49 FBA_CMD16 FBA_CMD17 FBA_CMD16 89 TP8508 TPAD14-OP-GP FBB_D48 FBB_D47 FBB_CMD14 FBB_CMD14 90,91 FBA_CMD18
AP30 AA29 1 A32 C17
FBA_D51 FBA_D50 FBA_CMD17 FBB_D49 FBB_D48 FBB_CMD15 FBB_CMD15 90,91
AP32 AA28 C31 D18
FBA_D52 FBA_D51 FBA_CMD18 FBA_CMD18 89 FBB_D50 FBB_D49 FBB_CMD16 FBB_CMD17 FBB_CMD16 91 TP8513 TPAD14-OP-GP
AM33 AC34 C32 E18 1
FBA_D53 FBA_D52 FBA_CMD19 FBA_CMD19 89 FBB_D51 FBB_D50 FBB_CMD17
AL31 AC33 B32 F18
FBA_D54 FBA_D53 FBA_CMD20 FBA_CMD20 88,89 FBB_D52 FBB_D51 FBB_CMD18 FBB_CMD18 91
AK33 AA32 D29 A20
FBA_D55 FBA_D54 FBA_CMD21 FBA_CMD21 88,89 FBB_D53 FBB_D52 FBB_CMD19 FBB_CMD19 91
89 FBA_D[56..63] AK32 AA33 A29 B20
FBA_D55 FBA_CMD22 FBB_D53 FBB_CMD20

2
FBA_D56 FBA_CMD22 88,89 FBB_D54 FBB_CMD20 90,91
AD34 Y28 C29 C18
FBA_D57 FBA_D56 FBA_CMD23 FBA_CMD23 88,89 FBB_D55 FBB_D54 FBB_CMD21 FBB_CMD21 90,91 R8507 R8508 R8511 R8512 R8513 R8514 R8515 R8516
AD32 Y29 91 FBB_D[56..63] B29 B18
FBA_D58 FBA_D57 FBA_CMD24 FBA_CMD24 88,89 FBB_D56 FBB_D55 FBB_CMD22 FBB_CMD22 90,91
AC30 W31 B21 G18 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
FBA_D59 FBA_D58 FBA_CMD25 FBA_CMD25 88,89 FBB_D57 FBB_D56 FBB_CMD23 FBB_CMD23 90,91
AD33 Y30 C23 G17
FBA_D60 AF31
FBA_D59 FBA_CMD26
AA34
FBA_CMD26 88,89 FBB_D58 A21
FBB_D57 FBB_CMD24
F17
FBB_CMD24 90,91 OPT OPT OPT OPT OPT OPT OPT OPT

1
FBA_D61 FBA_D60 FBA_CMD27 FBA_CMD27 88,89 FBB_D59 FBB_D58 FBB_CMD25 FBB_CMD25 90,91
AG34 Y31 C21 D16
FBA_D62 FBA_D61 FBA_CMD28 FBA_CMD28 88,89 FBB_D60 FBB_D59 FBB_CMD26 FBB_CMD26 90,91
AG32 Y34 B24 A18
FBA_D63 FBA_D62 FBA_CMD29 FBA_CMD29 88,89 FBB_D61 FBB_D60 FBB_CMD27 FBB_CMD27 90,91
AG33 Y33 C24 D17
FBA_D63 FBA_CMD30 FBA_CMD31 FBA_CMD30 88,89 TP8509 TPAD14-OP-GP FBB_D62 FBB_D61 FBB_CMD28 FBB_CMD28 90,91
V31 1 B26 A17
FBA_CMD31 FBB_D63 FBB_D62 FBB_CMD29 FBB_CMD29 90,91
C26 B17
C FBB_D63 FBB_CMD30 FBB_CMD31 FBB_CMD30 90,91 TP8512 TPAD14-OP-GP C
P30 R32 E17 1
88 FBA_DQM0 FBA_DQM0 FBA_CMD_RFU0 FBB_CMD31
F31 AC32
88 FBA_DQM1 FBA_DQM1 FBA_CMD_RFU1
F34 E11 C12
88 FBA_DQM2 FBA_DQM2 90 FBB_DQM0 FBB_DQM0 FBB_CMD_RFU0
M32 E3 C20
88 FBA_DQM3 FBA_DQM3 90 FBB_DQM1 FBB_DQM1 FBB_CMD_RFU1
AD31 1D5V_VGA_S0 A3
89 FBA_DQM4 FBA_DQM4 90 FBB_DQM2 FBB_DQM2
AL29 C9 1D5V_VGA_S0
89 FBA_DQM5 FBA_DQM5 90 FBB_DQM3 FBB_DQM3
89 FBA_DQM6
AM32
FBA_DQM6 DIS_OPT 91 FBB_DQM4
F23
FBB_DQM4
AF34 R28 R8503 1 2 F27
89 FBA_DQM7 FBA_DQM7 FBA_DEBUG0 R8506 1 91 FBB_DQM5 FBB_DQM5
AC28 2 60D4R2F-GP C30 DIS_OPT
FBA_DEBUG1 10KR2J-3-GP 91 FBB_DQM6 FBB_DQM6 R8509 1
DIS_OPT 91 FBB_DQM7
A24
FBB_DQM7 FBB_DEBUG0
G14 2
M31 G20 R8510 1 2 60D4R2F-GP
88 FBA_DQS_WP0 FBA_DQS_WP0 FBB_DEBUG1 10KR2J-3-GP
88 FBA_DQS_WP1
G31
FBA_DQS_WP1 DIS_OPT
E33 R30 D10
88 FBA_DQS_WP2 FBA_DQS_WP2 FBA_CLK0 FBA_CLK0 88 90 FBB_DQS_WP0 FBB_DQS_WP0
M33 R31 D5
88 FBA_DQS_WP3 FBA_DQS_WP3 FBA_CLK0# FBA_CLK0# 88 90 FBB_DQS_WP1 FBB_DQS_WP1
AE31 AB31 C3 D12
89 FBA_DQS_WP4 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1 89 90 FBB_DQS_WP2 FBB_DQS_WP2 FBB_CLK0 FBB_CLK0 90
AK30 AC31 B9 E12
89 FBA_DQS_WP5 FBA_DQS_WP5 FBA_CLK1# FBA_CLK1# 89 90 FBB_DQS_WP3 FBB_DQS_WP3 FBB_CLK0# FBB_CLK0# 90
AN33 E23 E20
89 FBA_DQS_WP6 FBA_DQS_WP6 91 FBB_DQS_WP4 FBB_DQS_WP4 FBB_CLK1 FBB_CLK1 91
AF33 E28 F20
89 FBA_DQS_WP7 FBA_DQS_WP7 91 FBB_DQS_WP5 FBB_DQS_WP5 FBB_CLK1# FBB_CLK1# 91
B30
91 FBB_DQS_WP6 FBB_DQS_WP6
A23
91 FBB_DQS_WP7 FBB_DQS_WP7
M30 K31
88 FBA_DQS_RN0 FBA_DQS_RN0 FBA_WCK1
H30 L30
88 FBA_DQS_RN1 FBA_DQS_RN1 FBA_WCK1#
E34 H34 D9 F8
88 FBA_DQS_RN2 FBA_DQS_RN2 FBA_WCK23 90 FBB_DQS_RN0 FBB_DQS_RN0 FBB_WCK1
M34 J34 E4 E8
88 FBA_DQS_RN3 FBA_DQS_RN3 FBA_WCK23# 90 FBB_DQS_RN1 FBB_DQS_RN1 FBB_WCK1#
AF30 AG30 B2 A5
89 FBA_DQS_RN4 FBA_DQS_RN4 FBA_WCK45 90 FBB_DQS_RN2 FBB_DQS_RN2 FBB_WCK23
AK31 AG31 A9 A6
89 FBA_DQS_RN5 FBA_DQS_RN5 FBA_WCK45# 90 FBB_DQS_RN3 FBB_DQS_RN3 FBB_WCK23#
AM34 AJ34 D22 D24
89 FBA_DQS_RN6 FBA_DQS_RN6 FBA_WCK67 91 FBB_DQS_RN4 FBB_DQS_RN4 FBB_WCK45
AF32 AK34 D28 D25
89 FBA_DQS_RN7 FBA_DQS_RN7 FBA_WCK67# 91 FBB_DQS_RN5 FBB_DQS_RN5 FBB_WCK45#
A30 B27
91 FBB_DQS_RN6 FBB_DQS_RN6 FBB_WCK67
J30 B23 C27
FBA_WCKB1 91 FBB_DQS_RN7 FBB_DQS_RN7 FBB_WCK67#
THE FBA_WCKBxx J31
FBA_WCKB1#
PINS ARE USED J32 D6
FBA_WCKB23 FBB_WCKB1
ONLY ON GK107 J33 THE FBB_WCKBxx D7
FBA_WCKB23# FBB_WCKB1#
THEY ARE NC AH31 PINS ARE USED C6
FBA_WCKB45 FBB_WCKB23
FOR GF108 AJ31 1D05V_VGA_S0
ONLY ON GK107 B6
FBA_WCKB45# FBB_WCKB23#
AND FOR GF117 AJ32 THEY ARE NC F26
FBA_WCKB67 FBB_WCKB45
AJ33 L8501
FOR GF108 E26
FBA_WCKB67# FBB_WCKB45#
AND FOR GF117 A26
TPAD14-OP-GP TP8503 FB_VREF FBA_PLL_AVDD FBB_WCKB67
1 H26 U27 1 2 A27
FB_VREF FBA_PLL_AVDD FBB_WCKB67#
H17 FBA_PLL_AVDD
N13P-GS-A1-GP FCM1005KF-300T03-GP FBB_PLL_AVDD
GPU FBVDDQ Decoupling
1

C8520 30ohm@100MHz ESR=0.2

SCD1U10V2KX-5GP
1D5V_VGA_S0
DIS_OPT C8505 C8506 N13P-GS-A1-GP SC:decap
71.0N13P.00U
SC22U6D3V5MX-2GP

DIS_OPT X7R PLACE CLOSE TO GPU BALLS


SC1U16V3KX-5GP
2

1
4 OF 17 VGA1D
DIS_OPT DIS_OPT
SCD1U10V2KX-5GP

71.0N13P.00U C8510 14/17 FBVDDQ


DIS_OPT

2
AA27
FBVDDQ_1 C8528
AA30
FBVDDQ_2

1
AB27 C8501 C8502 C8507 C8508 C8527 C8525 C8513 C8514 C8519 C8523 C8517 C8522
FBVDDQ_3

SC1U6D3V2KX-GP
FBVDDQ_4
AB33 DY DY DY

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
AC27 DY

SC1U16V3KX-5GP

SC1U16V3KX-5GP
2

2
FBVDDQ_5

SC4D7U6D3V3KX-GP
Place under GPU near
DIS_OPT Place under GPU near FBVDDQ_6
AD27 DY DY DY DY
AE27
FBVDDQ_7
AF27
FBVDDQ_8
AG27
FBVDDQ_9
B13
B FBVDDQ_10 B
B16
FBVDDQ_11
B19
FBVDDQ_12
E13 1D5V_VGA_S0
FBVDDQ_13
E16
FBVDDQ_14
FBVDDQ_15
E19 PLACE CLOSE TO GPU BALLS
H10
FBVDDQ_16
H11
FBVDDQ_17
H12
FBVDDQ_18
H13
FBVDDQ_19
H14
FBVDDQ_20

1
H15 C8503 C8504 C8529 C8511 C8512
DY C8530 C8526 C8515 C8516 C8521 C8524 C8518 C8531
FBVDDQ_21
FBVDDQ_22
H16 DY DY

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
H18 DY

SC1U16V3KX-5GP

SC1U16V3KX-5GP
2

2
FBVDDQ_23

SC4D7U6D3V3KX-GP
FBVDDQ_24
H19 DY DY
FBVDDQ_25
H20 DY DY
H21
FBVDDQ_26
H22
FBVDDQ_27
H23
FBVDDQ_28
H24
FBVDDQ_29
H8
FBVDDQ_30
H9
FBVDDQ_31
L27
FBVDDQ_32
M27 DIS_OPT
FBVDDQ_33
FBVDDQ_34
N27 DIS_OPT DIS_OPT
FBVDDQ_35
P27 DIS_OPT
FBVDDQ_36
R27 DIS_OPT DIS_OPT
T27
FBVDDQ_37
T30
FBVDDQ_38
T33
FBVDDQ_39
V27
FBVDDQ_40
FBVDDQ_41
W27 X7R, Under GPU.
W30
FBVDDQ_42
W33
FBVDDQ_43
Y27
FBVDDQ_44

TPAD14-OP-GP TP8501 1 FBVDDQ_SENSE F1


FB_VDDQ_SENSE
1D5V_VGA_S0
TP8502 1 FB_GND_SENSE F2
TPAD14-OP-GP FB_GND_SENSE
R8501
2 1 FB_CAL_PD_VDDQ J27
40D2R2F-GP FB_CAL_PD_VDDQ
DIS_OPT FB_CAL_PU_GND H27
FB_CAL_PU_GND

FB_CAL_TERM_GND H25
FB_CAL_TERM_GND

N13P-GS-A1-GP

71.0N13P.00U DIS_OPT

2
R8504 R8502

42D2R2F-GP

51R2J-2-GP
A A

1
OPT OPT

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_DP/LVDS/CRT/GPIO(3/5)
Size Document Number Rev
A1
Colossus 1
Date: Wednesday, January 04, 2012 Sheet 85 of 103

5 4 3 2 1
5 4 3 2 1

3D3V_VGA_S0
VGA1N 14 OF 17
4/17 DACA
GF108/GKx GF117 GF117 GF108/GKx
1D05V_VGA_S0 NV request to need to be keeped
DACA_VDD AG10 NC NC R4 1 R8605 22K2R2J-2-GP
DACA_VDD I2CA_SCL L8601

1
R8612 R5 1 R8606 22K2R2J-2-GP
NC I2CA_SDA
10KR2J-3-GP AP9 1 2
DACA_VREF TSEN_VREF
DIS_OPT VGA1O 15 OF 17
AP8 NC NC AM9
DACA_RSET DACA_HSYNC

1
FCM1005KF-181T00-GP
C8605 C8606
NC AN9 11/17 XTAL_PLL

2
DACA_VSYNC

SCD1U10V2KX-5GP

SC22U6D3V5MX-2GP
DIS_OPT

2
NC AK9 DIS_OPT DIS_OPT GPU_PLL_VDD AD8
DACA_RED SP_PLLVDD PLLVDD
L8602 AE8
SP_PLLVDD
NC AL10
D DACA_GREEN D
1 2 AD7
VID_PLLVDD NC DIS_OPT
NC AL9
DACA_BLUE
FCM1608KF-181T00-GP GF108/GKx GF117

N13P-GS-A1-GP

1
C8601 C8603 C8604 C8602
DIS_OPT TP8603 1 VIDEO_CLK_XTAL_SS H1 J4 N12P_XTAL_OUTBUFF
DIS_OPT XTAL_SSIN XTAL_OUTBUFF

SC22U6D3V5MX-2GP
71.0N13P.00U

2
SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP
TPAD14-OP-GP H3 H2
XTAL_IN XTAL_OUT

1
N13P-GS-A1-GP

1
20PF 5% 50V +/-0.25PF 0402 R8608

R8607 71.0N13P.00U DIS_OPT 10KR2J-3-GP

10KR2J-3-GP R8609 DY

2
27MHZ_IN 1 1MR2J-1-GP
2 27MHZ_OUT

2
X8601

2
DIS_OPTDIS_OPT
DIS_OPT
DIS_OPT
DIS_OPT DIS_OPT R8610
DIS_OPT 1 4
390R2J-1-GP DIS_OPT 01/04/12 N13P-GL

1
2 3 27MHZ_OUT_R
3D3V_S0
U8602

1
1 C8607 C8608
18 CLK_27M_VGA B SC12P50V2JN-3GP XTAL-27MHZ-85-GP SC12P50V2JN-3GP
VCC
5 DY DIS_OPT SB
2

2
92,93 PWR_VGA_CORE_PGOOD A 27MHZ_IN
4 1 2
Y 82.30034.641
3
GND R8638 2ND = 82.30034.651
DIS_OPT
74LVC1G08GW-1-GP 0R2J-2-GP 3RD = 82.30034.681
73.01G08.L04
3D3V_VGA_S0 2ND = 73.7SZ08.DAH

R8630 DY
2 1

0R0402-PAD

3D3V_VGA_S0
Q8601 PURE_HW_SHUTDOWN# 27,28,36
SMBC_THERM_NV 1 6 SML1_CLK 18,27,29,79
4
3

2 5

D
RN8601
SRN4K7J-8-GP 3 4 SMBD_THERM_NV U8601
18,27,29,79 SML1_DATA
DIS_OPT 2N7002K-2-GP
2N7002KDW-GP DIS_OPT
1
2

SMBC_THERM_NV 84.2N702.A3F 3D3V_VGA_S0


SMBD_THERM_NV 2nd = 84.2N702.E3F
3RD = 84.2N702.F3F

S
C C
GPIO8_OVERT#
3D3V_VGA_S0

3D3V_S0
DIS_OPT

1
VGA1Q 17 OF 17 3D3V_VGA_S0 R8637
DIS_OPT 2K2R2J-2-GP
10/19 MISC1
SMBC_THERM_NV
DIS_OPT
T4
I2CS_SCL SMBD_THERM_NV
T3 84.2N702.J31

2
I2CS_SDA R8636
2ND = 84.2N702.W31 Q8602
R2 1 R8601 22K2R2J-2-GP 3 1 2
I2CC_SCL R1
R3 1 R8602 22K2R2J-2-GP 1
I2CC_SDA 10KR2J-3-GP
2
R7 1 R8603 22K2R2J-2-GP R2
TPAD14-OP-GP TP8604 P2800_GPU_DXN I2CB_SCL GPU_DPRSLP 92
1 K4 R6 1 R8604 22K2R2J-2-GP Q8603 PDTC144EU-1-GP
THERMDN I2CB_SDA
3
TPAD14-OP-GP TP8605 1 P2800_GPU_DXP K3 VGAGPIO16 1 R1
THERMDP
DIS_OPT 2 DIS_OPT
R2
DIS_OPT

1
AM10 DIS_OPT PDTC144EU-1-GP 84.00144.I11
TPAD14-OP-GP TP8602 N12P_JTAG_TMS JTAG_TCK R8635
TPAD14-OP-GP TP8606
1
N12P_JTAG_TDI
AP11
JTAG_TMS DIS_OPT DIS_OPT 2K2R2J-2-GP
1 AM11
TPAD14-OP-GP TP8601 1 N12P_JTAG_TDO AP12
JTAG_TDI DIS_OPT 2ND = 84.05144.011
JTAG_TDO 3D3V_VGA_S0 3D3V_VGA_S0
N12P_GPIO_JTAG_TRST AN11 P6

2
JTAG_TRST# GPIO0 VID4 92
M3 VID3 92 84.00144.I11
GPIO1
L6
GPIO2
4
3

P5 R8617
RN8602 GPIO3 10KR2J-3-GP 2ND = 84.05144.011
P7
GPIO4
SRN10KJ-5-GP
GPIO5
L7 VID1 92 DIS_OPT
M7 VID2 92
GPIO6
1

N8 N12P_GPIO7_H51 TP8607 TPAD14-OP-GP R8611


2

GPIO7 GPIO8_OVERT# 10KR2J-3-GP


M1
1
2

GPIO8 N12P_GPIO9_J71 TP8609 TPAD14-OP-GP


GPIO9
M2
GPIO10_VREFCTRL TP8610 TPAD14-OP-GP
DIS_OPT
L1 1 D8601
GPIO10
M5 DY
2

GPIO11 VID0 92
N3 PWR_LEVEL A K
GPIO12 AC_PRESENT 19,27
M4 VID5 92
GPIO13 VGAGPIO16 1 TP8608 TPAD14-OP-GP
R8
GPIO16 1SS355GP-GP
GPIO20
P4 83.00355.F1F
GPIO21
P1 2ND = 83.00355.D1F

D8602
A K GPU_PROTECT# 27
N13P-GS-A1-GP
1SS355GP-GP
83.00355.F1F
DIS_OPT 71.0N13P.00U 2ND = 83.00355.D1F
DIS_OPT
3D3V_VGA_S0

VGA1P 16 OF 17
12/17 MISC2
2

B B
R8632
DY 10KR2J-3-GP

H6 ROM_CS#
1

ROM_CS#
H5 ROM_SI_D3
ROM_SI ROM_SO_C4
H7
STRAP0 ROM_SO ROM_SLK_D4
J2 H4
STRAP1 STRAP0 ROM_SCLK
J7
STRAP2 STRAP1
J6
STRAP3 STRAP2
J5
STRAP4 STRAP3
J3
STRAP4 3D3V_VGA_S0

R8634
2

BUFRST#
L2 2 1 UP N13P-GL R8633
10KR2J-3-GP 10KR2J-3-GP

STRAP_REF0_GND_N9 J1 L3
1

MULTI_STRAP_REF0_GND CEC

R8633=UP N13P-GL
1

R8633=DY N13P-GS/GT
R8613
DIS_OPT
40K2R2F-GP

N13P-GS-A1-GP
2

DIS_OPT

3D3V_VGA_S0

3D3V_VGA_S0
3D3V_VGA_S0 10KR by NV
R8619
10KR2F-2-GP
1

R8626 R8618
DIS_STRAP0_U 10KR2F-2-GP 2KR2F-3-GP
1

R8628 DY DY DY DY R8620
R8629 15KR2F-GP
45K3R2F-L-GP 4K99R2F-L-GP R8622 R8624 DIS_STRAP2_U
2

DY DY 45K3R2F-L-GP 34K8R2F-1-GP
2

STRAP3 STRAP0 ROM_SI_D3


STRAP4 STRAP1 ROM_SO_C4
A STRAP2 ROM_SLK_D4 A
1

R8631 R8615
4K99R2F-L-GP R8616 R8623 R8625 R8621 R8614 15KR2F-GP
45K3R2F-L-GP
DY
R8627 20KR2F-L-GP 10KR2J-3-GP
10KR2J-3-GP DY 24K9R2F-L-GP
2KR2J-1-GP

DIS_STRAP4_D DIS_STRAP3_D ROM SI_D


DIS_STRAP1_D DIS_ROM_SCLK_D
2

DIS_ROM_S0_D

<Core Design>

N13P-GL Wistron Corporation


21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_POWER(4/5)
Size Document Number Rev
A1
Colossus 1
Date: Wednesday, January 04, 2012 Sheet 86 of 103

5 4 3 2 1
5 4 3 2 1

VGA1I 9 OF 17

EDP 60A A2 GND_1


15/17 GND_1/2
GND_71 AM25 VGA1H 8 OF 17
AA17 GND_5 GND_72 AN1 16/17 GND_2/2
(TDP 55W) AA18
AA20
AA22
GND_6
GND_7
GND_73
GND_74
AN10
AN13
AN16
N19
N2
GND_141 GND_170 T28
T32
GND_8 GND_75 GND_142 GND_171
VGA_CORE AB12 AN19 N21 T5
GND_9 GND_76 GND_143 GND_172
AB14 AN22 N23 T7
GND_10 GND_77 GND_144 GND_173
AB16 AN25 N28 U12
GND_11 GND_78 GND_145 GND_174
AB19 AN30 N30 U14
VGA1F 6 OF 17 GND_12 GND_79 GND_146 GND_175
Under GPUSC:decap AB2 GND_13 GND_80 AN34 N32 GND_147 GND_176 U16
13/17 NVVDD AB21 AN4 N33 U19
GND_14 GND_81 GND_148 GND_177
A33 GND_2 GND_82 AN7 N5 GND_149 GND_178 U21
AA12 AB23 AP2 N7 U23
VDD_1 GND_15 GND_83 GND_150 GND_179
AA14 AB28 AP33 P13 V12
VDD_2 GND_16 GND_84 GND_151 GND_180
D AA16 VDD_3 AB30 GND_17 GND_85 B1 P15 GND_152 GND_181 V14 D
DIS_OPT DIS_OPTDIS_OPT DY DY DIS_OPTDIS_OPT AA19 VDD_4 AB32 GND_18 GND_86 B10 P17 GND_153 GND_182 V16
1

1
C8711 AA21 AB5 B22 P18 V19
C8714 C8713 C8712 SC10U6D3V3MX-GP C8704 C8703 C8702 C8701 VDD_5 GND_19 GND_87 GND_154 GND_183
AA23 AB7 B25 P20 V21
VDD_6 GND_20 GND_88 GND_155 GND_184
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
AB13 AC13 B28 P22 V23
2

2
VDD_7 GND_21 GND_89 GND_156 GND_185
AB15 VDD_8 AC15 GND_22 GND_90 B31 R12 GND_157 GND_186 W13
AB17 VDD_9 AC17 GND_23 GND_91 B34 R14 GND_158 GND_187 W15
AB18 AC18 B4 R16 W17
VDD_10 GND_24 GND_92 GND_159 GND_188
AB20 VDD_11 AA13 GND_3 GND_93 B7 R19 GND_160 GND_189 W18
AB22 VDD_12 AC20 GND_25 GND_94 C10 R21 GND_161 GND_190 W20
AC12 AC22 C13 R23 W22
VDD_13 GND_26 GND_95 GND_162 GND_191
AC14 AE2 C19 T13 W28
VDD_14 GND_27 GND_96 GND_163 GND_192
AC16 AE28 C22 T15 Y12
VDD_15 GND_28 GND_97 GND_164 GND_193
AC19 AE30 C25 T17 Y14
VDD_16 GND_29 GND_98 GND_165 GND_194
AC21 AE32 C28 T18 Y16
VDD_17 GND_30 GND_99 GND_166 GND_195
AC23 VDD_18 AE33 GND_31 GND_100 C7 T2 GND_167 GND_196 Y19
M12 VDD_19 AE5 GND_32 GND_101 D2 T20 GND_168 GND_197 Y21
DIS_OPTDIS_OPTDIS_OPTDIS_OPT DIS_OPTDIS_OPT DIS_OPT M14 VDD_20 AE7 GND_33 GND_102 D31 T22 GND_169 GND_198 Y23
1

1
M16 VDD_21 AH10 GND_34 GND_103 D33
SC4D7U6D3V3KX-GP

C8731 C8730 C8729 C8728 C8727 C8726 C8725 M19 AA15 E10
VDD_22 GND_4 GND_104
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
M21 AH13 E22
2

2
VDD_23 GND_35 GND_105
M23 AH16 E25
VDD_24 GND_36 GND_106
N13 AH19 E5
VDD_25 GND_37 GND_107
N15 AH2 E7
VDD_26 GND_38 GND_108
N17 AH22 F28 AG11 AH11
VDD_27 GND_39 GND_109 GND_F GND_H
N18 AH24 F7
VDD_28 GND_40 GND_110
N20 AH28 G10
VDD_29 GND_41 GND_111
N22 AH29 G13
VDD_30 GND_42 GND_112
SC:decap P12 VDD_31 AH30 GND_43 GND_113 G16
P14 AH32 G19
VDD_32 GND_44 GND_114
P16 VDD_33 AH33 GND_45 GND_115 G2
P19 VDD_34 AH5 GND_46 GND_116 G22
P21 VDD_35 AH7 GND_47 GND_117 G25 GND_OPT_1 C16
P23 AJ7 G28 W32
VDD_36 GND_48 GND_118 GND_OPT_2
1

C8722 C8721 C8724 C8723 C8720 C8719 C8718 C8717 R13 AK10 G3
VDD_37 GND_49 GND_119
R15 AK7 G30 Optional CMD GNDs (2)
VDD_38 GND_50 GND_120
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

R17 AL12 G32 NC for 4-Lyr cards


2

VDD_39 GND_51 GND_121


C R18 AL14 G33 C
VDD_40 GND_52 GND_122 N13P-GS-A1-GP
R20 AL15 G5
VDD_41 GND_53 GND_123
R22 AL17 G7
VDD_42 GND_54 GND_124
T12
T14
VDD_43 AL18
AL2
GND_55 GND_125 K2
K28 DIS_OPT 71.0N13P.00U
VDD_44 GND_56 GND_126
T16 VDD_45 AL20 GND_57 GND_127 K30
T19 VDD_46 AL21 GND_58 GND_128 K32
T21 VDD_47 AL23 GND_59 GND_129 K33
T23 AL24 K5
VDD_48 GND_60 GND_130
U13 AL26 K7
VDD_49 GND_61 GND_131
U15 AL28 M13
VDD_50 GND_62 GND_132
U17 VDD_51 AL30 GND_63 GND_133 M15
SC:decap NEAR TO GPU U18
VDD_52
AL32
GND_64 GND_134
M17
U20 AL33 M18
VDD_53 GND_65 GND_135
U22 AL5 M20
VDD_54 GND_66 GND_136
V13 AM13 M22
VDD_55 GND_67 GND_137
V15 AM16 N12
VDD_56 GND_68 GND_138
V17 AM19 N14
VDD_57 GND_69 GND_139
V18 AM22 N16
VDD_58 GND_70 GND_140
V20
VDD_59
1

V22
TC8701 C8707 C8706 C8705 C8708 C8710 C8715 C8716 VDD_60
W12
VDD_61
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

DY DY W14 N13P-GS-A1-GP
2

VDD_62
SE330U2VDM-L-GP

SC22U6D3V5MX-2GP

SC47U6D3V5MX-1-GP

SC4D7U6D3V3KX-GP

DY DY DY DY DY W16 VDD_63
W19
W21
VDD_64 71.0N13P.00U DIS_OPT
VDD_65
W23
VDD_66
Y13
VDD_67
Y15
VDD_68
Y17
VDD_69
Y18
VDD_70
DIS_OPT Y20
VDD_71
Y22
VDD_72 VGA1E
5 OF 17
N13P-GS-A1-GP 9/17 XVDD

71.0N13P.00U DIS_OPT
B CONFIGURABLE B
POWER
CHANNELS
U1
XVDD_1
U2
XVDD_2
U3
XVDD_3
U4
XVDD_4
U5
XVDD_5
U6
XVDD_6
U7
XVDD_7
U8
XVDD_8

VGA1G 7 OF 17 3D3V_VGA_S0 V1
XVDD_9
17/17 NC/VDD33 V2
XVDD_10
V3
XVDD_11
AC6 J8 V4
NC#AC6 VDD33_1 XVDD_12
AJ28 K8 V5
NC#AJ28 VDD33_2 XVDD_13
AJ4
NC#AJ4 VDD33_3
L8 DIS_OPTDIS_OPT DIS_OPT DIS_OPT XVDD_14
V6
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

AJ5 M8 DIS_OPT V7
AL11
NC#AJ5
NC#AL11
VDD33_4
X7R X7R X7R X7R
XVDD_15
XVDD_16
V8 XVDD_1~38=No Connect
1

C15
NC#C15 C8709 C8734 C8732 C8733 C8735 C8736
D19
NC#D19
SC4D7U6D3V3KX-GP

D20 SC1U6D3V2KX-GP W2
2

NC#D20 XVDD_17
D23 NC#D23 XVDD_18 W3
D26 NC#D26 XVDD_19 W4
H31
NC#H31 DIS_OPT XVDD_20
W5
T8 W7
NC#T8 XVDD_21
V32 W8
NC#V32 XVDD_22

N13P-GS-A1-GP 0.1U Under GPU


Y1
XVDD_23
Y2
DIS_OPT 71.0N13P.00U XVDD_24
Y3
4.7U NEAR TO GPU XVDD_25
Y4
A XVDD_26 A
XVDD_27 Y5
XVDD_28 Y6
Y7
1U NEAR TO GPU XVDD_29
Y8
XVDD_30 <Variant Name>

AA1
XVDD_31
XVDD_32
AA2 Wistron Corporation
AA3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
XVDD_33 Taipei Hsien 221, Taiwan, R.O.C.
XVDD_34 AA4
XVDD_35 AA5
AA6 Title
XVDD_36
DIS_OPT XVDD_37 AA7
GPU_DPPWR/GND(5/5)
XVDD_38 AA8
71.0N13P.00U Size Document Number Rev
N13P-GS-A1-GP Custom
Colossus 1
Date: Wednesday, January 04, 2012 Sheet 87 of 103
5 4 3 2 1
5 4 3 2 1

D D

1D5V_VGA_S0 Frame Buffer Patition A-Lower Half 1D5V_VGA_S0

1
C8808 C8809 C8807 C8806 C8816 C8821 C8815 C8814
OPT OPT OPT OPT OPT OPT OPT OPT

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
2

2
VRAM17 VRAM17 VRAM18 VRAM18
FBA_D[8..15] 85 FBA_D[0..7] 85
1

1
C8811 C8810 C8813 C8812 K8 E3 FBA_D9 C8818 C8817 C8819 C8820 K8 E3 FBA_D1
VDD DQL0 FBA_D13 VDD DQL0 FBA_D4
OPT OPT OPT DY K2
VDD DQL1
F7 DY DY DY OPT K2
VDD DQL1
F7

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
N1 F2 FBA_D8 N1 F2 FBA_D3
2

2
VDD DQL2 FBA_D14 VDD DQL2 FBA_D7
R9 F8 R9 F8
VDD DQL3 FBA_D11 VDD DQL3 FBA_D2
B2 H3 B2 H3
VDD DQL4 FBA_D12 VDD DQL4 FBA_D5
D9 H8 D9 H8
VDD DQL5 FBA_D10 VDD DQL5 FBA_D0
G7 G2 G7 G2
VDD DQL6 FBA_D15 VDD DQL6 FBA_D6
R1 H7 R1 H7
VDD DQL7 VDD DQL7
N9 FBA_D[16..23] 85 N9 FBA_D[24..31] 85
VDD FBA_D18 VDD FBA_D27
D7 D7
DQU0 FBA_D20 DQU0 FBA_D28
A8 C3 A8 C3

1
C8827 VDDQ DQU1 FBA_D16 C8828 VDDQ DQU1 FBA_D26
A1 C8 A1 C8
1

1
C8832 C8831 C8829 VDDQ DQU2 FBA_D21 C8834 C8833 C8830 VDDQ DQU2 FBA_D30
OPT C1
VDDQ DQU3
C2 OPT C1
VDDQ DQU3
C2

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
OPT OPT C9 A7 FBA_D17 OPT OPT C9 A7 FBA_D25

2
VDDQ DQU4 VDDQ DQU4

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
D2 A2 FBA_D22 D2 A2 FBA_D31
2

2
VDDQ DQU5 FBA_D19 VDDQ DQU5 FBA_D24
E9 B8 E9 B8
VDDQ DQU6 FBA_D23 VDDQ DQU6 FBA_D29
F1 A3 F1 A3
VDDQ DQU7 VDDQ DQU7
H9 H9
VDDQ VDDQ
H2 C7 FBA_DQS_WP2 85 H2 C7 FBA_DQS_WP3 85
VDDQ DQSU VDDQ DQSU
B7 FBA_DQS_RN2 85 B7 FBA_DQS_RN3 85
VRAM1_VREF DQSU# VRAM1_VREF DQSU#
H1 H1
VRAM2_VREF VREFDQ VRAM2_VREF VREFDQ
M8 F3 FBA_DQS_WP1 85 M8 F3 FBA_DQS_WP0 85
VRAM_ZQ1 VREFCA DQSL VRAM_ZQ2 VREFCA DQSL
C
1
R8801
OPT 2
243R2F-2-GP
L8
ZQ DQSL#
G3 FBA_DQS_RN1 85 1
R8802
OPT 2
243R2F-2-GP
L8
ZQ DQSL#
G3 FBA_DQS_RN0 85
C
K1 FBA_CMD2 85 K1 FBA_CMD2 85
ODT ODT
85,89 FBA_CMD9 N3 85,89 FBA_CMD9 N3
A0 A0
85,89 FBA_CMD11 P7 85,89 FBA_CMD11 P7
A1 A1
85,89 FBA_CMD8 P3 L2 FBA_CMD0 85 85,89 FBA_CMD8 P3 L2 FBA_CMD0 85
A2 CS# A2 CS#
85,89 FBA_CMD25 N2 T2 FBA_CMD5 85,89 85,89 FBA_CMD25 N2 T2 FBA_CMD5 85,89
A3 RESET# A3 RESET#
85,89 FBA_CMD10 P8 85,89 FBA_CMD10 P8
A4 A4
85,89 FBA_CMD24 P2 85,89 FBA_CMD24 P2
A5 A5
85,89 FBA_CMD22 R8 T7 FBA_CMD4 85,89 85,89 FBA_CMD22 R8 T7 FBA_CMD4 85,89
A6 NC#T7 A6 NC#T7
85,89 FBA_CMD7 R2 L9 85,89 FBA_CMD7 R2 L9
A7 NC#L9 A7 NC#L9
85,89 FBA_CMD21 T8 L1 85,89 FBA_CMD21 T8 L1
A8 NC#L1 A8 NC#L1
85,89 FBA_CMD6 R3 J9 85,89 FBA_CMD6 R3 J9
A9 NC#J9 A9 NC#J9
85,89 FBA_CMD29 L7 J1 85,89 FBA_CMD29 L7 J1
A10/AP NC#J1 A10/AP NC#J1
85,89 FBA_CMD23 R7 85,89 FBA_CMD23 R7
A11 A11
85,89 FBA_CMD28 N7 85,89 FBA_CMD28 N7
A12/BC# A12/BC#
85,89 FBA_CMD20 T3 J8 85,89 FBA_CMD20 T3 J8
A13 VSS A13 VSS
85,89 FBA_CMD14 M7 M1 85,89 FBA_CMD14 M7 M1
NC#M7 VSS NC#M7 VSS
M9 M9
VSS VSS
J2 J2
VSS VSS
85,89 FBA_CMD12 M2 P9 85,89 FBA_CMD12 M2 P9
BA0 VSS BA0 VSS
85,89 FBA_CMD27 N8 G8 85,89 FBA_CMD27 N8 G8
BA1 VSS BA1 VSS
85,89 FBA_CMD26 M3 B3 85,89 FBA_CMD26 M3 B3
BA2 VSS BA2 VSS
T1 T1
VSS VSS
A9 A9
VSS VSS
85 FBA_CLK0 J7 T9 85 FBA_CLK0 J7 T9
CK VSS CK VSS
85 FBA_CLK0# K7 E1 85 FBA_CLK0# K7 E1
CK# VSS CK# VSS
P1 P1
VSS VSS
85 FBA_CMD3 K9 85 FBA_CMD3 K9
CKE CKE
G1 G1
VSSQ VSSQ
F9 F9
VSSQ VSSQ
85 FBA_DQM2 D3 E8 85 FBA_DQM3 D3 E8
DMU VSSQ DMU VSSQ
85 FBA_DQM1 E7 E2 85 FBA_DQM0 E7 E2
DML VSSQ DML VSSQ
D8 D8
VSSQ VSSQ
D1 D1
VSSQ VSSQ
85,89 FBA_CMD13 L3 B9 85,89 FBA_CMD13 L3 B9
WE# VSSQ WE# VSSQ
85,89 FBA_CMD15 K3 B1 85,89 FBA_CMD15 K3 B1
CAS# VSSQ CAS# VSSQ
85,89 FBA_CMD30 J3 G9 85,89 FBA_CMD30 J3 G9
RAS# VSSQ RAS# VSSQ

H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP
72.52G63.A0U 72.52G63.A0U
B B

1D5V_VGA_S0 1D5V_VGA_S0
1

1
R8805 R8808

FBA_CLK0
OPT OPT

1K33R2F-GP
1K33R2F-GP
2

2
1

VRAM1_VREF VRAM2_VREF
R8809
1

1
162R2F-GP R8806 R8807
1

1
OPT OPT C8803 OPT C8805
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
2

OPT OPT
1K33R2F-GP

1K33R2F-GP
2

2
2

2
FBA_CLK0#

A A

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM1,2 (1/4)
Size Document Number Rev
A2 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 88 of 103
5 4 3 2 1
5 4 3 2 1

D
Frame Buffer Patition A-Upper Half D

1D5V_VGA_S0 1D5V_VGA_S0

1
C8920 C8929 C8919 C8917 C8916 C8918 C8912
OPT OPT DY C8913 OPT DY OPT DY

SCD1U10V2KX-4GP
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
2

2
VRAM19 VRAM19 VRAM20 VRAM20
FBA_D[56..63] 85 FBA_D[48..55] 85

1
C8909 C8908 C8928 C8910 K8 E3 FBA_D59 C8905 C8906 C8915 C8907 K8 E3 FBA_D49
VDD DQL0 FBA_D62 VDD DQL0 FBA_D53
DY OPT OPT DY K2
VDD DQL1
F7 DY OPT OPT OPT K2
VDD DQL1
F7

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
N1 F2 FBA_D58 N1 F2 FBA_D51

2
VDD DQL2 FBA_D63 VDD DQL2 FBA_D52
R9 F8 R9 F8
VDD DQL3 FBA_D57 VDD DQL3 FBA_D50
B2 H3 B2 H3
VDD DQL4 FBA_D61 VDD DQL4 FBA_D54
D9 H8 D9 H8
VDD DQL5 FBA_D56 VDD DQL5 FBA_D48
G7 G2 G7 G2
VDD DQL6 FBA_D60 VDD DQL6 FBA_D55
R1 H7 R1 H7
VDD DQL7 VDD DQL7
N9 FBA_D[32..39] 85 N9 FBA_D[40..47] 85
VDD FBA_D32 VDD FBA_D43
D7 D7
DQU0 FBA_D36 DQU0 FBA_D46
A8 C3 A8 C3
VDDQ DQU1 FBA_D34 VDDQ DQU1 FBA_D42
A1 C8 A1 C8
1

1
C8927 C8926 C8925 C8930 VDDQ DQU2 FBA_D38 C8921 C8922 C8923 C8924 VDDQ DQU2 FBA_D44
C1 C2 C1 C2
VDDQ DQU3 FBA_D33 VDDQ DQU3 FBA_D41
OPT OPT OPT OPT C9
VDDQ DQU4
A7 OPT OPT OPT OPT C9
VDDQ DQU4
A7
SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP
D2 A2 FBA_D37 D2 A2 FBA_D45
2

2
VDDQ DQU5 FBA_D39 VDDQ DQU5 FBA_D40
E9 B8 E9 B8
VDDQ DQU6 FBA_D35 VDDQ DQU6 FBA_D47
F1 A3 F1 A3
VDDQ DQU7 VDDQ DQU7
H9 H9
VDDQ VDDQ
H2 C7 FBA_DQS_WP4 85 H2 C7 FBA_DQS_WP5 85
VDDQ DQSU VDDQ DQSU
B7 FBA_DQS_RN4 85 B7 FBA_DQS_RN5 85
VRAM3_VREF DQSU# VRAM3_VREF DQSU#
H1 H1
VRAM4_VREF VREFDQ VRAM4_VREF VREFDQ
C M8 F3 FBA_DQS_WP7 85 M8 F3 FBA_DQS_WP6 85 C
VRAM_ZQ3 VREFCA DQSL VRAM_ZQ4 VREFCA DQSL
1
R8902
OPT 2
243R2F-2-GP
L8
ZQ DQSL#
G3 FBA_DQS_RN7 85 1
R8901
OPT 2
243R2F-2-GP
L8
ZQ DQSL#
G3 FBA_DQS_RN6 85
K1 FBA_CMD18 85 K1 FBA_CMD18 85
ODT ODT
85,88 FBA_CMD9 N3 85,88 FBA_CMD9 N3
A0 A0
85,88 FBA_CMD11 P7 85,88 FBA_CMD11 P7
A1 A1
85,88 FBA_CMD8 P3 L2 FBA_CMD16 85 85,88 FBA_CMD8 P3 L2 FBA_CMD16 85
A2 CS# A2 CS#
85,88 FBA_CMD25 N2 T2 FBA_CMD5 85,88 85,88 FBA_CMD25 N2 T2 FBA_CMD5 85,88
A3 RESET# A3 RESET#
85,88 FBA_CMD10 P8 85,88 FBA_CMD10 P8
A4 A4
85,88 FBA_CMD24 P2 85,88 FBA_CMD24 P2
A5 A5
85,88 FBA_CMD22 R8 T7 FBA_CMD4 85,88 85,88 FBA_CMD22 R8 T7 FBA_CMD4 85,88
A6 NC#T7 A6 NC#T7
85,88 FBA_CMD7 R2 L9 85,88 FBA_CMD7 R2 L9
A7 NC#L9 A7 NC#L9
85,88 FBA_CMD21 T8 L1 85,88 FBA_CMD21 T8 L1
A8 NC#L1 A8 NC#L1
85,88 FBA_CMD6 R3 J9 85,88 FBA_CMD6 R3 J9
A9 NC#J9 A9 NC#J9
85,88 FBA_CMD29 L7 J1 85,88 FBA_CMD29 L7 J1
A10/AP NC#J1 A10/AP NC#J1
85,88 FBA_CMD23 R7 85,88 FBA_CMD23 R7
A11 A11
85,88 FBA_CMD28 N7 85,88 FBA_CMD28 N7
A12/BC# A12/BC#
85,88 FBA_CMD20 T3 J8 85,88 FBA_CMD20 T3 J8
A13 VSS A13 VSS
85,88 FBA_CMD14 M7 M1 85,88 FBA_CMD14 M7 M1
NC#M7 VSS NC#M7 VSS
M9 M9
VSS VSS
J2 J2
VSS VSS
85,88 FBA_CMD12 M2 P9 85,88 FBA_CMD12 M2 P9
BA0 VSS BA0 VSS
85,88 FBA_CMD27 N8 G8 85,88 FBA_CMD27 N8 G8
BA1 VSS BA1 VSS
85,88 FBA_CMD26 M3 B3 85,88 FBA_CMD26 M3 B3
BA2 VSS BA2 VSS
T1 T1
VSS VSS
A9 A9
VSS VSS
85 FBA_CLK1 J7 T9 85 FBA_CLK1 J7 T9
CK VSS CK VSS
85 FBA_CLK1# K7 E1 85 FBA_CLK1# K7 E1
CK# VSS CK# VSS
P1 P1
VSS VSS
85 FBA_CMD19 K9 85 FBA_CMD19 K9
CKE CKE
G1 G1
VSSQ VSSQ
F9 F9
VSSQ VSSQ
85 FBA_DQM4 D3 E8 85 FBA_DQM5 D3 E8
DMU VSSQ DMU VSSQ
85 FBA_DQM7 E7 E2 85 FBA_DQM6 E7 E2
DML VSSQ DML VSSQ
D8 D8
VSSQ VSSQ
D1 D1
VSSQ VSSQ
85,88 FBA_CMD13 L3 B9 85,88 FBA_CMD13 L3 B9
WE# VSSQ WE# VSSQ
85,88 FBA_CMD15 K3 B1 85,88 FBA_CMD15 K3 B1
CAS# VSSQ CAS# VSSQ
85,88 FBA_CMD30 J3 G9 85,88 FBA_CMD30 J3 G9
RAS# VSSQ RAS# VSSQ

B H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP B
72.52G63.A0U 72.52G63.A0U

1D5V_VGA_S0 1D5V_VGA_S0

1
FBA_CLK1 R8904 R8906
OPT OPT

1K33R2F-GP
1K33R2F-GP
1

2
R8909
162R2F-GP VRAM3_VREF VRAM4_VREF
OPT
1

1
R8905 R8903
2

1
OPT C8911 OPT C8914
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
FBA_CLK1#
OPT OPT
1K33R2F-GP

1K33R2F-GP
2

2
2

A A

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM3,4 (2/4)
Size Document Number Rev
A2 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 89 of 103

5 4 3 2 1
5 4 3 2 1

D D

1D5V_VGA_S0 Frame Buffer Patition B-Lower Half 1D5V_VGA_S0

1
C9010 C9013 C9020 C9009 C9016 C9018 C9021 C9015
DY DY DY OPT OPT OPT DY OPT

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
2

2
VRAM21 VRAM21 VRAM22 VRAM22
FBB_D[8..15] 85 FBB_D[0..7] 85
1

1
C9007 C9003 C9002 C9001 K8 E3 FBB_D9 C9017 C9004 C9006 C9005 K8 E3 FBB_D1
VDD DQL0 FBB_D13 VDD DQL0 FBB_D4
OPT DY OPT OPT K2
VDD DQL1
F7 DY OPT DY DY K2
VDD DQL1
F7
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
N1 F2 FBB_D11 N1 F2 FBB_D3
2

2
VDD DQL2 FBB_D12 VDD DQL2 FBB_D5
R9 F8 R9 F8
VDD DQL3 FBB_D10 VDD DQL3 FBB_D2
B2 H3 B2 H3
VDD DQL4 FBB_D15 VDD DQL4 FBB_D6
D9 H8 D9 H8
VDD DQL5 FBB_D8 VDD DQL5 FBB_D0
G7 G2 G7 G2
VDD DQL6 FBB_D14 VDD DQL6 FBB_D7
R1 H7 R1 H7
VDD DQL7 VDD DQL7
N9 FBB_D[16..23] 85 N9 FBB_D[24..31] 85
VDD FBB_D18 VDD FBB_D26
D7 D7
DQU0 FBB_D20 DQU0 FBB_D30
A8 C3 A8 C3
VDDQ DQU1 FBB_D16 VDDQ DQU1 FBB_D25
A1 C8 A1 C8
1

1
C9023 C9024 C9008 C9019 VDDQ DQU2 FBB_D22 C9026 C9025 C9012 C9022 VDDQ DQU2 FBB_D31
C1 C2 C1 C2
VDDQ DQU3 FBB_D17 VDDQ DQU3 FBB_D24
OPT OPT OPT OPT C9
VDDQ DQU4
A7 DY OPT OPT C9
VDDQ DQU4
A7

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
D2 A2 FBB_D23 D2 A2 FBB_D28
2

2
VDDQ DQU5 FBB_D19 VDDQ DQU5 FBB_D27
E9 B8 E9 B8
VDDQ DQU6 FBB_D21 VDDQ DQU6 FBB_D29
F1 A3 F1 A3
VDDQ DQU7 VDDQ DQU7
H9 H9
VDDQ VDDQ
H2 C7 FBB_DQS_WP2 85 H2 C7 FBB_DQS_WP3 85
VDDQ DQSU VDDQ DQSU
B7 FBB_DQS_RN2 85 B7 FBB_DQS_RN3 85
VRAM5_VREF DQSU# VRAM5_VREF DQSU#
H1 H1
VRAM6_VREF VREFDQ VRAM6_VREF VREFDQ
M8 F3 FBB_DQS_WP1 85 M8 F3 FBB_DQS_WP0 85
VRAM_ZQ5 VREFCA DQSL VRAM_ZQ6 VREFCA DQSL
C
1
R9004
OPT 2
243R2F-2-GP
L8
ZQ DQSL#
G3 FBB_DQS_RN1 85 1
R9001
OPT 2
243R2F-2-GP
L8
ZQ DQSL#
G3 FBB_DQS_RN0 85
C
K1 FBB_CMD2 85 K1 FBB_CMD2 85
ODT ODT
85,91 FBB_CMD9 N3 85,91 FBB_CMD9 N3
A0 A0
85,91 FBB_CMD11 P7 85,91 FBB_CMD11 P7
A1 A1
85,91 FBB_CMD8 P3 L2 FBB_CMD0 85 85,91 FBB_CMD8 P3 L2 FBB_CMD0 85
A2 CS# A2 CS#
85,91 FBB_CMD25 N2 T2 FBB_CMD5 85,91 85,91 FBB_CMD25 N2 T2 FBB_CMD5 85,91
A3 RESET# A3 RESET#
85,91 FBB_CMD10 P8 85,91 FBB_CMD10 P8
A4 A4
85,91 FBB_CMD24 P2 85,91 FBB_CMD24 P2
A5 A5
85,91 FBB_CMD22 R8 T7 FBB_CMD4 85,91 85,91 FBB_CMD22 R8 T7 FBB_CMD4 85,91
A6 NC#T7 A6 NC#T7
85,91 FBB_CMD7 R2 L9 85,91 FBB_CMD7 R2 L9
A7 NC#L9 A7 NC#L9
85,91 FBB_CMD21 T8 L1 85,91 FBB_CMD21 T8 L1
A8 NC#L1 A8 NC#L1
85,91 FBB_CMD6 R3 J9 85,91 FBB_CMD6 R3 J9
A9 NC#J9 A9 NC#J9
85,91 FBB_CMD29 L7 J1 85,91 FBB_CMD29 L7 J1
A10/AP NC#J1 A10/AP NC#J1
85,91 FBB_CMD23 R7 85,91 FBB_CMD23 R7
A11 A11
85,91 FBB_CMD28 N7 85,91 FBB_CMD28 N7
A12/BC# A12/BC#
85,91 FBB_CMD20 T3 J8 85,91 FBB_CMD20 T3 J8
A13 VSS A13 VSS
85,91 FBB_CMD14 M7 M1 85,91 FBB_CMD14 M7 M1
NC#M7 VSS NC#M7 VSS
M9 M9
VSS VSS
J2 J2
VSS VSS
85,91 FBB_CMD12 M2 P9 85,91 FBB_CMD12 M2 P9
BA0 VSS BA0 VSS
85,91 FBB_CMD27 N8 G8 85,91 FBB_CMD27 N8 G8
BA1 VSS BA1 VSS
85,91 FBB_CMD26 M3 B3 85,91 FBB_CMD26 M3 B3
BA2 VSS BA2 VSS
T1 T1
VSS VSS
A9 A9
VSS VSS
85 FBB_CLK0 J7 T9 85 FBB_CLK0 J7 T9
CK VSS CK VSS
85 FBB_CLK0# K7 E1 85 FBB_CLK0# K7 E1
CK# VSS CK# VSS
P1 P1
VSS VSS
85 FBB_CMD3 K9 85 FBB_CMD3 K9
CKE CKE
G1 G1
VSSQ VSSQ
F9 F9
VSSQ VSSQ
85 FBB_DQM2 D3 E8 85 FBB_DQM3 D3 E8
DMU VSSQ DMU VSSQ
85 FBB_DQM1 E7 E2 85 FBB_DQM0 E7 E2
DML VSSQ DML VSSQ
D8 D8
VSSQ VSSQ
D1 D1
VSSQ VSSQ
85,91 FBB_CMD13 L3 B9 85,91 FBB_CMD13 L3 B9
WE# VSSQ WE# VSSQ
85,91 FBB_CMD15 K3 B1 85,91 FBB_CMD15 K3 B1
CAS# VSSQ CAS# VSSQ
85,91 FBB_CMD30 J3 G9 85,91 FBB_CMD30 J3 G9
RAS# VSSQ RAS# VSSQ

H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP
72.52G63.A0U 72.52G63.A0U
B B

1D5V_VGA_S0 1D5V_VGA_S0
1

1
FBB_CLK0 R9003 R9006
OPT OPT

1K33R2F-GP
1K33R2F-GP
1

2
R9009
162R2F-GP VRAM5_VREF VRAM6_VREF
OPT
1

1
R9005 R9002
2

1
OPT C9011 OPT C9014
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
FBB_CLK0# OPT OPT
1K33R2F-GP

1K33R2F-GP
2

2
2

A A

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM5,6 (3/4)
Size Document Number Rev
A2 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 90 of 103
5 4 3 2 1
5 4 3 2 1

D
1D5V_VGA_S0 Frame Buffer Patition B-Upper Half 1D5V_VGA_S0
D

1
C9120 C9129 C9119 C9113 C9116 C9117 C9118 C9112
OPT DY OPT DY DY OPT DY DY

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
2

2
VRAM23 VRAM23 VRAM24 VRAM24
FBB_D[56..63] 85 FBB_D[48..55] 85

1
C9109 C9107 C9128 C9108 K8 E3 FBB_D56 C9105 C9104 C9115 C9106 K8 E3 FBB_D49
VDD DQL0 FBB_D61 VDD DQL0 FBB_D55
OPT OPT OPT DY K2
VDD DQL1
F7 OPT OPT OPT DY K2
VDD DQL1
F7

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
N1 F2 FBB_D58 N1 F2 FBB_D51

2
VDD DQL2 FBB_D60 VDD DQL2 FBB_D53
R9 F8 R9 F8
VDD DQL3 FBB_D57 VDD DQL3 FBB_D50
B2 H3 B2 H3
VDD DQL4 FBB_D63 VDD DQL4 FBB_D54
D9 H8 D9 H8
VDD DQL5 FBB_D59 VDD DQL5 FBB_D48
G7 G2 G7 G2
VDD DQL6 FBB_D62 VDD DQL6 FBB_D52
R1 H7 R1 H7
VDD DQL7 VDD DQL7
N9 FBB_D[32..39] 85 N9 FBB_D[40..47] 85
VDD FBB_D34 VDD FBB_D42
D7 D7
DQU0 FBB_D38 DQU0 FBB_D46
A8 C3 A8 C3
VDDQ DQU1 FBB_D32 VDDQ DQU1 FBB_D40
A1 C8 A1 C8

1
C9127 C9126 C9125 C9130 VDDQ DQU2 FBB_D39 C9123 C9124 C9122 C9121 VDDQ DQU2 FBB_D47
C1 C2 C1 C2
VDDQ DQU3 VDDQ DQU3

SCD1U10V2KX-5GP
FBB_D33 FBB_D41
OPT OPT OPT OPT C9
VDDQ DQU4
A7 OPT OPT OPT OPT C9
VDDQ DQU4
A7

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP
D2 A2 FBB_D37 D2 A2 FBB_D45
2

2
VDDQ DQU5 FBB_D35 VDDQ DQU5 FBB_D43
E9 B8 E9 B8
VDDQ DQU6 FBB_D36 VDDQ DQU6 FBB_D44
F1 A3 F1 A3
VDDQ DQU7 VDDQ DQU7
H9 H9
VDDQ VDDQ
H2 C7 FBB_DQS_WP4 85 H2 C7 FBB_DQS_WP5 85
VDDQ DQSU VDDQ DQSU
B7 FBB_DQS_RN4 85 B7 FBB_DQS_RN5 85
VRAM7_VREF DQSU# VRAM7_VREF DQSU#
H1 H1
VRAM8_VREF VREFDQ VRAM8_VREF VREFDQ
M8 F3 FBB_DQS_WP7 85 M8 F3 FBB_DQS_WP6 85
VRAM_ZQ7 VREFCA DQSL VRAM_ZQ8 VREFCA DQSL
1
R9104
OPT 2
243R2F-2-GP
L8
ZQ DQSL#
G3 FBB_DQS_RN7 85 1
R9102
OPT 2
243R2F-2-GP
L8
ZQ DQSL#
G3 FBB_DQS_RN6 85
C K1 FBB_CMD18 85 K1 FBB_CMD18 85 C
ODT ODT
85,90 FBB_CMD9 N3 85,90 FBB_CMD9 N3
A0 A0
85,90 FBB_CMD11 P7 85,90 FBB_CMD11 P7
A1 A1
85,90 FBB_CMD8 P3 L2 FBB_CMD16 85 85,90 FBB_CMD8 P3 L2 FBB_CMD16 85
A2 CS# A2 CS#
85,90 FBB_CMD25 N2 T2 FBB_CMD5 85,90 85,90 FBB_CMD25 N2 T2 FBB_CMD5 85,90
A3 RESET# A3 RESET#
85,90 FBB_CMD10 P8 85,90 FBB_CMD10 P8
A4 A4
85,90 FBB_CMD24 P2 85,90 FBB_CMD24 P2
A5 A5
85,90 FBB_CMD22 R8 T7 FBB_CMD4 85,90 85,90 FBB_CMD22 R8 T7 FBB_CMD4 85,90
A6 NC#T7 A6 NC#T7
85,90 FBB_CMD7 R2 L9 85,90 FBB_CMD7 R2 L9
A7 NC#L9 A7 NC#L9
85,90 FBB_CMD21 T8 L1 85,90 FBB_CMD21 T8 L1
A8 NC#L1 A8 NC#L1
85,90 FBB_CMD6 R3 J9 85,90 FBB_CMD6 R3 J9
A9 NC#J9 A9 NC#J9
85,90 FBB_CMD29 L7 J1 85,90 FBB_CMD29 L7 J1
A10/AP NC#J1 A10/AP NC#J1
85,90 FBB_CMD23 R7 85,90 FBB_CMD23 R7
A11 A11
85,90 FBB_CMD28 N7 85,90 FBB_CMD28 N7
A12/BC# A12/BC#
85,90 FBB_CMD20 T3 J8 85,90 FBB_CMD20 T3 J8
A13 VSS A13 VSS
85,90 FBB_CMD14 M7 M1 85,90 FBB_CMD14 M7 M1
NC#M7 VSS NC#M7 VSS
M9 M9
VSS VSS
J2 J2
VSS VSS
85,90 FBB_CMD12 M2 P9 85,90 FBB_CMD12 M2 P9
BA0 VSS BA0 VSS
85,90 FBB_CMD27 N8 G8 85,90 FBB_CMD27 N8 G8
BA1 VSS BA1 VSS
85,90 FBB_CMD26 M3 B3 85,90 FBB_CMD26 M3 B3
BA2 VSS BA2 VSS
T1 T1
VSS VSS
A9 A9
VSS VSS
85 FBB_CLK1 J7 T9 85 FBB_CLK1 J7 T9
CK VSS CK VSS
85 FBB_CLK1# K7 E1 85 FBB_CLK1# K7 E1
CK# VSS CK# VSS
P1 P1
VSS VSS
85 FBB_CMD19 K9 85 FBB_CMD19 K9
CKE CKE
G1 G1
VSSQ VSSQ
F9 F9
VSSQ VSSQ
85 FBB_DQM4 D3 E8 85 FBB_DQM5 D3 E8
DMU VSSQ DMU VSSQ
85 FBB_DQM7 E7 E2 85 FBB_DQM6 E7 E2
DML VSSQ DML VSSQ
D8 D8
VSSQ VSSQ
D1 D1
VSSQ VSSQ
85,90 FBB_CMD13 L3 B9 85,90 FBB_CMD13 L3 B9
WE# VSSQ WE# VSSQ
85,90 FBB_CMD15 K3 B1 85,90 FBB_CMD15 K3 B1
CAS# VSSQ CAS# VSSQ
85,90 FBB_CMD30 J3 G9 85,90 FBB_CMD30 J3 G9
RAS# VSSQ RAS# VSSQ

H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP
72.52G63.A0U 72.52G63.A0U
B B

1D5V_VGA_S0 1D5V_VGA_S0

1
R9103 R9106
FBB_CLK1
OPT OPT

1K33R2F-GP

1K33R2F-GP
2

2
1

R9109 VRAM7_VREF VRAM8_VREF


162R2F-GP
1

1
OPT R9105 R9101

1
OPT C9111 OPT C9114
2

SCD1U10V2KX-5GP SCD1U10V2KX-5GP
OPT OPT
1K33R2F-GP

1K33R2F-GP
2

2
FBB_CLK1#
2

A A

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM7,8 (4/4)
Size Document Number Rev
A2 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 91 of 103

5 4 3 2 1
5 4 3 2 1

DCBATOUT
1 2 PR9249 3218_VID5 DIS_OPT GL -1 1226
86 VID5
0R0402-PAD-1-GP

3218_VID4
84.03668.037 84.03668.037
1 2 PR9246 1 2

SC10U25V5KX-GP
86 VID4 5V_S0 PU9201 PU9202
0R0402-PAD-1-GP

1
5V_S0

PC9233
PR9260 2 2
1 2 PR9245 3218_VID3 10R3F-GP 3 3
86 VID3
D 0R0402-PAD-1-GP 1 4 1 4 D

2
86 GPU_DPRSLP 10 10

1
SC4D7U10V5KX-4GP
1 2 PR9244 3218_VID2 9 9
86 VID2
0R0402-PAD-1-GP PR9234 7 7 PC9245
0R2J-2-GP SE47U25VM-14-GP
2 DY 1 8 6 8 6

2
1
PC9237
1 2 PR9250 3218_VID1 5 5 79.47612.A0L
86 VID1
0R0402-PAD-1-GP
VGA_CORE

2
86 VID0 1 2 PR9251 3218_VID0 FDMS3600-02-RJK0215-COLAY-GP FDMS3600-02-RJK0215-COLAY-GP

2
0R0402-PAD-1-GP PL9201 DIS_OPT
PC9244 1 2PWR_VGA_BST1_C
1 2 1 2
SC1U10V2KX-1GP

PR9225
-1 1220 PR9259 PC9232

3218_VID0
3218_VID1
3218_VID2
3218_VID3
3218_VID4
3218_VID5

1
COIL-D36UH-3-GP-U

PG9214
VGA_AGND 1R3F-GP SCD33U16V3KX-1GP PT9201 PT9202 79.47719.2CL
3D3V_S0 79.47719.2CL 2nd = 79.47719.2GL
DIS_OPT DIS_OPT DIS_OPT

SE470U2VDM-6-GP

SE470U2VDM-6-GP
VGA_AGND
DIS_OPT

2
1
3D3V_VGA_S0 2nd = 79.47719.2GL
DIS_OPT

10R2F-L-GP
68.R3610.20S

GAP-CLOSE-PWR-3-GP
49
48
47
46
45
44
43
42
41
40
39
38
37

2
1
-1 1220 PU9209
PR9253 74.03218.A33 2nd = 68.R3610.10T

VID0
VID1
VID2
VID3
VID4
VID5
VID6
PSI#
DPRSLP
PH0
PH1
GND

VCC
DY 3KR2J-2-GP
93 8209A_EN/DEM_VGA 1 PR9233 2
0R0402-PAD-1-GP

2
8,19,27,36,46,47 PM_SLP_S3#
PR9262 2 DY 1 0R2J-2-GP PWR_VGA_EN 1
EN BST1
36 PWR_VGA_BST1 DIS_OPTDIS_OPT
2 35 PWR_VGA_DRVH1
86,93 PWR_VGA_CORE_PGOOD
3
PWRGD DRVH1
34 PWR_VGA_SW1 DIS_OPT
IMON SW1 PWR_VGA_SWFB1
4 33 1 2 RP9262
PWR_VGA_FBRTN CLKEN# SWFB1 100R2F-L1-GP-U
1 2 5 32
PWR_VGA_FB FBRTN PVCC PWR_VGA_DRVL1
2 1 6 31
PWR_VGA_COMP 7
FB NCP3218GMNR2G-GP DRVL1
30 DIS_OPT DCBATOUT
PC9238 PR9210 PWR_VGA_TRDET# COMP PGND PWR_VGA_DRVL2
1 2 8
TRDET# DRVL2
29 GL -1 1226
SC150P50V2JN-3GP 127KR2F-GP 9 28 PWR_VGA_SWFB2 1 2

1
PC9234 PR9222 VARFREQ SWFB2 PWR_VGA_SW2
DIS_OPT DIS_OPT
SC18P50V2JN-1-GP 5K11R2F-L1-GP
10
VRTT SW2
27
PWR_VGA_DRVH2 RP9261
84.03668.037 84.03668.037
11 26

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
TTSNS DRVH2 PU9204 PU9205
12 25 PWR_VGA_BST2 100R2F-L1-GP-U
DIS_OPT

1
GND BST2

PC9214

PC9225

PC9226
PR9223 2 2

CSCOMP
DIS_OPT
VGA_FB_SENSE

CSSUM
34K8R2F-1-GP

SWFB3
CSREF
5V_S0 3 3

PWM3
RAMP
LLINE

OD3#
2 1 2 1VGA_FB_COMP
1 2 DIS_OPT 1 4 1 4

IREF
RPM

ILIM

2
RT
10 10
C PR9243 PC9231 9 9 C
1K65R2F-GP SC150P50V2JN-3GP VGA_AGND 7 7

13
14
15
16
17
18
19
20
21
22
23
24
DIS_OPT DIS_OPT DIS_OPT 8 6 8 6 DIS_OPTDIS_OPT

PWR_VGA_CSCOMP
5 5 DIS_OPTDIS_OPT

PWR_VGA_CSSUM
PWR_VGA_CSREF
1 PR9268 2 1 2 PR9247

PWR_VGA_RAMP
VGA_CORE

PWR_VGA_LLINE
PWR_VGA_IREF
PWR_VGA_RPM
49D9R2F-GP VGA_CORE

PWR_VGA_ILIM
PWR_VGA_RT
0R0402-PAD-1-GP FDMS3600-02-RJK0215-COLAY-GP FDMS3600-02-RJK0215-COLAY-GP
DIS_OPT NV_VCCSENSE 83 PL9202
1 2 1 2 1 2
DIS_OPT

PR9224
1 PR9269 2 1 2 PR9248 PR9209 PR9258 PC9222

1
COIL-D36UH-3-GP-U

PG9216
49D9R2F-GP 13KR2F-GP 1R3F-GP SCD33U16V3KX-1GP PT9203 PT9204
0R0402-PAD-1-GP 1 2
DIS_OPT DIS_OPT DIS_OPT

SE470U2VDM-6-GP

SE470U2VDM-6-GP
NV_VSSSENSE 83 DIS_OPT 79.47719.2CL

2
1

1
DIS_OPT

10R2F-L-GP
PC9203 2nd = 79.47719.2GL
SC1KP50V2KX-1GP
2

2 GAP-CLOSE-PWR-3-GP

2
1
PR9271

1
PR9235

PR9236

PR9241

PR9238
DIS_OPT PR9213 79.47719.2CL

20KR2F-L-GP
DIS_OPT 1K91R2F-1-GP

PR9214
VGA_AGND 1 2 2nd = 79.47719.2GL

1
0R0402-PAD-1-GP

2
DY DIS_OPT

2
VGA_AGND
DIS_OPT
DIS_OPT

2
80K6R2F-GP

69K8R2F-GP

649KR2F-GP

SC1U25V3KX-1-GP
162KR2F-L-GP

1
VGA_RAMP_L

PC9242
DIS_OPT

1
2
3D3V_VGA_S0 PC9240
NV:HW default boot up voltage to SC1500P50V2KX-2GP

2
GL=0.95V. need to stuff
PR9263, PR9278, PR9273, VGA_AGND VGA_AGND DIS_OPT PR4259
PR9274, PR9281, PR9282 DIS_OPT
DIS_OPT DIS_OPT
DIS_OPT 1 200KR2F-L-GP
2
PR9239 DIS_OPT
1

B B
PR9263 PR9272 PR9273 PR9274 PR9275 PR9276
DCBATOUT 1 2 DIS_OPT
10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

1KR2F-3-GP 1 PR9240 2 VGA_CSCOMP_SWFB1


DY DY DY PC9235 249KR2F-GP
1

SC1KP50V2KX-1GP
DIS_OPT
2

PR9242
VID5_1 VID3_1 VID2_1
1 DIS_OPT
2 VGA_CSCOMP_SWFB2
2

3218_VID5 249KR2F-GP
DIS_OPT
3218_VID4 DIS_OPT
VGA_AGND

3218_VID3

3218_VID2

3218_VID1

3218_VID0
1

PR9277 PR9278 PR9279 PR9280 PR9281 PR9282


10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

DY DY
2

VID4_0 VID1_0 VID0_0


DY

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

NCP3218_VGACORE25W
Size Document Number Rev
A2 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 92 of 103
5 4 3 2 1
5 4 3 2 1

VGA chip sequence: 3V_VGA_S0>VGA_CORE>1D5V_VGA>1D05V_VGA


3V_VGA_S0 VGA_CORE 1.5V_VGA_S0
1D5V_VGA_S0
3D3V_S5
Design current = 9A

2
PR9337
10KR2J-3-GP

D
100mils or Copper Shape D

1
1D5V_PGD 5V_S5
DY
DGPU_PWR_EN# 1 2 PR9304 DIS_OPT
0R2J-2-GP
DMP2130L-7-GP 3D3V_VGA_S0 PR9303 1 2 10KR2F-2-GP
DIS_OPT

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
3D3V_VGA_S0

PC9331

PC9332

PC9333

PC9334
IGPU H PQ9302

SCD1U10V2KX-5GP

PC9346
3D3V_S0 S

1
IGPU with BACO L D PD9301

D
DIS_OPT 84.02130.031

G
2ND = 84.03413.A31 3D3V_VGA discharge

2
2

1
DIS_OPT DGPU_PWR_EN K A 8209A_EN/DEM_VGA 8209A_EN/DEM_VGA 92

G
PR9316
10KR2J-3-GP DIS_OPT

2
PC9309 CH551H-30GP-GP
SCD1U10V2KX-5GP 83.R5003.J8F
1

Design Current = 9A
PR9317_1 1 PR9317 2 PR9317_2 2ND = 83.R5003.H8H
DIS_OPT DIS_OPT
DIS_OPT
DIS_OPT
10KR2J-3-GP PU9331 DIS_OPT
4K02R2F-GP
DIS_OPT DIS_OPT PR9331 PWR_1D5V_VSENSE+ A2 B5
SENSE+ VDD

2
2 1 2 1 PWR_1D5V_VSENSE- A3 C5 1D5V_VGA_S0
SENSE- VDD 400mils or Copper Shape

4
PR9314 -1 0104 PR9336 D5
PQ9303 PR9333 0R0402-PAD-1-GP VDD
470R2J-2-GP PL9331
2N7002KDW-GP 4K02R2F-GP 1 2 PWR_1D5V_STAT A4
8209A_EN/DEM_VGA 1 STAT
DIS_OPT DIS_OPT 2PWR_1D5V_OE A5 B2 PWR_1D5V_VX 1 2
84.2N702.A3F DIS_OPT

1
PC9335 PR9334 OE VX#B2
B3

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
1

3
150R2F-1-GP VX#B3

PC9345

PC9338

PC9339

PC9341

PC9343

PC9340
2nd = 84.2N702.E3F 1 2 1 2 B4
DY

SCD1U10V2KX-4GP

SCD1U10V2KX-5GP
3RD = 84.2N702.F3F 10KR2J-3-GP VX#B4 IND-D2UH-14-GP

1D5V_SENSE_1
PR9335 SC3300P50V2KX-1GP C2
VX#C2

1
PC9344

PC9337
DIS_OPT 3.3V_RUN_VGA_1
DIS_OPT A1
AGND VX#C3
C3
C4
VX#C4 DIS_OPT
DIS_OPT PC9342 DIS_OPT B1 D2

2
2N7002K-2-GP

2
GND VX#D2
PR9307 1 2 PC9336 C1 D3
AGND_386 GND VX#D3
S D1 D4
SC4700P50V2KX-1GP SC2200P50V2KX-2GP GND VX#D4 68.R2010.10Q

1
3D3V_S0 1 2
D 2nd = 68.R2010.20B
10KR2F-2-GP VT385FCX-ADJ-GP
G DIS_OPT DIS_OPT
21 DGPU_PWR_EN#
PQ9304 DIS_OPT DIS_OPT DIS_OPT
DIS_OPT
DIS_OPT
DIS_OPT
DIS_OPT
DIS_OPT
DIS_OPT

1
PG9331
84.2N702.J31 PR9332 1 2 74.00385.03Z
2ND = 84.07002.I31 DGPU_PWR_EN 13KR2F-GP
3RD = 84.2N702.W31 GAP-CLOSE-PWR-3-GP

2
AGND_386

DIS_OPT
Close to PL9331

C C

Close to output MLCC

1D05V_VGA Diff pair


PR9338
3D3V_VGA_S0 should ramp-up before VGA_Core PWR_1D5V_VSENSE+_R 1 2

VGA_Core should ramp-up before 1D5V_VGA_S0 0R0402-PAD-1-GP

1D5V_VGA_S0 should ramp up VSENSE-TRACE


1D05V_VGA_S0 ROUTED DIFFERENTIALLY
so 1D05V_VGA_S0 EN have to fine tune RC delay PR9339
after VGA_Core Design current = 3.8A PARALLEL TO VSENSE+ 1 2

0R0402-PAD-1-GP

Close to output MLCC

1D5V_VGA_S0

-1 1220
5V_S5 PC9356
1

1 PR9351 2 1D05_VGA_VCNTL SC1U6D3V2KX-GP


0R0402-PAD-1-GP
2
1

PU9301
PC9350 1D05V_VGA_S0
SC1U6D3V2KX-GP
2

5
VIN#5
6 4
PR9355 VCNTL VOUT#4
7 3
POK VOUT#3
1

1D5V_PGD 1D05V_VGA_EN PR9357


1 2 8
EN FB
2 R1
1

0R0402-PAD-1-GP 9 1 PC9359
VIN#9 GND
SC100P50V2JN-3GP

9K1R2J-1-GP
-1 1220
2
1

DY
2

APL5930KAI-TRG-GP 1D05_VGA_FB
DY
2

PC9355
SC1U6D3V2KX-GP 74.05930.03D
1

R2 PR9358
B 28K7R2F-GP B
2

Discharge Circuit

PR9305

3D3V_VGA_S0 1 2 1D05V_VGA_EN#1
DIS_OPT
100KR2J-1-GP
3D3V_VGA_S0
Discharge Circuit
6

4
1

PQ9301
PR9301 2N7002KDW-GP
10KR2J-3-GP
1D5V_VGA_S0 84.2N702.A3F DIS_OPT
1

PD9203 2 1 DY 2nd = 84.2N702.E3F


2

83.R0304.A8F 3RD = 84.2N702.F3F


2ND = 83.R2004.B8F CH751H-40PT-GP 3D3V_VGA_S0 1 2PR9302
86,92 PWR_VGA_CORE_PGOOD DGPU_PWROK 22
0R0201-PAD-GP
PR9306
DIS_OPT DIS_OPT
1

VGA_CORE 1D05V_VGA_DISCHG
2 1 1D05V_VGA_S0
PD9204 2 1 PC9302 1D05V_VGA_EN
83.R0304.A8F SC100P50V2JN-3GP
DIS_OPT
2

2ND = 83.R2004.B8F CH751H-40PT-GP 470R2J-2-GP

DIS_OPT

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DISCRETE VGA POWER


Size Document Number Rev
A1 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 93 of 103

5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 94 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 95 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 96 of 103
5 4 3 2 1
5 4 3 2 1

S1 S2 S3 S4
H1 H4 H5 H10
HOLE335R115-GP HOLE335R115-GP HOLE335R115-GPSTF256R117H221-GP
STF237R117H83-1-GP
STF237R117H83-1-GP
STF237R113H115-GP SPR1 SPR2 SPR3 SPR4 SPR5
HOLE256R115-GP H19 H9
HOLE HOLE
SPRING-9-GP
SPRING-57-GP
SPRING-57-GP
SPRING-24-GP-U
SPRING-24-GP-U
DY DY

1
1

1
D D

1
34.49U23.001 34.42T14.002

1
34.42T14.002
-1 0104 by Thermal
H11
HOLET335B256R115-GP H6 H7 H8 H20 H21
H12 H13 H14 H15 H16 H17 H18 HOLE256R115-GP HOLE256R115-GP HOLE256R115-GP HOLE256R115-GP HOLE
HOLE276R150-2-GP HOLE276R150-2-GP
HOLE276R150-2-GP
HOLE276R150-2-GP
HOLE276R150-2-GP
HOLE276R150-2-GP
HOLE276R150-2-GP
1

1
1

1
ZZ.PAD01.021
1D05V_S0 3D3V_AUX_KBC 5V_S5 ZZ.00PAD.D11
C 3D3V_AUX_S5 C

1
EC9719 EC9718 EC9717

1
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
EC9701 EC9702 EC9703 EC9704 EC9705 EC9706 EC9707 EC9708
1

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
EC9732 EC9733 EC9734 EC9735 EC9736 DY DY

2
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

DY DY DY DY DY DY

2
DY DY
2

1
5V_S0 EC9709 EC9710 EC9711 EC9712 EC9713 EC9714 EC9715 EC9716

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
DY DY

2
DY
1

1
EC9720 EC9721 EC9722 EC9723 EC9724 EC9725 EC9726 EC9727 EC9728 EC9729 EC9730 EC9731
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
DY DY DY DY DY DY DY DY DY
B B
2

2
DCBATOUT

2
EC9747 EC9748 EC9749 EC9750 EC9751 EC9752
3D3V_S5

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP
1

1
1

EC9739 EC9740 EC9741 EC9742 EC9743 EC9744 EC9745 EC9746 EC9737 EC9738
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
2

<Core Design>

DY DY DY DY DY
A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors


Size Document Number Rev
A4 1
Colossus
Date: Wednesday, January 04, 2012 Sheet 97 of 103
5 4 3 2 1
5 4 3 2 1

SPR10 SPR20 SPR21 SPR22

SPR11 SPR13
SPRING-57-GP SPRING-5-GP SPRING-5-GP SPRING-5-GP
SPRING-63-GP SPRING-57-GP

DDR3 for EMI


1

1
34.42T14.002 SPR6 change into SPR10

1
SPR7 change into SPR20 34.42T14.002
SPR8 change into SPR21 34.4Y806.001
D D
SPR9 change into SPR22

DCBATOUT DCBATOUT_5V 1D5V_VGA_S0 1D05V_VGA_S0


EC9801

EC9802

EC9803

EC9804

EC9805

EC9806

EC9807

EC9808

EC9809

EC9810

EC9811

EC9812

EC9813

EC9814

EC9815

EC9816

EC9817

EC9818

EC9819

EC9823

EC9824

EC9828
2

1
1

2
SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
1D05V_S0 0D85V_PW R 5V_S0 VCC_GFXCORE LCDVDD 3D3V_S0

G9801
EC9829

EC9830

EC9831

EC9832

EC9833

EC9834

EC9835

EC9836
1 2
1

1
GAP-CLOSE-PW R-3-GP
C G9802 C
2

2
SCD1U50V3KX-GP

SCD1U50V3KX-GP
1 2
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
GAP-CLOSE-PW R-3-GP
G9803
1 2
GAP-CLOSE-PW R-3-GP
G9804
1 2
GAP-CLOSE-PW R-3-GP
G9805
1 2

GAP-CLOSE-PW R-3-GP
AUD_AGND

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Change History
Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 98 of 103
5 4 3 2 1
5 4 3 2 1

Chief River Platform Power Sequence


(AC mode) red word: KBC GPIO
(DC mode) red word: KBC GPIO

+RTC_VCC
+RTC_VCC T1 >9ms
T1 >9ms
RTC_RST#
RTC_RST#
DCBATOUT
DCBATOUT T2
T2
Within logic high level and disable if
3D3V_AUX_S5
it is less than the logic low level.
3D3V_AUX_S5
D KBC GPIO34 control power on by 3V_5V_EN D

S5_ENABLE Sense the power button status


Press Power button
Platform to KBC GPXIOD3
5V_S5 T3 KBC_PWRBTN#
V5REF_Sus must be powered up before EC_ENABLE#_1(GPIO31) keep low
VccSus3_3, or after VccSus3_3 within 3D3V_S5 T4 3D3V_AUX_KBC
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before
T3 KBC GPIO34 control power on by 3V_5V_EN
VccSus3_3 within 0.7 V.
+5VA_PCH_VCC5REFSUS T5 S5_ENABLE
KBC GPXIOA6 to PCH
RSMRST#_KBC(EC Delay 40ms) T6 >10ms 5V_S5 T4
PCH to KBC GPIO5E V5REF_Sus must be powered up before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
PCH_SUSCLK_KBC T7 >5ms VccSus3_3, or after VccSus3_3 within 3D3V_S5 T5
0.7 V. Also, V5REF_Sus must power
KBC GPXIOA11 to PCH down after VccSus3_3, or before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
Not floating. VccSus3_3 within 0.7 V.
AC_PRESENT 0ms<T8 <90ms +5VA_PCH_VCC5REFSUS T6

T7 >16ms KBC GPIO20 to PCH


Press Power button
3D3V_AUX_KBC PM_PWRBTN#
Platform to KBC GPXIOD3
Sense the power button status
AC KBC_PWRBTN#
KBC GPXIOA5 to PCH
This signal has an internal T9 >16ms PM_RSMRST# T8 >10ms
pull-up resistor and has an KBC GPXIOA5 to PCH
internal 16 ms de-bounce on the PCH to KBC GPIO5E
input. AC PM_PWRBTN#
PCH_SUSCLK_KBC T9 >5ms

AC PM_PWRBTN# DC PCH_RSMRST#
T10 T10
PCH to KBC GPIO8 PCH to KBC GPIO8
PM_SLP_S4# PM_SLP_S4#
T11 PCH to KBC GPIO4 T11 PCH to KBC GPIO4
PM_SLP_S3# >30us PM_SLP_S3# >30us
KBC GPIO23 to LAN KBC GPIO23 to LAN
PM_LAN_ENABLE PM_LAN_ENABLE
Enable by PM_SLP_S4# Enable by PM_SLP_S4#
1D5V_S3 T12 1D5V_S3 T12

C
DDR_VREF_S3(0.75V) T13 DDR_VREF_S3(0.75V) T13 C
+5V_RUN & +3.3V_RUN need meet 0.7V difference +5V_RUN & +3.3V_RUN need meet 0.7V difference
5V_S0 T14 5V_S0 T14

V5REF must be powered up before 3D3V_S0 T15 V5REF must be powered up before 3D3V_S0 T15
Vcc3_3, or after Vcc3_3 within 0.7 V. Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V. Vcc3_3, or before Vcc3_3 within 0.7 V.
+5VS_PCH_VCC5REF T16 +5VS_PCH_VCC5REF T16

1D5V_S0 T17 1D5V_S0 T17

1D8V_S0 T18 1D8V_S0 T18

0D75V_S0 T19 0D75V_S0 T19


1D8V_S0 & 1D5V_S3 power ready 1D8V_S0 & 1D5V_S3 power ready
RUNPWROK T20 RUNPWROK T20

1D05V_VTT T21 1D05V_VTT T21


TPS51219R PGOOD TPS51219R PGOOD
1.05VTT_PWRGD(D85V_PWRGD) T22 1.05VTT_PWRGD T22

0D85V_PWR(0D85V_S0) T23 0D85V_S0 T23

0D85V_S0 0D85V_S0
T24 TPS51461RGER PGOOD T24 TPS51461RGER PGOOD
D85V_PWRGD D85V_PWRGD

SetVID ACK SetVID ACK


CPU SVID BUS 50us< T25 <2000us CPU SVID BUS 50us< T25 <2000us

VCC_CORE VCC_CORE

VCC_GFXCORE VCC_GFXCORE
T26 T26
<5ms
VT1318MFQX PGOOD to system <5ms
VT1318MFQX PGOOD to system
IMVP_PWRGD IMVP_PWRGD

CLK_EXP_P CLK_EXP_P
B
ALL_SYS_PWRGD=D85V_PWRGD ALL_SYS_PWRGD=D85V_PWRGD B
This signal represents the Power T27 >99ms KBC GPIOXA9 to PCH This signal represents the Power T27 >99ms KBC GPIOXA9 to PCH
Good for all the non-CORE and S0_PWR_GOOD Good for all the non-CORE and S0_PWR_GOOD
non-graphics power rails. non-graphics power rails.
T28 >0us T28 >0us
D85V_PWRGD D85V_PWRGD
2ms< T29 <650ms PCH to CPU 2ms< T29 <650ms PCH to CPU
PM_DRAM_PWRGD PM_DRAM_PWRGD
T30 >1ms T30 >1ms
T31 >2ms T31 >2ms
1D8V_S0 1D8V_S0
5ms< T32 <650ms PCH to CPU 5ms< T32 <650ms PCH to CPU
H_CPUPWRGD H_CPUPWRGD

SYS_PWROK T33 >0ms SYS_PWROK T33 >0ms


T34 >1ms+60us T34 >1ms+60us
1ms< T35 <100ms PCH to all system 1ms< T35 <100ms PCH to all system
PLT_RST# PLT_RST#
T36 <200us T36 <200us
DMI DMI

1D5V_VGA_S0(Discrete only)

N13P Power-Up/Down Sequence

3D3V_S0
PCH GPIO54 output
DGPU_PWR_EN#(Discrete only)

3D3V_VGA_S0(Discrete only)
3D3V_VGA_S0 above NCP3218 VIH
8209A_EN/DEM_VGA(Discrete only)
A A
VGA_CORE(Discrete only) Ta >0ms
Tb >0ms
1D5V_VGA_S0(Discrete only)

Tc >0ms
1D05V_VGA_S0(Discrete only)

NCP3218 PGOOD <Core Design>


DGPU_PWROK(Discrete only)
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
For power-down, reversing the ramp-up sequence is recommended. Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Sequence
Size Document Number Rev
A1 1
Colossus
Date: Monday, December 26, 2011 Sheet 99 of 103
5 4 3 2 1
5 4 3 2 1

COLOSUSS POWER BLOCK DIAGRAM


D D

AC
Adapter VT1318MFQX VCC_CORE
5V_S5 DC/DC
VIN
(CPU_CORE) VCC_GFXCORE
R2703 3D3V_AUX_KBC
D85V_PWRGD (VGFX_CORE)
RT8223M 5V_AUX_S5 VIN
OR3J 27 VR_ON
KBC_PWR_ON VREG5
EN IMVP_PWRGD
DC U1701 PGOOD1
DCBATOUT 3D3V_AUX_S5 RTC_AUX_S5
VIN VREG3 VIN SVID PGOOD2
Battery CH715FGP 17 SVID
DC/DC 42~44
Charger (+V3ALW/+V5ALW) 3D3V_S5 3D3V_S0
VIN
PM_SLP_S3# QM3004M3
BQ24738RGRR EN 36
C 40 C
1D5V_S3 1D5V_S0
VIN
5V_S5 5V_S0 QM3004M3
VIN PM_SLP_S3
PM_SLP_S3# QM3004M3 EN 36
EN 36
PGOOD 41

5V_S5
VDD RT8207MZQW RT8068A
1D5V_S3
1.5/0.75V Vout 3D3V_S5
VIN
1.8V 1D8V_S0
DCBATOUT RUNPWROK
RSMRST# VIN PGOOD PM_SLP_S3# RUNPWROK
EN
PM_SLP_S4# 47
S5
46
3D3V_S0
1D5V_S3
VLDOIN
3D3V_VGA_S0 0D75V_S0
DGPU_PWR_EN DMP2130L VTT
B
93 B
PWR_0D75V_EN
S3
(PM_SLP_S3#) 46
DCBATOUT
VIN VGA_CORE
5V_S5
8209A_EN/DEM_VGA NCP3218G V5 TPS51219R
EN/PSM PWR_VGA_CORE_PGOOD 1D05V_VTT (for CPU_VCCP)
PWRGD DCBATOUT
VIN
1.05V Vout 1D05V_S0 (for PCH)
92
PWR_1D05V_1V_EN 0D85V_EN
EN PGOOD
5V_S5 45
1D5V_VGA_S0
1D5V_VGA_EN VT385FCX 5V_S5
93 V5DRV TPS51461
(8209A_EN/DEM_VGA)
VIN
VCCSA 0D85V_PWR
1D05V_S0 Vout
0D85V_EN D85V_PWRGD
1D05V_VGA_S0 EN PGOOD
TPCC8065 48
1D5V_PGD 93
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram


Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 100 of 103
5 4 3 2 1
5 4 3 2 1

PCH SMBus Block Diagram 3D3V_S5 3D3V_S0 KBC SMBus Block Diagram 3D3V_S5



3D3V_S0 SRN10KJ-5-GP
SRN2K2J-1-GP SRN2K2J-1-GP

DIMM 1 TouchPad Conn.
D PSDAT1 TPDATA
TP_DATA TPDATA D
SMBCLK PCH_SMB_CLK
PCH_SMBCLK SCL
PSCLK1 TPCLK
TP_CLK TPCLK 27
SMBDATA PCH_SMB_DATA
PCH_SMBDATA SDA
14
18 3D3V_S5 3D3V_AUX_KBC
SMBus Address:A0
2N7002SPT

SRN2K2J-8-GP DIMM 2
3D3V_S0 PCH_SMBCLK SCL
3D3V_S5 PCH_SMBDATA SDA
15
SRN4K7J-8-GP

SML1CLK

SMBus Address:A4 SRN33J-7-GP Battery Conn.
SML1DATA PCH_SML1CLK GPIO17/SCL1 BAT_SCL BAT_SCL0 CLK_SMB 27
mSATA GPIO22/SDA1 BAT_SDA BAT_SDA0 DAT_SMB SMBus address:16
SRN2K2J-1-GP
PCH_SMBCLK SMB_CLK
PCH_SML1DATA 2N7002SPT PCH_SMBDATA
SMB_DATA
103
SML0CLK SML0_CLK BQ24725
SML0DATA SML0_DATA PCH_SML0_CLK
TouchPad
KBC SCL 27
3D3V_S0 PCH_SML0_DATA 69 SDA SMBus address:12
ENE
SML1_CLK 27
To KBC
PCH SML1_DATA 27 KB9016QF
SRN2K2J-1-GP
C C

3D3V_S5
SDVO_CTRLCLK PCH_HDMI_CLK Level DDC_CLK_HDMI

SDVO_CTRLDATA PCH_HDMI_DATA
Shift DDC_DATA_HDMI

HP_CLK
Headphone
3D3V_S0
HP_DATA
AMP 29
SRN2K2J-1-GP

SMBC_THERM_NV
VGA 86 GPIO73/SCL2 SML1_CLK SCL

SRN2K2J-1-GP
SMBD_THERM_NV thermal sensor GPIO74/SDA2 SML1_DATA SDA PCH
18

L_DDC_CLK LCD_SMBCLK

L_DDC_DATA LCD_SMBDATA
G-Sensor
G_CLK
CRT_DDC_CLK CRT_DDC_CLK SCLK
G_DAT SDATA
CRT_DDC_DATA CRT_DDC_DATA 79

SMBus address:xx

B B

DDC1CLK LCD_SMBCLK CLK

DDC1DATA LCD_SMBDATA DATA LCD CONN


103

DDC2CLK

DDC2DATA

103 3D3V_S0 5V_CRT_S0

VGA
3D3V_S0
SRN2K2J-1-GP SRN10KJ-6-GP

CRT_DDCCLK_CON

CRT_DDCDATA_CON
CRT CONN
5V_HDMI

2N7002DW-1-GP

A A
SRN1K5J-GP

<Core Design>
DDC2CLK DDC_CLK_HDMI
DDC2DATA DDC_DATA_HDMI
HDMI CONN Wistron Corporation
103 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SMBUS Block Diagram


Size Document Number Rev
A2 1
Colossus
Date: Monday, December 26, 2011 Sheet 101 of 103
5 4 3 2 1
5 4 3 2 1

Thermal Block Diagram Audio Block Diagram


D D

PORTD_+R SPKR_R+

DY PORTD_-R SPKR_R- MAIN


DY DY PORTD_+L SPKR_L+
SPEAKER
PAGE28 DXP P2800_DXP PORTD_-L SPKR_L-

MMBT3904-3-GP
P58
SC2200P50V2KX-2GP

DXN P2800_DXN
UMA Place near CPU
Codec PORTF_R FSPK_R
OUT_R+
Speaker AMP
Thermal PWM CORE
92HD91 PORTF_L FSPK_L TPA2012D2RTJR
OUT_R-

OUT_L+
2nd
P2800 OUT_L- SPEAKER
MMBT3904-3-GP
P58
PAGE27 AD4 SYS_THRM TDR T8
C
KBC AD3 CPU_THRM TDL

OTZ THERM_SYS_SHDN#
2N7002
D
PURE_HW_SHUTDOWN#
EN 3V/5V PORTB_L HP_OUT_L HPA_OUT_L HP
C

Head Phone AMP


ENE9016 S
G
IMVP_PWRGD PGOD
VR PORTB_R HP_OUT_R HPA00929RTJR HPA_OUT_R
Put under CPU(T8 HW shutdown) OUT P29

PORTA_L MIC_L0
FANPWM0 FANFB0

TP THRMDA
PORTA_R MIC_R0
MIC
PAGE18 VREFOUT_A +VREFOUT_A
FAN_TACH1
FAN1_PWM

PCH
TP THRMDC
VGA IN P29

5V_S0 SMBC_THERM_NV
SML1CLK PCH_SML1CLK I2CS_SCL
DualMOS
FAN_TACH1_C

SML1DATA PCH_SML1DATA SMBD_THERM_NV I2CS_SDA

B
86
DMIC_CLK/GPIO1 DMIC_CLK Digital B
DMIC_0/GPIO2 DMIC_DATA
MIC
P49
PWM TACH

FAN

MONO_OUT MONO_OUT
Woofer AMP WOOFER_- Woofer
TPA3111D1 WOOFER_+

P30
P29

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal/Audio Block Diagram


Size Document Number Rev
A3 1
Colossus
Date: Monday, December 26, 2011 Sheet 102 of 103
5 4 3 2 1
5 4 3 2 1

1D5V_S0 1D5V_S0_MSATA
3D3V_S0 3D3V_S0_MSATA R10304
2 DY 1
1 R10303 2

1
0R3J-0-U-GP C10311 C10312 C10313

2
0R0603-PAD-1-GP C10308 C10309 C10310 DY DY DY

SCD1U16V2KX-3GP
SC10U6D3V5KX-1GP

SCD1U16V2KX-3GP
D DY D

2
SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

SCD01U16V2KX-3GP
2

1
-1 1220

mSATA
MSATA1
53
1D5V_S0_MSATA 3D3V_S0_MSATA
NP1
1

1
3 DYC10306
SCD1U10V2KX-4GP
4
5

2
6
7
8
9
10
C 11 C
12
13
14
15
16

17
18
19
20
21
22 PLT_RST# 5,21,27,31,32,36,65,71,82,83
17 SATA_RXP1 1 2 C10303 SATA_RXP1_C 23
24 3D3V_S0_MSATA
17 SATA_RXN1 1 2 C10304 SATA_RXN1_C 25 C10305
26 1 2
SCD01U16V2KX-3GP 27
SCD01U16V2KX-3GP 28 SCD1U10V2KX-4GP
SCD01U16V2KX-3GP 29
SCD01U16V2KX-3GP 30 mSATA_PCH_SMBCLK R10302 1 2 PCH_SMBCLK 14,15,18
17 SATA_TXN1 1 2 C10302 SATA_TXN1_C 31 0R0402-PAD-1-GP
32 mSATA_PCH_SMBDATA R10301 1 2 PCH_SMBDATA 14,15,18
17 SATA_TXP1 1 2 C10301 SATA_TXP1_C 33 0R0402-PAD-1-GP
34
35
36
3D3V_S0_MSATA 37 -1 1220
B B
38
39
40
41
42
43
44
45
46 CLK_PCI_DEBUG 21,71
47
48
49 3D3V_S0_MSATA
50
22 mSATA_DET# 51
52
NP2

54
1

DYC10307
SCD1U10V2KX-4GP
SKT-MINI52P-95-GP
2

H= 5.2 mm
62.10043.E61
2ND = 62.10043.F81

677867-FM5
A <Core Design> A

1st 677867-FM5 Wistron Corporation


21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2nd 677867-AM5 Taipei Hsien 221, Taiwan, R.O.C.
3rd 677867-BM5
Title
4th 677867-LM5
mSATA
Size Document Number Rev
A3 1
Colossus
Date: W ednesday, January 04, 2012 Sheet 103 of 103
5 4 3 2 1

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