Digital Design

Chapter 3:
Sequential Logic Design -- Controllers
Slides to accompany the textbook Digital Design, with RTL Design, VHDL,
and Verilog, 2nd Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2010.
http://www.ddvahid.com

Copyright 2010 Frank Vahid

Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,
subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf
Digital
with animations) may Design 2e
not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means.
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Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors
Frank Vahid
may obtain PowerPoint source or obtain special use permissions from Wiley see http://www.ddvahid.com for information.
 3.1

Introduction
1
a 1
Sequential circuit b
0 Combinational
digital circuit
F

Output depends not just on present inputs (as in

combinational circuit), but on past sequence of inputs
1
Stores bits, also known as having state a
0 Sequential ? F
Simple example: a circuit that counts up in binary b digital circuit

This chapter will:

Must know
Design a new building block, a flip-flop, to store one bit sequence of
Combine flip-flops to build multi-bit storage register past inputs to
Describe sequential behavior with finite state machines know output
Convert a finite state machine to a controller
sequential circuit with a register and combinational logic

Digital Design 2e
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Frank Vahid Note: Slides with animation are denoted with a small red "a" near the animated items
 3.2
Storing One Bit Flip-Flops
Example Requiring Bit Storage
Call Blue light
button Bit 1
Flight attendant call button Cancel
button
Storage

Press call: light turns on

1. Call button pressed light turns on
Stays on after button released
Press cancel: light turns off Call Blue light

Stays off after button released

button Bit 1 a
Cancel Storage
Logic gate circuit to implement this? button

2. Call button released light stays on

Call Q
Cancel Call Blue light
a button Bit 0
Doesnt work. Q=1 when Call=1, but Cancel Storage

doesnt stay 1 when Call returns to 0 button

Need some form of feedback in the circuit 3. Cancel button pressed light turns off

Digital Design 2e
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 First attempt at Bit Storage
Need some sort of feedback S Q
Does circuit on the right do what we want? t
No: Once Q becomes 1 (when S=1), Q stays 1
forever no value of S can bring Q back to 0
S 0 S 1 S 1 S 0
0Q S 1 0Q 1Q 1Q 1Q a
0 0 0 1 1
t t t t t

1
S
0
1
t
0
1
Q
0

Digital Design 2e
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Frank Vahid
 Bit Storage Using an SR Latch
S (set) SR latch
Does the circuit to the right, with cross-coupled
NOR gates, do what we want?
Yes! How did someone come up with that circuit?
Q
Maybe just trial and error, a bit of insight...
R (reset)
S=0 S=0 S=1 S=0
t t t t Recall NOR
1 1 0 0 0
0 0 1 1 1
0

1
1 1 0 0 0
0 Q 0 Q 1 1 X
Q Q

R=1 R=0 R=0 R=0

1
S
0
R1
0 a

t 1
0
1
Q
0

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 Example Using SR Latch for Bit Storage
SR latch can serve as bit Call Blue light
storage in previous example button Bit
Storage
Cancel
of flight-attendant call button button

Call=1 : sets Q to 1
Q stays 1 even after Call=0 1
Call S 0
Cancel=1 : resets Q to 0 button

But, theres a problem...

Blue light
Q
Cancel
button
R
1

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 Problem with SR Latch
Problem
If S=1 and R=1 simultaneously, we dont know what value Q will take
1
S
0
1
R
0
1
t
0
1
Q
a
0

a
Q may oscillate. Then, because one path will be 1
slightly longer than the other, Q will eventually t
0
settle to 1 or 0 but we dont know which. 1
Q
Known as a race condition. 0

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 Problem with SR Latch
Designer might try to avoid problem using external circuit
Circuit should prevent SR from ever being 11
But 11 can occur due to different path delays
External circuit
Call Call S SR latch
button 1
Call
0

1
Cncl
Q 0
Cancel
button R
Cncl 1
S
0
Assume 1 ns delay per gate. The longer path from Call to SR = 11
R than from Call to S causes SR=11 for short time
1
could be long enough to cause oscillation R
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 Problem with SR Latch
Glitch can also cause 1
undesired set or reset Call
0
External circuit
Call Call S SR latch 1
button Cncl
0

Q 1
Cancel S
R
button Cncl 0
SR = 01
1 (undesired
Suppose this wire has 4 ns delay R glitch)
0
4 ns
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 Solution: Level-Sensitive SR Latch
Add enable input C Level-sensitive SR latch
S
Only let S and R change when C=0 S1
Ensure circuit in front of SR never sets
SR=11, except briefly due to path delays C
Set C=1 after time for S and R to be stable
When C becomes 1, the stable S and R Q
value passes through the two AND gates to R
R1
the SR latchs S1 R1 inputs. 1
Call
0 S
Level-sensitive SR latch Q
1 C
S Cncl Q
Call S1 0 R

1
S Level-sensitive
0 SR latch symbol
C
Clk 1
R
0
Q
1
R C Glitch on R (or S)
R1 0
Cncl doesnt affect R1 (or
1
S1 (S1)
0 Correct
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Frank Vahid a R1 0 enabled
 Level-Sensitive D Latch
D latch
SR latch requires careful design to D S
S1
ensure SR=11 never occurs
D latch relieves designer of that C

burden
Q
Inserted inverter ensures R always
R1
opposite of S R
a
1
D
0
1
C D Q
0 C Q

1
S1 D latch symbol
0 a

1
R1
0

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 Problem with Level-Sensitive D Latch
D latch still has problem (as does SR latch)
When C=1, through how many latches will a signal travel?
Depends on how long C=1
Clk_A signal may travel through multiple latches
Clk_B signal may travel through fewer latches

1 1? 1? 1?
Y D1 Q1 D2 Q2 D3 Q3 D4 Q4

C1 C2 C3 C4

Clk

Clk_A Clk_B

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 Problem with Level-Sensitive D Latch
D latch D latch
D2 0>1
D1 S1 S2
0>1 0>1
0>1

C2
C1 D3 Q3 D4 Q4
C3 C4
Q1 R2 Q2
R1 0>1 1>0 0>1
1>0
Clk
(a) Short clock
Long clock
Clk Clk
D1 D1
Q1/D2 Q1/D2 Q1 doesn't change a

a
S2 S2
R2 R2
Q2 2nd latch set Q2
(b) (c)
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 D Flip-Flop
Can we design bit
Flip-flop: Bit storage that stores on clock edge
storage that only
stores a value on One design master-servant
the rising edge of a Clk = 0 master enabled, loads D, appears at Qm.
clock signal? Servant disabled.
rising edges Clk = 1 Master disabled, Qm stays same.
a
Servant
Clk
latch enabled, loads Qm, appears at Qs.
Thus, value at D (and hence at Qm) when Clk
changes from 0 to 1 gets stored into servant
Clk
D flip-flop
D latch D latch D/Dm
D Q
Dm Qm Ds Qs
Cm
Q
Cm Cs Qs Qm/Ds
master servant Cs
Note:
Hundreds
Clk Qs
of different
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exist
 D Flip-Flop
Solves problem of not knowing through how many latches a signal
travels when C=1
In figure below, signal travels through exactly one flip-flop, for Clk_A or
Clk_B
Why? Because on rising edge of Clk, all four flip-flops are loaded
simultaneously then all four no longer pay attention to their input, until the
next rising edge. Doesnt matter how long Clk is 1.

1 1
Y D1 Q1 D2 Q2 D3 Q3 D4 Q4
Two latches inside
each flip-flop

Clk

Clk_A Clk_B

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 D Flip-Flop

D Q D Q Internal design: Just

invert servant clock
The triangle
means edge-
Q Q rather than master
triggered clock
input
Symbol for rising-edge Symbol for falling-edge
triggered D flip-flop triggered D flip-flop

rising edges falling edges

Clk Clk

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 D Latch vs. D Flip-Flop
Latch is level-sensitive
Stores D when C=1
Flip-flop is edge triggered
Stores D when C changes from 0 to 1
Saying level-sensitive latch or edge-triggered flip-flop is
redundant
Comparing behavior of latch and flip-flop:

Clk 1 2
a

D 3 4 5 6

Latch follows D
Q (D latch) 7 8
while Clk is 1
Flip-flop only loads D
Q (D flip-flop) 9 10
Digital Design 2e
during Clk rising edge
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 Clock Signal
Flip-flop Clk inputs typically connect to one clock signal
Clk
Coming from an oscillator component Osc.
Generates periodic pulsing signal
Below: "Period" = 20 ns, "Frequency" = 1/20 ns = 50 MHz
"Cycle" is duration of 1 period (20 ns); below shows 3.5 cycles

1
Clk
0
Time: 0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns
0 1 0 1 0 1 0

Freq. Period
100 GHz 0.01 ns
10 GHz 0.1 ns
Period/Freq shortcut: Remember 1 ns 1 GHz 1 GHz 1 ns
100 MHz 10 ns
10 MHz 100 ns
Digital Design 2e
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 Flight-Attendant Call Button Using D Flip-Flop
D flip-flop will store bit Call Call
D
button Comb. D Q Blue

Inputs are Call, Cancel, and present value Cancel Cncl Circuit
light

of D flip-flop, Q button
Clk Q
Q L
Truth table shown below

Preserve value: if
Q=0, make D=0; if
Q=1, make D=1
Cancel -- make Call Call Blue
D=0 but ton D Q
light
Cancel Cancel
but ton
Clk Q
Call -- make D=1 Q

Lets give priority

to Call -- make Circuit derived from truth table,
D=1 using Chapter 2 combinational
logic design process
Digital Design 2e
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 Bit Storage Summary
SR latch Level-sensitive SR latch D latch D flip-flop
S (set) S D S
S1 S1 D latch D latch
D Q
Dm Qm Ds Qs
C C Q
Cm Cs Qs
Q Q Q master servant
R
R1 R1 Clk
R (reset) R
Feature: S=1 Feature: S and R only Feature: SR cant be 11. Feature: Only loads D value
sets Q to 1, R=1 have effect when C=1. Problem: C=1 for too long present at rising clock edge,
resets Q to 0. An external circuit can will propagate new values so values can't propagate to
Problem: prevent SR=11 when through too many latches; other flip-flops during same
SR=11 yields C=1. for too short may not clock cycle. Tradeoff: uses
undefined Q, Problem: avoiding result in the bit being more gates internally, and
other glitches SR=11 can be a burden. stored. requires more external gates
may set/reset than SRbut transistors today
inadvertently. are more plentiful and cheaper.

We considered increasingly better bit storage until we arrived at the

robust D flip-flop bit storage
Digital Design 2e
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 Basic Register
Typically, we store multi-bit items
e.g., storing a 4-bit binary number
Register: multiple flip-flops sharing clock signal
From this point, well use registers for bit storage
No need to think of latches or flip-flops
But now you know whats inside a register

I3 I2 I1 I0
4-bit register
D D D D I3 I2 I1 I0
Q Q Q Q reg(4)
clk Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

Digital Design 2e
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 Example Using Registers: Temperature Display
Temperature history display
Sensor outputs temperature as 5-bit binary number
Timer pulses C every hour
Record temperature on each pulse, display last three recorded values

Present 1 hour ago 2 hours ago

Display Display Display
Temperature
sensor
24
x4 a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
21 x3
a
18 x2
TemperatureHistoryStorage
x1
x0
timer
C

Digital Design 2e
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 Example Using Registers: Temperature Display
Use three 5-bit registers

a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
24
I4 Q4 I4 Q4 I4 Q4
21 x4
I3 Q3 I3 Q3 I3 Q3
x3
18 x2
I2 Q2 I2 Q2 I2 Q2
I1 Q1 I1 Q1 I1 Q1
a
x1
I0 Q0 I0 Q0 I0 Q0
x0
Ra Rb Rc
C
TemperatureHistoryStorage

x4...x0 15 18 20 21 21 22 24 24 24 25 25 26 26 26 27 27 27 27

a Ra 0 18 21 24 25 26 27
Note that registers
only loaded on rising Rb 0 0 18 21 24 25 26
clock edges
Rc 0 0 0 18 21 24 25
Digital Design 2e
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 3.3

Finite-State Machines (FSMs) and Controllers

Want sequential circuit with b Controller
particular behavior over time x
laser

Example: Laser timer clk

Pushing button causes x=1 for patient

exactly 3 clock cycles
Precisely-timed laser pulse
0
How? Lets try three flip-flops
0 b
b=1 gets stored in first D flip- D Q D Q D Q
flop 1
Then 2nd flip-flop on next a clk
cycle, then 3rd flip-flop on x
next
OR the three flip-flop outputs, 1
so x should be 1 for three
cycles
Bad job what if button
Digital Design 2e
a pressed a second time during
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Frank Vahid those 3 cycles?
 Need a Better Way to Design Sequential Circuits
Also bad because of ad hoc design process
How create other sequential circuits?
Need
A way to capture desired sequential behavior
A way to convert such behavior to a sequential circuit

Step Description
Step 1: Create a truth table or equations, whichever is
Capture the
Capture most natural for the given problem, to describe
function
behavior the desired behavior of each output of the
combinational logic.
Like we had for
designing This substep is only necessary if you captured the
function using a truth table instead of equations. Create
combinational Step 2:
2A: Create
equations an equation for each output by ORing all the minterms
for that output. Simplify the equations if desired.
circuits Convert
to circuit 2B: Implement For each output, create a circuit corresponding
as a gate- to the outputs equation. (Sharing gates among
based circuit multiple outputs is OK optionally.)
Digital Design 2e
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 Capturing Sequential Circuit Behavior as FSM
Outputs: x
Finite-State Machine (FSM) clk^
x=0 x=1
Describes desired behavior of
sequential circuit Lo Hi
Akin to Boolean equations for
combinational behavior
clk^
List states, and transitions
among states
Lo Hi Lo Hi Lo Hi Lo Hi
Example: Toggle x every clock
cycle
Two states: Lo (x=0), and Hi cycle 1 cycle 2 cycle 3 cycle 4
clk
(x=1)
Transition from Lo to Hi, or Hi to
Lo, on rising clock edge (clk^) state Lo Hi Lo Hi
Arrow points to initial state Outputs:
(when circuit first starts)
x
Depicting multi- Lo Hi a

bit or other info

Digital Design 2e or
Copyright 2010 in a timing 26
Frank Vahid diagram Lo Hi
 FSM Example: Three Cycles High System
Want 0, 1, 1, 1, 0, 1, 1, 1, ...
For one clock cycle each Outputs: x
Capture as FSM x=0 clk^ x=1 clk^ x=1 clk^ x=1
Four states: 0, first 1, second Off On1 On2 On3
1, third 1
Transition on rising clock clk^
a

edge to next state

clk
State Off On1On2On3 Off On1On2On3 Off

Outputs:
x
a

Digital Design 2e
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 Three-Cycles High System with Button Input
Four states Inputs: b Outputs: x
x=0
Wait in Off while b is 0 clk^
Off b'*clk ^
(b*clk^)
When b is 1 (b*clk^), b*clk^
x=1 clk^ x=1 clk^ x=1
transition to On1 On1 On2 On3
Sets x=1
Next two clock edges,
transition to On2, then On3 clk

So x=1 for three cycles after Inputs:

button pressed b

State Off Off Off Off Off On1On2On3 Off

Outputs:
x
Digital Design 2e
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 FSM Simplification: Rising Clock Edges Implicit
Inputs: b; Outputs: x
Every edge ANDed with rising x=0
clk^
clock edge Off b *clk^
What if we wanted a transition
b*clk ^
without a rising edge x=1 clk^ x=1 clk^ x=1
We dont consider such On1 On2 On3
asynchronous FSMs less
common, and advanced topic
Only consider synchronous Inputs: b; Outputs: x
FSMs rising edge on every x=0
transition
Off b
a

b
x=1 x=1 x=1
Note: Transition with no associated condition
thus transistions to next state on next clock cycle On1 On2 On3

Digital Design 2e
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 FSM Definition
FSM consists of Inputs: b; Outputs: x
Set of states x=0
Ex: {Off, On1, On2, On3} Off b
Set of inputs, set of outputs
Ex: Inputs: {b}, Outputs: {x} b
x=1 x=1 x=1
Initial state
On1 On2 On3
Ex: Off
Set of transitions
Each with condition We often draw FSM graphically,
Describes next states known as state diagram
Ex: Has 5 transitions
Set of actions Can also use table (state table), or
textual languages
Sets outputs in each state
Ex: x=0, x=1, x=1, and x=1

Digital Design 2e
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 FSM Example: Secure Car Key
Many new car keys include
tiny computer chip
When key turned, cars computer
(under engine hood) requests
identifier from key Inputs: a; Outputs: r
Key transmits identifier
Wait
Else, computer doesnt start car
r=0 a
a
FSM
Wait until computer requests ID K1 K2 K3 K4
(a=1) r=1 r=1 r=0 r=1
Transmit ID (in this case, 1 1 0 1)

Digital Design 2e
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 FSM Example: Secure Car Key (cont.)
Inputs: a; Outputs: r
Nice feature of FSM
Wait
Can evaluate output behavior r=0 a
a
for different input sequence
Timing diagrams show states K1 K2 K3 K4

r=1 r=1 r=0 r=1

and output values for different
input waveforms
Q: Determine states and r value for
given input waveform:
clk clk
Inputs Inputs
a
a
State Wait Wait K1 K2 K3 K4 Wait Wait State Wait Wait K1 K2 K3 K4 Wait K1

Outputs Output a

r r

Digital Design 2e
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 Ex: Earlier Flight-Attendant Call Button
Previously built using SR latch,
Call Blue light
then D flip-flop button Bit
Cancel Storage
Capture desired bit storage button

behavior using FSM instead

Clear and precise description of
desired behavior
Well later convert to a circuit
Inputs: Call, Cncl Outputs: L

L=0 Call L=1

Call' LightOff LightOn

(Cncl*Call')'
Cncl*Call'

Digital Design 2e
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 How To Capture Desired Behavior as FSM

List states
Give meaningful names, show initial state
Optionally add some transitions if they help
Create transitions
For each state, define all possible transitions leaving that state.
Refine the FSM
Execute the FSM mentally and make any needed improvements.

Digital Design 2e
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 FSM Capture Example: Code Detector
Unlock door (u=1) only Start
s 1
u
when buttons pressed r
Red Code Door
in sequence: g detector lock
Green
start, then red, blue, Blue b
green, red a

Input from each button: a

s, r, g, b Inputs: s,r,g,b,a
Also, output a Outputs: u
Wait Wait for start button
indicates that some
colored button u=0 s s'
pressed
Capture as FSM Start Wait for first coloredbutton
a
List states u=0 ar
Some transitions
included ab ag ar
Red1 Blue Green Red2
u=0 u=0 u=0 u=1

Digital Design 2e
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 FSM Capture Example: Code Detector
Capture as FSM Start
s
u
List states r Door
Red Code
Create transitions a Green
g detector lock
Blue b
a

Inputs: s,r,g,b,a
Outputs: u
Wait
a
u=0 s s' ar'
Start a'
u=0 ar
ab ag ar
Red1 Blue Green Red2
u=0 u=0 u=0 u=1

Digital Design 2e
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Frank Vahid
 FSM Capture Example: Code Detector
Capture as FSM Start
s
u
List states r Door
Red Code
Create transitions a Green
g detector lock
Repeat for remaining Blue b
states a
Refine FSM
Mentally execute Inputs: s,r,g,b,a
Works for normal Outputs: u
sequence
Check unusual cases Wait
All colored buttons u=0 s s'
pressed ar' ab' ag' ar'
Door opens!
Start a'
Change conditions:
other buttons NOT u=0
pressed also ar
ab ag ar
Red1 Blue Green Red2
a' a' a'
u=0 u=0 u=0 u=1
Digital Design 2e
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 FSM Capture Example: Code Detector
s
Start
u
Red r Door
Code
g detector lock
a Green
Blue b
a

Inputs: s,r,g,b,a
Outputs: u
Wait
u=0 s s'
')'
'g

')
rb

b')'
'g'
a(

'
Start

a(rb'g')
br

a' a(gr'
a(

u=0
arb'g'
abr'g' agr'b' arb'g'
Red1 Blue Green Red2
a' a' a'
u=0 u=0 u=0 u=1
Digital Design 2e
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Frank Vahid
 3.4

Controller Design Laser timer FSM

Inputs: b; Outputs: x
Converting FSM to sequential circuit x=0
Circuit called controller Off b
Standard controller architecture
State register stores encoding of b
x=1 x=1 x=1
current state
e.g., Off:00, On1:01, On2:10, On3:11 On1 On2 On3
Combinational logic computes outputs
and next state from inputs and current
state Controller for laser timer FSM
Rising clock edge takes controller to Laser timer controller
next state b x
FSM Combinational n1 FSM
Controller logic
I O inputs outputs
Combinational
n0
FSM logic FSM s1 s0
General inputs outputs
S clk State register
form m
m-bit m
a clk
state register

Digital Design 2e N
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 Controller Design Process
Step Description
Step 1:
Capture the Create an FSM that describes the desired behavior
Capture
FSM of the controller.
behavior
Use state register of appropriate width and combinational
2A: Set up logic. The logics inputs are the state register bits and the
architecture FSM inputs; outputs are next state bits and the FSM outputs.

2B: Encode Assign unique binary number (encoding) to each state.

Usually use fewest bits, assign encoding to each state by
the states counting up in binary.
Step 2:
Convert Translate FSM to truth table for combinational logic such that
to circuit 2C: Fill in the logic will generate the outputs and next state signals for
the truth table the given FSM. Ordering the inputs with state bits first makes
the correspondence between the table and the FSM clear.
2D: Implement Implement the combinational logic using any method.
combinational
logic
Digital Design 2e
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Frank Vahid
 Controller Design: Laser Timer Example
Step 1: Capture the FSM Inputs: b; Outputs: x
x=0
Already done 00
Off b
Step 2A: Set up architecture a

b
2-bit state register (for 4 states) x=1 x=1 x=1

Input b, output x 01 On1 10 On2 11 On3

Next state signals n1, n0

Step 2B: Encode the states

outputs
inputs
FSM
b x

FSM
Combinational n1
Any encoding with each state logic
unique will work n0
a
s1 s0

clk State register

Digital Design 2e
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 Controller Design: Laser Timer Example (cont)
Step 2C: Fill in truth table Inputs: b; Outputs: x
x=0
00
Off b
a
b
x=1 x=1 x=1
01 On1 10 On2 11 On3

outputs
inputs
FSM

FSM
b x
Combinational n1
logic
n0
s1 s0
clk State register

Digital Design 2e
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Frank Vahid
 Controller Design: Laser Timer Example (cont)
Step 2D: Implement

outputs
inputs
FSM

FSM
b x
combinational logic Combinational n1
logic
n0
a
s1 s0
clk State register

x = s1 + s0 (note that x=1 if s1=1 or s0=1)

n1 = s1s0b + s1s0b + s1s0b + s1s0b

n1 = s1s0 + s1s0

n0 = s1s0b + s1s0b + s1s0b

n0 = s1s0b + s1s0

Digital Design 2e
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Frank Vahid
 Controller Design: Laser Timer Example (cont)
Step 2D: Implement b
Combinational Logic
x

outputs
inputs
combinational logic (cont)

FSM

FSM
b x
Combinational n1
logic n1 a
n0
s1 s0
clk State register
n0

s1 s0

clk State register

x = s1 + s0
n1 = s1s0 + s1s0
n0 = s1s0b + s1s0

Digital Design 2e
Copyright 2010 44
Frank Vahid
 Understanding the Controllers Behavior
x=0 x=0 x=0
00 b 00 b 00 b
Off Off Off
b b b
x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1
01 On1 10 On2 11 On3 01 On1 10 On2 11 On3 01 On1 10 On2 11 On3

b x b x b x
0 0 0
0 0 0 1 0 0 1 1 1
0 0 1
n1 n1 n1
0 0 1
0 0 0 a
0 1 0
n0 n0 n0
0 1 0
0 0 0
s1 s0 s1 s0 s1 s0
clk clk clk
0 0 0 0 0 1
0 0 0 1 1 0

clk state=00 state=00 state=01

Inputs:
b
Outputs:
x

Digital Design 2e
Copyright 2010 45
Frank Vahid
 Controller Example:
Button Press Synchronizer

Button press
bi synchronizer
bo
controller

Want simple sequential circuit that converts button press to

single cycle duration, regardless of length of time that
button was actually pressed
We assumed such an ideal button press signal in earlier example,
like the button in the laser timer controller

Digital Design 2e
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Frank Vahid
 Controller Example:
Button Press Synchronizer (cont)

outputs
inputs

FSM
bi bo

FSM
FSM inputs: bi; FSM outputs: bo Step 2A: Set up architecture
Combinational
bi logic n1
bi
bi n0
A bi B bi C bi s1 s0 n1 = s1s0bi + s1s0bi a
n0 = s1s0bi
bo=0 bo=1 bo=0 State register bo = s1s0bi + s1s0bi = s1s0
clk
Combinational logic
Step 1: Capture FSM bo

bi

n1
FSM inputs: bi; FSM outputs: bo
bi n0
bi
bi
00 bi 01 bi 10 bi
s1 s0
bo=0 bo=1 bo=0
State register
clk
Step 2B: Encode states
Step 2C: Fill in truth table Step 2D: Implement
combinational logic
Digital Design 2e
Copyright 2010 47
Frank Vahid
 Controller Example: Sequence Generator
Want generate sequence 0001, 0011, 1100, 1000, (repeat)
Each value for one clock cycle
Common, e.g., to create pattern in 4 lights, or control magnets of a stepper motor
w
Inputs: none; Outputs: w,x,y,z x Inputs: none; Outputs: w,x,y,z
y
wxyz=0001 wxyz=1000 Combinational z wxyz=0001 wxyz=1000
logic
A D n1 A D
n0 00 11
s1 s0
State register 01 10
B C clk B C
wxyz=0011 wxyz=1100 wxyz=0011 wxyz=1100
Step 1: Create FSM Step 2A: Set up architecture Step 2B: Encode states
w
w = s1 x
x = s1s0 y
y = s1s0
z
z = s1
a
n1 = s1 xor s0
n0 = s0
n0 n1
s1 s0
clk State register
Digital Design 2e Step 2C: Fill in truth table
Copyright 2010 Step 2D: Implement combinational logic 48
Frank Vahid
 Controller Example: Secure Car Key
Inputs: a; Outputs: r
(from earlier example)
Wait
r=0 a a
Step 1

a
K1 K2 K3 K4
r=1 r=1 r=0 r=1
a r
Step 2A
Combinational
logic n2
n1
n0

s2 s1 s0
clk State register

Inputs: a; Outputs: r

000
r=0 a
Step 2B

001 010 011 100

r=1 r=1 r=0 r=1
Step 2C
Digital Design 2e
Copyright 2010
Well omit Step 2D 49
Frank Vahid
 Converting a Circuit to FSM (Reverse Engineering)
2D: Circuit to eqns Step 1: FSM (get from table)
What does this y=s1 a A B

circuit do? z = s1s0

n1=(s1 xor s0)x states
x y D C
n0=(s1*s0)x
z 2C: Truth table Outputs:y, z

A B states
n1 yz=10 yz=10
with
D C outputs
n0 yz=00 yz=01

s1 s0
Inputs: x; Outputs:y, z
State register
clk x
x A B yz=10
yz=10 x x
Work backwards D x C yz=01

yz=00
2B: (Un)encode states x

Pick any state names you want states with

outputs and
Digital Design 2e transitions
Copyright 2010 50
Frank Vahid 2A: Set up arch already done
 Reverse Engin. the D-flip-flop Flight Atten. Call Button
Call
button D Q Blue 2C:
light
Cancel Truth
button
Clk Q table
L

2B:
(Un)encode
2D: Circuit to eqns states
L=Q
D = Cncl'Q + Call (next state) 2A: Set up
arch (nothing
Dont let the way the circuit is drawn to do)
confuse you; the combinational logic is Inputs: Call, Cncl Outputs : L

everything outside the register L=0 Call L=1

Step 1: FSM Call' LightOff LightOn

(get from table) Cncl'+Call
Call'*Cncl
Digital Design 2e
Copyright 2010 51
Frank Vahid
 Common Mistakes when Capturing FSMs

Non-exclusive transitions Incomplete transitions

a

a a

b ab
ab=11 what if
next state? ab=00?

ab

a a

ab ab

Digital Design 2e
Copyright 2010 52
Frank Vahid
 Verifying Correct Transition Properties
Can verify using Boolean algebra Answer:
a * ab
Only one condition true: AND of each condition pair (for = (a * a) * b
transitions leaving a state) should equal 0 proves pair =0*b
can never simultaneously be true =0 a
OK!
One condition true: OR of all conditions of transitions
leaving a state) should equal 1 proves at least one a + ab
= a*(1+b) + ab
condition must be true = a + ab + ab
Example = a + (a+a)b
a =a+b
Fails! Might not
be 1 (i.e., a=0,
ab b=0)

Q: For shown transitions, prove whether:

* Only one condition true (AND of each pair is always 0)
* One condition true (OR of all transitions is always 1)
Digital Design 2e
Copyright 2010 53
Frank Vahid
 Verifying transition properties
Recall code detector FSM
We fixed a problem with the Wait
u=0 s s a
transition conditions
Do the transitions obey the two Start
required transition properties? u=0 ar a
Consider transitions of state ab ag ar
Start, and the only one true Red1 Blue Green Red2
a a a
property u=0 u=0 u=0 u=1
ar * a a * a(r+b+g) ar * a(r+b+g) Intuitively: press red and blue
= (a*a)r = 0*r = (a*a)*(r+b+g) = 0*(r+b+g) buttons at same time: conditions
= (a*a)*r*(r+b+g) = a*r*(r+b+g) ar, and a(r+b+g) will both be
=0 =0 = arr+arb+arg true. Which one should be
taken?
= 0 + arb+arg
= arb + arg Q: How to solve? a

= ar(b+g)
A: ar should be arbg
Fails! Means that two of Starts
(likewise for ab, ag, ar)
transitions could be true
Note: As evidence the pitfall is common,
Digital Design 2e we admit the mistake was not initially intentional.
A reviewer of an earlier edition of the book caught it. 54
Copyright 2010
Frank Vahid
 Simplifying Notations
a=0 a=0
FSMs b=1 b=0
Assume unassigned c=0 c=1
output implicitly a
assigned 0
clk a
Sequential circuits
b=1 b=0
Assume unconnected c=1
clock inputs connected
to same external clock

Digital Design 2e
Copyright 2010 55
Frank Vahid
 Mathematical Formalisms
Two formalisms to capture behavior thus far
Boolean equations for combinational circuit design
FSMs for sequential circuit design
Not necessary
But tremendously beneficial
Structured methodology
Correct circuits
Automated design, automated verification, many more advantages

Digital Design 2e
Copyright 2010 56
Frank Vahid
 3.5

More on Flip-Flops and Controllers

Non-ideal flip-flop behavior clk
Cant change flip-flop input too close to clock edge
Setup time: time D must be stable before edge D
Else, stable value not present at internal latch
Hold time: time D must be held stable after edge setup time
Else, new value doesnt have time to loop around
and stabilize in internal latch clk

Setup time violation D

D latch C
D
S
D 1 hold time
Q S
C 2
u

3 4
Q R
u 7
R Q Leads to oscillation!
Q 5 6
Digital Design 2e
Copyright 2010 57
Frank Vahid
 Metastability clk

D
Violating setup/hold time can lead to bad
situation
setup time
Metastable state: Any flip-flop state other violation
than stable 1 or 0
Eventually settles to either, but we dont Q
know which
For internal circuits, we can make sure to metastable
observe setup time state
But what if input is from external
(asynchronous) source, e.g., button ai

press?
Partial solution
Insert synchronizer flip-flop for a

asynchronous input
Special flip-flop with very small setup/hold
time ai

synchronizer
Digital Design 2e
Copyright 2010 58
Frank Vahid
 Metastability
Synchronizer flip-flop doesnt completely prevent metastability
But reduces probability of metastability in dozens/hundreds of internal flip-
flops storing important values
Adding more synchronizer flip-flops further reduces probability
First ff likely stable before next clock; second ff very unlikely to have setup time
violated
Drawback: Change on input is delayed to internal flip-flops
By three clock cycles in below circuit

Probability of flip-flop being

metastable is:
very
very very incredibly
low low low low
a

ai

synchronizers
Digital Design 2e
Copyright 2010 59
Frank Vahid
 Example of Reducing Metastability Probability
Recall earlier secure car key controller
Inputs: a; Outputs: r a

Wait
r=0 a
a
Adding synchronizer flip-flop reduces
K1 K2 K3 K4
metastability probability in state
r=1 r=1 r=0 r=1
outputs
register, at expense of 1 cycle delay
a r
Original
D a r
Combinational a
FSM

inputs

logic n2 flip-flop
Combinational
n1 n2
logic
n0 n1
n0
s2 s1 s0 s2 s1 s0

clk
State register clk
State register

Digital Design 2e a
Copyright 2010 60
Frank Vahid
 Flip-Flop Set and Reset Inputs
Some flip-flops have D Q D Q D
AR
Q

additional reset/set inputs Q

Q Q
Synchronous AR AS
R

Synch. reset: Clears Q to 0 on

next clock edge
Synch. set: Sets Q to 1 on next
clock edge
Have priority over D input
Asynchronous
Asynch. reset: Clear Q to 0,
independently of clock
Example timing diagram shown
Asynch. set: set Q to 1, indep. of
clock

Digital Design 2e
Copyright 2010 61
Frank Vahid
 Initial State of a Controller
All our FSMs had initial state Inputs: x; Outputs: b
x=0
But our sequential circuits did not
Off b
Can accomplish using flip-flops
b
with reset/set inputs x=1 x=1 x=1
Shown circuit initializes flip-flops to On1 On2 On3
01
Designer must ensure reset- b x
Combinational
controller input is 1 during power n1
logic
up of circuit n0
s1 s0
By electronic circuit design State register
clk
D Q D Q
Controller with reset to initial
Q Q
state 01 (assuming state Off reset
R S

was encoded as 01). controller

Digital Design 2e
Copyright 2010 62
Frank Vahid
 Glitching
Glitch: Temporary values on outputs that appear soon after
input changes, before stable new output values
Designer must determine whether glitching outputs may
pose a problem
If so, may consider adding flip-flops to outputs
Delays output by one clock cycle, but may be OK
Called registered output

b x xr
Combinational n1 D
logic flip-flop
n0
s1 s0
State register
Laser timer controller with flip-
flop to prevent glitches on x from
unintentionally turning on laser
Digital Design 2e
Copyright 2010 63
Frank Vahid
 Glitching
Alternative registered output approach, avoid 1 cycle delay:
Add extra state register bit for each output
Connect output directly to its bit
No logic between state register flip-flop and output, hence no glitches

Inputs: b Outputs: x
b x
x=0
Combinational n1
000
Off b logic n0
nx
b
s1 s0 sx
x=1 x=1 x=1
011 On1 101 On2 111 On3 State register

Digital Design 2e But, uses more flip-flops, plus more

Copyright 2010 64
Frank Vahid logic to compute next state
 Product Profile: Pacemaker

Digital Design 2e
Copyright 2010 65
Frank Vahid
 Product Profile: Pacemaker

Pacemaker Inputs: s, z
Osc Outputs: t, p
ra la t=1, p=0
s
rv lv ResetTimer sz
Controller
p
t z Wait
sz
Timer s
t=0
(counts down p=0 Pace p=1
from 0.8s) t=0

Basic pacemaker

Digital Design 2e
Copyright 2010 66
Frank Vahid
 Product Profile: Pacemaker

Pacemaker right atrium Inputs: sa, za, sv, zv

Osc Outputs: pa, ta, pv, tv
left atrium ta=1
sa
sa*za
pa ResetTimerA
Controller
sv
WaitA
pv sa*za
pa=1
ta za tv zv sv
right left PaceV PaceA
sa
ventricle ventricle pv=1
sv*zv WaitV tv=1
TimerA TimerV
ResetTimerV
sv*zv
Atrioventricular
pacemaker
Digital Design 2e
Copyright 2010 67
Frank Vahid
 Chapter Summary
Sequential circuits
Have state
Created robust bit-storage device: D flip-flop
Put several together to build register, which we used to store state
Defined FSM model to capture sequential behavior
Using mathematical models Boolean equations for combinational
circuit, and FSMs for sequential circuits is important
Defined Capture/Convert process for sequential circuit
design
Converted FSM to standard controller architecture
So now we know how to build the class of sequential
circuits known as controllers
Digital Design 2e
Copyright 2010 68
Frank Vahid