Circuit and Process Co-Design with Vertical Gate-All-Around

Nanowire FET Technology to Extend CMOS Scaling

for 5nm and Beyond Technologies
T. Huynh Bao1,2, D. Yakimets1,3, J. Ryckaert1, I. Ciofi1, R. Baert1, A.Veloso1, J. Boemmels1, N. Collaert1, P. Roussel1,
S. Demuynck1, P. Raghavan1, A. Mercha1, Z. Tokei1, D. Verkest1,2, A. V-Y. Thean1, P. Wambacq1,2
1
Imec, Kapeldreef 75, B-3001 Leuven, Belgium; Email: huynh@imec.be
2
Vrije Universiteit Brussel, Brussel, Belgium; 3Katholieke Universiteit Leuven, Heverlee, Belgium

AbstractThis paper presents a vertical gate-all-around
nanowire FET (VFET) architecture targeting 5nm and beyond
technologies, and a new standard-cell construct for digital flow
implementation. VFET technology circuits and parasitics for
processes and design features aligned with 5nm CMOS are
systematically assessed for the first time. Self-aligned quadruple
pattering (SAQP) is implemented to achieve required 12nm half-
pitch interconnects, and the worst case RC delay corner is 1.4X
slower than best case corner. Our work shows that interconnect
delay variability of a wire of average length in SoCs can
overwhelm device variability. Consequently, a new device
architecture with a smaller footprint as VFET would effectively
lower the BEOL variability by shortening the wirelength and
help SRAM bit cells to follow 50% area scaling trend. It is shown
that a VFET-based D Flip-Flop (DFF) and 6T-SRAM cell can
offer 30% smaller layout area than FinFET (or equivalent lateral
2D) based designs. Furthermore, we obtain a 19% reduction in
routing area of a 32-bit multiplier implemented with a VFET-
based standard-cell library w.r.t. the FinFET design.
Keywords5nm, DTCO, multiple patterning, parametric yield,
SRAM, standard-cell library, statistical simulation, variability,
vertical GAA nanowire FETs
I. INTRODUCTION
Challenged by upcoming limitations of lithography,
patterning, and costs, the continual circuit density for scaling
post 7nm is in question. In 2D conventional layouts, gate and
contact placement competes to limit cell width as in Fig. 1
while interconnect routing congestion limits cell height.
At the same time, parasitics, variability, and device
electrostatics are among the process factors that limit the circuit
performance, important to power scaling. Overcoming these
limitations to extend CMOS scaling may require fairly
disruptive architectures that demand early process-design
cross-disciplinary assessments. Starting with anticipated 5nm
technology, this paper will address technological and design-
related issues of VFETs as a potential candidate to succeed 2D
logic/SRAM layouts.
II. EXPERIMENTS
A. Device
Process assumptions are depicted in Fig. 2. Nanowires
(NW) are formed on Silicon wafer by either hetero-epitaxial
growth or an etch definition with a hard-mask template
patterned by directed self-assembly to achieve deep sub-
lithographic features/pitches. The channel may be Si, Ge, III-V
and are surrounded by high-k metal gate stack to achieve
ultimate electrostatic control [1]. Top and bottom electrode
(TE, BE) are assumed to be Tungsten (W). Source/Drain (S/D)
connections are made by W contacts.

Fig. 2. (a) FEOL and BEOL stack assumptions. (b) 3D VFET inverter
generated by Raphael which is used for extracing parasitics

A target compact model is built based on BSIM-CMG [2].

RC parasitics are extracted and modeled by Raphael [3] as
described in Fig. 2. Device Vth shifts and current gain
variability are extrapolated from imec devices as in Fig. 3
(Avt=1mV.m, A=0.94%.m) and modeled by voltage and
current sources [4].
Fig. 1. Source/Drain contact size scaling challenges: a trade-off between
electrostatic control (Lg) and S/D resistance.

978-1-4799-4376-0/14/$31.00 2014 IEEE 102

 Carlo simulation framework and unit capacitance distribution
are presented in Fig. 5.

Fig. 3. Pelgrom plots for FDSOI MOSFET and FinFET[5-9]

B. BEOL
To achieve the required 24nm metal pitch interconnects, a
SAQP process flow is assumed as in Fig. 4a, providing a good
control in critical dimension uniformity (CDU), line width
roughness (LWR) and line-edge roughness (LER) [10]. MC,
MS, MG are metal trenches which are defined by the mandrel,
spacer and gap between the mandrel respectively. Process
parameters and their variation are derived from measurements
and summarized in the Table I.
Fig. 5. (a) Monte Carlo simulation framework. (b) Probability density
function for unit capacitance
C. Design
NAND2 layout of VFET and FinFET architecture is shown
in Fig. 6 and design guidelines are described in Table II. The
vertical stacking structure of the S/D in VFET can significantly
reduce cell footprint area. Therefore, for VFET, cell height can
be extended to 11 tracks with inbound power rails to allow for
more routing resources, contacted gate pitch (CGP) is relaxed
to 36nm, routing orientation is restricted to 1D for litho-
friendly designs.

Fig. 4. (a) SAQP process flow assumptions. (b) Resistivity measurement of

Tungsten for 5nm technology dimensions Fig. 6. NAND2 implementations with VFET and FinFET architecture

TABLE I. PROCESS ASSUMPTIONS The area of VFET-based NAND2 is 120F2. Here F is the
Parameters 5nm label given for a semiconductor processs minimum critical
dimension, aka the M1 half-pitch. Numerical values in this
Metal barrier thickness [nm] 1
study are obtained for the F=12nm technology node
Dielectric barrier [nm] 5
TABLE II. DESIGN GUIDE LINE
Dielectric barrier k-value 5.5
Aspect ratio 2 Parameters FinFET VFET
Mandrel CD/3-CDU [nm] 36/3 Vdd [V] 0.5 0.5
Spacer CD/3-CDU [nm] 12/1.5 Lg [nm] 10 15
Etch variation (3) [nm] 3.75 CGP [nm] 32 36
CMP variation (3) [nm] 9 M1/M2 [nm] 24 24
Cell height [Tracks] 9 11
A low-k copper dual damascene process is applied for NW diameter [nm] NA 7
interconnect metallization with a CVD Mn metal barrier and a #NW or FIN 4 4
SiCN dielectric barrier. Cu and W resistivity are expected to Power rails abutted inbound
increase rapidly at a narrow trench due to the scattering of
electrons at the line edge and quantum confinement. Fig. 4b
illustrates the effect of increasing resistivity for W. The Monte A place and route (PnR) of a 32-bit multiplier was
implemented by using both standard-cell libraries. A 6T-
SRAM cell was also considered and evaluated.

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 III. RESULT AND DISCUSSION The implication of interconnect variability is also clearly
shown in Fig. 10. By increasing 9% area of the SRAM bit cell
A. Variability to allow a wider bitline, the read access time can offer 2 times
No significant capacitance variations occur among line MS, faster at the same yield target.
MC and MG: average s/mean=10%. However, the resistance
suffers from a large variation: the worst case resistance per unit
length (MG) s/mean=50% (Fig. 7)

Fig. 10. Parametic yield plot for SRAM read access time

Fig. 7. Mean and standard deviation of unit resistance and capacitance
The wire delay is getting more significant and becoming
balance with the device delay when scaling (Fig. 8). We found
that BEOL interconnect delay variability of a wire of average
length in SoCs (150 CGP [11]) start to overwhelm device
variability due to high resistances when shrinking metal CD
(Fig. 9). This implies a need for major improvements in
interconnect architecture or an new device architecture with a
smaller footprint which will be addressed in the following
sections.
B. Standard cell
A 26-transistor DFF implemented with VFET is depicted in
Fig. 6. VFETs allow to optimize S/D contact resistance and the
gate length as they are no longer defined by lithography and
limited by the cell width. The comparison in Fig. 11 confirms
that VFET can achieve a high layout density with the 1D
routing constraint and an 11% relaxed CGP.

Lateral FET [nm] VFET

28 10 5 5nm
Gate density *[%] 72 54 54 100
Area [m2] 2.1 0.7 0.17 0.12
Mx routing 2D 2D 2D 1D
Fig. 11. VFET DFF layout and benchmarking results

Fig. 8. Breakdown of interconnect and gate delay of an inverter fanout (FO)

1 driving a 150 CGP wielength C. 6T-SRAM Cell
The layout of SRAM bit cell is shown in Fig. 12 and its
area benchmarking is depicted in Fig. 13. Thank to vertical
architecture, two pull-up transistors can be placed on a same
row which save around 30% of area with respect to FinFET
architecture. The VFET-based SRAM can keep following the
50% area scaling trend strongly better than lateral FET bit cell.

Fig. 9. Transistor-interconnect variability balance Fig. 12. SAQP compatible layout of a SRAM cell implemented with VFET

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 Large contact resistance degrades Gm and disturbs the
static noise margin (SNM) of an SRAM cell. This effect will be
amplified at higher Vdd which is a traditional technique to
improve yields. Fig. 14 indicates a dramatic drop on SNM
when increasing Vdd. From simulation results, we suggest rc
should be below 5e-9 .cm2 in order to maintain downscaling
of SRAM cells.
IV. CONCLUSIONS
A holistic approach is used to address critical challenges for
5nm technology and to demonstrate the benefits of VFETs. The
large interconnect resistance and variations require a novel
interconnect architecture and a device architecture which have
a smaller footprint as VFET to effectively reduce the
wirelength. A 9% increase in SRAM cell area can obtain 2
times faster in the read access time. S/D contact resistivity is
required to be below 5e-9 .cm2 in order to continue
downscaling of 6T-SRAM cells. A VFET-based DFF layout
and SRAM bit cell can offer a 30% layout area reduction. A
19% area reduction is obtained for a 32-bit multiplier
implemented with the VFET-based standard-cell library w.r.t.
the FinFET design.

ACKNOWLEDGMENT
SDA, PDK and ICI team are greatly acknowledged for their
supports. The author also wishes to thank imecs CORE
partners for their stimulating discussions.

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