1028
3, MAY/JUNE 2009
A Sinusoidal PWM Method With Voltage Balancing
Capability for Diode-Clamped Five-Level Converters
Zhiguo Pan, Member, IEEE, and Fang Zheng Peng, Fellow, IEEE
AbstractThis paper presents a novel sinusoidal pulsewidth
modulation control method with voltage balancing capability for
the diode-clamped five-level rectifier/inverter system. A complete
analysis of the voltage balance theory is given. The voltage balanc-
ing effects of the third harmonic offset injection to all three-phase
voltages are discussed. The proposed control utilizes the offset
voltage to regulate the average currents flowing into and out of the
inner junction without affecting output line-to-line voltage. The
voltage balancing was achieved by selecting proper offset voltages
for both sides. A five-level experimental system is built up and used
to prove the theory.
Index TermsAC motor drive, active rectifier, multilevel
converter.
I. I NTRODUCTION
I N RECENT YEARS, multilevel converters have begun to
play a more and more important role in medium-voltage
high-power applications. Compared with traditional two-level
voltage converters, the primary advantages of multilevel con-
verters are their smaller output voltage steps, which result
in higher power quality, lower harmonic components, higher
voltage capability, better electromagnetic compatibility, and
lower switching losses [1], [2].
The multilevel converter synthesizes the staircase output
voltage which follows the sinusoidal waveform with minimum
harmonics. In order to satisfy the same harmonic requirement,
the frequency needed by the multilevel converter is much lower
than the conventional converter. Therefore, the multilevel con-
verter can achieve higher efficiency. The multilevel converters
also have lower dV /dt [3], [4]. It has been found recently
that the high dV /dt in the high-power pulsewidth modulation
(PWM) converter can induce corona discharge and lead to
bearing or winding insulation failure.
The multiple dc-bus capacitors in multilevel converters pro-
vide the capability of outputting multilevel voltage waveform.
Paper IPCSD-08-080, presented at the 2007 IEEE Applied Power Elec-
tronics Conference and Exposition, Anaheim, CA, February 25March 1,
and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY
APPLICATIONS by the Industrial Power Converter Committee of the IEEE
Industry Applications Society. Manuscript submitted for review June 26, 2007
and released for publication November 17, 2008. Current version published
May 20, 2009.
Z. Pan is with the ABB Corporate Research Center, Raleigh, NC 27606-5200
USA (e-mail: z.pan@ieee.org).
F. Z. Peng is with the Department of Electrical Engineering, Michigan State
University, East Lansing, MI 48824 USA (e-mail: fzpeng@egr.msu.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIA.2009.2018962
0093-9994/$25.00 2009 IEEE
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO.
However, it also requires additional circuits and special control
methods to keep the capacitor voltages well balanced. For the
three-level diode-clamped converter, because there are only one
additional voltage junction, the neutral point, and the symmetry
of the upper and lower capacitors, it has self-voltage balancing
potential. However, the neutral point has a low frequency ripple
at three times of the fundamental frequency. Some new research
works have addressed on eliminating or attenuating the low
frequency ripple [5][8].
However, the dc-bus voltage balancing for diode-clamped
multilevel converters with the number of levels greater than
three is more complicated. The multilevel converter capacitors
tend to overcharge or completely discharge. Eventually, the
converter converges to a three-level converter. Corzine et al.
proposed a dcdc front end to regulate the center capacitor
voltage of a four-level converter [9]. PWM hysteresis control
method has been proposed to regulate the dc bus of a five-
level rectifier [10]. Then, the multiband hysteresis comparator
control strategy has been extended to a five-level back-to-back
system. Although the technique is simple, the characteristics
are not sufficient as a motor drive system. Thus, an improved
control strategy using the space vector PWM has also been
proposed. The improved control strategy is able to solve the
voltage ripples in the dc link [11], [12]. Similar voltage balanc-
ing technique has also been discussed in [13][15].
A voltage balancing control method for the five-level back-
to-back rectifier/inverter system is presented in [16] and [17].
The method relies on coordination between the rectifier and
inverter switching angles to achieve capacitor charge balance
and, at the same time, minimize the switching harmonics of
both the rectifier and inverter. Although the voltage balancing
can be achieved in all operation ranges, the output voltage still
has lower order harmonic components due to limited switching
per cycle. This problem will get more prominent when the mod-
ulation index is low due to fundamental frequency switching
and the constraint of the charge balancing.
In this paper, the voltage balancing control theory is extended
to sinusoidal PWM (SPWM), which is simple, easy to be
implemented, and able to effectively reduce the lower order
harmonic components. A per-unit approach is used to analyze
the average current flowing into or out of the inner junction.
The voltage balancing effects of the third harmonic voltage
injection added to all three-phase voltages are discussed and
utilized to balance the dc bus voltage. By selecting proper offset
voltages on both rectifier and inverter sides, the average current
flowing into the inner junction can be adjusted to be equal to
that flowing out from it, therefore balancing the dc-bus voltage.
Meanwhile, the output voltage remains the same because of the
PAN AND PENG: PWM METHOD WITH VOLTAGE BALANCING CAPABILITY FOR DIODE-CLAMPED CONVERTERS 1029

Fig. 2. Voltage and current waveforms of the rectifier and inverter side.

Fig. 1. Simplified five-level diode-clamped back-to-back converter (one phase

leg only).

line-to-line voltage redundancy. Simulation results are provided

to prove the voltage balancing capability of the proposed con-
trol. A five-level experimental system is built up and used to
validate the theory.

II. V OLTAGE B ALANCING OF F UNDAMENTAL

F REQUENCY S WITCHING
Fig. 1 shows a simplified five-level diode-clamped back-to-
back converter, where only one phase leg is considered because
of the symmetry. In the back-to-back structure, two identical
five-level converters are connected with a shared dc bus. The
left half side is connected to the utility and acts as a rectifier,
while the right half side is connected to the load and acts
as an inverter. Although the back-to-back topology requires
doubling the number of switching devices, it has the following Fig. 3. Five-level SPWM output voltage and inner junction current.
advantages: charge flowing into the junction V4 should be zero, i.e.,
1) lower input current harmonics;
R2 I2
2) bidirectional power flow control;
3) ability to control the voltage of the dc bus; iR sin d = iL sin d. (1)
4) ability to control an input power factor. R1 I1

For the multilevel converter, the back-to-back topology
can also regulate the voltage of each dc bus. Because of the
symmetry of the system, the unbalance tendencies of both sides
have a potential to compensate each other. With a proper control
strategy, net current flowing into each level can be regulated
to zero.
Since the reactive components of the current for both the
rectifier and inverter have no effect on the voltage balance, only
the active components of the currents need to be considered
[16]. The voltage and the active current waveforms for a
five-level back-to-back system are shown in Fig. 2. Fig. 2(a)
shows the voltage and current waveforms of the rectifier, where
VR and VR1 are the rectifier staircase voltage waveform and
its fundamental component, respectively, and iR is the active
rectifier current waveform. Fig. 2(b) shows the waveforms of
the inverter.
Because of the symmetry, we only need to balance the inner
junction V4 . In order to balance junction V4 , the average net
Then, we can get the charge balancing equation
IR (cos R2 cos R1 ) = IL (cos I2 cos I1 ) (2)
where IR and IL are the amplitude of the rectifier current
and the load current, respectively. Combined with other system
constraints, the switching angle combinations that satisfy the
voltage balance requirement can be calculated, and the one with
lowest total harmonic distortion (THD) is chosen [16].
III. C ARRIER -B ASED SPWM C ONTROL
The carrier-based SPWM control is proven to be able to
effectively reduce the lower harmonic components. Fig. 3(a)
shows the five-level SPWM voltage waveform, where the mod-
ulation index M is 0.85. The sinusoidal reference voltage vref
is given by
Vdc
vref = M sin . (3)
2
1030 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 3, MAY/JUNE 2009

Unlike the traditional two-level converter, which only has one

triangular carrier, the five-level converter has four triangular
carriers, each one representing one capacitor in the dc bus.
In order to investigate the average current flowing into the
inner junction, similar method from the fundamental frequency
switching can be used. Assuming that the current is sinusoidal
and in phase with the voltage, we can generate the current
flowing into or out of the inner junction V4 according to the
voltage waveform, as shown in Fig. 3(b). Since the SPWM
control is used, the current flowing into V4 has more pulses.
The average inner junction current Iavg , which is defined as the
average current flowing into/out of the inner junction V4 , can be
calculated based on the current waveform by
 2
0 i Ipk 
Iavg = = (cos si cos ei ) (4)
2 2 i

where s and e are the start and end angles of each pulse,
which are determined by the voltage reference Vref and the Fig. 4. Inner junction current for a given reference voltage. (a) Reference
voltage. (b) Duty cycle of inner junction current i4 . (c) Equivalent i4 .
triangular carrier, and Ipk is the peak value of the current.
The peak current Ipk is determined by the input/output power is Vdc /4, and the base value of the current is Ipk . Therefore,
and rectifier/inverter voltage, as shown in we have
 vref
P 2P Vref = = 2M (9)
Ipk = 2 = . (5) Vdc /4
3VR 3 M 2Vdc2 
iL = iL /Ipk = sin (10)

i4 = i4 /Ipk . (11)
Substitute (5) into (4), we can get
 Accordingly, the voltages of the five dc-bus junctions become
4P (cos si cos ei ) 2, 1, and 0.
Iavg = i . (6)
3Vdc M The switching angles in (8) are determined not only by the
To simplify the analysis, the average inner junction current modulation index but also by carrier frequency factor and the
can be normalized by choosing the base value as phase angles of each carrier. Therefore, it is complicated to
calculate all the switching angles, particularly when the carrier
4P frequency factor mf is high. On the other hand, it can be
Iavg,base = . (7)
3Vdc seen from Fig. 3(b) that the envelope of the current waveform
follows the sinusoidal reference. The current waveform can be
Accordingly, the per-unit value of the average inner junction approximated to a series of current pulses whose duty cycle

current Iavg is given as is determined by the voltage reference. Therefore, when the
 carrier frequency is far greater than the fundamental frequency,
 (cos si cos ei )
Iavg = i . (8) the sinusoidal reference can be assumed as a constant value
M during each switching cycle. Thus, the duty cycle of the PWM
Since the voltage of the inner junction is based on the waveform can be calculated, and the duty cycle of the current
net current flowing into the junction, in order to balance the flowing into junction V4 can be written as
junction voltage, the average inner junction current flowing into   
2 vref , if 1 vref 2
V4 in the rectifier side Iavg,in must be equal to the average Di4 =   (12)
vref , if 0 vref 1.
inner junction current flowing out of V4 in the inverter side
Iavg,out . In the per-unit systems, the base value is determined It can be further simplified to

by the system operation point only, and the per-unit value is 1abs (1abs(2M sin )) , when
determined by the control method, modulation indexes, and Di4 () = (13)
0, when > .
switching angels. Since the Iavg,base values for both sides are
the same, we only need to compare the per-unit values Iavg  Therefore, i4 can be approximated as the duty cycle times
 the load current. Since the per-unit value of load current is a
for both sides. Once the control strategy is determined, Iavg
can be calculated without the actual voltage and current. The sinusoidal waveform with a peak value of one, the equivalent i4
usage of the per-unit value makes the analysis more simple and can be defined as
universal. i4eq () = Di4 () sin . (14)
Similarly, the per-unit value can be used for the reference
voltage Vref and the current iL , i4 . The base value of the Fig. 4 shows the approximate waveform of the duty cycle of
voltage chosen is the voltage of each dc-bus capacitor, which current i4 , where M equals 0.9. From Fig. 4(b), it can be seen
PAN AND PENG: PWM METHOD WITH VOLTAGE BALANCING CAPABILITY FOR DIODE-CLAMPED CONVERTERS 1031

Fig. 6. Offset voltage with minimum inner junction current.

Fig. 5. Average inner junction currents versus M and mf for SPWM control.

that Di4 is higher when vref 

is close to one, and it is lower control algorithm discussed in [16] and [17], the switch angles

when vref is close to zero or two. Fig. 4(c) shows the equivalent cannot be directly controlled in SPWM control. Instead, the
current i4eq flowing into/out of junction V4 . The average inner output voltage reference has to be changed to regulate the
junction current in per-unit value can be obtained by average inner junction current.
Fortunately, the line-to-line redundancy of three-phase sys-
2 2 tem provides the possibility to change the phase voltage while
 1 1
Iavg = i4 d Di4 iL d keeping the output line-to-line voltage the same. By adding
M M proper offset voltage to all three-phase voltages, it is possible
0 0
2 to regulate the average current flowing into junction V4 without
1 changing the output line-to-line voltage.
= Di4 sin d
M The output current is constant in the per-unit system, which is
0
 a unit sinusoidal waveform. If we want to reduce average inner
1 
junction current Iavg , we need to reduce the duty cycle Di4 ,
= 1 abs (1 abs(2M sin )) sin d. (15) 
M which means choosing an offset voltage that makes vref closer
0 
to zero or two. On the contrary, if we want to increase Iavg , we


For M = 0.9, Iavg can be calculated by (15) as 0.3496. Fig. 5 need to choose an offset voltage that makes vref closer to one.
shows the average inner junction current of the SPWM control In order to keep the symmetry between the three-phase
for different modulation indexes and different carrier frequency voltages and within each phase voltage, the frequency of offset
factors. The solid line shows the results of the simplification voltage needs to be three times the fundamental frequency.
when the carrier frequency factor is high. The stars show the Therefore, for each 2 cycle waveform of voset , only /6
average current for different modulation indexes when mf = 7, can be changed independently. Since the average inner junction
and the dots show the results when mf = 15. It can be seen that current is proportional to the integration of the production of
the results from the simplified method are close to the results the duty cycle D and sin , as shown in (15), the duty cycle D

from the one using actual switching angles, particularly when has more influences on Iavg when sin has a higher value.
mf is greater than 15. Since mf is usually greater than 15, the Therefore, the offset voltage voset will be chosen based on its
average inner junction current can be calculated without mf , effect at [/3, /2], where iL reaches its peak.
which makes it easier to analyze the charge balancing. Take the waveforms shown in Fig. 4 as an example. In order
However, based on the analysis before, the average input to minimized the average inner junction current, the offset

current Iavg,in 
has to equal the average output current Iavg,out voltage needs to be chosen so that the phase voltage reference
to keep the voltage balanced. Unfortunately, it can only be is close to zero or two. Based on that, an offset voltage is
guaranteed when both MR and MI are less than 0.5, which determined and is shown in Fig. 6(a) and (b) with the sinusoidal
means that the five-level converter has degraded to a three-level reference voltage, and the phase voltage reference after the
converter, or MR equals MI , which limits the capability to offset voltage is added. The equivalent inner junction current
perform variable frequency drive. i4eq can be calculated by (14) and shown in Fig. 6(c). It can be
seen that the new phase voltage is equal to two when is in
[/3, 2/3]; therefore, the inner junction current in that range
IV. R EGULATION OF THE A VERAGE I NNER
becomes zero. Therefore, the average inner junction current of
J UNCTION C URRENT
this control method reduced from 0.35 to 0.27.
For the SPWM control, the average current is determined Similarly, we can choose an offset voltage to maximize the
by the output voltage reference. Unlike the switch-angle-based average current by making the phase voltage close to one.
1032 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 3, MAY/JUNE 2009

Fig. 7. Offset voltage with maximum inner junction current.

Fig. 7(a) shows the reference voltage and the corresponding 

Fig. 8. Relationship of average inner junction current Iavg and pulse-
offset voltage based on the previous analysis. The phase ref- width W .
erence voltage after the offset voltage has been added is shown
in Fig. 7(b). It can be seen that the new phase voltage is close
to one when is within [/3, 2/3]; therefore, the duty cycle
of the current is also close to one in [/3, 2/3], where the
current reaches its peak. The equivalent inner junction current
i4eq is shown in Fig. 6(c). The average inner junction current of
this control method raised from 0.35 to 0.42.

V. V OLTAGE B ALANCING IN C ARRIER -B ASED

SPWM C ONTROL
In the previous section, the effect of the offset voltage on the
average inner junction current is discussed, and the maximum
and minimum values of the average current when the modula-
tion index is equal to 0.9 are given as an example. By adjusting
the pulsewidth of the offset voltage, it is possible to adjust Iavg
 
to any value between Iavg,max and Iavg,min .
From Fig. 6, it can be seen that offset voltage Voset,min has
three positive pulses and three negative pulses. The widths of
all the pulses are /3. If the pulsewidth is reduced, the average

Fig. 9. Average inner junction current Iavg versus M for the proposed
current will be increased accordingly. Similarly, the average control.
current will be reduced if the pulsewidth of the Voset,max is
reduced. The effect of the corresponding offset voltage can be

calculated and is shown in Fig. 8. When W is less than zero, current Iavg,out also keeps 0.3 for all modulation indexes from 0
it represents that the new offset voltage is based on voset,max . to 0.95 to keep the dc bus balanced. For example, if MR and MI
The absolute value of W determines the pulsed width based on are 0.95 and 0.6, respectively, both the input and output currents
the chosen offset voltage. It can be seen that the average current of the inner junction can be set to 0.3 by choosing proper offset

can be changed to any given average current Iavg between voltages with proper pulsewidth. Fig. 10 shows the rectifier
 
Iavg,max and Iavg,min by adjusting the pulsewidth W . side. The offset voltage is based on Voset,max to increase the
 
Similarly, Iavg,max and Iavg,min for different modulation inner junction average current, and the pulsewidth W of the
indexes can be calculated and are shown in Fig. 9. The top offset voltage is set to 0.49 to regulate the average current that
line shows the maximum average current versus modulation flowed into junction V4 to be 0.3. For the inverter side, the
indexes, and the bottom line shows the minimum average offset voltage is based on Voset,min , and the pulsewidth W of
current versus modulation indexes. The area in between is the the offset voltage is set to 0.64, to make sure that the average
operation region of the carrier-based SPWM control. current that flowed out from junction V4 is also equal to 0.3, as
In order to balance the voltage of the dc bus, the average shown in Fig. 11. Therefore, the dc bus should be balanced. The
input current from the rectifier side and that from the inverter simulation results are shown in Fig. 12. It can be seen that the
side need to be the same. Therefore, the average input current dc-bus voltages are well balanced, and both input and output

Iavg,in can be set to 0.3. For the inverter side, the average output currents are sinusoidal.
PAN AND PENG: PWM METHOD WITH VOLTAGE BALANCING CAPABILITY FOR DIODE-CLAMPED CONVERTERS 1033

Fig. 10. Offset voltage waveforms for M = 0.95. (a) Sinusoidal reference
and the offset voltage. (b) Phase reference voltage. (c) Equivalent inner junction
current.

Fig. 12. Simulation results for SPWM control when MR = 0.95 and
MI = 0.6.

Fig. 11. Offset voltage waveforms for M = 0.6. (a) Sinusoidal reference and
the offset voltage. (b) Phase reference voltage. (c) Equivalent inner junction
current.

VI. E XPERIMENTAL R ESULTS

A five-level three-phase back-to-back 10-kW converter/
inverter prototype was constructed for laboratory validation of Fig. 13. Picture of the 10-kW prototype.
the proposed control. The system consists of six identical phase
leg submodules, as shown in Fig. 13. Each phase leg submodule
is implemented on a printed circuit board, which is composed of
four layers and has a maximum continuous capacity of 20 A for
the power circuitry. A 5-hp induction motor has been connected
to the system as a load. The control strategy is implemented by
a DSP board based on ADSP-21065L by Analog Devices.
Fig. 14 shows the voltage waveforms of each voltage level
during steady-state operation. It can be seen that the voltage
of dc bus is stabilized at 330 V and all voltage levels are
well balanced. Fig. 15 shows the detailed waveforms, when
the modulation index of the inverter is 0.6. Therein, CH3 is
the input current, CH4 is the output current, and CH1 and
CH2 are the SPWM line-to-line waveforms of the rectifier and
inverter, respectively. It can be seen that the current waveforms Fig. 14. DC-bus voltage waveform.
1034 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 3, MAY/JUNE 2009
Fig. 15. AC waveform of the SPWM control when MR = 0.95 and MI =
0.6. (Ch1) Rectifier voltage (100 V/div). (Ch2) Inverter voltage (100 V/div).
(Ch3) Input current (5 A/div). (Ch4) Output current (10 A/div). Time:
5 ms/div.
are almost sinusoidal. To get the THD of the waveform, fast
Fourier transform is applied to obtain the spectrum of the input
current. The THD of the output current is only 2.7%.
VII. C ONCLUSION
In this paper, a novel SPWM method with voltage balancing
capability was proposed based on the detailed analysis of the
dc-bus balancing mechanism. A per-unit system is utilized
to simplify the analysis. The proposed method also utilized
the line-to-line voltage redundancy to adjust the net current
flowing into the inner junction to balance the dc-bus voltages,
while still maintaining very low THD on the current waveform.
Simulation and experimental results proved that the proposed
control strategy can effectively balance the dc-bus voltage of a
five-level diode-clamped rectifier/inverter system.
R EFERENCES
[1] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point-clamped
PWM inverter, IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518523,
Sep. 1981.
[2] J. S. Lai and F. Z. Peng, Multilevel convertersA new breed of
power converters, IEEE Trans. Ind. Appl., vol. 32, no. 3, pp. 509517,
May/Jun. 1996.
[3] L. Tolbert, F. Z. Peng, and T. G. Habetler, Multilevel converters for
large electric drives, IEEE Trans. Ind. Appl., vol. 35, no. 1, pp. 3644,
Jan./Feb. 1999.
[4] C. Newton, N. Sumner, and T. Alexander, Multi-level converters: A
real solution to high voltage drives? in IEE Colloq. Update New Power
Electron. Tech. (Dig. No. 1997/091), 1999, pp. 3/13/5.
[5] N. Celanovic and D. Boroyevich, A comprehensive study of neutral-point
voltage balancing problem in three-level neutral-point-clamped voltage
source PWM inverters, IEEE Trans. Power Electron., vol. 15, no. 2,
pp. 242249, Mar. 2000.
[6] P. Josep, R. Pindado, D. Boroyevich, and P. Rodrguez, Limits of the
neutral-point balance in back-to-back-connected three-level converters,
IEEE Trans. Power Electron., vol. 19, no. 3, pp. 722731, May 2004.
[7] D. Zhou, A self-balancing space vector switching modulator for three
level motor drives, IEEE Trans. Power Electron., vol. 17, no. 6, pp. 1024
1031, Nov. 2002.
[8] D. H. Lee, S. Lee, and F. Lee, An analysis of midpoint balance for
the neutral-point-clamped three-level VSI, in Proc. 29th IEEE PESC,
May 1998, vol. 1, pp. 193199.
[9] K. Corzine, J. Yuen, and J. Baker, Analysis of a four-level DC/DC
buck converter, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 746751,
Aug. 2002.
[10] T. Ishida, K. Matsuse, K. Sasagawa, and L. Huang, DC voltage control
strategy for a five-level converter, IEEE Trans. Power Electron., vol. 15,
no. 3, pp. 508515, May 2000.
[11] T. Ishida, T. Miyamoto, T. Oota, K. Matsuse, K. Sasagawa, and L. Huang,
A control strategy for a five-level double converter with adjustable DC
link voltage, in Conf. Rec. 37th IEEE IAS Annu. Meeting, Oct. 2002,
vol. 1, pp. 530536.
[12] T. Ishida, K. Matsuse, T. Miyamoto, K. Sasagawa, and L. Huang, Fun-
damental characteristics of five-level double converter with adjustable
DC voltages for induction motor drives, IEEE Trans. Ind. Electron.,
vol. 49, no. 4, pp. 775782, Aug. 2002.
[13] G. Sinha and T. Lipo, A four-level inverter based drive with a passive
front end, IEEE Trans. Power Electron., vol. 15, no. 2, pp. 285294,
Mar. 2000.
[14] M. Marchesoni and P. Tenca, Diode-clamped multilevel converters: A
practicable way to balance DC-link voltage, IEEE Trans. Ind. Electron.,
vol. 49, no. 4, pp. 752765, Aug. 2002.
[15] Y. Familiant, D. G. Holmes, T. Lipo, and B. McGrath, A general mod-
ulation strategy for a five-level three-phase current source inverter with
regulated intermediate dc link currents, in Conf. Rec. 42nd IEEE IAS
Annu. Meeting, Sep. 2007, pp. 581588.
[16] Z. Pan, F. Z. Peng, K. A. Corzine, V. R. Stefanovic, J. M. Leuthen,
and S. Gataric, Voltage balancing control of diode-clamped multilevel
rectifier/inverter systems, IEEE Trans. Ind. Appl., vol. 41, no. 6,
pp. 16981706, Nov./Dec. 2005.
[17] Z. Pan and F. Z. Peng, Harmonics optimization of the voltage balancing
control for multilevel converter/inverter systems, IEEE Trans. Power
Electron., vol. 21, no. 1, pp. 211218, Jan. 2006.
Zhiguo (Zach) Pan (S02M07) received the B.S.
degree in electrical engineering from Xian Jiaotong
University, Xian, China, in 1997, the M.S. degree
in electrical engineering from Tsinghua University,
Beijing, China, in 2001, and the Ph.D. degree in elec-
trical engineering from Michigan State University,
East Lansing, in 2005.
He is currently a Power Electronics R&D En-
gineer with the ABB Corporate Research Center,
Raleigh, NC. Prior to that, he was with Direct Drive
Systems, Cerritos, CA, as a Senior Power Electronics
Engineer from 2005 to 2008. His research interests include converter topolo-
gies, motor drives, and renewable energy conversion.
Fang Zheng Peng (M92SM96F05) received
the B.S. degree in electrical engineering from Wuhan
University, Wuhan, China, in 1983, and the M.S.
and Ph.D. degrees in electrical engineering from
Nagaoka University of Technology, Nagaoka, Japan,
in 1987 and 1990, respectively.
He was with Toyo Electric Manufacturing
Company, Ltd., from 1990 to 1992, as a Research
Scientist, where he was engaged in research and
development of active power filters, flexible ac trans-
mission system (FACTS) applications, and motor
drives. From 1992 to 1994, he was with Tokyo Institute of Technology, Tokyo,
Japan, as a Research Assistant Professor, where he initiated a multilevel inverter
program for FACTS applications and a speed-sensorless vector control project.
From 1994 to 2000, he was with Oak Ridge National Laboratory (ORNL), as
a Research Assistant Professor at the University of Tennessee, Knoxville, from
1994 to 1997, and was a Staff Member and the Lead (principal) Scientist of
the Power Electronics and Electric Machinery Research Center, ORNL, from
1997 to 2000. In 2000, he joined Michigan State University, East Lansing, as an
Associate Professor, where he is currently a Full Professor in the Department
of Electrical and Computer Engineering. He is the holder of over ten patents.
Dr. Peng has received many awards, including the 1996 First Prize Paper
Award and the 1995 Second Prize Paper Award of the Industrial Power Con-
verter Committee at the IEEE Industry Applications Society Annual Meeting;
the 1996 Advanced Technology Award of the Inventors Clubs of America, Inc.,
International Hall of Fame; the 1991 First Prize Paper Award from the IEEE
TRANSACTIONS ON INDUSTRY APPLICATIONS; and the 1990 Best Paper
Award from the Transactions of the Institute of Electrical Engineers of Japan,
which is the Promotion Award of the Electrical Academy. He was the Chair
of the Technical Committee for Rectifiers and Inverters of the IEEE Power
Electronics Society from 2001 to 2005 and was an Associate Editor for the
IEEE TRANSACTIONS ON POWER ELECTRONICS from 1997 to 2001, for
which has been an Associate Editor again since 2005.