TECHNOLOGICAL UNIVERSITY OF THE PHILIPPINES

COLLEGE OF ENGINEERING
ELECTRONICS ENGINEERING DEPARTMENT

ASSIGNMENT NO. 2
FET AND OP-AMP

SUBMITTED BY:
AUTRIZ, RENJELLE MAE D.
MERIN, CAMILLE ANGELA L.
PUNONGBAYAN, AIRAH JAN N.
BSECE-3A

SUBMITTED TO:
ENGR. E.A. GALIDO

FEBRUARY 20, 2017

 FET SAMPLE PROBLEMS
1 The value of drain current (ID) at the operating point is ________________. Verify whether the
FET will operate in the pinch-off region. Vp = -2V, IDSS = 4mA.

REDRAW:

Solution:
We can obtain ID by using the formula,
2
ID = IDSS(1 )

We know that,
VGS = VGG IDRs
2
VGG = VDD 1+2

8.57106
VGG = 24V (12+8.57)(106 )

VGG = 10V
2
ID = IDSS(1 )

Express ID and IDSS in mA,

10 (3) 2
ID = 4 x(1 )
2

9ID2 73ID + 144 = 0

Therefore, ID1 = 3.39mA and ID2 = 4.72mA
As ID = 4.72mA > 4mA = IDSS, this value is inappropriate. So, IDQ is 3.39mA.
To determine whether the FET is operating at pinch-off region,
VGSQ = VGG IDQRs
VGSQ = 10 (3.30X10-3)(3X103)
VGSQ = -0.17V
VDSQ = VDD IDQ(RD + RS)
VDSQ = 24 3.39X10-3(0.91 + 3) X 103
VDSQ = 10.745V
VDGQ = VDSQ VGSQ
VDGQ = 10.745 + 0.17 = 10.915V
VDGQ is greater than |VP| = 2V. Hence, the FET is in the pinch-off region.
2. For the circuit shown in figure below, determine- IDQ, VGSQ and VDS. The JFET
used has IDSS = 9 mA and VGS(OFF) = -3V.

Solution:
*Apply KVL on the left side
VGS IDRS + VSS = 0
VGS = IDRS - VSS
2
ID = IDSS(1 )

VGS(OFF) = VP = -3V
10 (1.5) 2
ID = 9X10-3(1 )
3

9103
ID = (3 + (10 (1.5k)ID))2
33

(1k)ID = 9 + 6(10 (1.5k) + + (10 (1.5k)ID)2

(1k)ID = 9 + 60 (9k)ID + 100 (30k)ID + (2.25M)ID2
(2.25M)ID2 (40k)ID +169 = 0
Therefore, ID1 = 6.91mA and ID2 = 10.86mA
As ID = 10.86mA > 9mA = IDSS, this value is inappropriate. So, IDQ is 6.91mA.
From VGSQ = VGG IDQRs
VGSQ = -(6.91mA)(1.5k) (-10V)
VGSQ = - 0.365V
*Applying KVL on the right side
VDD IDRD VDS IDRS VSS = 0
VDS = 20V (6.91mA)(1.8k + 1.5k) (-10V)
VDS = 7.197V

3. Determine the value of ZI, ZO and AV. IDSS = 2mA, VP = -6V rd = 10k

AC Equivalent Circuit

Solution:
Zi = RG = 1M
 6
RDS = = 2 = 3k

RDS = RS
rd 10RD
10k 10(2k)

(1 + + )

10k 20k not satisfied so ZO formula to be used is ZO = ( )
(1 + + + )

2
gm = (1 )
| |

VGS = -IDRS
2
ID = IDSS(1 )

2
VGS = -IDSSRS(1 )

2
VGS = -(2mA)(3k) (1 )
6
6
VGS = 62 (VGs + 6)2

-6VGS = VGS2 + 12VGS + 36

VGS2 + 18VGS + 36 = 0
Therefore, VGS1 = -2.292V and VGs2 = -15.708V
As VGS2 = -15.708V> 6V = VP, this value is inappropriate. So, VGS is -2.292V.
2(2) 2.292
gm = (1 )
|6| 6

gm = 0.42mS
3
(1 +(0.42)(3)+ )
10
ZO = 3 2 (2)
(1 +(0.42)(3) + + )
10 10

ZO = 1.855k

AV = =
(1 + + + )

(0.42)(2)
AV = 3 2
(1 +(0.42)(3) + + )
10 10

AV = 0.304
4. The value of VGS is ____________. IDSS = 5mA, VP = -4V and rd = 25k

Solution:
VGS = -IDRS
2
ID = IDSS(1 )

2
VGS = -IDSSRS(1 )

2
VGS = -(5mA)(4.7k) (1 )
4
23.5
VGS = (VGs + 4)2
42

-0.681VGS = VGS2 + 8VGS + 16

VGS2 + 8.681VGS + 16 = 0
Therefore, VGS1 = -2.655V and VGs2 = -6.026V
As VGS2 = -6.026V> 4V = VP, this value is inappropriate. So, VGS is -2.655V.
5. Determine the value of the output voltage VO of the Self-Biased Configuration shown
below, whose IDSS is 12mA and VGS(off) is -5V.

Solution First, find the DC output current.

2
= (1 )
()
910 2
= 12 (1 )
5
ID = 1.96 mA
Using this value, solve for VD
VD = VDD IDRD
VD = 12V (1.96 mA)(910 )
VD = 1.808 V
Next, calculate gm as follows:
VGS = -IDRS
VGS = -(1.96 mA)(910 )
VGS = 1.78V

2
0 = |()|
2 12
0 = 5
gm0 = 4.8 mS

= 0 (1 )
()
1.78
= 4.8 (1 )
5)

gm = 3.091 mS
Finally, find the ac output voltage.
Vout = AVVin = gmRDVin
Vout = (3.091mS)(5.2k )(100mV) = 1.607 VRMS
 The total output voltage is an AC signal with a peak-to-peak value of
1.607 V 2.828 = 4.546 V, riding a dc level of 1.808 V.
Vout total = 4.546 V
6. Determine the minimum voltage gain of the amplifier shown below. VDD is
negative because it is a p-channel device. The gm minimum is 2000S.

Solution This common-gate amplifier has a load resistor, so the effective

drain resistance is RD||RL and the minimum voltage gain is
AV = gm(RD||RL)
AV = (2000S)(40k ||10k )
AV = 16

7. The JFET in the amplifier shown below has a trans conductance gm = 1mA/V. If the
source resistance RS is very small compared to RG, find the voltage gain of the amplifier.
 Solution The trans conductance of JFET, gm = 1mA/V,
= 1000 mho
= 1000 10-6 mho
The total ac load (i.e. RAC) in the drain circuit consists of the
parallel combination of RD and RL i.e.

Total a.c. load, RAC = RD||RL

RAC = 16 k || 10 k
RAC = 6.154 k
Voltage gain, AV = gmRAC
AV = (1000 10-6)(6.154 103)
AV = 6.154

8. The small-signal voltage gain of a circuit biased with a constant-current source and
incorporating a source bypass capacitor shown below is _______________.

VTh = 0.8 V
kn = 1 mA/V2
rd =

Solution:
Since the dc gate current is zero, the dc voltage at the source terminal is VS = -VGSQ, and the
gate-to-source voltage is determined from
IDQ = IQ = kn (VGSQ VTh)2
or
0.5 = (1)( VGSQ 0.8)2
which yields
VGSQ = -VS = 1.51 V
The quiescent drain-to-source voltage is
 VDSQ = VDD - IDQRD VS = 5 (0.5)(7) (-1.51) = 3.01 V
The transistor is therefore biased in the saturation region.
gm = 2 kn (VGSQ - VTh) = 2(1)(1.50 0.8) = 1.4 mA/V
V0 = - gm Vgs RD
Vgs = Vi

AV = = - gm RD = -(1.4)(7) = -9.8

9. The voltage values in a p-channel JFET circuit shown below are VD =_______,
VGS =_______, and VSD = _______.

IDSS = 2.5 mA
Vp = +2.5 V

(9)
ID = IQ = 0.8 mA =

VD = (0.8)(4) 9 = -5.8 V
2
ID = IDSS (1 )

2
0.8 = 2.5 (1 )
2.5

VGS = 1.086 V
VS = 1 - VGS = 1 1.086 = -0.086 V
VSD = VS - VD = -0.086 (-5.8) = 5.71 V
 10. The small-signal voltage gain of a common-source circuit shown below is ________.
Circuit parameters: Transistor parameters:
VDD = 10 V VTh = 1.5 V
R1 = 70.9 k kn = 0.5 mA/V2
R2 = 29.1 k ro = 100 k
RD = 5 k

Solution:
2 29.1
VGSQ = ( )( VDD) - (70.9 + 29.1)(10) = 2.91 V
1 + 2

IDQ = kn (VGSQ - VTh)2 = (0.5)(2.91-1.5)2 = 1 mA

VDSQ = VDD IDQRD = 10 (1)(5) = 5V
gm = 2kn (VGSQ - VTh) = 2 (0.5)(2.91 1.5) = 1.41 mA/V
VO = -gmVgs (ro || RD)

AV = = - gm (ro || RD)

= -(1.41)(100||5)
AV = -6.71
 OP-AMP SAMPLE PROBLEMS
1-3. Find the VO of the following.

Solution:

VO = - ( 1 + 2 )
1 2

120 120
VO = - ( 20 (0.75) + (0.5))
12

VO = -0.5V

VO1 = - ( 1 1)
1

470
VO1 = - ( 40 (24))
VO1 = -0.282V
2 2
VO2 = - ( 01 + 2 )
3 4

180 180
VO2 = - ( 12 (0.282) + (0.5))
22

VO2 = 4.234V

1 1 1 1
VO1 = -Rf1Vi (1 + + + )
2 3 4
1 1 1 1
VO1 = -(15k)(2.5V) (200 + + + )
100 50 25

VO1 = -2.813V

VO2 = (1 + )Vi
6
150
VO2 = (1 + )(-2.813)
30

VO2 = -16.878V
4. Given The op=amp configuration below, determine the value of Rf required to
produce a closed-loop voltage gain of -100.

Solution Knowing that Ri = 8.2k and the absolute value of the closed loop
gain is |Acl(I)| = 100, calculate Rf as follows:

|Acl(I)| =
Rf = |Acl(I)|Ri
Rf= (100) ( 8.2k )
Rf = 820k

5. The closed-loop gain is __________ in the given noninverting amplifier below.

Solution For noninverting amplifier, the closed loop gain is

Acl = 1 +
470 k
Acl = 1 + 5.2 k

Acl = 91.385
6. Determine the output voltage below.

Solution A general expression is given for a unity-gain summing amplifier

with n inputs, where all resistors are equal in value.
Vout = - (Vin1 + Vin2 + Vin3 ++ Vinn)
Vout = - (-10V + 13 v + 3V)
Vout = -6V
7. The output voltage of the scaling adder below is ______.

Solution A different weight can be assigned of each input of a summing

amplifier by simply adjusting the values of the input resistors. The
weight of a particular input is set be the ratio of Rf to the resistance
Rn.

Vout = - [1 Vin1 + 2 Vin2 + 3 Vin3 ++ Vinn]
60k
Weight of input 1: 1 = 3.3k = 18.182
60k
Weight of input 2: 2 = 500k = 0.12
60k
Weight of inpute 1: 3 = 4.7k = 12.766
Vout = - [(18.182)(4V) + (0.12)(10v) + (12.766)(-8V)]
Vout = - [ 72.728 + 1.2 -102.128 ]
Vout = -28.2
 8. The ac output voltage of the summing amplifier below drive by three audio signals is
_______.

Solution:
100
Av1(CL) = =-5
20
100
Av2(CL) = = - 10
10
100
Av3(CL) = =-2
50

Vout = (-5)(100 mVpp) + (-10)(200 mVpp) + (-2)(300 mVpp) = -3.1 Vpp

9. Design an inverting op-amp with the configuration shown below.
The op-amp circuit is to be designed to have a closed-loop gain of AV = -100 and an input
resistance of R1 = 50 k . All resistance must be less than 500 k.

il = = i2
1

vX = 0 - i2R2 = -vI ( 2 )
1
i2 + i4 = i3
0
=
2 4 3

1 1 1
-vx ( + + )= 0
2 4 3 3

1 1 1
-vI ( 2 ) ( + + )= 0
1 2 4 3 3

AV = = - ( 2 ) (1 + 3 + 3 ) = - ( 2 ) (1 + 3 ) 3
1 4 2 1 4 1

2 3
If for example, we arbitrarily choose = =8
1 1

-100 = -8 (1 + 3 ) 8
4

3
=10.5
4

If R1 = 50 k then,
R2 = R3 = 400k
and
R4 = 38.1 k
10. Design an inverting amplifier with a closed-loop voltage gain of AV = -5
Assume the op-amp is driven by a sinusoidal source vl = 0.1tvolts, which can
supply a maximum current of 20 A. Assume that frequency is low, which means that
any frequency effects can be neglected.
Solution:
0.1
ii = 1 =
1 1

if ii (max) = 20 A, then the minimum

value of R1 is
3 0.1
R1(min) = = = 5
1 (max) 20 106

AV = 2 = 5
1

R2 = 5R1 = 25 k
 INSTRUMENTATION AMPLIFIER

Note that two noninverting amplifiers A1 and A2, are used in the input stage, and a difference
amplifier, A3, is the second, or amplifying stage.
The voltages at the inverting terminals of the voltage followers are equal to the input
voltages.
The curret in resistor R1 is then
 12
1 =
1
The current in resistors R2 is alo i1 and the ouput voltages of op-amps A1 abd A2 are, respectively,
2 2
1 = + 12 = (1 + ) 12
1 1
and
2 2
2 = 12 + 12 = (1 + ) 12
1 1
The output of the difference amplifier is given as
4
= (2 01)
3
substituting vo1 and vo2 in the equation of vo we find the outpt voltages, as follows
4 22
= (1 + ) (12 )
3 1