DMT 231 ANALOGUE

ELECTRONICS

Lecture I
Introduction to Field Effect Transistors
FIELD EFFECT TRASISTOR
(FET)
ADVANTAGES OF FET
TYPES OF FET & ITS
OPERATION
 FET Advantages
Voltage-controlled amplifier: input impedance
very high
Low noise output: useful as preamplifiers
when noise must be very low because of high
gain in following stages
Better linearity: distortion minimized
Low inter-electrode capacity: at high
frequency, inter-electrode capacitance can
make amplifier work poorly. FET desirable in
RF stages
 Types of FET
FET

JFET MOSFET MESFET

n channel Enhancement mode
p channel n channel
p channel
Enhancement/Depletion mode
n channel
p channel
 Junction FET (JFET)
D D
ohmic
contact

G p n p Structure G n p n

n-channel p-channel
S S

D D

Symbol
G G

S S
 Metal-Oxide-Semiconductor
MOS (MOSFET)
DEPLETION

dielectric
ENHANCEMENT

metal
p

n-channel p-channel
 JFET Operation
depletion region

n
n
VDD VDD
p p p p

VGG
n n

Gate-source is reversed-biased
zero current at gate
IDS flow through the channel and determined by the width of
depletion region and the width of the channel
 MOSFET Operation
electron
inversion layer
G G
S D S D

n+ n+ n+ ------- n+

p-type p-type

SS
No voltage applied to gate
Current is zero
SS
+ve voltage applied to gate
Electron inversion layer is created
Current is generated between
source and drain
 FET BIASING
JFET BIAS CIRCUITS
Self-bias
Voltage-divider bias

MOSFET BIAS CIRCUITS

Voltage-divider bias
Drain-feedback bias
Equivalence biasing of JFET &
BJT
JFET BJT
2
VGS
I D I DSS 1 <==> I C I B
VP
ID IS <==> IC I E
IG 0 A <==> VBE 0.7V
 JFET Bias Circuits
- Self-Bias
+VDD

RD
VGS VG VS I D RS
IG = 0

VDS VDD I D RD RS
RG RS
 JFET Bias Circuits
- Voltage-divider Bias
+VDD

R2
R1 RD VG VDD
ID R1 R2

VG
VG VGS
R2 RS
ID
RS
 MOSFET Bias Circuits
- Voltage-divider Bias
+VDD
R2
VGS V DD
R1 RD R1 R2

VDS VDD I D RD
R2

where I D K VGS VTN

2
 MOSFET Bias Circuits
- Drain-Feedback Bias
+VDD

RD
RG
VGS VDS VDD I D RD
IG = 0
 LOAD LINE

SELF-BIASED JFET
VOLTAGE-DIVIDER BIAS
JFET
 LOAD LINE
- SELF-BIASED JFET
+VDD
Example 9V

Determine the Q-point for the RD

JFET circuit. The transfer 2.2K

characteristic curve is given

in the figure.
RG RS
10M 680
For ID=0,
VGS=-IDRS=(0)(680)=0V
From the curve,
IDSS=4mA; so ID=IDSS=4mA
ID (mA)
VGS=-IDRS=-(4m)(680)=-2.72V

4 IDSS
ID=2.25mA
VGS=-1.5V Q
2.25

-VGS (V)
-6 -2.72 -1.5
VGS(off)
 LOAD LINE
- VOLTAGE-DIVIDER BIAS JFET
+VDD
Example 8V

Determine the Q-point for

R1 RD
the JFET circuit. The
2.2M 680
transfer characteristic curve
is given in the figure.
R2
RS
2.2M
3.3K
For ID=0,
R2 2.2
VGS VG VDD 8 4V
R1 R2 4.4
For VGS=0,
VG VGS VG 4
ID 1.2mA
RS RS 3.3K
ID (mA)

12 IDSS

ID=1.8mA
VGS=-1.8V

Q
1.8
-VGS (V) VGS (V)
-3 -1.8 4
1.2
VGS(off)
 EXERCISES (Load Line JFET)
1. Determine the Q-point for the JFET +VDD
circuit. The transfer characteristic curve 6V
is given in the figure.
RD

ID (mA) 820

IDSS = 5mA

RG RS
10M 330

-VGS (V)
VGS(off)=-3.5
 EXERCISES (Cont)
2. Determine the Q-point for the JFET
+VDD
circuit. The transfer characteristic curve
12V
is given in the figure.
ID (mA)
R1 RD
IDSS = 5mA 3.3M 1.8K

R2
RS
2.2M
3.3K

-VGS (V)
VGS(off)=-4V
FET CHARACTERISTICS

JFET
MOSFET
 JFET CHARACTERISTICS
DRAIN CHARACTERISTIC
ID
VGS

VGS=0
IDSS
ohmic region

breakdown region

Saturation region

VP=|VGS (off)|
VP VDS
 JFET CHARACTERISTICS
TRANSFER CHARACTERISTIC ID

I D I DSS 1 VGS 2
VP
IDSS

N-CHANNEL

-VGS
VP
JFET DATA SHEET

For MMBF5459 VGS (off) = -8.0V (max)

IDSS = 9.0 mA (typ.)
MOSFET CHARACTERISTICS
TRANSFER CHARACTERISTIC
(Depletion MOSFET) ID

I D I DSS 1
VGS 2
VP
N-CHANNEL
IDSS

-VGS
VGS(off)=VP
MOSFET CHARACTERISTICS
TRANSFER CHARACTERISTIC
(Enhancement MOSFET)
ID

I D K VGS VTN
2

N-CHANNEL

K in formula can be calculated by

substituting data sheet values
ID(on) for ID and VGS at which ID(on)
is specified for VGS

VTN +VGS
 E-MOSFET DATA SHEET

ID(on) = 75 mA (minimum) at
VTN = 0.8 V and VGS = 4.5V

I D ( on) 75mA
K 5.48mA / V 2

VGS VTN 2 4.5 0.82