AppNote MG590175

A P P N O T E S SM

Tips for Achieving High Compression

By: Ron Press

Last Modified: May 15, 2015

Table of Contents
Achieving High Compression ........................................................................................................................ 1
Analyze_compression............................................................................................................................... 2
Compression Advisor................................................................................................................................ 2
Design Characteristics that can Hurt Compression ...................................................................................... 3
False and multicycle paths ....................................................................................................................... 3
Specific Guidelines for Higher Compression ................................................................................................ 3
Encoding Capacity .................................................................................................................................... 3
Low power settings ............................................................................................................................... 3
Clustering.............................................................................................................................................. 3
Highly specified bits .............................................................................................................................. 4
Compaction ............................................................................................................................................... 4
X-bounding ........................................................................................................................................... 4
Memories .............................................................................................................................................. 4
False and multicycle paths ................................................................................................................... 5
Additional Enhancements for Higher Compression ...................................................................................... 5
EDT Test Points ........................................................................................................................................ 5
Logic BIST ................................................................................................................................................ 5
Hierarchical DFT ....................................................................................................................................... 5
Broadcast of input channels ................................................................................................................. 5
Dual mode compression ........................................................................................................................... 5
Impact of very high compression ratios ........................................................................................................ 6
Potential for routing congestion ................................................................................................................ 6
Logic size .................................................................................................................................................. 6
Performance ............................................................................................................................................. 6

Achieving High Compression

This document summarizes guidelines on how to achieve high compression using TestKompress. Some
designs can use compression ratios as high as 1000x or 2000x and still achieve very good results while
others could be limited to lower compression. The most common characteristics that can impact the level
of compression are described herein.

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Tips for High Compression

Analyze_compression
Analyze_compression is a command that can be used on any scan inserted design to report the
maximum chain to channel ratio before you start to lose coverage. It reports the compression ratio limit
but this limit is rarely the optimal confi
configuration that results in the best compression.

Compression Advisor
One utility that is very helpful in determining the best compression results possible is the
compression_advisor utility. It is available in circuits and solutions which the application engineers have
access to. The utility will report the best compression configuration and results based on a design and
channel or chain constraints that are defined by the user. T This is a logical first starting point when
assessing a designs potential compression. It will automatically make tradeoffs of how to most efficiently
allocate channel pins available to input and output channels. Often the best compression configuration
has asymmetric input to output channels.

The higher the number of internal chains, the shorter the chains and the less test time per pattern.
However, at some point there are diminishing returns with shortening the scan chains because we include
additional
nal bits with each pattern for low power controls (if used), x masking, and initialization.
Compression_advisor utility takes this into consideration when selecting the optimal compression
configuration.

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Tips for High Compression

Design Characteristics that can Hurt Compression

There are several design characteristics that can make high compression particularly difficult. Here are a
few to watch out for.

False and multicycle paths

A very large number of false and multicycle paths can hurt the ATPG and compression results.
Sometimes this happens due to an error in the SDC file used to define false and multicycle paths. Often
when false and multicycle paths are overspecified and interfering with results you will see many patterns
being generated but only a subset being kept. Thus, with every 64 patterns shown during ATPG a
smaller number is found to be effective and kept with the pattern set.

The x_statistics report shown below is a good method of finding the SDC definitions which are hurting
ATPG results the most.

ANALYSIS> read_sdc mod.sdc

ANALYSIS> set_timing_exceptions_handling -x_statistics on
ANALYSIS> create_patterns
ANALYSIS> report_false_paths -x_statistics -count 3
// Total 255 paths out of 350 paths produced Xs.
// ---- --------------- ------------ --------------------
// Path Type Number of Xs File and line number
// ---- --------------- ------------ --------------------
// 1 false path 4424790 mod.sdc (line 32761)
// 2 false path 3460790 mod.sdc (line 32761)
// 3 multicycle path 463897 mod.sdc (line 30390)
// Only the first 3 paths producing the most Xs were reported

Specific Guidelines for Higher Compression

Design and setup characteristics that can impact compression are described below. Some have an effect
on the TestKompress decompressor and some on the compactor.

Encoding Capacity
The TestKompress decompressor has a ring generator and XOR cloud. They decode the incoming serial
data from the tester scan channels and convert it into the specified bits in the scan chains needed to
detect targeted faults. The other non-specified bits are produced as random values by the decompressor.

Encoding capacity is the the amount of specified bits that can be provided through the decompressor.
Some characteristics that can hinder encoding capacity or require too many specified bits are described
below.

Low power settings

More aggressive low power settings will result in more patterns. Low power shift settings result in some
scan chains being held to a constant 0 on a pattern by pattern basis. The chains that are held off depend
on the faults being targeted for each pattern. As a result, only bits in the chains that are not held off can
be provided for each pattern; effectively lowering the encoding capacity.

Clustering
If there are too many specified bits that are clustered together in the scan scan chain positions then it
might not be possible to provide those bits through the decompressor. This situation can occur due to
condition bits or enable bits being placed in the same position of many scan chains. If this occurs then

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Tips for High Compression

you will see a message during ATPG about clustering and the amount of impact that it is having on test
coverage.

The report_edt_abort_analysis command can identify the cause of clusting and the scan chain cells that
cause the most conflicts as shown below.

> set_edt_abort_analysis_options -max_cubes_to_analyze {unlimited | maxCubes}

> create_patterns
> report_edt_abort_analysis
// EAB test cube analysis results for EDT block 'piccpu_90':
.....
// Approximate encoding capacity = 63
//
// EAB test cube size distribution:
// Specified bits Specified bits / Capacity (%) EAB cubes
// -------------- ----------------------------- ---------
// 37 - 44 60.00% - 70.00% 1
// 44 - 50 70.00% - 80.00% 8
// 50 - 56 80.00% - 90.00% 16
// 56 - 63 90.00% - 100.00% 16
// > 63 > 100% 8
//
// Analyzed a total of 3 EAB cubes.
// Top specified scan cells are:
// ID Specified Gate Chain Shift Constraint
// times postion
// -- --------- ------------------------------------ ---------------- ------- ---------------------------
// 1 2(66.67%) '/gate_path/i/phase_reg_0/Q' (31096) piccpu_90_chain1 16 Cell Constraints
// 2 2(66.67%) '/gate_path/inst_reg_11/' (31093) piccpu_90_chain1 13
// 3 2(66.67%) '/gate_path/inst_reg_10/' (31092) piccpu_90_chain1 12 Condition of NCP user_ncp_3
.....
// Top specified shift positions are:
// Shift position Specified times Average specified times per cube
// -------------- --------------- --------------------------------
// 4 4 1
// 5 4 1
// 12 4 1

Highly specified bits

If there are some scan cells that need to be specified for many patterns then it is often advantageous to
include them in the same scan chain. For example, clock gater control bits which are accessed during
low power ATPG should be grouped in common control chains so some of the bits arent trying to be
masked off due to low power shift. Similarly, test points added with EDT Test Point features will be
accessed more than other cells and should be grouped together in the same chains. These chains will
still be included within the TestKompress logic.

Compaction
The TestKompress compactor is a series of XOR gates that combine the internal chains into few output
channels. Often compression_advisor will report a channel configuration that has a lot fewer channel
outputs than inputs for the optimal compression configuration. However, if there are many internal X
states then more output channels would be needed.

X-bounding
The higher the number of X states, the bigger impact on compression. Unknown or X states are reported
as E5 DRCs. One method of removing X states is to perform x-bounding. This is typically used for logic
BIST but is available for ATPG purposes as well using a LogicBIST or ScanPro license. X-bounding is a
form of test logic insertion to prevent X states from propogating through the circuit. It will help improve
the compression results in designs with many X states.

Memories

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Tips for High Compression

Memories can be a source of X states. To simplify ATPG and improve the compression results,
memories can be bypassed during test. This will prevent the X states from propagating from the memory
outputs. Note that during at-speed tests it is often desireable to model memories and test through them.

False and multicycle paths

False and multicycle paths are X generators. If the path is active then an X will be captured which may
hurt compression.

Additional Enhancements for Higher Compression

EDT Test Points
EDT Test points are added specifically to improve compression results. We see an average of 2x to 4x
better compression when adding 1% to 2% of the scan cell population as EDT Test Points. Note that
there is a test_point_advisor utility available in circuits and solutions that the application engineers have
access to. It shows the tradeoffs in number of test points compared to compression impact.

Logic BIST
Often Logic BIST is viewed as a method of high compression. It can normally run at very high
frequencies since the input and output data is produced internally and isnt slowed down by tester
capabilities or IO pad frequency limitations.

Hierarchical DFT
Hierarchical DFT is the allocation of the full channel bandwidth to one block or group of blocks at a time.
Often it is utilized for large designs since the patterns can be completed at the block level and retargeted
or merged at the top with other blocks. It requires adding wrapper chains to the hierarchical blocks so
they can be isolated during test. Moving ATPG to the block level often results in 10x faster ATPG run
time and 10x smaller compute resources. However, hierarchical DFT also often produces 2x to 3x better
compression results (fewer test cycles) than running flat ATPG.

Broadcast of input channels

If there are identical and duplicate blocks in a design then hierarchical DFT can be used by creating
patterns for one of duplicates and then broadcasting all the input channels to all duplicates. Thus, 100
duplicate blocks can be tested with just one channel input broadcat to all of them in parallel. The output
channels still need to be independent to enable diagnosis.

It is also possible to broadcast input channels to non-identical blocks. The most efficient test of non-
identical blocks is usually hierarchical DFT but if that isnt available then channel sharing for non-identical
blocks will provide an average of 2x better compression compared to modular TestKompress.

Dual mode compression

Sometimes it is advantageous to have a super high compression for one test insertion with a little loss in
test coverage and then a second compression configuration for a second test insertion. This is supported
with the dual mode compression option in TestKompress. For such a case, you might exceed the
maximum recommended compression ratio.

One usage of dual mode in this manner is for multisite test. Some designs can use 1000x or 2000x
compression ratio with less than 2% coverage loss for multisite wafer test with just one scan channel.
Then later during packaged part test run a different compression configuration with perhaps 12 channels
for full coverage and a compression in the 100x range.

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Tips for High Compression

Impact of very high compression ratios

Potential for routing congestion
Often compression technologies have routing issues when configured with very high compression ratios.
TestKompress was designed to handle these high compression ratios and has been successful in many
designs with thousands of chains and over 800 chains feeding a single compactor. We are not aware of
any routing issues with TestKompress in over a decade of usage.

By default, TestKompress will recognize where there are more than 500 chains being fed by a
decompressor. In such a case, TestKompress automatically will segment the EDT decompressor logic
into instances that feed groups of 500 or fewer chains. As a result, these segmented decompressor
instances will get placed in the vicinity of the chains they connect to and avoid routing issues. There are
only a few signals that pass from one decompressor segment to another.

Logic size
The number of levels in the spatial compactor is logarithmic of the number of scan chains. If there are 200
chains going to a compactor, there will be about 8 levels of logic. The area overhead for the compactor
doesnt change much if you have two compactors each of size 100 inputs (with 1 outputs) versus one of
size 200 inputs (with 1 output).

Performance
As the numbers of levels in the spatial compactor varies in the log-scale, the depth is not very high. Given
that by default we register the output of the compactor today, there is very little impact on performance.
With chains/channels ratio of 200-300 there is no impact on the shift speed.

If shift speed is a concern, one can always use compactor pipelining. And for long wires between the
channel pins at the EDT IP interface and the chip-level pins, one can always use channel pipelining.

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