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transitions are taken in response to external stimuli. Finally the state machine must produce some desired
configuration of outputs. State transitions and the output configuration are mediated by combinational
logic acting on the inputs to the circuit and the circuit's internal state. The basic design of the FSM is
shown in the figure at right.
Here is the pattern for designing with the FSM formalism:
1. Determine what states / transitions are needed in order to solve the problem.
2. Draw the state diagram, labelling the states and the edges.
3. Develop a mapping between state and representation in FFs.
4. Write out the state transition table (see below).
5. Find the combinational logic which implements this state.
Finding the states and transitions
This is probably the most difficult part and requires some trial and error. There is no magic formula to
apply here. You must learn to generalize by considering the examples given below.
State diagrams
Once you have the states and transition rules then drawing the diagram is pretty easy. The states are
usually drawn as circles with one or more directed arrows giving paths to other states when certain
criteria are met. It's helpful to list all possibilities even if the state machine stays in the same state (at
the next clock edge) in which case you should draw an arrow which loops back to the same state.
Mapping states to registers
In principle the designer is free to employ any mapping but in principle there are two common general
choices:
Binary-coded states: in this case, the states are simply numbered 1 through N and the flip-flops
represent the number in binary, thus, you need ceil(log2N) FFs to hold the state. The order is still a
free parameter here and very often, well-chosen ordering can produce a simpler circuit,
One-hot states: for the one-hot case, the designer allocates 1 FF per state and when that state is
active the corresponding FF is logic HIGH and the rest are logic LOW. This configuration is chosen
as it usually produces simpler combinational logic at the expense of exponentially more flip-flops.
One-hot mappings are often used in FPGAs where the number of flip flops is very large.
State transition table
This is an extension of the truth table concept. The basic idea is to list all flip flops in the FSM and any
dependent inputs on the left side of the table the flip flop configuration and the flip-flop bits
representing the next state and any outputs on the right. Then, using the same techniques for
implementation of truth tables in combinational logic, derive the logic expressions for each next-state FF
bit and output signals.
Examples
It always helps to see a few examples of FSMs completely worked through. Three examples of increasing
complexity will be covered here.
Example #1: synchronous counter
We have already discussed the limitations of the ripple counter. A better design for fast, robust counters
uses an FSM and is called a synchronous counter. The goal is this: make a circuit which counts on clock
edges. For clarity this example only is a 3-bit counter and doesn't include set or reset inputs that would
probably be found on a real synchronous counter.
States
The states are obvious in this example: there must be a distinct state for every number in the counter.
There is also a pretty obvious mapping of state to flip-flop registers: the registers hold the binary-coded
number.
Transitions
There are no external stimuli aside from a clock signal which only serves to control the timing when the
state transitions take place. The states transition in the manner that state 0 goes to state 1 goes to state
2 ... goes to state 15 goes to 0 ... and so on.
State diagram
The state diagram of this FSM is shown in the figure at left. The 3 bits of the flip flops are shown inside
the circles. Transitions are not labeled as there is always and only one immediate exit from each state.
State transition table
Q2 Q1 Q0 D2 D1 D0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
The state transition table is simply written with the ouputs of the current state of the flip flops (Qi) as
inputs to the combinational logic arrangement which must produce the next set of inputs to the
registers (Di on the right).
The logic expressions which implement this table are:
D0 = Q0
D1 = Q0Q1
D2 = Q2(Q1 Q0)
Finally, the circuit implementation is given in the figure below:
There are three possible states which can describe the life cycle of this circuit:
ARMED
The circuit is armed waiting for a trigger. IN=0 will keep the circuit in ARMED state, IN=1
will cause it to go to EDGE.
EDGE
The circuit has just detected the leading edge on the input. This state can only persist for one
clock cycle. If IN=0 then the FSM will go back to ARMED. If IN=1 then it must enter the
WAITING state, described next.
WAITING
The circuit saw the leading edge on the input but the input is still high. That is to say that it is
waiting, looking for the trailing edge of the input pulse. As long as IN=1 the FSM will remain
here. As soon as IN=0 it can return to the ARMED state.
The state diagram for this FSM is shown at right:
State-to-register mapping
There are 3 states thus at least 2 flip flops are needed to hold the state. I've chosen to enumerate the
state ARMED = "00", EDGE = "01", and WAITING = "10" to save a logic gate in making the output: the
output is high only for the EDGE state therefore it can be immediately identified as the output of
register 0 (recall that I write the bit strings MSB first).
State transition table
Q1 Q0 IN D1 D0 OUT
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 0 1
1 0 0 0 0 0
1 0 1 1 0 0
1 1 X FORBIDDEN
Now the state transition table involves an input and an output which can be seen to be exactly equal to
the register output, Q0. The expressions to realize this table are
D0 = IN Q0 Q1
D1 = IN (Q0 Q1)
OUT = Q0
And ... realized in discrete gates it looks like this:
From <http://homepages.ulb.ac.be/~khanson/PHYS-F314/2011/notes/digital-03.html>