I386

Memory Management
&
Segmentation
Memory Management (1)
Segmentation
in which a logical address is converted to a linear
address
paging (optional)
in which a linear address is converted to a physical
address
to perform translation,the following data
structure are used
descriptors
descriptor tables
selectors
segment registers
Memory Management Register
GDTR & LDTR : global & local descriptor table register,point
to the segment descriptor table
IDTR : interrupt descriptor table registers,point to a table of
entry points for interrupt handlers
TR : task register,point to the pcb of current task
Memory Management (2)
15 0 31 0
logical
selector offset
address

segment
translation
paging disable
PG?
paging enable
linear
dir page offset
address
page
translation

31 0
physical
address
Segment Translation
15 0

selector offset

descriptor table

segment base address

+
descriptor

linear
dir page offset
address
Segment Registers
80386 stores information from descriptors in segment
register,thereby avoiding consult a descriptor table every time it
accessed memory
each segment register has a visible portion and an invisible
portion;the visible part are manipulated as if there were 16-bit
registers,the invisible part are manipulated by processor.
16-bit visible
selector hidden descriptor

CS
SS
DS
ES
ES
FS
Using Segment
Basic Flat Model
Protected Flat Model
Multisegment Model
Segment Descriptors
providing the processor with the data it needs to map a logical
address into a linear address
Base : defines the location of the segment within 4 gigabytes
Limit : defines the size of segment (20 bits)
reset G bit : in unit of one byte,a limit of up to 1 megabytes

set G bit : in unit of 4 kilobytes,a limit of up to 4 gigabytes

Granularity bit : specifies the units with which the LIMIT field is
interpreted
Type : distinguishes between various kinds of descriptors
DPL : descriptor privilege level,for protection mechanism
Segment Present bit : the segment is presented or not
Access bit : processor set the bit when accessed
Segment Descriptors
31 23 15 7 0
A limit
Base 31..24 G X 0 V 19..16 p DPI 1 TYPE A base 23..16 4
L

segment base 15..0 segment limit 15..0 0

A - Accessed
AVL - abailable for use by systems programmers
DPL - descriptor privilege level
G - granularity
P - segment present
Segment Descriptor Tables
the table is simply a memory array of 8-byte
entries that contains descriptors
two kinds of tables
GDT : global descriptor table
LDT : local descriptor table
the table may contains up to 8192 descriptors,64K
in size
the first entry of GDT (index=0) is not used by the
processor
LGDT & LLDT instructions load the base address
and limit into gdt & ldt
Segment Descriptor Tables
Global descriptor table Local descriptor table

M M

N+3 N+3
N+2 N+2
N+1 N+1
N N

(unused) 0 0

GDTR LDTR
Segment Selectors
the selector portion of a logical address identifies a descriptor by specifying
a descriptor table and indexing a descriptor within that table
Index:select one of 192 descriptors in a descriptor table.the processor
multiplies this index value by 8 (the length of a descriptor) and adds the
result to the base of the descriptor table to access the appropriate segment
descriptor in the table.
Table Indicator : specifies to which descriptor table the selector refers.a
zero indicates the GDT;a one indicates the LDT
Requested Privilege Level : for protection mechanism

15 0
index T

RPL requested privilege level

T1 table indicator