a) Draw the Y chart and explain the VLSI design process.

b) Enlist the classification of CMOS digital logic families. Why CMOS VLSI design is batter
techniques than its counter parts?
c) Explain the concept of regularity, modularity, semi custom and full custom styles of VLSI
system design.
d) What are the various processes of CMOS fabrication? Illustrate the main steps in a typical
n_well process.
e) Explain the scaling down of MOS-Transistor using constant Field Scaling and its limitation.
f) Explain symbol, different colours and lines used for drawing stick diagram. Draw a stick
diagram of CMOS inverter.

a) Consider a CMOS inverter circuits with the following parameters V DD = 3.3V, VTn= 0.6V,
VTp= -0.7V, n COX =60 A/V2, (W/L)n = 8, , p COX =20 A/V2, (W/L)p = 12. Calculate the noise
margin of the circuits

a) Draw a 4 x I multiplexer using Transmission Gate (TG).

b) Enlist the classification of dynamic CMoS logic circuit and discuss the advantage of dynamic
logic circuit over static CMOS logic circuit.
c) Discuss the charge sharing problem in VLSI circuits. Explain various circuit techniques used in
domino CMOS circuits for solving charge sharing problem.
d) Draw a neat diagram of CMOS SRAM cell and explain it. Explain leakage currents and refresh
operation in DRAM cells.
e) Give a logic circuit example in which stuck-at-0 fault and stuck-at- 1 fault are
indistinguishable.
f) Discuss the various design techniques involved in low power CMOS VLSI circuits.
g) Write a short note on adiabatic logic circuit.
h) Explain the different kinds of physical defect (faults) that can occur on a CMOS circuits.
Define the terms Controllability and Operability.
i) Discuss in brief Ad-Hoc Testable design techniques.
j) Write a short note on Buit-in-self test (BIST) techniques

Explain the CAD Tools for VLSI Design.

Define VLSI design methodology (Y Chart) and MOS Scaling

Discuss the classification of CMOS digital logic families

Draw a 4x1 Multiplexer using Transmission Gate (TG)

Explain the CMOS inverter switching characteristic and explain the definitions of delays and
transition times.

Enlist the Layout design process and design rules of CMOS circuit. Draw a stick diagram of CMOS NOR
gate.

In a logic Design logic function is Z = (A+B+C+D) (E+F+c) (H+D) implemented with domino CMOS
circuits diagram with implements load.
Discuss the overview of power Consumption in CMOS logic circuits.

Design 2 input EXOR Logic Gate using CMOS Transmission Gate.

Discuss the operation of single stage register circuits. Design a SR flip-flop CMOS circuits.

Design a D flip-flop using CMOS Transmission Gate circuits.

Discuss the low power MTCMOS VLSI designs techniques.

Discuss the Hierarchy of various semiconductor technologies with Moore's and VLSI design flow.

Write an expression for power dissipation in CMOS inverter

Write short notes on Mosfet Scaling and Channel Length Modulation.

Explain two input XOR gate using CMOS logic circuits, TG gate and Pass Transistor logic

Explain the two kinds of design rules *micro rules and lambda rules.

Explain limitations of scaling in VLSI fabrication technology

Draw a stick diagram for 2 input NAND Logic Gate using CMOS Logic.

Implement the Boolean function f(A,B,C)= a.gC + ABC +ABe usingCMOSlogic.