ECEN5807 Lecture 44

Final exam
Take home, open notes, textbook, materials posted on the course
website
On D2L: Friday May 3, 11am to Wednesday May 8, 5pm.
Late work will received zero credit
Absolutely no collaboration allowed, please read the exam front page
carefully
4 problems
Today
Finish intro to digital control of high-frequency switched-mode power
converters
Conclusions

ECEN5807
 Digitally Controlled Buck Converter
iL(t) Iout

+ L +

+ C R
Vg vo

_ _
Scaling and
Dead-time control H(s) anti-aliasing
filter
fs = 1 MHz duty-cycle _
command error error
dc[n] Compensator e[n] ve
Digital A/D
PWM ndpwm Gc(z) converter +
+
Vref

Apply the digital PID Gc(z) to the buck converter example

Analyzing the system requires understanding the effects of two
samplers
A/D converter
Digital PWM + switched-mode power stage
ECEN5807
 D/A: DPWM + Power Stage
PWM modulation
quantizer edge A/D PWM
ts tp ts
dc[n] Hold vo(t)
sampler
vo
g
PWM is a sampler! (in
analog too)
Re-sampling of PWM iL(t) Iout

creates an additional + L +

effective delay of DT +
Vg C R vo

Switched mode power _ _

stage acts as hold Dead-time control

function g(t) duty-cycle
fs = 1 MHz _
command error error
Quantizer again Digital
dc[n] Compensator e[n]
A/D
ve
+
assumed ideal with unity PWM ndpwm Gc(z) converter
+
gain Vref

ECEN5807
 Loop delay
Vg vo Total delay in the control loop:
Switched-mode
DC-DC converter load
td = tc + td1 + DTs + tg
H
g
V
tc = A/D conversion time
DPWM
d
Compensator
e
A/D
ve +
ref
td1 = processing time
DTs = modulator delay
Digitally controlled DC-DC converter tg = gate-driver propagation delay

nTs (n+1)Ts
Total delay td is the vo[n] vo[n+1]
time between the
vo(t)
A/D sampling and
vs(t)
the PWM sampling
g1(t)
There is no sample-
and-hold in the sample
model tc td1 d[n]Ts tg
td
Timing diagram
ECEN5807
 Loop Delay Discussion

Total loop delay td can significantly reduce phase

margin with respect to the template design
Can estimate additional phase margin needed in
analog template
For example: td = DT = 360 ns, fc = 100 kHz

m t d f c 360

m (360 ns)(100 kHz) 360 13

ECEN5807
 Design Example with Digital Control
iL(t) Iout

+ L +
Power stage parameters
+ C R
Vg vo
fs = 1/T = 1 MHz
_ _
Vref = 1.8 V,
Dead-time control

duty-cycle
Iout = 0 to 5 A
fs = 1 MHz _
command error error
Digital dc[n] Compensator e[n] A/D ve
+
Vg = 5 V
PWM ndpwm Gc(z) converter
+ L = 1 H
Vref

RL = 30 m
Digital Compensator
f c 100 kHz C = 200 F
Gcm 5.45 f p1 300 kHz
Resr = 0.8 m
f z 33 kHz f L 8 kHz m 53o
VM = 1 V
Gc ( z ) 28.5
z 0.9493 z 0.8063
H=1
z 1z 0.01278
ECEN5807
 Digital System: Loop Gain Response
60

40
td = 0 s
magnitude [db]

20

0 Discrete Design
-20 Analog Template
-40

3 4 5
10 10 10

0
Results
-50
fc = 113 kHz
phase [deg]

-100

-150
PM = 57 deg
-200
GM = 7.7 dB
-250
3 4 5
10 10 10
frequency [Hz]

ECEN5807
 Loop Gain Response including Loop Delay
60

40 Results for
td = DT=360 ns:
magnitude [db]

20

0
fc = 105 kHz
PM = 44 deg
-20
GM = 14.5 dB
-40

3 4 5
10 10 10

-50
phase [deg]

-100
td = 0
-150
td = DT = 360 ns
-200
td = 0.6T = 600 ns
-250
3 4 5
td = (1+D)T=1.36 s
10 10 10
frequency [Hz]
ECEN5807
 Load Transient Response
1.82
1.81
td = DT = 0.36 s
vo 1.8
1.79 Load transient:
1.78 2.5 A to 5 A
4.8 5 5.2 5.4 5.6 5.8 6 6.2 6.4 6.6 6.8
-4
x 10
8 1.8 vo
6 1.795
1.79
iL 4
1.785
2
1.78
0 4.8 5 5.2
4.8 5 5.2 5.4 5.6 5.8 6 6.2 6.4 6.6 6.8 -4
x 10
-4
x 10
0.8
v 20 mV
0.6
10 s settling
d 0.4
time
0.2

0 Next: include A/D and

4.8 5 5.2 5.4 5.6 5.8 6 6.2 6.4 6.6 6.8
DPWM quantization and
20 s/div x 10
-4
check the results
ECEN5807
 Simple Digital Compensator Design Summary
1. Design an analog compensator Gc(s) using traditional techniques
Loop analysis: standard averaged model of the switching converter
Compensator template: remove any high frequency poles associated
with analog hardware
Design: meet specifications in s-domain, include additional phase
margin to compensate for anticipated total delay, td
2. Apply BLT mapping to determine digital compensator coefficients
Set fcrit = cross-over frequency fc
3. Implementation in custom IC, FPGA, or microcontroller/DSP
Note: there are many other more advanced approaches and techniques
Digital compensators can be designed directly in Z-domain based on
converter discrete-time models
Models and design techniques have been developed to deal with
quantization effects, and finite word-lengths for signals and
coefficients

ECEN5807
 Digital SMPS Control:
Examples of More Advanced Features

1. Efficiency optimization
2. Embedded network analyzer
3. Time-optimal dynamic responses

ECEN5807 11
 Example 1: efficiency optimization
dead-time problem

Optimum utilization of a synch. rectifier depends on dead-time selection:

I. Too long time delays result in body diode conduction poor efficiency.
II.Too short time delays result in cross conduction of Q1 and Q2 poor efficiency.
Optimum dead times depend on circuit parameters, process/temperature variations,
and operating conditions (Vg, V, fs, I)
The impact on efficiency is greater at higher switching frequencies!
ECEN5807
 Dead-time control approaches
Q1 iL
Vg Q2 + L +
vg1 vg2 vs C vout R iL
_
_
vs
td2 td1
Gate
driver
vg2
g Duty-cycle
command _
d e vg1
PWM Compensator +
+
Controller Vref

Fixed dead times, td1max, td2max

Dead times often far from optimum, efficiency penalties
Ideal diode emulation based on switch node voltage sensing
More complicated, specialized gate drivers including fast analog circuitry
Best performance only with integrated power MOSFETs
ECEN5807
 Digital sensorless dead-time optimization
Q1 iL
iL [5A/div] Vg Q2 + L +
vs C vout R
Before optimization, vg1 vg2 _
vs efficiency is 87.3% _
Gate
drivers
vg1 g1 g2
Vref - Vq/2
+
Duty-cycle
x _
d PID
DPWM
Compensator y
vg2 td2 td1
Low pass +
_
filter
D Vref + Vq/2
Dead-time LP(z)
d Digital
Optimizer
Controller A/D

iL [5A/div] Near-optimum dead times found by

After optimization, minimizing the duty-cycle command
vs efficiency is 92.4%
Simple digital search algorithm
vg1 No additional power-stage sensing or
analog circuitry
vg2 No specialized gate drivers
Independent of power MOSFETs
approximately 1,000 gates
ECEN5807
 Example 2: embedded network analyzer
vin + Applications:
+ Switched-Mode Power Converter vout
_
Vg Simplified design and test
H On-line health monitoring
-
DPWM +
D
Programmable 1 e[n]
A/D Vref
Auto-tuning
Compensator +
2
u[n]
PRBS Improved robustness and reduced
FPGA
design time or system cost
Correlation
controller

< 30,000 gates + 10 kB RAM Control-to-output frequency response

System-ID approach:
Inject pseudo- Output voltage
random perturbation
Cross-correlate with
output voltage to
obtain system
impulse response
FFT generates
frequency responses

ECEN5807
 Example 3: Improved Large-Signal Dynamic Responses
Buck Converter
Vin
S vo
Modulator
L iload Worst-case transient:
C high-slew-rate
step load
ESR

Controller
+
Vref

vo (t)
vo vripple Output voltage deviation vo< vomax
Vo
tr Recovery time tr < trmax
i L(t)
t
i L
Iload Goal: meet the specifications
t
S
with a minimum-size or
a minimum-cost filter
t

ECEN5807
 Ideal Time-Optimal Control
Buck Converter
Vin
S L vo
iload vo (t)
Modulator
vo vripple
C
Vo
tr

i L(t)
t
Controller
+
Vref i L
Iload Q1
t
Q2
Ideal time-optimal response S
to a step-down load
transient t

A single off-on sequence brings the output voltage back to new

steady-state regulation in minimum time, and with minimum voltage
deviation
vo and tr found from the capacitor charge balance Q1 + Q2 = 0
Note: duty cycle is saturated to 0 or 1 during the transient
ECEN5807
 Proximate time-optimal digital control
PTOD = standard PWM + switching-surface controller
vs + load
iL L ic
+ V Q1
g Q2 vout
C
_

Transient-triggered
c c2
switching surface
Nonlinear switching surface controller
controller
fsample = Nos fs
Over-sampling of
cDPWM c2DPWM
voltage error e
qad
Fast transient d Vref
responses for fs DPWM PID
e +
arbitrary large-signal Window-flash
disturbances Constant-frequency PWM controller A/D
Digital capacitor
current estimation Standard digital PWM controller
Constant-frequency steady-state operation
Conservative PID, large small-signal stability margins
ECEN5807
 Experimental illustration of controller effects
on the required filter capacitance C

Exp 1: digital time-optimal controller Exp 2: digital PID controller

50 mV/div 50 mV/div vo
vo (a) (b)

iL iL
4 s/div 4 s/div
5 A/div 5 A/div

S S

Load enable L = 400 nH, C = 658 F Load enable L = 400 nH, C = 1.7 mF

With low-ESR capacitors, controller performance can affect the size and cost significantly

ECEN5807
 Power Electronics Courses at CU-Boulder
Introduction to Power Electronics (PE1)
ECEN5797
(offered every Fall semester)

Modeling and Control Techniques in Resonant and Soft-Switching

Power Electronics (PE2) Techniques in Power Electronics (PE3)
ECEN5807 ECEN5817
(offered in alternate Spring (offered in alternate Spring semesters,
semesters, 2013, 2015, ) 2014, 2016, )

Professional Certificate in Power Electronics

http://ecee.colorado.edu/copec/book/pecert.html

If you have completed all 3 courses with a grade of B- or higher,

send a request to Adam Sadoff, Adam.Sadoff@colorado.edu
ECEN5807
 http://ecee.colorado.edu/~ecen5817/

ECEN5807
 ECEN5817 Course Outline

1. Analysis of resonant converters using the sinusoidal

approximation
Classical series, parallel, LCC, and other topologies
Modeling based on sinusoidal approximation
Zero voltage and zero current switching concepts
Resonant converter design techniques based on frequency response
2. Sinusoidal analysis: small-signal ac behavior with frequency
modulation
Spectra and envelope response
Phasor transform method
3. State-plane analysis of resonant converters
Fundamentals of state-plane and averaged modeling of resonant circuits
Exact analysis of the series and parallel resonant dc-dc converters

ECEN5807
 ECEN5817 Course Outline

4. Configurations and state plane analysis of soft-switching converters

Quasi-resonant (resonant-switch) topologies
Quasi-square wave converters
Soft switching in forward and flyback converters
Zero voltage transition converter
DC-DC converter with fixed conversion ratio (DC transformer)
5. Energy-Efficiency and Renewable Energy Applications

ECEN5807
 New DOE GATE Center: Innovative Drivetrains in
Electric Automotive Technology Education (IDEATE)
http://mocha-java.uccs.edu/IDEATE/
Joint center between CU-Boulder and UC Colorado Springs campuses
Graduate certificate in Electric Drivetrain Technology (EDT)

Two new courses at CU-Boulder, both offered on campus and off campus via CAETE
ECEN5017 Power Electronics for Electric Drive Vehicles,
ecee.colorado.edu/~ecen5017, Fall semesters
ECEN5737 Adjustable Speed AC Drives,
ecee.colorado.edu/~ecen5737/, Spring semesters
ECEN5807
 ECEN5017 Power Electronics for Electric Drive Vehicles
ecee.colorado.edu/~ecen5017

Architectures, modeling and simulations of electric drivetrains

Analysis, modeling and design of vehicle power electronics

One of four courses in the new Graduate Certificate in Electric Drivetrain

Technology, through a Department of Energy sponsored GATE Center of
Excellence in Innovative Drivetrains in Electric Automotive Technology
Education (IDEATE), http://mocha-java.uccs.edu/IDEATE/

ECEN5807
 Introduction to Power Electronics on Coursera
https://www.coursera.org/course/powerelectronics

ECEN5807 26
 Thank you and good luck with the finals

ECEN5807 27