| [Document subtitle]

SAP
SAP1 1
(SIMPLE AS POSSIBLE)

OBJECTIVES:

To be familiar with SAP-1

To learn the different parts of SAP-1

To be knowledgeable on how each of the parts of SAP-1 works

INTRODUCTION:

The term "architecture" is used to define the components of the circuit, its

conceptual structure and even depicts how data flows and how it could be controlled. In

addition, it is under the umbrella of architecture to show the logical design of the system

and its several implementations.

SAP1 is an abbreviation of Simple As Possible, it is the first of the series of

microprocessors which the simplest possible complete and functional architecture. It is

made up from discrete integrated circuits, most of which are available in the Philippine

market. A SAP1 is an 8-bit computer with four address lines which is able to hold sixteen

different address locations.

It is the most basic model of a microprocessor for the design only contains the

basic requirements for a functional processor. It could be thus said that the primary

function of the SAP1 is to provide a model that could explain how a microprocessor works,

how it could interact with other parts of the system such as the Input and Output thus the

instruction set of SAP1 is limited and concise.

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SAP-1 FIGURE:

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SAP-1 MACHINE CYCLE:

A single instruction cycle may be composed of several machine cycles, for SAP1,

the instruction cycle is basically the same as its machine cycle, composing of the FETCH

and EXECUTION, and below are the five instructions for SAP1:

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EXPERIMENT 1: PROGRAM COUNTER
Experiment 1: Program counter
OBJECTIVES:

To further understand the functions of the program counter in SAP-1

To be familiar on how the program counter works

INTRODUCTION:

The program counter (PC), commonly called the instruction pointer (IP)

in Intel x86 and Itanium microprocessors, and sometimes called the instruction address

register (IAR), the instruction counter, or just part of the instruction sequencer, is

a processor register that indicates where a computer is in its program sequence.

In most processors, the PC is incremented after fetching an instruction, and holds

the memory address of ("points to") the next instruction that would be executed. (In a

processor where the increment precedes the fetch, the PC points to the current instruction

being executed.)

Instructions are usually fetched sequentially from memory, but control

transfer instructions change the sequence by placing a new value in the PC. These

include branches (sometimes called jumps), subroutine calls, and returns. A transfer that

is conditional on the truth of some assertion lets the computer follow a different sequence

under different conditions.

A branch provides that the next instruction is fetched from somewhere else in

memory. A subroutine call not only branches but saves the preceding contents of the PC

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somewhere. A return retrieves the saved contents of the PC and places it back in the PC,

resuming sequential execution with the instruction following the subroutine call.

MATERIALS:

1pc Breadboard

2pcs IC 74LS107

4pcs LEDs

1pc 4-pin DIP switch

SCHEMATIC DIAGRAM:

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MULTISIM:

PIN CONFIGURATION:

74LS107

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EXPECTED OUTPUT:

The expected output should appear as if the LED lights are counting from 1 to 15

(in binary, base 2)

SIMULATION:

The circuit trainer has built in control switches and value switches. For this run,

you must make sure that the value switches are all off (low) and RUN and AUTO are on

(high).

QUESTION/S:

Observe and explain the transition of the LED lights and write your observation below.

_________________________________________________________________________

_________________________________________________________________________

ADDITIONAL TASK:

After you have effectively created a working program counter, incorporate the use

of a SEVEN SEGMENT DISPLAY. You can use a decoder in order to effectively show

the expected output (which is the same, but this time it must be displayed on its decimal

format, counting from 1-15.

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NAME: _____________________________

ACTIVITY: PROGRAM COUNTER

DATE SUBMITTED: ____________________

___________________________________ GRADE

INSTRUCTORS SIGNATURE

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 Experiment 2: input and mar
EXPERIMENT 2: INPUT AND MAR

OBJECTIVES:

To be knowledgeable on how the input and MAR works

To further understand how the READ, WRITE, AUTO and CLEAR

functions

INTRODUCTION:

The INPUT and MAR includes the address and data switch registers. Switch

registers are part of input unit, allows us to send 4 address bits and 8 data bits to the

RAM.

The memory address register (MAR) is the part of SAP-1 memory. During a

computer run, the address in the program counter is latched in to the MAR. A bit later, the

MAR applies this 4-bit address to the RAM where a read operation is performed.

MATERIALS:

1pc 74LS173

1pc 74LS157

4pcs LED

1pc 4-pin DIP switch

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SCHEMATIC DIAGRAM:

MULTISIM:

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PIN CONFIGURATION:

74LS173

74LS157

EXPECTED OUTPUT:

When LM is on, MAR is active. It will get its input from the Program Counter,

otherwise, it will not function.

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SIMULATION:

In the control switches, set the PROGRAM, AUTO, CLEAR and WRITE to on

(high).

You could observe that there are individual switches dedicated exclusively to the

MAR. Set them all OFF (low).

QUESTION/S:

1. Why do you think that there is a need to set the switches off during this RUN?

_________________________________________________________________________

_________________________________________________________________________

2. What will be the output when you set the PROGRAM in the control switch high

while the rest of the switches are low?

_________________________________________________________________________

_________________________________________________________________________

3. What will be the output when you set the AUTO in the control switch high while

the rest of the switches are low?

_________________________________________________________________________

_________________________________________________________________________

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4. What will be the output when you set the CLEAR in the control switch high while

the rest of the switches are low?

_________________________________________________________________________

_________________________________________________________________________

5. What will be the output when you set the WRITE in the control switch high while

the rest of the switches are low?

_________________________________________________________________________

_________________________________________________________________________

NAME: _____________________________

ACTIVITY: INPUT AND MAR

DATE SUBMITTED: ____________________

___________________________________ GRADE

INSTRUCTORS SIGNATURE

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 Experiment 3: Random access memory

OBJECTIVES:

To further know how the random access memory functions in SAP-1

To acquire the knowledge on how the random-access memory stores data

INTRODUCTION:

Random-access memory is a form of computer data storage. A random-

access memory device allows data items to be read or written in almost the same amount

of time irrespective of the physical location of data inside the memory. In contrast, with

other direct-access data storage media such as hard disks, CD-RWs, DVD-RWs and the

older drum memory, the time required to read and write data items varies significantly

depending on their physical locations on the recording medium, due to mechanical

limitations such as media rotation speeds and arm movement.

RAM contains multiplexing and demultiplexing circuitry, to connect the data lines

to the addressed storage for reading or writing the entry. Usually more than one bit of

storage is accessed by the same address, and RAM devices often have multiple data

lines and are said to be '8-bit' or '16-bit' etc. devices.

In today's technology, random-access memory takes the form of integrated

circuits. RAM is normally associated with volatile types of memory (such

as DRAM memory modules), where stored information is lost if power is removed,

although many efforts have been made to develop non-volatile RAM chips. Other types

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of non-volatile memories exist that allow random access for read operations, but either

do not allow write operations or have other kinds of limitations on them. These include

most types of ROM and a type of flash memory called NOR-Flash.

MATERIALS:

2pcs 74LS189

1pc 8-pin DIP switch

1pc 4-pin DIP switch

8pcs LEDs

SCHEMATIC DIAGRAM:

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MULTISIM:

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PIN CONFIGURATION:

74LS189

EXPECTED OUTPUT:

The key to understand the RAM is to know that this is an independent circuit, which

means either we remove the clock source or we connect it, we will achieve the same

output. The expected output is whatever the input in its respective address, with or without

the clock source.

SIMULATION:

The main point of the microprocessor is to interpret and run instruction, thus we

initialize the instruction through inputting data. Using the Switching Module (there are

control switches and value switches) follow through the instructions below:

The control switches, set the PROG, AUTO, CLEAR and WRITE to ON (high). You

could observe that there are individual switches dedicated exclusively to the MAR.

Set them all OFF (low).

In Address 0H, store a random value of your choice.

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QUESTION/S:

1. What is your stored value?

_________________________________________________________________________

_________________________________________________________________________

Turn the switch WRITE on (high) then immediately turn it to READ on (high)

2. What are your observations?

_________________________________________________________________________

_________________________________________________________________________

NAME: _____________________________

ACTIVITY: RANDON ACCESS MEMORY

DATE SUBMITTED: ____________________

___________________________________ GRADE

INSTRUCTORS SIGNATURE

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EXPERIIMENT 4: INSTRUCTION REGISTER
Experiment 4: Instruction register
OBJECTIVES:

To familiarize the functions of Instruction Register

INTRODUCTION:
It is the part of a CPU's control unit that stores the instruction currently being

executed or decoded. In simple processors each instruction to be executed is loaded into

the instruction register which holds it while it is decoded, prepared and ultimately

executed, which can take several steps.

Some of the complicated processors use a pipeline of instruction registers where

each stage of the pipeline does part of the decoding, preparation or execution and then

passes it to the next stage for its step. Modern processors can even do some of the steps

out of order as decoding on several instructions is done in parallel.

Decoding the op-code in the instruction register includes determining the

instruction, determining where its operands are in memory, retrieving the operands from

memory, allocating processor resources to execute the command (in super

scalar processors), etc.

The output of IR is available to control circuits which generate the timing signals

that control the various processing elements involved in executing the instruction.

In the Instruction cycle, the instruction is loaded into the Instruction register after

the processor fetches it from the memory location pointed by the Program Counter.

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MATERIALS:

1pc breadboard
2pcs 74LS173
1pc 8pin DIP switch

SCHEMATIC DIAGRAM:

MULTISIM:

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PIN CONFIGURATION:

74LS173

SIMULATION:

Whatever data you input will also be the output. Refer to LEDs.
QUESTION/S:

1) With the same settings for the switches in the previous runs, observe the LED
depicting how the Instruction Register separates the 8-bit data to two sets of 4
bits. Why does the IR need to do this?

_________________________________________________________________________

_________________________________________________________________________

2) What do you call these two sets of 4-bit data?

_________________________________________________________________________

_________________________________________________________________________

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NAME: _____________________________

ACTIVITY: INSTRUCTION REGISTER

DATE SUBMITTED: ____________________

___________________________________ GRADE

INSTRUCTORS SIGNATURE

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EXPERIMENT 5: CONTROLLER SEUENCER
Experiment 5: CONTROLLER SEQUENCER
OBJECTIVES:

To be able to understand the functions of the controller sequencer

To further understand the CP EP LM CE L1E1 LA EA SUEULBLO machine language

INTRODUCTION:

Before each computer runs, a CLR signal is sent to the program counter and CLK

signal to the instruction register. This resets the program counter to 0000 and wipes out

the last instruction register.

A clock signal CLK is sent to all buffer registers; this synchronizes the operation of the

computer ensuring that things happen when they are supposed to happen.

The 12-bit that comes out of the controller sequencer form a word controlling the rest

of the computer (like a supervisor telling others what to do). The 12 wires carrying the

control word are called the control bus. The control word has the format of: CON =

CP EP LM CE L1E1 LA EA SUEULBLO.

This word determines how the registers will wait to the next positive CLK edge. For

example, a high EP and a low LM means that the program counter are latched into the

MAR on the next positive clock edge. As another example, a low CE and a low LA means

that the addressed RAM word will be transferred to the accumulator.

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MATERIALS:

2pcs breadboard

1pc 8pin DIP switch

1pc 4pin DIP switch

2pcs 74LS04 IC

5pcs 74LS08 IC

3pcs 74LS32 IC

12pcs LED switch

SCHEMATIC DIAGRAM:

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MULTISIM:

PIN CONFIGURATION:

74LS04

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74LS08

74LS32

SIMULATION:
With the same settings as the previous runs using AUTO and MAR Address is

set to 0H, complete the table with your observations below:

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 CYCLE OBSERVATION
T1

T2

T3

T4

T5

T6

EXPECTED OUTPUT:

The expected output is same as the theory. It must be able to show the states

and respective code (CP EP LM CE L1E1 LA EA SUEULBLO) high if active.

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QUESTION/S:

What op-code describes the observations you stated above?

_________________________________________________________________________

_________________________________________________________________________

NAME: _____________________________

ACTIVITY: CONTROLLER SEQUENCER

DATE SUBMITTED: ____________________

___________________________________ GRADE

INSTRUCTORS SIGNATURE

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EXPERIMENT 6:
EXPERIMENT 6: ACCUMULATOR ADDER/SUBTRACTOR
Accumulator adder/subtractor
OBJECTIVES:

To be knowledgeable on how the accumulator functions

To be familiarize to the operations and functions of adder/subtractor

INTRODUCTION:

The accumulator is a buffer register that stores immediate answers during a

computer runs. It has two output. The first one goes directly to the Adder-Subtractor. The

three state output goes to the W-bus when EA is high.

An addersubtractor is a circuit that is capable of adding or subtracting depending

on a control signal. It is also possible to construct a circuit that performs both addition and

subtraction at the same time. It is a 2's complement adder-subtractor. This module is

asynchronous, which means that its contents can change as soon as the input word

change.

MATERIALS:

74LS83

74LS173

2pcs 8pin DIP switch

16pcs LEDS

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SCHEMATIC DIAGRAM:

MULTISIM:

ACCUMULATOR:

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ADDER/SUBTRACTOR:

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PIN CONFIGURATION:

74LS173

74LS83

EXPECTED OUTPUT:
Accumulator: When La is on, the Accumulator must be loaded, thus the input

must be taken from the W-bus (or in this case, the switches). When EA is on, the 74LS126

will function and thus it will either enable the output or not.

Adder-Subtractor : Must be able to perform basic arithmetic functions and must be

displayed in binary format through the LEDs.

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SIMULATION:

With the same settings as the previous runs, pre-load the SAP1 Trainer with two

different decimals.

Manually, observe the results projected in the Adder-Subtractor Module.

NAME: _____________________________

ACTIVITY: ACCUMULATOR / ADDER - SUBTRACTOR

DATE SUBMITTED: ____________________

___________________________________ GRADE

INSTRUCTORS SIGNATURE

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 EXPERIMENT
EXPERIMENT 7: BOUTPUT
7: B AND AND OUTPUT REGISTER
REGISTER

OBJECTIVES:

To be familiar with the functions of B Register

To be knowledgeable with the functions of output register

INTRODUCTION:

The B register is also a buffer register. A low LB and positive CLK edge load the

word on the W-bus into the B-register. The two state output of the B register drives the B-

register.

At the end of a computer run, the accumulator contains the answer to the problem

being solved.

At this point, we need to transfer the answer to the outside world. This is where the

output register is used. When EA is high, is low, the next positive clock edge loads the

word of the accumulator into the output register. The output register is often called an

output port processed data can leave the computer through these register.

MATERIALS:

2pcs 74LS173

2pcs 74LS83

8pcs LEDs

2pcs 8-pin DIP switch

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SCHEMATIC DIAGRAM:

MULTISIM:

B REGISTER:

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OUTPUT REGISTER:

Instructional Manual in Computer System Architecture 36 | P a g e

PIN CONFIGURATION:

74LS173

EXPECTED OUTPUT:

The B-Register, from its name itself must serve as a buffer, thus whatever input is

the output.

The Output Register, when LO is on, must display the final output, no matter which

is required, in seven segment display.

NAME: _____________________________

ACTIVITY: B AND OUTPUT REGISTER

DATE SUBMITTED: ____________________

___________________________________ GRADE

INSTRUCTORS SIGNATURE

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SELF TEST
Self-test:
1. The Accumulator is an integral part of the SAP1 Circuit. What do you think would
happen if the Accumulator is removed from the circuit?

_________________________________________________________________________

_________________________________________________________________________

2. According to the results of the experiment, what is the practical use of a B-

Register?

_________________________________________________________________________

_________________________________________________________________________

3. Why does the SAP1 Circuit rarely use direct connections and uses the W-Bus?

_________________________________________________________________________

_________________________________________________________________________

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REFERENCE/S
Reference/s:

Photos:

Google Images
Stock Photos

Content:

Simple as Possible Computer 1 (SAP1) Architecture by Dadhi Ghimire

www.wikipedia.com/Instruction_Register
www.wikipedia.com/Memory_Address_Register

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Acknowledgement:

ABADILLA, DOMINIQUE B.

CABASAL, LLOYD B.

CAIDO, CAMILLE C.

ESPINOZA, ROLLY B.

GUILLEN, JERRYSON A.

LICMO-AN, KRISTINNE ANNE P.

LIWALIW, JOHN REY C.

LIWANAGAN, BIEN ANGELO T.

MATEO, JOHN PAUL A.

MEDALLE, ZEBRED G.

ORBINO, JACKIELYN

PACHECO, KEVIN T.

RODRIGUEZ, REGINALD

TAPALGO, REYNALDO P.

VENTURERO, JOHN ANGELO B.

ADVISER:

ENGR. JOAN P. LAZARO

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