EE6372 Semiconductor Process

Integration
Home Work3

Pavan Kumar Kota

Question 1 (25%)
What two types of strained silicon structures would you typically use in order to increase the
drive current in a PMOS device? Describe how these types of structures actually stress the
channel and briefly describe the process flows to generate these types of devices. Use graphs,
schematics, or micrographs to support your explanation.
Ans:
Lattice squeezing decreases the resistance for hole current flow in the direction of squeeze.
Squeezing of the Lattice can be achieved by either
a) Embedded SiGe in S/D: Filling up of the S/D regions close to the channel with SiGe
(preferably epitaxial grown SiGe : e-SiGe) would put uniaxial compressive strain on the
channel as the SiGe lattice is bigger than Si lattice.
Process Flow: Additional Integration steps are inserted after the spacer is formed.
i) Capping on NMOS devices to prevent Si recess etch and SiGe doping
ii) Selective Si recess etch of Si from S/D regions
iii) Selective In-Situ doped epitaxial SiGe growth
iv) Removing the capping on NMOS devices

Figure 1 : PMOS Ion vs Ioff for e-SiGe[1]

b) Compressive Stress Liner (Contact-End Stop – Stress Liner): A permanently stressed

compressive liner transfers mechanical stress to the channel through Si active area and
poly gate.
Process Flow: Deposition of stress liner has the whole integration process as-is with the
inclusion of few steps after silicide formation.
i) A layer of Tensile Nitride stress liner is deposited
ii) The Nitride layer is selectively etched off the PMOS region
iii) A highly compressive Nitride stress liner is deposited
iv) The compressive Nitride layer is selectively etched off the NMOS region
The Stress liner, increases the mobility of the carriers and does not affect/modify either
gate depletion or the impurity profile (GIDL,DIBL are not modified).
Figure 2 : Drive Current Enhancement with Stress Liner[1]

Figure 3 : Dual stress liner process flow

Question 2 (25%)
Explain the four basic sources of parasitic resistance in the source/drain contact structure. How
are the magnitudes of the source and drain extension resistance and contact resistance related to
the channel resistance? Why? Describe how this affects the source/drain doping and the contact
resistance.
Ans:
The current to/from the channel passes out through the S/D regions, S/D contacts and finally
into the metals. Hence for high performance the resistance of the S/D paths should be small. The
total resistance seen for the current to enter the (R S) channel from the metal is modeled as sum of
four resistances

R S=Rco + R sh + Rsp + Rac

Figure 4 : Resistances in current path from channel to metal[2]

a) Contact Resistance (Rco) between metal and S/D region

The S/D contact resistance has the contribution from the deeper junction and its contact
to the silicide.
RcoW >= ρc/2LL
Where ρc is the specific contact resistivity of the silicon-to-silicide interface in ohm/cm2.
LL is the lithographically drawn length.
b) Sheet Resistance (Rsh) of the bulk region of the S/D region
For all short channel devices the sheet resistance of the S/D region is replaced with
Source-Drain Extension Resistance (RSDE). Reason being the current flows through the
SDE and then into the S/D region filled with silicide.

c) Spreading Resistance (Rsp)

The current from the channel enters the S/D region through the accumulation region and
then spreads into the S/D region. The resistance seen while spreading from is accounted
in Rsp.
 d) Accumulation Layer Resistance (Rac)
When the MOS device is turned on, the channel region is inverted because of the
potential on the Gate. Since there is a S/D overlap region with the gate, the gate potential
causes accumulation in the S/D overlap region (Ex: In an NMOS device, a positive
potential on gate creates accumulation in the overlap region). The resistance offered by
this charge accumulation to current flow is modeled as Rac. With device scaling S/D
doping has increased and hence Rac has become insignificant.

Comparison with Rsat:

The channel resistance on-resistance Rsat is defined as VDD/IDsat or equivalently written as

When Rs reaches approximately 10% of Rsat, the saturation current is reduced by 8%. The goal is
to keep the degradation less than 10% in IDsat. Also from the above equation, Rsat decrease with
every technology node, hence Rs also has to decrease with every node.

Figure 5 : Allowable values of RSDE+Rsp for 8-10% degradation in IDsat[2]

“From Figure 5, it is possible to estimate the value of (R sp+Rsde) that will be required for
MOSFET’s scaled down to 50nm. The center curve in the Figure 1Figure 5 shows the calculated
values of the channel resistance RsatW of MOSFET’s from the 0.25 micron node down to the 50
nm node. The upper and lower curves show what the value of 20(R sp+Rsde)W would be if the
SDE region had sheet resistance values of 500ohm/sq and 1000ohm/sq respectively. This graph
is for n-channel, and for p-channel devices values would be about 20% higher.
The data indicates that the sheet resistance values of (Rsp+Rsde) will need to be about 650ohm/sq
for 250 nm MOSFET’s and about 900ohm/sq for 50nm MOSFET’s if the value of 20(R sp+Rsde)W
needed to limit the degradation in Idsat to 8-10% is to be achieved. However, since the junction
depths of the SDE regions decrease as the gate lengths are reduced, in order to keep the sheet
resistance- values in the 650-900ohm/sq range, the average doping densities in the SDE regions
will have to be increased. The peak value of the doping will have to exceed 1019 /cm3”[2].
 Figure 6 : Allowed values of Rco for 8-10% degradation in IDsat[2]

“To have a 10% or less contribution, the data indicates that ρ c must be in the range of 10-7
ohm/cm2 for 0.25 micron MOSFET’s, but must get down to around 4x10 -8 ohm/cm2 for 50nm
MOSFET’s. For a barrier height of about 0.5ev, the required doping density needed to achieve
such a low value of ρc is above 1020 /cm3 [2]. This means that the silicon regions in contact with
the silicide will have to be very heavily doped, a condition that may not be possible to attain in
50nm MOSFET’s with conventional structures” [2].

Question 3 (25%)
There is an increasing push to go to an elevated source/drain contact structure at 32 nm and
beyond. Explain what an elevated source/drain contact structure is and why this type of structure
would help address the resistance issues occurring within the source/drain structure as the
devices are scaled to smaller dimensions.
Ans:
To keep the parasitic resistances of S/D regions low, they have to be deep regions and cannot
be narrow. Increasing the depth of the S/D regions below the substrate surface increases the RSDE.
Hence a heavily-doped elevated (above substrate surface) selective Epi-Si contact structure is
preferred.

Figure 7 : Elevated S/D structure[2]

Elevated S/D structure has the following advantages

a) Reduced RSDE as the side-wall spacer can be thinned.
b) A thicker/deeper S/D junction can be made to contain the silicide and hence reduce
leakage.
c) The epi-taxially grown S/D can be heavily doped to reduce contact resistance.
The disadvantages of elevated S/D structure are that they need additional steps for selective
doping for n+, p+ and also to constraint the diffusion of S/D regions from going too far below
the gate all later process should be at low temperatures.

Question 4 (25%)
NiSi offers a number of distinct advantages over both TiSi2 and CoSi2. Explain what those
advantages are. The advantages of NiSi were recognized over fifteen years ago. Why hasn’t this
technology been implemented until the last few years?
Ans:
Advantages of NiSi are
1) Low temperature silicidation process
In CMOS process Silicidation is carried out after source drain formation. At sub-100nm
nodes, the process temperatures are kept low to control the junction diffusions (SDE
diffusions). Hence silicides with low silicidation temperatures and low sheet resistances
at such low temperatures are preferred. NiSi has the lowest silicidation temperatures and
a low and stable sheet resistance over the low temperature range. Figure 8 shows the
variation of sheet resistance for NiSi and TiSi2 for various silicidation temperatures.

Figure 8 : Sheet Resistance with Silicidation Temperatures[3]

2) Low silicon consumption

Silicon consumption is defined as the distance between the initial silicon interface and the
bottom of the silicide. Since NiSi is monosilicide, the silicon consumption is less than
disilicides (TiSi2, CoSi2). Less silicon consumption aids in decreasing the overall
resistance by increasing the thickness of silicide and hence reducing the sheet resistance.

Figure 9 : Silicon Consumption[3]

 3) No bridging failure property
If for silicidation, the moving species is metal, then the metal atoms creep onto the
sidewalls and if the moving species is Si, Si creeps on to the sidewall. A metal creep on
the sidewalls is not a problem as it will be removed in the subsequent step. Where as a Si
creeping onto the sidewall might react with the Metal and form silicide on the sidewall
which cannot be removed and will form a short. NiSi is preferred over TiSi2, as it has Ni
as the moving species.

Figure 10 : Bridging due to movement of Si

4) No adverse narrow line effect on sheet resistance

As the silicide lines get narrower the properties of the silicides changes. For TiSi 2, the
sheet resistance increases due to two reasons a) Lack of transition of crystal structure
from C49 to C54, b) Thinner films created at the edge because Si is moving species for
salicidation. For NiSi, sheet resistance decreases, because of formation of thicker edge
films, due to movement of Ni and there is no crystal modifications for NiSi for resistance
reduction.
5) Smaller contact resistance for both n- and p-Si
6) Higher activation rate of B for SiGe poly gate electrode
7) Smaller mechanical Stress

NiSi – (Nickel monosilicide) technology was proposed in 1991 showing all its advantages over
TiSi2 and CoSi2. The only problem with NiSi was that the process temperatures had to be less
than 700-7500C, beyond which NiSi converts to NiSi 2, which looses all its advantages. The
process temperatures for technology nodes during that time were very high and so NiSi could not
be used. Now at sub-100nm nodes the process temperatures are to be kept low, to keep the ultra
shallowness of the junctions and so NiSi is being used.

References
1) V. Chan et al., "Strain for CMOS Performance Improvement," IEEE 2005 Custom
Integrated Circuits Conference, p667-674, 2005
2) S. Wolf, “Silicon Processing for the VLSI Era,”Lattice Press, 2002.
3) H. Iwai et al., "NiSi Salicide Technology for Scaled CMOS," Microelectronic
Engineering, Vol.60, p157-169, 2002