Professional Documents
Culture Documents
Bonuses:
Participation to Digilent contest (www.digilent.ro, www.digilentinc.com) other
hardware contests (nope for BattleLab Robotica)
If no of attendances at the lecture >= 7 you can get a maximum 1 point
bonus to the written exam mark (~ no. of attendances)
Restrictions:
The repartition of the students in groups/half-groups is the one stated at
the beginning of the semester
You are not allowed to change your schedule of laboratory attendance
during the semester without the approval of the DMP lecture staff.
Lecture References
Lecture documents
http://users.utcluj.ro/~tmarita/PMP/PMPCurs.htm
Textbook ATMega
M. A. Mazidi, S. Naimi, S. Naimi, The AVR Microcontroller and Embedded
Systems Using Assembly And C, 1-st Edition, Prentice Hall, 2009.
Textbooks (8086 family mP)
Barry B. Brey, The Intel Microprocessors: 8086/8088, 80186,80286, 80386 and
80486. Architecture, Programming, and Interfacing, 4-rd edition, Prentice Hall,
1997 British Council Library (Cluj)
S. Nedevschi, L. Todoran, Microprocesoare, editura UTC-N, 1995 UTCN
Library
Additional documents
Data sheets from Atmel, Intel etc. (www.digilentinc.com, http://www.atmel.com/ )
Further study (for homework, lab & project)
2 cycle access
ALU operations
ATmega64L vs Atmega 2560
High-performance, Low-power AVR 8-bit Microcontroller High Performance, Low Power AVR 8-Bit Microcontroller
Advanced RISC Architecture Advanced RISC Architecture
130 Powerful Instructions Most Single Clock Cycle Exec. 135 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers + Peripheral 32 8 General Purpose Working Registers + Peripheral
Control Registers Control Registers
Fully Static Operation Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz Up to 16 MIPS Throughput at 16MHz
On-chip 2-cycle Multiplier On-Chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments High Endurance Non-volatile Memory Segments
64KBytes of In-System Reprogrammable Flash 256KBytes of In-System Self-Programmable Flash
2KBytes EEPROM 4Kbytes EEPROM
4KBytes Internal SRAM 8Kbytes Internal SRAM
Write/Erase Cycles: 10,000 Flash/100,000 EEPROM Write/Erase Cycles:10,000 Flash/100,000 EEPROM
Data retention: 20 years at 85C/100 years at 25C(1) Data retention: 20 years at 85C/ 100 years at 25C
Peripheral Features Peripheral Features
Two 8-bit Timer/Counters with Separate Prescalers and Two 8-bit Timer/Counters with Separate Prescaler and
Compare Modes Compare Mode
Two Expanded 16-bit Timer/Counters with Separate Prescaler, Four 16-bit Timer/Counter with Separate Prescaler, Compare-
Compare Mode, and Capture Mode and Capture Mode
Real Time Counter with Separate Oscillator Real Time Counter with Separate Oscillator
Two 8-bit PWM Channels Four 8-bit PWM Channels
Six PWM Channels with Programmable Resolution from 1 to Twelve PWM Channels with Programmable Resolution from 2
16 Bits to 16 Bits
8-channel, 10-bit PWM ADC 8/16-channel, 10-bit ADC
Byte-oriented Two-wire Serial Interface Four Programmable Serial USART
Dual Programmable Serial USARTs Master/Slave SPI Serial Interface
Master/Slave SPI Serial Interface Byte Oriented 2-wire Serial Interface
Programmable Watchdog Timer with On-chip Oscillator Programmable Watchdog Timer with Separate On-chip
On-chip Analog Comparator Oscillator
Speed Grades On-chip Analog Comparator
0 - 8 MHz @ 2.7 - 5.5V for ATmega64L Speed Grade:
ATmega2560/ATmega2561:
- 0 - 16MHz @ 4.5V - 5.5V
Memory and I/O map
AVR address spaces
Flash: $000 - $7FFF
ATmega64 Program Counter (PC) - 15 bits
Program memory is addressable on words (2 bytes): 32K
x 16 biti (64KB)
Program memory cannot be extended
ATmega 2560
ATmega64L
GPR
Groups of registers:
32 x 8-bit GPR (R0 R31); R(0:15), R(16:31), R(26:31)
1 cycle read/write various possible usage
X, Y, Z, (16 bits); indirect
addressing of instruction and
data memory