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OptiMOS2 Power-Transistor
Product Summary
Features
V DS 20 V
For fast switching converters and sync. rectification
R DS(on),max 1.95 m
Qualified according to JEDEC1) for target applications
ID 100 A
Super Logic level 2.5V rated; N-channel
Avalanche rated
V GS=2.5 V, T C=100 C 95
V GS=4.5 V, T A=25 C,
30
R thJA=45 K/W2)
I D=50 A, V DS=16 V,
Reverse diode dv /dt dv /dt di /dt =200 A/s, 6 kV/s
T j,max=150 C
1)
J-STD20 and JESD22
T A=25 C,
2.8
R thJA=45 K/W 2)
Thermal characteristics
Static characteristics
Gate threshold voltage V GS(th) V DS=V GS, I D=350 A 0.7 0.95 1.2
V DS=20 V, V GS=0 V,
Zero gate voltage drain current I DSS - - 1 A
T j=25 C
V DS=20 V, V GS=0 V,
- - 100
T j=125 C
2)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 m thick) copper area for drain
connection. PCB is vertical in still air.
3)
See figure 3
Rev. 1.1 page 2 2008-08-11
BSC019N02KS G
Dynamic characteristics
Fall time tf - 8 -
Q sw V GS=0 to 4.5 V
Switching charge - 21 29.8
V DS=0.1 V,
Gate charge total, sync. FET Q g(sync) - 59 78.5 nC
V GS=0 to 4.5 V
Reverse Diode
V GS=0 V, I F=50 A,
Diode forward voltage V SD - 0.8 1.2 V
T j=25 C
V R=10 V, I F=50 A,
Reverse recovery charge Q rr - 55.6 - nC
di F/dt =100 A/s
4)
See figure 16 for gate charge parameter definition
120 120
100 100
80 80
P tot [W]
I D [A]
60 60
40 40
20 20
0 0
0 40 80 120 160 0 40 80 120 160
T C [C] T C [C]
103 101
limited by on-state
resistance
10 s
100 s
102 100
0.5
1 ms
0.2
Z thJC [K/W]
0.1
I D [A]
10 ms
101 10-1 0.05
0.02
DC
0.01
100 10-2
single pulse
10-1 10-3
-1 0 1 2
10 10 10 10 10-6 10-5 10-4 10-3 10-2 10-1 100
V DS [V] t p [s]
200 9
4V 3V
175
2.5 V 2.4 V 8
7
150
6
1.8 V
125
R DS(on) [mW]
2.2 V 5
I D [A]
100
4 2V
75
2.2 V
3
2V 2.5 V
50
2 3V
4.5 V
25 1.8 V 1 3.5 V
1.6 V
0 0
0 1 2 3 0 10 20 30 40 50
V DS [V] I D [A]
100 350
300
75
250
200
g fs [S]
I D [A]
50
150
25 C
100
25
150 C
50
0 0
0 1 2 3 0 25 50 75 100
V GS [V] I D [A]
4 1.6
3 1.2
R DS(on) [m]
3500 A
V GS(th) [V]
2 98 % 0.8 350 A
typ
1 0.4
0 0
-60 -20 20 60 100 140 -60 -20 20 60 100 140
T j [C] T j [C]
105 103
102
104
Ciss 25 C
150 C
C [pF]
I F [A]
Coss
101
150 C, 98%
103
25 C, 98%
Crss
100
102 10-1
0 5 10 15 20 0 0.5 1 1.5 2
V DS [V] V SD [V]
103 5
16 V
4
25 C 10 V
102
3 4V
V GS [V]
100 C
I AV [A]
125 C 2
101
100 0
100 101 102 103 0 20 40 60 80
t AV [s] Q gate [nC]
24
V GS
Qg
22
V BR(DSS) [V]
20
V g s(th)
18
Q g(th) Q sw Q g ate
Q gs Q gd
16
-60 -20 20 60 100 140
T j [C]
PG-TDSON-8: Outline
Footprint
Dimensions in mm
Package Outline
PG-TDSON-8: Tape
Dimensions in mm
Published by
Infineon Technologies AG
81726 Munich, Germany
2008 Infineon Technologies AG
All Rights Reserved.
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