Slide 1

Introduction

Slide 2

Overview

Slide 3

Overview of our specific part of cluster project and institute project

Slide 4

Our design activities

Slide 5

Cluster project under IIT Guwahati

Slide 6

The aim and objective of the cluster project

Slide 7

Block diagram of transmitter part

Slide 8

Block diagram of RF part

Slide 9

Specification of subsystems (Amplifier specification)

Slide 10

Specification of subsystems (RF modulo specification)

Slide 11

Detailed PERT chart

Slide 12

Institutes project (reversible watermarking)

Slide 13

The aim and objective of the institutes project

Slide 14

Concept of Digital Watermarking (it is a copy right protection of ownership of any multimedia objects
(such as image, video, audio and text))

Slide 15

Standard Definition of Digital Watermarking

Slide 16

General Procedure for Digital Watermarking

It has two parts. They are

1) Encoder for data embedding and

2) Decoder for data extracting.

Slide 17

The encoder takes watermark data and original or host image as inputs to produce the watermarked
image. It is also encrypted by a key data with only known by the sender and receiver.

In decoding, the decoder needs the original image to extract the watermarked image from the
watermarked image

Slide 18

The main different between a conventional digital watermarking and reversible watermarking

Slide 19

We are focusing on the three basic and well known algorithms for reversible watermarking. They are

1. Difference Expansion (mainly used when image pixels are in uniform region)
2. Improved Rhombus Interpolation (can be used on image pixels even they are not in uniform
region )
3. Adaptive Feedback based Difference Expansion (It gives us the guarantee to provide the
highest payload with higher PSNR at all times.) highest payload means higher embedding
capacity and higher PSNR(Peak Signal to Noise Ration) means higher different between
original and watermarked image (Both are depends on the SSIM which should not excess 1)

Slide 20
The name of institutes project: The proposed Adaptive Feedback (AF) using DE Based Reversible
Watermarking (RW)

Slide 21

Flow chart for Adaptive Feedback based RIW using DE. We added some additional steps to add an
adaptive feedback with existing Difference Expansion algorithm for reversible Watermarking to provide
highest payload with higher PSNR at all times.

Slide 22

Basic building block diagram of Adaptive feedback based Reversible Watermarking:-

The image (let size of image is 512512) is first taken by a digital camera and then stored into RAM or
memory devices. The processor then read the data in one dimensional (1D) way (for 512512 there is
total 262,144 data) see fig.1. Then processor performs or processes the proposed algorithm on the
image and provides the watermarked image as output.
In other hand the decoder takes the watermarked image as input and provides the decoded Image as
Output. The decoded should be matches with the original image.
Foe m n matrix value (2D value)
1
1 2 2.
1 2 = .. = 1 2 . (data read as a 1D way)
..
1 2 .

Fig. 1
Slide 23

Specification of FPGA based Reversible Watermarking. by taking a look on the other existing FPGA
based RW algorithms , This proposed FPGA based architecture of RW algorithm should follow the
following specification to becomes the best architecture among them
Power- Overall system power-( 4.4V -5V)
Frequency Clock frequency-(> 4.32 MHz)
I/O stands for Input and output ports:- (should be =<61% i/o port of the FPGA ) less i/o means
less execution time required to complete overall process.
LUT Look up table-used to adjust the contrast characteristics of an image there are several
LUT made for a single FPGA to adjust several properties of Images. Among them 0.14% is used
for adjusting the contract characteristics of an image.
Throughput The amount of data processed per clock cycle (bits per Second) -55Mbps for 170
MHz frequency means 55Mbps data should be processed per each 170 MHz sine wave frequency
(clock frequency)
Critical Path- Maximum Clock Frequency- The maximum delay between any two sequential
elements in a design will determine the max clock speed-10.67ns (for single cycle).
Avg. SSIM (Structural Similarity Index Matrix):- the SSIM between original and watermarked
image should be less than 1 to provide that the data of original image is changed due to embed the
watermark data. The SSIM between original and decoded image should be 1 as our purpose to get
back the original image from the watermarked image without any lost.
Avg. Fun Out:-gives an idea of how efficiently routed or congested our design may be, and
probably how likely to meet our timing constraints.
Latency The time between data input and processed data output (clock cycle) 242 ns
Slide 24

Software installation status

Slide 25

Work done at other institute

Slide 26

Detailed PERT Chart

Slide 27

Budget Outlay

Slide 28

Manpower Details

Slide 29

H/w & S/w wise Break-up

Slide 30