System Verilog Interview Questions

1. What is clocking block?

2. What are modports?
3. What are interfaces?
4. What are virtual interfaces? How can it be used?
5. What is a class?
6. What is program block?
7. What is a mailbox?
8. What are semaphores?
9. Why is reactive scheduler used?
10.what are rand and randc?
11.What is the difference between keywords: rand and randc?
12.What is the use of always_ff?
13.What are static and automatic functions?
14.What is the procedure to assign elements in an array in systemverilog?
15.What are the types of arrays in systemverilog?
16.What are assertions?
17.What is the syntax for ## delay in assertion sequences?
18.What are virtual classes?
19.Why are assertions used?
20.Explain the difference between data types logic and reg and wire?
21.What is callback?
22.What are the ways to avoid race condition between testbench and RTL using
SystemVerilog?
23.Explain event regions in systemverilog?
24.What are the types of coverages available in systemverilog?
25.How can you detect a deadlock condition in FSM?
26.What is mutex?
27.What is the significance of seed in randomization?
28.What is the difference between code coverage and functional coverage?
29.If the functional coverage is more that code coverage, what does it means?
30.How we can have #delay which is independent of time scale in system
verilog?
31.What are constraints in systemverilog?
32.What are the different types of constraints in systemverilog?
33.What is an if-else constraint?
34.What is inheritance and give the basic syntax for it?
35.What is the difference between program block and module?
36.What is final block?
37.What are dynamic and associative arrays?
38.What is an abstract class?
39.What is the difference between $random and $urandom?
40.What is the use of $cast?
41.What is the difference between mailbox and queue?
42.What are bidirectional constraints?
43.What is circular dependency and how to avoid this problem?
44.What is the significance of super keyword?
45.What is the significance of this keyword?
46.What are input and output skews in clocking block?
47.What is a scoreboard?
48.Mention the purpose of dividing time slots in systemverilog?
49.What is static variable?
50.In simulation environment under what condition the simulation should end?
51.What is public declaration?
52.What is the use of local?
53.Difference b/w logic & bit?
54.How to take an asynchronous signal from clocking block?
55.What is fork-join, types and differences?
56.Difference between final and initial blocks?
57.What are the different layers in Testbench?
58.What is the use of modports?
59.What is the use of package?
60.What is the difference between bit [7:0] and byte?
61.What is chandle in systemverilog ?
62.What are the features added in systemverilog for function and task?
63.What is DPI in systemverilog?
64.What is inheritance?
65.What is polymorphism?
66.What is Encapsulation?
67.How to count number of elements in mailbox?
68.What is covergroup?
69.What are super, abstract and concrete classes?
70.Explain some coding guidelines you followed in your environment ?
71.What is Verification plan? What it contains?
72.Explain how messages are handled?
73.What is difference between define and parameter?
74.Why ?always? block not allowed inside program block?
75.How too implement clock in program block?
76.How to kill process in fork/join ?
77.Difference between Associative and dynamic arrays?
78.How to check whether randomization is successful or not?
79.What is property in SVA?
80.What advantages of Assertions?
81.What are immediate Assertions?
82.What are Assertion severity system level task? What happens if we won?t
specify these tasks?
83.What is difference between Concurrent and Immediate assertions?
84.In which event region concurrent assertions will be evaluated?
85.What are the main components in Concurrent Assertions?
86.What are the main components in Concurrent Assertions?
87.What is goto Replication operator in SVA?
88.What is difference between x [->4:7] and x [=4:7] in SVA?
89.What are implication operators in Assertions?
90.Can a constructor qualified as protected or local in systemverilog?
91.What are advantages of Interfaces?
92.How automatic variables are useful in Threads?
 Verilog Interview Questions

1. What is the race condition in verilog?

2. List the levels of abstraction in verilog?
3. Which are the two types of design methodologies?
4. Num = 'bX; What will be the value of Num?
5. What are the differences between wire and register?
6. What are the differences between logical AND and reduction AND?
7. What is the difference between swapping the contents of two registers
with temp register and without temp register?
8. How logical shift differs from arithmetic shift?
9. What is the conditional operator and how it is used?
10. What is the difference between == and ===?
11. What exactly expression reg[8*13:1] string_val; signifies?
12. When output port is generated by a submodule what will be the type
of output
a. Register b. wire
13. List the built in primitives?
14. Name the two possible ways by which we can instantiate the
modules?
15. Which assignment statement we usually use in dataflow modeling?
16. What are rise delay and turn off delays?
17. What is inter delay? explain with an example
18. What is intra delay? explain with an example
19. What are the difference between inter and intra delays
20. Which is the stable one in the following
21. What are the differences between continuous and procedural
assignments?
22. What are the differences between assignment in initial and always
blocks?
23. What are the differences between blocking and non blocking
statements?
24. What are the differences between Task and Functions?
25. How re-entrant task,function differs from static task,functions ?
26. How we can convert static task and function to re-entrant task and
function?
27. What is an effect of keyword automatic for re-entrant task?
28. What is an fork--join exactly mean?
29. Which assignment statement will be used in Behavioral modeling?
30. Always and initial blocks are called ______ blocks
31. Always and initial blocks are called ______ blocks. 31. What is
sensitivity list?
32. What are procedural assignment statements?
33. How we can avoid race condition?
34. How we can represent a blocking and non blocking assignments?
35. List process synchronization supported by verilog?
36. What actually event does?
37. What wait does actually?
38. What forever loop does?
39. When generate statements are used?
40. List out the different methods to create generate statement?
41. Which are the two types of UDP's in verilog?
42. Why RTL synthesis is important?
43. What is the difference between always with @ and always without
@?
44. What is the difference between $display and $monitor?
45. Write a code for 2:1 Mux?
46. Write a Verilog code which divides the clock by 2?
47. Write a code which converts 4 bit binary to gray code?
48. Write a code for one hot counter?
49. Write a code for 16 bit counter?
50. Write a code for 8 bit parity checker?
51. Write a code for 8 bit shift-left register?
52. Write a code for 8 bit Unsigned adder?
53. Write a code for comparator?
54. When we use FSMs?
55. Difference between `define and parameter?
56. What value is inferred when multiple procedural assignments made to
the same reg variable in an always block?
57. What are snake paths?
58. What is constant propagation? How can I use constant propagation
to minimize area?
59. What happens to the bits of a reg which are declared, but not assigned
or used?
60. Why we use `ifdef and generate for in verilog?
61. What is the difference between using `ifdef and generate?
62. What is retime logic between registers?
63. Why one-hot encoding is preferred for FSMs?
64. What are the main factors that affect testability of a design?
65. What are the various methods to reduce power during RTL coding?
66. What is the advantage of using hierarchical names to refer to Verilog
objects?
67. What are the disadvantages of using hierarchical name to refer to
Verilog objects?
68. What is the effect of specifying delays in assignments during
synthesis?
69. What is the synthesized hardware for the verilog code below?
70. What is the synthesized hardware for the verilog code below?
71. How to avoid unintentional latches in the design?
72. What is a "full" case statement?
73. What is a "parallel" case statement?
74. Pros and cons of latch and Flip-Flop?
75. Write a verilog code for D flip flop with Synchronous reset?
76. Write a verilog code for D flip flop with asynchronous Reset?
77. Write a verilog code for D flip flop with gated clock?
78. What are the guidelines for coding priority encoders?
79. What are the limitations of using tri-state logic?
80. What is the effect of specifying a function without a range?
81. How to selectively enable or disable monitoring?
82. What is the main limitation of fork-join in Verilog?
83. What are the differences and similarities between the logical (<<, >>)
and the arithmetic (<<<,>>>) shift operators?
84. What is the difference between the logical (==) and the case (===)
equality operators?
85. What is the difference between assign-deassign and force-release?
86. What is a critical path in a design?
87. If there are only inputs and no output what it will be synthesized?
88. what is the difference between casex and casez?
89. Write a Verilog code for ring counter?
90. What is `timescale?
91. What are different types of Verilog simulators?
92. How we can use Verilog function to define the width of a multi-bit
port, wire, or reg type?
93. What is alias?
94. What is the difference between: c = con ? a : b; and if (con) c = a; else
c = b;
95. What is scheduling semantics for the simulation time in Verilog?
96. What is PLI?
97. List all the system tasks and their purpose?
98. What is a netlist?
99. How memory is declared in Verilog?
100. What are the guidelines for using functions in Verilog?
Digital Interview Questions

1. What are the applications of buffer?

2. Why Digital signal are mostly used for transmission than analog?
3. What is excitation table?
4. What is difference between synchronous flip-flop and
asynchronous flip-flop?
5. Draw pseudo random sequent sequence generator to generate 15
random patterns?
6. What are the applications of pseudo random sequent sequence
generator?
7. How to find the Propagation delay, Clock to Output?
8. How to find the Propagation delay, input to output delay?
9. How to calculate Setup time?
10. How to calculate the value for Hold time?
11. How to calculate the Maximum Clock rate (MCLK)?
12. What is Clock Skew?
13. Define Clock Gating?
14. Why NAND gate is preferable over NOR gate for fabrication?
15. What is Noise Margin?
16. When metastability will occur? Different ways to avoid this?
17.For a NAND gate if signal A arrives at the NAND gate later than
signal B. To optimize delay of the two series inputs A and B which
one is placed near to the output?
18. Given only two xor gates one must function as buffer and another
as inverter?
19. How to achieve 180 degree exact phase shift?
20. How to implement Full adder using decoder?
21. Design 4 bit comparator circuit?
22. Implement f (A,B,C,D) = m(1,4, 5, 7, 9, 12, 13) using 4 to 1
mux?
23. How to fix the setup and hold violation?
24. What is setup time and hold time?
25. What will happen if there is setup time and hold time violation?
26. What is clock skew?
27. Define local-skew, global-skew and useful-skew?
28. What is meant by virtual clock? Why do i need it?
29. What is slack?
30. Define Moore and Mealy state machine?
31. What is the difference between mealy and moore state machine?
32. Difference between one-hot and binary encoding?
33. What is significance of RAS and CAS in SDRAM?
34. What will happen if contents of register are shifter left, right?
35. For the FIFO rules, what are underflow and overflow conditions?
36. Why interrupts are active low?
37. Which one estimating maximum clock frequency of a circuit, set
up time or hold time?
38. Differences between D-Latch and D flip-flop?
39. What is a multiplexer?
40. How can you convert an SR Flip-flop to a JK Flip-flop?
41. How can you convert the JK Flip-flop to a D Flip-flop?
42. What is Race-around problem? How can you rectify it?
43. How do you detect if two 4-bit signals are same?
44. 7 bit ring counter's initial state is 0100010. After how many clock
cycles will it return to the initial state?
45. How to convert D flip-flop into divide by 2?
46.What is the max clock frequency the circuit can handle, if
T_setup= 6nS T_hold = 2nS T_propagation = 10nS ?
47.If N number of XNOR gates are connected in series such that the
N inputs are given to A0 & A1 of first XNOR gate and A2 & O/P
of First XNOR to second XNOR gate and so on. Nth XNOR gates
output is final output. How does this circuit work?
48. How will you implement a Full subtracter from a Full adder?
49. What is the difference between setup and hold time?
50. In a 3-bit Johnson's counter what are the unused states?
51. What is an LFSR?
52. What is false path? How to determine this? What are the effects of
false path in circuit?
53. If two similar processors, one with a clock skew of 100ps and
other with a clock skew of 60ps. Which one will consume more
power? Why?
54. What are multi-cycle paths?
55. If two counters counting up to 16, built from negedge DFF, First
circuit is synchronous and second is "ripple", which circuit has a
less propagation delay? Why?
56. What is the difference between RAM and FIFO?
57.The circle can rotate clockwise and back. Use minimum hardware
to build a circuit to indicate the direction of rotation?
58.How many 2 input xor's are needed to implement 16 input parity
generator?
59.Design a circuit for finding the 9's compliment of a BCD number
using 4-bit binary adder and some external logic gates?
60.What is the difference between write-back and write through
cache?
61. What is the difference between Synchronous, Asynchronous
communication?