B465

5 4 3 2 1
PRELIMINARY GUAM S1G4 SCHEMATIC DESIGN

DDR III, 1333MT/S UNBUFFERED DDR3 Optional CPU
Channel A NEAR SODIMM Temperature sensor
HDT 18,19 16
16
Channel B UNBUFFERED DDR3

FAR SODIMM
D
EXTERNAL CLOCK GENERATOR SCAN AMD S1G4 CPU D
16 18,19
SLG8LP625
20 SB-TSI
14,15,16,17 16
OUT
IN
HyperTransport
LINK0
16x16
LVDS CON LVDS MUX RS880M

43
HyperTransport LINK0 CPU I/F

PARK_XT_S3 X16 PCIE MUX
31--40 DX10 IGP
LVDS/TVOUT/TMDS Ambient Light Sensor
I2C I/F BOOTSTRAPS
VGA CON CRT MUX DISPLAY PORT X2 ROM(NB)
C
44 24 52 C
Side Port Memory
1 X16 PCIE I/F
1 X4 PCIE I/F WITH SB
6 X1 PCIE I/F
GPP PCIE INTERFACE
21,22,23,24,25
PCIE
LAN&CARDREADER JMC261
48 X4
USB 2.0
MINIPCIE WIFI AZALIA CODEC
47 HD AUDIO I/F
GPP INTERFACE SB820M CX20671
USB#4 42
USB2.0 (14)+1.1(2)
SATA III (6 PORTS)
SIM
card MINIPCIE USB 2.0 4 X1 PCIE GEN2 I/F
49
socket USB#8
B
INT. CLK GEN. SATA III I/F Mobile 2.5" HDD Mobile ODD 41 B
41
GB MAC
Bluetooth Finger Print CAM HW MONITOR
Reader USB#3 USB#1 USB#0 USB 2.0
USB#7 45 USB#6 45 USB#5 45 46 46 46 PCI/PCI BDGE
HW MONITOR I/F HW MONITOR CPU Tempreture Sensor
INT. RTC 28
EC 26,27,28,29
HD AUDIO
SPI I/F SPI ROM
LPC I/F 28
SPI I/F
ACPI 1.1 I2C I/F BOOTSTRAPS
ROM (SB) 30
BATTERY CHAGER CPU CORE CPU MEMORY POWER

7 8 9
DISCHARGE CIRCUIT
A
SYSTEM MAIN POWER 1V1DUAL/VLDT/ 1.5V/1.5VDUAL/ A
13 VCC_NB/+1.1V 10 1.8V/3.3V/5V 11
SCANNED IT8502E
MATRIX PS2 EC
KEYBOARD TOUCH PAD Bitland Information Techonogy Co.,Ltd.
RESET,FAN 49 49 49 Notebook R&D Division
& ENABLES 55
Title
BLOCK DIAGRAM
Size Document Number Rev
Custom 1.0
BM5016
Date: Thursday, August 05, 2010 Sheet 1 of 54
5 4 3 2 1
5 4 3 2 1
D
TABLE OF CONTENTS D
C C
B B
A A
Bitland Information Techonogy Co.,Ltd.

Notebook R&D Division
Title
TABLE OF CONTENTS
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
AMD S1G4
CPU_VDDA_RUN CPU_VDDIO_SUS
DDRiII SODIMMX2--SYSTEM
BATTERY BATTERY +VIN CPU core CPU_VDD_RUN@38A VCCA 2.5V VDD MEM 4A
11.1V 62WHr CHARGER PWM MEM_VTT
VTT_MEM 0.5A
ISL6251 ISL6265A
CPU_VDD_RUN VDD CORE
1.375-1.500V 36A CLOCK GEN
AC ADAPTOR CPU core CPU_VDDNB_RUN@4A CPU_VDDNB_RUN VDDNB CORE
15-16V 90W PWM 0.9V 4A +3.3V BEAD 3.3V
ISL6265A VLDT
D
BEAD VLDT 1.2V TPDA D
CPU_VDDIO_SUS@9A CPU_VDDIO_SUS HD CODEC

DDR3 PWM VDD MEM TPDA +5V
LDO VTT MEM_VTT@1.5A BEAD 5V AUDIO
VDDR +3.3V OP
TPS51128&RT9199GSP AOZ1024 VDDR 1.5A BEAD 3V
+5V PWM +3.3VDUAL
BEAD
+1.1VDUAL@10A RS880M
+1V~1.2V SW VLDT
+1.1V SW +VCC_NB_RUN BEAD VDDHTTX 1.2V 0.68A
+1.1V
ISL6228 BEAD VDDHTRX+HT 1.1V 0.68A
+1.1V SMSC1100--EC
BEAD VDDPCIE 1.1V 1.1A +3.3VDUAL
+1.8V 3.3V 0.5A
+1.8V SW +1.8V@1.3A BEAD VDDA18 1.8V 0.64A
MAX8716-2/2 +VCC_NB
VDDC 1.0V-1.1V 7.6A LCD PANEL
+3.3V +3.3V
VDDG33 3.3V 0.06A SW 3.3V 1.5A
+1.8V
+3.3VALW BEAD VDDG18 1.8V 0.005A
+1.5V
+5VALW BEAD VDD18_MEM 1.8V 0.005A
+5V SW +1.5V BACK LIGHT
+3V SW BEAD VDD_MEM 1.8V 0.23A
C
+3.3V C
+5V LDO +3.3VDUAL@8A BEAD AVDD 3.3V 0.125A
+3V LDO +1.8V +VIN LED_BL
+5VDUAL@8A BEAD VDDLT18 0.22A
tps51125 +3.3V +VDD_MAIN
BEAD VDDLT33 0A
+1.8V USB X2 FR
BEAD PLLs 1.8V 0.1A +5VDUAL
+1.1V 5VDual
BEAD PLLs 1.1/1.2V 0.23A
VDDC PWM VDDC@15A
AMD SB800
TPS51128 +3.3V
VDDIO_33_PCIGP 3.3V 0.020A
+1.8V
VDDIO_18_FC 1.8V 0.050A
+1.1V
BEAD VDDAN_11_PCIE 1.1V 1A
CPU_VDDIO_SUS MVDDQ +1.5V 4A +3.3V
SWITCH BEAD VDDPL_33_PCIE 3.3V 0.030A
+1.1V MINI PCIE SLOT0,1,2
BEAD VDDAN_11_SATA 1.1V 0.8A +1.5V
+3.3V 1.5V (S0, S1) 0.5A
CPU_VDDIO_SUS 1.1V_1.0V_PWR 2.6A BEAD VDDPL_33_SATA 3.3V 0.020A each
SWITCH +3.3VDUAL
BEAD VDDAN_33_USB_S 3.3V 0.2A +3.3VDUAL 3.3V (S3, S5) 2.75A
+1.1VDUAL each
BEAD VDDAN_11_USB_S 1.2V 0.2A
+3.3VDUAL +3VRUN +1.1V SATA HD0,1
B
SWITCH VDDCR_11 1.1V 0.5A B
+1.1V
BEAD VDDAN_11_CLK 1.1V 0.4A
VDDIO_GBE_S/2 VDDRF_GBE_S +5V
+3.3VDUAL 1.8V_REG 1.5A +3.3VDUAL 5V (S3, S5) TBD
SWITCH VDDIO_33_GBE_S 3.3V
+1.5V +1.1VDUAL SATA ODD
VDDCR_11_GBE_S 1.1V +5V
PHY_VDDIO_DUAL 5V (S0, S1) TBD
VDDIO_GBE_S 3.3V
+3.3VDUAL
VDDIO_33_S 3.3V
CPU_VDDIO_SUS +1.5V@1A +1.1VDUAL
SWITCH VDDCR_11_S 1.1V
+1.1VDUAL VDDCD_11_USB 1.1V
BEAD
+5VDUAL +5V AZ_VDDIO_DUAL
VDDIO_AZ_S 3.3V OR 1.5V
SWITCH +1.1VDUAL
BEAD VDDCR_11_USB_S 1.1V
+3.3V
BEAD VDDPL_33_SYS 3.3V SYS PLL
+3.3VDUAL +3.3V +1.1V
SWITCH BEAD VDDPL_11_SYS 1.1 V SYS PLL
+3.3VDUAL
BEAD VDDPL_33_USB_S 3.3 V USB PLL
+3.3V CPU_VDDA_RUN +3.3VDUAL
BEAD VDDAN_33_S 3.3V HWM
2.5V LDO +3.3VDUAL
A BEAD VDDXL_33_S 3.3V A
+1.1V DUAL +1.1V

SWITCH AMD SB800
VDDC
MVDDQ Bitland Information Techonogy Co.,Ltd.
+3.3VDUAL S3,S4,S5 Notebook R&D Division
1.5V LDO 1.1V_1.0V_PWR PARK_XT_S3 Title
POWER DELIVERY CHART
+1.5VDUAL 1.8V_REG Size Document Number Rev
+3.3VDUAL SWITCH Custom 1.0
+3VRUN BM5016
5 4 3 2 1
5 4 3 2 1
Power on Sequence required:
SB800:
1, +3.3VDUAL ramp before +1.1VDUAL
2, +3.3V ramp before +1.8v CPU_LDT_RST#
3, +1.8V ramp before +1.1v (SB TO CPU)
4, +3.3v ramp before +1.1v
5, +3.3VALW_R ramping down time > 300us
6, 50uS <= All power rails except +3.3VALW_R <= 40mS
7, 100uS <= +3.3VALW_R <= 40mS CPU_PWROK
(SB TO CPU) >1 mS Req.
RS880: CPU_CLKP/N running

1, 0 <(+3.3V) - (+1.8v) < 2.1
2, +1.8V ramp before +1.1v >1 mS Req.
3. +1.1V ramp before VCC_NB
running
D D
>1 mS Req. VCC_NB(all NB power) valid before NB_PWRGD.
SB OUTPUT NB_PWRGD
NB_PWRGD_IN
SLP_S3# 1V1DUAL_PWRGD
SB INPUT SB_PWRGD 1)+1.5V SWITCH TO +1.5VDUAL 2)LASSO_PWRON 3)LPCPD# for TPM 4) TO SB&KBC SYS_RST# 1V5_PWRGD/DNI
+1.2V_PWRGD KBC_GPIO77/DNI
+1.2V_PWRGD
PARK-XT_PGOOD
T3>0
1.8V_REG
T2>0
1.1V_1.0V_PWR RC=~ms
PCIE_REFCLKP/N RC=~ms
VDD_CT
T1>=0
RC=~ms
VDDC
RC=~ms
MVDDQ
RC=~22ms VCC_NB should not ramp before 1.1v

VCC_NB
RC=~4.7ms
VLDT
GROUP B
VRM_PWRGD AND 1V8_PWRGD

+1.1V
VRM_PWRGD
C RC=0 C
CPU_VDDR
RC=0
CPU_VDD_RUN
RC=0
CPU_VDDNB_RUN
VDDA_PWRGD
GROUP A
+2.5V_LDO
(CPU_VDDA_2.5_RUN)
+1.5V
1V8_PWRGD
RC=0
+1.8V
+5V/+3.3V
5V/3.3V_GATE
to S3
SLP_S3#
VDRAM_PWRGD
CPU MEM CTL &
DDR3 SODIMM PWRS
MEM_VTT VTT only will be shut down in S3 mode, and VTT for DDR3 SODIMM only.
MEM_VREF
CPU_VDDIO_SUS
SLP_S5#
Power button from EC to SB

PWR_BTN#_EC
20mS
CPU_THM/SB/SB_SCL1/2 delay
B RSMRST# B
SB_KB/SPI/LPC ROM PWRS
V3V5DUAL_PWRGD
1V1DUAL_PWRGD
SYSTEM_DUAL_PG_DELAY
+5VDUAL/+3.3VDUAL/+1.5VDUAL/+1.1VDUAL
DUAL RAILS When IMC, always on at all time( always PWR)
VDD_DUAL_EN
Power button pressed

Power button pressed
KBC is ready
AC not present scenario = LOW AC present= high
AC_OK
(ACIN detect)
KBC is powered by
A_VBAT & +3.3VALW +5VALW/+3.3VALW
LDO:5.4V
(from DCIN)
Battery inserted/AC IN
+VIN/+12V_HD
A_VBAT
A A

Title
POWER SEQUENCE CHART
D 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
EXTERNAL CLOCK MODE NB CLOCK INPUT TABLE

NB CLOCKS RS880M
HT_REFCLKP
100M DIFF
AMD NORTHBRIDGE HT_REFCLKN
100M DIFF
REFCLK_P
A-LINK
RS880M REFCLK_N
14M SE (1.1V)
GPP_REFCLK vref
GFX_REFCLK
100M DIFF(IN/OUT)*
NB_GFX_REFCLKP/N
GPP_REFCLK
GPP REF_CLK
NBLINK_RCLKP/N
D D
HT_REFCLKP/N
NC or 100M DIFF OUTPUT
14.318MHZ
GPPSB_REFCLK 100M DIFF
NB_OSC
100MHZ
100MHZ
100MHZ
100MHZ
A_SODIMM
B_SODIMM
* RS880M can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.
CLK_REQ in CLK GEN
PCIE_REFCLKP/N PCIE GFX PARK_XT(RS880M, 16 LANES) 25M Hz

100MHZ EXT_PCIE_PE2_CLKREQ# PARK_XT
MEM_MB_CLK1_P/N
MEM_MB_CLK2_P/N
MEM_MA_CLK1_P/N
MEM_MA_CLK2_P/N
25M_X1
25M_X2
PCI_CLK0
PCICLK0 FOR DEBUG PORT
33MHZ
27M Hz
SMSC_CLK
PCICLK1 STRAPS SETTING,
33MHZ PCIE GEN1/PCIE GEN2
AMD CPU_CLKP/N EXTERNAL AMD SB800

PCICLK2
PCICLK3
PCICLK4
PCI_CLK2
PCI_CLK3 STRAPS SETTING,
200MHZ PCI_CLK4 UNUSED CLOCKS
33MHZ
SIG4 CPU CLOCK GENERATOR EXT CLK MODE LPC_CLK0
LPCCLK0 EC/STRAPS SETTING :EC ENABLE
PCIE_PE2_CLKP/N 33MHZ
MINIPCIE SLOT (SB800, 1 LANE) LPC_CLK1
PORT2:WLAN LPCCLK1 STRAPS SETTING,
100MHZ EXT_PCIE_PE2_CLKREQ# 33MHZ
CLOCKS ENABLE
PCIE_LAN_CLKP/N RTCCLK
FOR SATA
14.31818MHz
PCIE GPP I/F (RS880M, 1 LANE) JMC261 AZ_BIT_CLK

100MHZ EXT_PCIE_LAN_CLKREQ# AZ_BITCLK HD AUDIO
SATA_X1 24MHZ
25M Hz
SPI_CLK
SPI_CLK SPI ROM & HEADER
DNI xxHZ
SATA_X2
25M Hz GBE_RXCLK
C C
GBE_TXCLK NC
SBSRC_CLKP/N
PCIE_RCLKP/N
100MHZ
CLK_48M_USB USBCLK
DNI 48MHZ
SB_OSC
32.768K Hz
INTERNAL CLOCK MODE

MEM_MA_CLK1_P/N
MEM_MA_CLK2_P/N SPM_CLK
A_SODIMM AMD NORTHBRIDGE SIDE PORT MEMORY CHIP
AMD xxxMHZ
A-LINK
MEM_MB_CLK1_P/N
RS880M GPP_REFCLK
B_SODIMM
MEM_MB_CLK2_P/N
SIG4 CPU REFCLKP/N
SB_NBLINK_RCLKP/N
NB_REFCLK_P/N
HT_REFCLKP/N
CPU_CLKP/N
100MHZ
100MHZ
100MHZ
200MHZ
B B
CPU_HT_CLKP/N
PCIE_RCLKP/N
NB_HT_CLKP/N
PARK_XT
NB_DISP_CLKP/N
27M Hz
PCI_CLK0 PCIE_REFCLKP/N
FOR DEBUG PORT PCICLK0 SLT_GFX_CLKP/N PCIE GFX PARK_XT(RS880M, 16 LANES)
100MHZ
SMSC_CLK SB_MXM_CLKREQ#
STRAPS SETTING,
PCICLK1
PCIE GEN1/PCIE GEN2 33MHZ
PCI_CLK2
PCICLK2
STRAPS 33MHZ
SETTING, PCI_CLK3
PCICLK3
UNUSED 33MHZ
CLOCKS PCI_CLK4
PCICLK4
33MHZ
LPC_CLK0
EC/STRAPS SETTING :EC ENABLE LPCCLK0
33MHZ
LPC_CLK1
STRAPS SETTING, LPCCLK1
33MHZ
CLOCKS ENABLE
RTCCLK
SPI ROM & HEADER

SPI_CLK
xxHZ
SPI_CLK AMD SB820M GPP_CLK2P/N
SB_PCIE_PE2_CLKREQ#
MINIPCIE SLOT (SB800, 1 LANE)
100MHZ PORT2:WIFI
AZ_BIT_CLK CLOCK GENERATOR CLK_REQ2 in SB
HD AUDIO AZ_BITCLK
PCIE_LAN_CLKP/N
24MHZ
GPP_CLK3P/N PCIE GPP I/F (RS880M, 1 LANE)
100MHZ JMC261
CLK_REQ3 in SB
25M Hz
A A
FOR MASTER FOR RTC FOR SATA
25M Hz 32.768K Hz 25M Hz

DNI Bitland Information Techonogy Co.,Ltd.
Title
CLOCK DISTRIBUTION
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
Thermal Systems
(Emergency Shutdown, Throttling, Fan Control)
1.5V TSI translate 3.3V TSI KBC

SMSC
G7
THERMTRIP_L translate THERMTRIP#
SID SDA3 (S5-S0)

D D
SIC SCL3
T7
ALERT_L TALERT# (S0)
translate
Y9
FANOUT2
SMBus Block Diagram

translate
MEMHOT_L
THERMDC
THERMDA
W18 AMD AMD
AA18 SDA0
VRM Power
SCL0
SB800 SB800
VRM_HOT#
AMD NON-POP
(S5-S0)
DUAL_SMB1 SDATA1
(master)
B6 SDA1
TEMPIN0 TEMPIN1 A6 (S5-S0)
S1G4 C6 TEMP_COMM TEMP_COMM C6
SCLK1 SCL1 ASF Only
F24 SDATA0 SDA0

PROCHOT# (S0)
SCLK0 SCL0
SDA2 (S5-S0) SDA3
PROCHOT_L translate OVERRIDE# DDR 2
M8 SCL2 (S5-S0) 1.8V SCL3
PWM FANOUT0 SO-DIMM
P5 FANIN0
TACH J401
TEMPIN3 AMD
TEMPIN2
translate
J4
GEVENT4# mini DDR 2 S1G4
SDA2
SCL2
PCI Exp x1 SO-DIMM
NON-POP
MPCIE1 J402
4-PIN CPU FAN mini MAX17009

SIC SVC (S3-S0) SVC
PCI Exp x1 CLK. Gen. CPU Core PWR PWM
MPCIE2 SID SVD SVD
9LRS4880 U2800
Place under DDR
U800
NON-POP
ADM TEMP
C 1032 SENSOR C
(Q600)
J106
SO-DIMM
EVENT
translate
SDA
SCL ADM
THERMDC AMD
1032 THERMDA
RS880
MXM
THERM# CPU Thermal

Sensor
NOPOP
ADM1032 EC
MAX1535
Thermal disaster prevention is implemented by PROCHOT_L and THERMTRIP_L with hardware battery charger
BAT_DAT
BAT_CLK
POP
(S5-S0) SMCLK0
SMDAT0
(S5-S0)
POP U2700
non-system dependant functions. Fan speed control will only be implemented GPU Thermal
Sensor U103
U8 (master)
by SB TSI software based implementation
3.3V SB-TSI SMCLK1 (S5-S0)
SMDAT1
KBC1100L
B
Power State / Voltage Rail Activity Summary B
Processor
Global Sleep Description RTC ALW DUAL SUS RUN
System Power
State State
State
G0 S0 C0 Running ON ON ON ON ON
G0 S0 C0 Running P-state transitions ON ON ON ON ON

under OS control
G0 S0 C1 Halt ON ON ON ON ON
Stop grant,
G0 S0 C2 caches snoopable ON ON ON ON ON
G0 S0 C3 TBD ON ON ON ON ON
Group Name Description
G0 S0 c4 TBD ON ON ON ON ON
INT: Stuff when use internal clock generator
G1 S1 OFF Powered on suspend ON ON ON ON ON EXT: Stuff when use external clock generator
DNI/NC: DO NOT INSTALL
G1 S3 OFF Sleeping Suspend to RAM ON ON ON ON OFF KBC: Stuff when use external KBC
IMC: Stuff when use internal EC
A
G2 S4 OFF Suspend to diskON ON ON ON OFF OFF
A11:Resistors marked with "A11" is only for SB800A11 ONLY. A
G2 S5 OFF Soft-off ON ON ON OFF OFF
G2/G3 S5 LOW OFF Battery IN ON ON OFF OFF OFF Bitland Information Techonogy Co.,Ltd.
Title
G3 OFF Mechanical off ON OFF OFF OFF OFF MISCELLANEOUS TABLES
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
VMB
1
@ PC149
@ PC150
nc_0.1u_0402_50V7K
AD_6251+ nc_2200P_0402_50V7K
2
PR11 1 8.2K 2 R0402 PR9 1 20K 2 R0402 PR10 1 10 2 R0402 PFB1
AD+ 100ohm@100MHz,3A
VPJ1 1 2 PF2
DC JACK 5P 1 2 7A
PCN1 VPFB1
PC2
FB0805 FUSE1206
VMB
as BM5910 VPF1 100ohm@100MHz,3A 1 2 ALW_EN ALW_EN 13 PFB3 100ohm@100MHz,3A 1 2
7A fb0805 PQ34 1 2
5
SHLD2 AD+
1 1 2 5A 1 2
0.1uF/25V,X7R
AO4419
BATT+ PF1
VPFB2 PQ48 SO8_50_150 FB0805 7A
C0603 bat_bp02071-p5651-7f
4
4 1206 100ohm@100MHz,3A
SHLD1 AO4419 8A PFB2 100ohm@100MHz,3A FUSE1206
8A C10376-10701-B
2
fb0805 SO8_50_150 PD7 5 1 2 1 2
3 PD13 1 2 1 8 1 2 5A 1 PR65 2 3 8A 6 8A FB0805 BATCON2
AD-2
AD-1
2
D SSM34PT VPFB3 2 7 2 7 @ PC140
@ PC141 D
NC_10U_1206_25V6M
NC_10U_1206_25V6M
NC_10U_1206_25V6M
SMA 100ohm@100MHz,3A 3 6 SBM54PT 0.015_1W_F 1 8 PC25
nc_0.1u_0402_50V7K
1
fb0805 PC24 5 SMA 1608 nc_2200P_0402_50V7K 1
PC253
PC255
PC256
S 1000P_0402_50V7K
1
2
1
PC23 PR131 D PD8 PC193 PD4 2 8
2 GND
1
100P_0402_50V8J 1000P_0402_50V7K PC116 100K G 1 2 470pF/50V,NPO 2 1 SM_BAT_SCL 3
3
2
PC22 PC21 0.01UF/25V,X7R R0402 C0603 49 BAT_DAT PR205 100 SM_BAT_SDA 4
4
1
1000P_0402_50V7K 100P_0402_50V8J C0402 SBM54PT PC3 SSM34PT 49 BAT_CLK 100
R0402 5
5
2
2
SMA 0.1uF/25V,Y5V SMA PR206 R0402 6
PR142 C0402 7 6 9
7 GND1
2
51K
R0402
Isense_SYSP PC184 PC185
49 EC_V3.3AL
1
PC192 PC191 5.6pF/50V,NPO
5.6pF/50V,NPO
1000pF/50V,NPO NC_100pF/50V,NPO Isense_SYSN +VIN C0402 C0402
C0402 C0402 PR133
2
51K
R0402
49 EC_V3.3AL PR132 1 8 8A PR207
51K 2 7 300K
R0402 3 6 R0402 PR208
5 BAT_INT# 49
1
PQ41 PC44PC18 PC43 PC7
PR15 PQ42 AO4419 NC_2200pF/50V,X7R
NC_0.1uF/25V,X7R
NC_0.1uF/25V,X7R
0.01uF/25V,X7R R0402 1K
4
3
3
51K PQ47 2N7002 SO8_50_150 C0402C0402 C0402 C0402
2
PQ49 2N7002 SOT23
R0402 49 EC_V3.3AL
PR47 2N7002 SOT23 del BAT_OV# PR14 1 510K 2 R0402
1
1K SOT23 1 1 1 49 EC_V3.3AL
49 ACOFF#
R0402
49 ACIN 1 2
2
PZD2 PZD1
2
2
2
PR140 PR12 2 2
2
1
PC9 PR48 4.7K PR16 0R
nc_0.1U_0402_16V7K
nc_0.1U_0402_16V7K
1
1
PR41 1000pF/50V,X7R R0402 PC135 3 SM_BAT_SCL 3 SM_BAT_SDA
PC26
PC27
51K 510K R0402
20K C0402 R0402 C0402 R0402
1
R0402 1000pF/50V,X7R @ 1 @ 1
2
1
3
PQ33 BAT54S BAT54S
2N7002 sot_23 sot_23
1 SOT23
3
PQ53
2
2N7002
2
1 SOT23
49 SHDN
1
PR21 PC8
Isense_SYSP 510K 1000pF/50V,X7R
2
R0402 C0402
2
1
1
1
PC134 PC137 PC10 PC117 PC136
0.01uF/25V,X7R 0.01uF/25V,X7R 0.01uF/25V,X7R 100pF/50V,NPO 1000pF/50V,NPO
C C0402 C0402 C0402 C0402 C0402 C
2
2
PU11
1uF/10V,X7R
PC127 1 2 C0603 VDDP 15 2 1 2
VDDP ACSET
1
R0402 PR172
0R
4.7
1
R0402 PC128
1uF/10V,X7R PR173 0.1uF/25V,Y5V
PC108 1 2 C0603 1 C0402 AD_6251+
VDD
2
24 6251_DCIN 1 2 1.5A Isense_SYSN

5V_internal_LDO DCIN PR212
0R
1
Isense_SYSP 19 R0402 PC148 PC142 PC144
CSIP
5
1000pF/50V,X7R 0.1uF/25V,X7R 10uF/25V,X7R
1
PC143 C0402 C0603 C1206

D
2
0.1uF/25V,Y5V PQ57
Isense_SYSN 1 2 C0402 20 17 1 2 4 AO4468
CSIN UGATE
2
PR175 PR176 PAK1212-8

G
10 0R
S
R0402 1000pF/50V,X7R R0402 PL3

3
2
1
PC130 1 2 C0402 10uH/4A/68mOHM

1
5 16 2 1 VDDP R0402
5600pF/50V,Y5V ICOMP BOOT 1 2
PC146 1 2 C0603 PD32 10K MHCI06030
PR177 12.6V
1
PC126 1N4148WS PL11

0.01uF/25V,X7R 0.1uF/25V,Y5V SOD323 nc_10uH/4A/68m BATT+
2
1 2 PC131 1 2 C0402 6 C0402 LS2_1040

VCOMP VBATS1
2
PR186
10K 18 phase phase 2A 1 2 1 2A 2 2A 1
PHASE
2
R0402 PR37 PR179 TPC60

5
NC_15.4K,1% PR49 50mOHM,1% NC_TestP
1
PR40 1 R0402 2 11 4.7F PC147 R1206 PC138 PC145
D
49 CHGVADJ VADJ
NC_31.6K,1% PQ58 0603 4.7uF/25V,X7R 10uF/25V,X7R 10uF/25V,X7R
1 R0402 2 PR32 14 4 AO4468 C1206 C1206 C1206
LGATE
21
2
10K PAK1212-8
G
PC41
1 R0402 2 3
S
49 CHG_ON EN 680P_50V_M_B
0402
3
2
1
1
2
B PR39 13 B
1 2 100K PGND
R0402
1 2 PC132 9
49 SET_I CHLIM
PR180 NC_0.01uF/25V,X7R 21 1 2
CSOP
1
+VIN
1
6.98K,1% C0402 PR181

AD+
1
R0402 PC129 2.2

R0402 1uF/10V,X7R R0402
15.4K,1%
2.39V_Vref8 C0603 1 1
VREF
2
PR182 22
CSON
2
SOD323 SOD323
1
R0402 1N4148WS/LMDL914T1G_SOD323-2~D 1N4148WS/LMDL914T1G_SOD323-2~D

10
20K_F ACLIM D88 D94
PR183 PC31
4 1 2 VDDP BATT-OVP=1/9*BATT+
0.1 Vref 23
CELLS PR36 CELLS CELLNUMBER 2 1 2 2 BATT+
2
NC_0 LI-3CELLS:13.5V----BATT-OVP=1.5012V
ACPRN R0402 CELL PIN 4 VDD
0.01UF/25V,X5R
1
R0402 7 1 2 ADC1 49 1 2 CELL PIN 3 GND VCC_358 LI-4CELLS :18.0V----BATT-OVP=2.001V

ICM PR184 PR35 C0402
10.5K_F CELL PIN 2 FLOAT
1
100 0R
PR185
1
1
R0402 PC133 R0402 PR50
12 3300pF/50V,X7R PR54 133K,1%
GND
2
C0402 133K,1%
Layout note: R0402
2
R0402
2
Far away from critical signal trace
2
ISL6251HAZ
1
SSOP24_25_150
1
PR51
PQ6 PR55 931K,1%
AD_6251+ NC_TP0610K-T1-E3_SOT23-3
931K,1% PU27B R0402
R0402ECADC LM358DT_SO8
2
8
3 1 6251_DCIN 100mV/25m ohm=4.0A. ECADC PR53
2
8
PU27A 5 PBATT_OVP
PR56
P
+
1
R0402 LM358DT_SO8 3ADPT_OUVP_DET 49 BATT_OVP 1 2 7
P
+ 0
NC_100K,1% Iaclim=1/PR8*(0.05*Vaclim/Vref+0.05) 49 ADAPT_OUVP 1 2 1
0 -
6
G
2
PR215 - 10K,1%
1
10K,1%
4
R0402
1
SET_I PR52 PC30
2
4
R0402 PR57 133K,1% 0.01UF/16V,X5R
2
PR266 1 2 NC_100K,1% 133K,1% R0402 C0402
2
0V 0A ADAPT_OUVP=1/9*AD+ R0402
2
R0402 ADAPT_OUVP_R BATT_OVP_R
2
1
0.66V 400mA Input OVP : 22.3V

PQ5 SOD323
NC_DTC115EUA_SC70-3 NC_1N4148WS
Input UVP : 17.26V
PD36
2 2 1 3.3V 2A
CHG_ON 49
A 2 1 A
SLP_S3# 9,11,27,40,49,51
ICHG=165mV/PR179*(VCHLIM/3.3V)
3
PD34
NC_1N4148WS
SOD323

Title
ADP IN/BATTERY CHARGER
D 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
Offset & VIN3
8
7
6
5
OFS/VFIXEN SVI VFIX +VIN
Droop PJP36
D
GND O O X PQ59 1 2
AO4468 4 UGATE_NB
1
CPU_VDDNB_RUN SO8_50_150 PAD-OPEN 4x4m
10U_1210_25V
10U_1210_25V
G
+3.3V X X O
C62
C64
S
PJ2 VDD_NB PL8
+5V X O X 4A
1
2
3
2
2 1 1 2 PHASE_NB
2 1
JUMP_43X118 2.2UH +-20% 8A 20mo PQ55
R249 R252 AO4468
8
7
6
5
0R 47
Metal VID Codes 2 1 2 1 SO8_50_150
D
330U_2.5V_R9mOHM
16 CPU_VDDNB_RUN_FB_H
1
1
4 LGATE_NB
10U_0805_10V
SVC SVD Output +
PC215
C73
G
0 0 1.1
S
R253
2
47
2
1
2
3
0 1 1.0 2 1
+5V
1 0 0.9 R267
10
1 1 0.8 1 2
D Updata on rev:1.1 CPU_VDD_RUN D
1 R270
0R VIN2 +VIN
C372 2 1 VIN1 PJP34
CPU_VDDNB_RUN_FB_L 16 1 2
VFIXEN VID Codes 1U
2 PJP35
X7R
2
1
PAD-OPEN 4x4m2
0.22uF_6.3V
SVC SVD Output 10V
1
1 Parallel
R144 PAD-OPEN 4x4m
180P
C26
C63
C71
10nF
0 0 1.4
1
22K_1% C374
0 1 1.2 R186 1000P
10 2
X7R
2
1 0 1.0 1 2
+VIN 25V
1 1
1 1 0.8 1
C376C375 CPU_VDD_RUN
C377 33P 1200P
2 2
1
0.1U X7R X7R
2
1
X7R R137 LGATE_NB
25V 25V
R145 VIN1
25V 11.5K_1%
44.2K_1% 1 1
2
PHASE_NB
10U_1210_25V
10U_1210_25V
10U_1210_25V
22uF_0805_6.3V
22uF_0805_6.3V
22uF_0805_6.3V
22uF_0805_6.3V
2
C378 C379
C66
C68
C69
1
2
CPU_VDD_RUN
C31
C43
C49
C44
2200P 0.01u
2 2
1
UGATE_NB C371 X7R X7R
0.22U PQ31 2 2 2 2 2 2 2 2 2 2
+3.3V +5V 2 UGATE_0 4 25V 25V
X7R
C389 C338 C340 C382 C383 C384 C385 C386 C387 C388
49
48
47
46
45
44
43
42
41
40
39
38
37
R199 25V
1
0R U2 SIR462DP-T1-GE3 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
2 1 R256 1 1 1 1 1 1 1 1 1 1
Panasonic X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R
GND
VIN
VCC
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
1
2.2 0.36UH_PCMC104T-R36MN1R17_30A_20%
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
3
2
1
R251 ETQP4LR36WFC LS2_1040 CPU_VDD_RUN
R142
10K 100K 1 2
2
2 1 1 36 PL15
OFS/VFIXEN BOOT_NB
1
PR2272.2_5%
330U_2.5V_R9mOHM
330U_2.5V_R9mOHM
R250 R257 C362
2
5
0R 1 1
2 1 2 35 1 2 2 1
10,51 VRM_PWRGD PGOOD BOOT_0 2.2 + + Updata on rev:1.1 for esd
PC217
PC218
680P_50V8J
R223
0R
0.22U
2
2 1 3 34 UGATE_0 PQ35 PQ37 1
16 CPU_PWRGD_SVID_REG PWROK UGATE_0 X7R 2 2
Pin 49 is GND Pin 4 LGATE_0 4
R246
0R 25V C1931
2 1 4 33 PHASE_0 SIR466DP-T1-GE3 SIR466DP-T1-GE3
16 CPU_SVD SVD PHASE_0 2
R247
0R ISP_0
3
2
1
3
2
1
2 1 5 32
16 CPU_SVC SVC PGND_0 +5V ISN_0
R248
0R
16,17 VDDA_PWRGD
2 1 6
ENABLE
ISL6265_QFN_48 6x6 LGATE_0
31 LGATE_0
C
49 VRM_RUN_EC
0.7 - 1.3 V 36A C
R2890 0RDNI 2 1 2 1 7 30 2 1
C180 4700P RBIAS PVCC
2 1 1 2 R47 R86 C61 VIN2
34.8K_1% 82.5K_1% 8 29 LGATE_1 2.2uF_X7R
OCSET LGATE_1
1
255 R87 X7R
10U_1210_25V
10U_1210_25V
10U_1210_25V
1 1
16V
C77
C74
C75
2 1 9 28 C380 C381
VDIFF_0 PGND_1
2
2200P 0.01u
1K_1% R88 PQ32 2 2
X7R X7R
10 27 PHASE_1 UGATE_1 4
FB_0 PHASE_1 25V 25V
C189 1200P SIR462DP-T1-GE3
2 1 1 2 11 26 UGATE_1
COMP_0 UGATE_1 Panasonic 0.36UH_PCMC104T-R36MN1R17_30A_20% CPU_VDD_RUN
C361
3
2
1
54.9K_1%R89
54.9K_1%R89 C233 X7R R136 2.2 ETQP4LR36WFC LS2_1040
1 216V 2 1 12 25 2 1 2 1 1 2
180P VW_0 BOOT_1 PL16
COMP_1
VDIFF_1
X7R 6.81K_1%R90
6.81K_1%R90
VSEN_0
VSEN_1
330U_2.5V_R9mOHM
330U_2.5V_R9mOHM
0.22U
RTN_0
RTN_1
1
16V C275 1000P
ISN_0
ISN_1
ISP_0
ISP_1
VW_1
PR228
2.2_5%
FB_1 1 1
1 2 X7R
25V + +
PC220
PC221
X7R
680P_50V8J
13
14
15
16
17
18
19
20
21
22
23
24
16V PQ39 PQ40
2
LGATE_1 4 LGATE_1 4 2 2
1
RTN_1
change from 16.2k to 16.5k SIR466DP-T1-GE3 SIR466DP-T1-GE3

C1932
ISP_0 2 1 CPU_VDD_RUN
2
3
2
1
3
2
1
1
Close to 16.2K_1%R91
16.2K_1%R91 2
CPU_VDD_RUN R93 ISN_1
R98 CPU socket PH2
100 R139 NC_10K_1% 4.02K_1% C276
1
1 2 2 1 1 2 0.1U 2
1 R131
X7R
2
2
ISN_0 NC_100K_0402_1%_TH11-4H104FT C360 4.02K_1%
22uF_0805_6.3V
22uF_0805_6.3V
22uF_0805_6.3V
22uF_0805_6.3V
16V R266
R111 2 0.1U
0R 1
C45
C48
C52
C50
6.81K_1% X7R
1
2 1 C356 2 1 ISP_1
16 CPU_VDD0_RUN_FB_H 16V
R112 0R 1000P NC_PH3
1
2 1 1 R134 NC_10K_5% R130 16.2K_1%

16 CPU_VDD0_RUN_FB_L X7R
2 1 1 2
16V
R99
100 Parallel 100K_0402_1%_TH11-4H104FT
1 2 ISN_1
Updata on rev:1.1
+1.8V
Close to R170 10K_1%

2 1 RTN_1 2
B
R104 CPU socket
100 B
1 2 2 C344
1200P Fou Uni-plane:
Update on rev:1.1 C277 1
X7R G16,G17,R39:Assembly
4700P 16V 2
1
2
R113 NC_0R X7R R38:Not Assembly

2 1 R128 C345
16 CPU_VDD1_RUN_FB_L 16V
1K_1% 180P
2R120 0R 1 1
16 CPU_VDD1_RUN_FB_H X7R
16V
1
2
R109 Parallel
CPU_VDD_RUN 100 R127 R129
1 2 255 54.9K_1%
1
A A

Title
CPU CORE PWR
D 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
+VIN
PJ7
3A
DDR_DCBATOUT 1 2
jump_gap_open_161x54
0.1U_25V_M
+3.3VDual
0603_X5R
1206_X5R
10U_25V_M
1
1
1206_X5R
10U_25V_M
PC74
PC75
PC76
Place these CAPS
close to FETs
2
D D
SIR462DP-T1-GE3
2
D
PR89
PQ29
10K_J PJ8
0402 PR103 4 G NC_1UH +-20% FDV0630-1R0M=P3 12A
+3.3VDual NC_0_F S PL9 1 2
1
0402 1 2 CPU_VDDIO_SUS
1
2
3
1 2 PC77 PL12 jump_gap_open_161x54
VDRAM_PWRGD 49 0.1U_25V_M 1.0UH_11.5x10.4
PJ9
0603_X5R
NC_100P_50V_K
12A
2
1 2 1 2 DDR_OUT1 1 2
1
PR143
0402_NPO
1
NC_10K_J jump_gap_open_161x54
1
PR90
PC78
330U_2V_7.3x4.3
330U_2V_7.3x4.3
0402
2
5
PR97 0R D
SIR466DP-T1-GE3
Iocp=19.6A
1
1
NC_1K_F PU3 D PR91
SIR466DP-T1-GE3
0603
0402 1 11 PR112 3.3_J
PQ30
+ +
PC79
PC81
0.1U_6.3V_K
PGOOD GND
2
1 2 DDR_TRIP 2 10 DDR_BST 0R0603 4 G
0402_X5R
PQ36
49 VDDIO_SUS_EN_EC TRIP VBST 0603
2
1 2 DDR_S5 3 9 DDR_DH 1 2 S 4 G
11,27,46,49 SLP_S5# EN DRVH
2
DDR_VFB 4 8 DDR_LX S
PC80
VFB SW
1
2
3
1
PR92 DDR_RF 5 7 PC82
NC_1U_10V_K
RF V5IN
1
2
3
1K_F 6 DDR_DL 1000P_50V_M
DRVL
0402 1
1
0402
0603_X5R
120K_F
0603_X7R
2
1
TPS51218DSCR +5VDual
PC83
PR93
1
PC84 update on rev:1.1
100K_F
null
4.7U_10V_K
0402
PR94
2
0805_X5R
2
2
R2853
200R
PR98
2 1
R2860 200R
11.5K_F 16 CPU_VDDIO_SUS_FB_H
2
PR96
10K 0402
C 0402 C
1
B B
CPU_VDDIO_SUS
+3.3VDual
2A 1
PU4
6
VIN VCNTL
2 5
1U_10V_K
GND2 NC1
2
PC199
1
3 7
0603_X5R
4.7U_6.3V_K REFEN NC2
1
+3.3VDual R576
PC98
0603_X5R
1
4 8
100K_F VOUT NC3
2
0402 9
GND1
2
2
RT9199GSP_SO8
PR82
3
0603_X5R
1U_10V_K
100K_J +0_75VRUN
2A
1
D Q50A
PC194
0402
2N7002DW-7-F R577 MEM_VTT
PJ10
1
5 G
0.1U_6.3V_K
10U_6.3V_Y
2
S 100K_F 1 2
0402_X5R
0805_Y5V
10U_6.3V_Y
6
PR267
0805_Y5V
0402
4
0R D Q50B jump_gap_open_161x54
PC86
PC87
PC88
2
0402 2N7002DW-7-F
1 2 2 G
7,11,27,40,49,51 SLP_S3# S
A A
NC_1U_10V_K
0603_X5R
1
1
PR268
PC197
1 2
49 MEM_VTT_EN
NC_0 0402
2

Title
CPU MEM PWR
C 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
FB_VCC_NB-1
PC68
Updated on Rev2.0
1
PC67 1U_0402_6.3V6K +5V
1U_0402_6.3V6K R3027
+5VDUAL +5VDUAL NC_56.2K R2965
2
PR87 PR88 NB_VOL_DET: 133K
2.2_0603_1% 2.2_0603_1% R3020
0: 0.95V / 1.1V
3
2 1 1 2 NC_4.7K
+VIN PJ15 1:0.95V / 1.25V Q2912
JUMP_43X118
2 1 R3028 NC_33K 1
2 1 49 NB_VOL_DET
ISL6228_B++ NC_2N7002E
1
@ PC124
@ PC139 PC70 PC69
2
nc_0.1u_0402_50V7K 0.1U_0603_25V7K 0.1U_0603_25V7K R2972
nc_2200P_0402_50V7K NC_56K +5V
2
PJ12
3
D JUMP_43X118 PR106 PR110 D
2 1 10_0603_1% 10_0603_1% R2966 Q2908
2 1
ISL6228_B+ ISL6228_B++
2 1 2 1
ISL6228_B+
47K
1
C2946 2N7002E
3
100nF
2
DNI
22K_0402_1%
2
1000P_0402_50V7K
PR188 1 Q2917
23 STRP_DATA
2
0_0402_5% PR115 R2953 0
1
+1.2V_PWRGD 1 2 18.2K_0402_1% 2N7002E
PR108
2
2
1
PC72 PR104 PC71
1000P_0402_50V7K 3.3K_0402_5% PR107 1000P_0402_50V7K R2958
PC73
2
1
2 1 1 2 60.4K_0402_1% 2K
2
<BOM Structure>
1
PR95
1
35K_0402_1%
FB_VCC_NB 2 1 FB_VCC_NB-1 29
PGOOD1
FSET1
VIN1
VCC1
VCC2
VIN2
FSET2
GND_T
PR99 PC91
R1822
2
PR111 0_0402_5% 3.3K_0402_5% 1000P_0402_50V7K
8.2K_0402_1% 8 28 1 2 1V1DUAL_PWRGD 49,51 PR101 2 1 1 2
FB1 PGOOD2 GPIO Mode Power Shift
1 2 6228_VCC_NBO1 56K_0402_1%
update on rev:1.1 PR114
1
51K_0402_1% STRP_DATA 1 0 PWM
ISL6228_B++ 9 27 FB_+1.1V-1 1 2 FB_+1.1V
VO1 FB2
4.7U_1206_25V6K
4.7U_1206_25V6K
1
PR100
PC104
PC105
RS880M VCC_NB 0.95V 1.1V N/A

20K_0402_1%
PC85 OCSET_VCC_NB 10 26 6228_+1.1VO2 1 2
OCSET1 VO2
2
8
7
6
5
0.033U_0603_50V7K
1 2 PQ23 RS880M VCC_NB
D1
D2
D3
D4
SI4172DY-T1-GE3 0.95V 1.25V

PR102
Vref=0.6V
2
VCC_NB_EN 11 25 OCSET_+1.1V
4 EN1 PU6 OCSET2
VCC_NB 0.95V--1.1V 12A 9.1K_0402_1% G
1UH_18A_20% ISL6228HRTZ-T_QFN28_4X4 +5VDUAL ISL6228_B+ PC102
S1
S2
S3
PJ11 VCC_NBP 68nf_0603_50V7K When JU2903 is installed with a jumper

1
C 2 1 1 2 LX_VCC_NB 12 24 +1.1VDUAL_EN 1 2 C
2 1 PHASE1 EN2
7 1
6 2
5 3
PL17 @PC89
@ PC89 R2954 0R
8
JUMP_43X118 LS2_1040 nc_0.01U_0402_25V7K
4.7U_1206_25V6K
4.7U_1206_25V6K
1
1
PQ22 1 2 @PC92
@ PC92
@ PC123
PC99
PC90
D1
D2
D3
D4
1
5
6
7
8
PC34 SI4168DY-T1-GE3 nc_0.1u_0402_50V7K
+ + PR113 UG_VCC_NB 13 23 PQ25 nc_2200P_0402_50V7K
D4
D3
D2
D1
UGATE1 PHASE2
2
PC33 @ 4.7_1206_5% SI4172DY-T1-GE3
2
4 PR105
G
2
1 2
PR116 15K_0402_1%
220U_6.3V_3528 220U_6.3V_3528 PC97 0_0603_5% 4 +1.1VDUAL
S1
S2
S3
6TPC47MB 6TPC47MB @ 680P_0402_50V7K 2 1 2 1BST_VCC_NB

14 22 UG_+1.1V G PL4
BOOT1 UGATE2 1uH/12A10mOHM +1.1VP
S3
S2
S1
2
1
2
3
1
LGATE1
LGATE2
PC101 PJ13
PGND1
PGND2
BOOT2
PVCC1
PVCC2
0.1U_0402_16V7K S_LX_+1.1V 1 2 2 1
2 1
3
2
1
1
MHCI06030
@ PR109
@PR109 JUMP_43X118
5
6
7
8
4.7_1206_5%
15
16
17
18
19
20
21
1
PQ24
D4
D3
D2
D1
DCR 3.3m ohm(max) Cout ESR=15m ohm SI4168DY-T1-GE3 + +
2
+5VDUAL +5VDUAL PR117 PC96
0_0603_5% 0.1U_0402_16V7K
2
1
+1.05VSP BST_+1.1V1 2 1 2 4 @ PC94
@PC94 PC170 PC172
G 680P_0402_50V7K
Vo=Vref*((PR80+PR82)/PR80)
2
2
CAP_7343 CAP_7343
S3
S2
S1
2
Ipeak=14.02A, Imax=9.81A PC100 PC93 220UF/6.3V/18M 6R3ME221M
1U_0402_6.3V6K 1U_0402_6.3V6K
Iocp=19A
1
3
2
1
220UF/6.3V/18M 6R3ME221M
Csen=L/(Rocset*DCR)
0.015U=1U/(Rocset*6m) Rocset=11.111K~11.8K DCR 6m ohm(max) Cout ESR=15m ohm
LG_VCC_NB LG_+1.1V
Iocp=(Rocset*10uA)/DCR Vo=0.6*((PR87+PR83)/PR83)=1.8V
Iocp=(11K*10uA)/(3.3m ohm*1.3) =15.1A 1.8VP Ipeak=11.93A, Imax=8.351A
update on rev:1.1 Csen=L/(Rocset*DCR)=1uF/(Rocset*6m ohm)=0.022uF
During Power Up =>Rocset=7.575K, Choose 10K because of thermal factor
@ PR178 +1.1VP
VCC_NBP 10K_0402_5%
1 2 VCC_NB_EN
0 < 3.3v - 1.8v < 2.1v Iocp=(Rocset*10uA)/DCR=(10K*10uA)/(0.006*1.3)=12.82A
8,51 VRM_PWRGD
+3.3V
1
1
1
B @PC95
@ PC95 @PC109 @PC110
@PC110 @PC112 @PC113 B
NC_0.1U_0402_16V7K NC_10U_0805_16V7K @PC103
@PC103 0.1U_0402_16V7K NC_10U_0805_16V7K
NC_10U_0805_16V7K
2
2
0.1U_0402_16V7K R2996
2
47K +5VDUAL
<DEVICE> <DEVICE> <DEVICE>
RB751V-40 D2910
1 2 +1.1V_EN
8,51 VRM_PWRGD
R2987
49 1V1_EN_EC 0R DNI R2924 10k
+5VDUAL
VLDT 1.1V 2A +1.2V_PWRGD 51
3
+1.1VDUAL +1.1V R2982 Q2909
10k
1
2N7002E
3
U64
2
+5VDUAL 5 R2981 1k 1 Q2941
6 3 MMBT3904
7 2 1 1
2
1 1 8 1 C2146 C2144
2
VLDT +1.1V C2147 C2177

R1794 10U_0805_10V4Z
100K_0402_5% PJ20 10U_0805_10V4Z SI4168_SO8 2 2
1U_0603_10V4Z
2 1 2 2
10U_0805_10V4Z
2 1
1
JUMP_43X118
VLDT_PWRGD#
6
+VSB
2 1 VLDT_GATE
@ PR189 R1802
1K_0402_5% Q3638A 200K_0402_5% 1
3
+1.1V_EN 1 2 2 C2145
2N7002DW-T/R7_SOT363-6
1
Q3638B 0.1U_0603_25V7K
1
R1801 VLDT_PWRGD#5 2
2N7002DW-T/R7_SOT363-6
100K_0402_5%
4
2
A A

Title
1V1DUAL/VLDT/VCC_NB/+1.1V
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
+5VDUAL
R2975 10
1
@PC164
@PC164
1U_0402_16V7K
2
+3.3VDUAL
1
D D
1
R1819
1
10K_0402_5% R1811
6
NC_1K_0402_5% U2904 @PC188 <DEVICE>
22U_1206_6.3V
VCNTL
2
2
51 1V8_PWRGD
R2974 0R 7
POK VIN
5
1A
2
+1.8VP +1.8V
PJ25
3 2 1
APL5912 VOUT1 4 2 1
VOUT R1810
1
7,9,27,40,49,51 SLP_S3#R2983 1K 8 PC190 JUMP_43X118
GND
EN
vin1
2 1
15K_0402_5%2 @ @PC187
@ PC187
<DEVICE>
FB NC_0.1U_0402_16V7K
22U_1206_6.3V
PC162
2
1
1
1
9
1
PC189 R1827 R1809 1 2
@ 10K_0402_5% 12K_0402_5%
1U_0402_16V7K
68P_0402_16V7K
2
@
update rev:1.1 update rev:1.1
+5VDUAL
R2988
10k
R2989 0
+5VDUAL 1V5_PWRGD 51
+5DUAL TO +5V
3
PQ3 +VSB
+5VDUAL +5V CPU_VDDIO_SUS +1.5V R2977 Q3048 TP0610K-T1-E3_SOT23-3
10k +VSBP
1 +VIN PJ14
2N7002E 3 1 2 1
2 1
4
3
U61 U62
nc_0.22U_1206_25V7K
2
5 5 R2976 1k 1 Q2940 JUMP_43X118
nc_0.1U_0603_25V7K
1
6 3 6 3 MMBT3904
1
7 2 7 2 PR29
PC16
PC17
1 1 1 1
2
1 1 8 1 C2132 C2133 1 1 8 1 C2136 C2134 100K_0402_1%
C2130 C2131 C2135 C2143 @ @
2
10U_0805_10V4Z 10U_0805_10V4Z PR31
2 2 2 2
2
10U_0805_10V4Z SI4800BDY-T1-E3_SO8 1U_0603_10V4Z 10U_0805_10V4Z SI4800BDY-T1-E3_SO8 1U_0603_10V4Z 22K_0402_1%
C 2 2
10U_0805_10V4Z 2 2
10U_0805_10V4Z 1 2 C
+VSB 2 1 5V/3.3V_GATE +VSB 2 1 +1.5V_GATE
3
R1795 R1796
200K_0402_5% 1 200K_0402_5% 1 PR34 Q3049
6
3
C2137 C2138 0_0402_5%
13,49 V3V5DUAL_PWRGD 1 2 1
Q31A NC_0.1U_0603_25V7K Q30B 0.1U_0603_25V7K 2N7002E
SUSP 2 2
2N7002DW-T/R7_SOT363-6 1V8_PWRGD# 5 2
2N7002DW-T/R7_SOT363-6
0.22U_0402_16V7K
2
1
PC19
update on rev:1.1
1
4
@
2
+5VDUAL
Updata on rev:1.3
+3VDUALTO +3.3V
2
+3.3VDUAL +3.3V R1792
100K_0402_5%
4
U63
1
5
6 3 1V8_PWRGD# +1.5VDUAL
7 2 +3.3VDUAL
1 1
6
1 1 8 1 C2139 C2140
C2141 C2142
10U_0805_10V4Z Q30A
10U_0805_10V4Z SI4800BDY-T1-E3_SO8 2 2
1U_0603_10V4Z 2 PU10 APL5312-15B_+1.5V PJ17
2 2 51 1V8_PWRGD
10U_0805_10V4Z 2N7002DW-T/R7_SOT363-6 1 5 2 1
VIN VOUT 2 1
1
2
1
1
R1797 PC121 1 2 3 4 JUMP_43X118 D47
100K_0402_5% NC_10uF/6.3V,X5R_+1.5V SHDN# BP
NC_1N5819
C0805 PR151 GND
SOD123
1
5V/3.3V_GATE NC_10K,5%_+1.5V PC122
2
1
2
2
R0402 NC_1UF/16V,X7R_+1.5V
C525 C518 C0402
2
NC_0.01uF/10V,X7R_+1.5V NC_0.01uF/10V,X7R+1.5V
1
C0603 C0603
FOR SB820M 15MA DEL +1.5V LDO

B B
CPU_VDD_RUN CPU_VDDNB_RUN +3.3V +5V MEM_VTT
R3058 R3040 R3064 R3061 R3062

100R 100R 100R 100R 100R
+3.3VDUAL
3
+5VDUAL CPU_VDDIO_SUS
Q3040 Q3033 Q3032 Q3034 Q3037
R3055 SUSP 1 1 1 1 1
100K 2N7002E 2N7002E 2N7002E 2N7002E 2N7002E R3057
100R
2
2
3
3
Q3041 R3056
100K Q3035
1
7,9,27,40,49,51 SLP_S3#
2N7002E 1
2N7002E
2
VCC_NB VLDT +1.5V +1.8V CPU_VDDR +1.1V
2
Q3036
R3063 0R1 C3011

9,27,46,49 SLP_S5#
C3013 R3053 2N7002E 100nF
100nF 100R R3059 R3060 R3065 R3050 R3066
2
100R 100R 100R 100R 100R
3
Q3030 Q3039 Q3038 Q3031 Q3029 Q3042
1 1 1 1 1 1
2N7002E 2N7002E 2N7002E 2N7002E 2N7002E 2N7002E
2
A A

Title
1.5V/1.5VDUAL/1.8V/3.3V/5V
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Title
//
C 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
+3.3VALW Update on rev:1.1
Vo1=5.01V ;Vo2=3.3V
REF
D NOTE: H---> 5v D
+3VALWP +5VALWP
R538 R539
L---> 4.65V
NC_0 0R
R526 R0402 R0402 R525 R527
NC_110K,1% R543 C731 C656 R540 NC_220K,1% NC_10K ,5%
13K,1% 220pF/50V,X7R 220pF/50V,X7R 30.1K,1% R0402 R0402
R0402 R0402 C0402 C0402 R0402
3
ADD RESISTOR TO GET -5% LOWER FOR +3.3V(3.1626V) VFB2 VFB1 NC_0R R3024 SMARTVOLT2 27
Q2931
PR24EN V3AL PR25EN V5ALR520
R518 20K,1% 1
20K,1% R0402 NC_2N7002E C2979
R0402 NC_100nF
2
EN_V3AL_TPS51125
EN_V5AL_TPS51125
PR24 C186 PR26
147K 1uF/25V,X5R 147K
R0402 C0805 R0402
VDC_TPS51125 +VIN .
REF
PJ26 +3.3VDUAL VDC_TPS51125
1
1 2 R1813
1 2 +3.3VALW 0R
VREF
ENTRIP2
VFB2
TONSEL
VFB1
ENTRIP1
R0402
JUMP_43X118
1
25
7 GND1 R504 C366 C363 PC111
C659 VO2 100K 10uF/25V,X7R
1000PF/50V,NPO 0.1uF/25V,X5R
2
1
PC125 C691 C663 4.7uF/10V,Y5V 24 R0402 . . C1206

10uF/25V,X7R 0.1uF/25V,X5R 1000PF/50V,NPO C0805 8 VO1
C1206 C0402 C0402 VREG3 C0402 C0402
2
C . . 23 C
PGOOD V3V5DUAL_PWRGD 11,49
8
7
6
5
2 1 9
C657 PR44 VBST2
D
5
6
7
8
PQ50 0.1uF/25V,X7R0R U31 22 1 PR45 2 C184 PQ51
AO4468 4 C0603 0603 10 VBST1 0F 0.1uF/25V,X7R AO4468 Iocp=9.7A
D
SO8_50_150 DRVH2 UP6182AQAG/TPS51125 0603 C0603 SO8_50_150
G
21 4
S
Iocp=10.8A 11 DRVH1 .
G
LLS
1
2
3
S
R541 20
LL1
3
2
1
10K 12 R542 PL2
PL1 R0402 DRVL2 10K 4.7uH/5.5A/15mOHM +5VDUAL
+3.3VDUAL PJ4 +3VALWP 19 R0402 +5VALWP PJ3
2 1 +3VALWP 1 2 DRVL1 1 2 2 1
2 1 4.7uH/5.5A/15mOHM MHCI06030 2 1
JUMP_43X118 MHCI06030 JUMP_43X118
SKIPSEL
VREG5
2
2
Lay
VCLK
GND
EN0
PR42
VIN
PR43
8
7
6
5
5
6
7
8
4.7F PD16 4.7,1%
1
1
0603 NC_1N4148WS 0603
D
D
13
14
15
16
17
18
+ SOD323 PD14 +
1
1
4 +5VALW 4 NC_1N4148WS
G
SOD323
G
1
1
2
2
PQ52
2
PC156 PQ38 PC157
S
S
220UF/6.3V/18M 6R3ME221M PC39 AO4468 AO4468 220UF/6.3V/18M 6R3ME221M

1
2
3
3
2
1
SO8_50_150
2
CAP_7343 680P_50V_M_B SO8_50_150 PC37 CAP_7343
1
0402 R522 R505 R521 680P_50V_NPO

NC_620K 0R NC_10K C185 C187 0402
Lay
1
R0402 R0402 1uF/25V,X5R 10uF/25V,X5R
C0805 C0805
. .
REF
+VIN
+5VALWP
B B
+3VALWP
C370 C368 C369 C761 C665

0.1uF/25V,X5R 0.1uF/25V,X5R 0.1uF/25V,X5R 0.1uF/25V,X5R
0.1uF/25V,X5R
C730 C367 C364 C365 C729 C0402 C0402 C0402 C0402 C0402
0.1uF/25V,X5R 0.1uF/25V,X5R 0.1uF/25V,X5R 0.1uF/25V,X5R 0.1uF/25V,X5R . . . . .
C0402 C0402 C0402 C0402 C0402
. . . . .
+5VALW
+5VALW
EN_V5AL_TPS51125 EN_V3AL_TPS51125
PR30 PR38
100k PQ56 PQ62 100k
3
3
R0402 2N7002 2N7002 R0402
SOT23 SOT23
49 VDD_DUAL_EN PD9 1 1N4148WS 1 1

SOD323 PR46
R0402 PQ60 PC20 PC28 PQ63
2
2
3
3
10 2N7002 NC NC 2N7002
7 ALW_EN PD10 1 1N4148WS EN_V5AL EN_V3AL SOT23 C0402 C0402 SOT23
SOD323 PC29
1
PR33 1000pF/50V,X7R EN_V5AL 1 1EN_V3AL

PJ1 100K C0402
A JOPEN R0402 A
2
2
RESISTOR_1
ns
2
Add Enable/OCP Circuit 090918

Title
SYSTEM PWR
C 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
D
CPU_VLDT 1.1V 1.5A D
CPU_VLDT U100A CPU_VLDT
D1 HT LINK AE2
D2 VLDT_A0 VLDT_B0 AE3
VLDT_A3 VLDT_B3
E3 AD1
21 HT_NB_CPU_CAD_H0 L0_CADIN_H0 L0_CADOUT_H0 HT_CPU_NB_CAD_H0 21
E2 AC1
21 HT_NB_CPU_CAD_L0 L0_CADIN_L0 L0_CADOUT_L0 HT_CPU_NB_CAD_L0 21
E1 AC2
F1 AC3
G3 AB1
G2 AA1
G1 AA2
H1 AA3
J1 W2
K1 W3
21
21
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
L3 L0_CADIN_L4
L0_CADIN_H5
L0_CADOUT_L4
L0_CADOUT_H5
V1
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
21
21
DEL HTPA Soft-Touch Duo Connectors
L2 U1
L1 U2
M1 U3
N3 T1
N2 R1
E5 AD4
F5 AD3
F3 AD5
F4 AC5
G5 AB4
H5 AB3
C H3 AB5 C
H4 AA5
K3 Y5
K4 W5
L5 V4
M5 V3
M3 V5
M4 U5
N5 T4
P5 T3
J3 Y1
21 HT_NB_CPU_CLK_H0 L0_CLKIN_H0 L0_CLKOUT_H0 HT_CPU_NB_CLK_H0 21
J2 W1
21 HT_NB_CPU_CLK_L0 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CPU_NB_CLK_L0 21
J5 Y4
21 HT_NB_CPU_CLK_H1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CPU_NB_CLK_H1 21
K5 Y3
21 HT_NB_CPU_CLK_L1 L0_CLKIN_L1 L0_CLKOUT_L1 HT_CPU_NB_CLK_L1 21
N1 R2
21 HT_NB_CPU_CTL_H0 L0_CTLIN_H0 L0_CTLOUT_H0 HT_CPU_NB_CTL_H0 21
P1 R3
21 HT_NB_CPU_CTL_L0 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CPU_NB_CTL_L0 21
P3 T5
21 HT_NB_CPU_CTL_H1 L0_CTLIN_H1 L0_CTLOUT_H1 HT_CPU_NB_CTL_H1 21
P4 R5
21 HT_NB_CPU_CTL_L1 L0_CTLIN_L1 L0_CTLOUT_L1 HT_CPU_NB_CTL_L1 21
SOCKET_638_PIN
B B
VLDT CPU_VLDT
R183
0.001R_1W
C335 C101 C102 C103 C104 C105 C106

10uF 4.7uF 22uF 220nF 220nF 180pF 180pF
C26 D26 E26 F26 G26 H26 J26 K26 L26 M26 N26 P26 R26 T26 U26 V26 W26 Y26 AA26 AB26 AC26 AD26
Place close to socket A24
A23
B25
B24
B23
C25
C24
C23
D25
D24
D23
E25
E24
E23
F25
F24
F23
G25
G24
G23
H25
H24
H23
J25
J24
J23
K25
K24
K23
L25
L24
L23
M25
M24
M23
N25
N24
N23
P25
P24
P23
R25
R24
R23
T25
T24
T23
U25
U24
U23
V25
V24
V23
W25
W24
W23
Y25
Y24
Y23
AA25
AA24
AA23
AB25
AB24
AB23
AC25
AC24
AC23
AD25
AD24
AD23
AE25
AE24
AE23
AF24
AF23
A22 B22 C22 D22 E22 F22 G22 H22 J22 K22 L22 M22 N22 P22 R22 T22 U22 V22 W22 Y22 AA22 AB22 AC22 AD22 AE22 AF22
A20 B20 C20 D20 E20 F20 H20 J20 K20 L20 M20 N20 P20 R20 T20 U20 V20 Y20 AA20 AB20 AC20 AD20 AE20 AF20
A19 B19 C19 D19 E19 F19 H19 J19 K19 L19 M19 N19 P19 R19 T19 U19 V19 Y19 AA19 AB19 AC19 AD19 AE19 AF19
* If VLDT is connected only on one side,

one 4.7uF cap should be added to A15
A14
B15
B14
C15
C14
D15
D14
E15
E14
F15
F14
G15
G14
H15
H14
J15
J14
K15
K14
L15
L14
T15
T14
U15
U14
V15
V14
W15
W14
Y15
Y14
AA15
AA14
AB15
AB14
AC15
AC14
AD15
AD14
AE15
AE14
AF15
AF14
A13 B13 C13 D13 E13 F13 G13 H13 J13 K13 L13 T13 U13 V13 W13 Y13 AA13 AB13 AC13 AD13 AE13 AF13
A the island side A12
A11
B12
B11
C12
C11
D12
D11
E12
E11
F12
F11
G12
G11
H12
H11
J12
J11
K12
K11
L12
L11 M11 N11 P11 R11

T12
T11
U12
U11
V12
V11
W12
W11
Y12
Y11
AA12
AA11
AB12
AB11
AC12
AC11
AD12
AD11
AE12
AE11
AF12
AF11
A
A8 B8 C8 D8 E8 F8 H8 J8 K8 L8 M8 N8 P8 R8 T8 U8 V8 W8 AA8 AB8 AC8 AD8 AE8 AF8
A7 B7 C7 D7 E7 F7 H7 J7 K7 L7 M7 N7 P7 R7 T7 U7 V7 W7 AA7 AB7 AC7 AD7 AE7 AF7
A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 T3 U3 V3 W3 Y3 AA3 AB3 AC3 AD3 AE3
A1
C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2 V2 W2 Y2 AA2 AB2 AC2 AD2 AE2
C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1 V1 W1 Y1 AA1 AB1 AC1 AD1

BGA638_50_26SQ_S1G3_OEM Notebook R&D Division
Title
S1G4 HT I/F
Custom 1.0
BM5016
5 4 3 2 1
A B C D E
Processor Memory Interface

U100C
MEM:DATA
18 MEM_MB_DATA[0..63] MEM_MA_DATA[0..63] 18
MEM_MB_DATA0 C11 G12 MEM_MA_DATA0
MEM_MB_DATA1 A11 MB_DATA0 MA_DATA0 F12 MEM_MA_DATA1
MEM_MB_DATA2 A14 MB_DATA1 MA_DATA1 H14 MEM_MA_DATA2
4 MEM_MB_DATA3 B14 MB_DATA2 MA_DATA2 G14 MEM_MA_DATA3 4
MEM_MB_DATA4 G11 MB_DATA3 MA_DATA3 H11 MEM_MA_DATA4
VDDR 1.05V 1.75A MEM_MB_DATA5 E11 MB_DATA4
MB_DATA5
MA_DATA4
MA_DATA5
H12 MEM_MA_DATA5
MEM_MB_DATA6 D12 C13 MEM_MA_DATA6
CPU_VDDR U100B CPU_VDDR MEM_MB_DATA7 A13 MB_DATA6 MA_DATA6 E13 MEM_MA_DATA7
PLACE THEM CLOSE TO MB_DATA7 MA_DATA7
MEM_MB_DATA8 A15 H15 MEM_MA_DATA8
CPU WITHIN 1" D10 W10 MEM_MB_DATA9 A16 MB_DATA8 MA_DATA8 E15 MEM_MA_DATA9
C10 VDDR1 MEM:CMD/CTRL/CLKVDDR5 AC10 MEM_MB_DATA10 A19 MB_DATA9 MA_DATA9 E17 MEM_MA_DATA10
B10 VDDR2 VDDR6 AB10 MEM_MB_DATA11 A20 MB_DATA10 MA_DATA10 H17 MEM_MA_DATA11
CPU_VDDIO_SUS AD10 VDDR3 VDDR7 AA10 MEM_MB_DATA12 C14 MB_DATA11 MA_DATA11 E14 MEM_MA_DATA12
VDDR4 VDDR8 A10 MEM_MB_DATA13 D14 MB_DATA12 MA_DATA12 F14 MEM_MA_DATA13
R105 39.2R M_ZP AF10 VDDR9 MEM_MB_DATA14 C18 MB_DATA13 MA_DATA13 C17 MEM_MA_DATA14
R100 0R R106 39.2R M_ZN AE10 MEMZP Y10 CPU_M_VREF_SUS MEM_MB_DATA15 D18 MB_DATA14 MA_DATA14 G17 MEM_MA_DATA15
MEMZN VDDR_SENSE CPU_VDDR_SENSE 17 MB_DATA15 MA_DATA15
MEM_MB_DATA16 D20 G18 MEM_MA_DATA16
C190 H16 W17 MEM_MB_DATA17 A21 MB_DATA16 MA_DATA16 C19 MEM_MA_DATA17
18 MEM_MA_RST# MA_RESET_L MEMVREF MB_DATA17 MA_DATA17
MEM_MB_DATA18 D24 D22 MEM_MA_DATA18
10uF T19 B18 MEM_MB_DATA19 C25 MB_DATA18 MA_DATA18 E20 MEM_MA_DATA19
18 MEM_MA0_ODT0 MA0_ODT0 MB_RESET_L MEM_MB_RST# 18 MB_DATA19 MA_DATA19
DNI V22 MEM_MB_DATA20 B20 E18 MEM_MA_DATA20
18 MEM_MA0_ODT1 MA0_ODT1 MB_DATA20 MA_DATA20
MEM_MA1_ODT0 U21 W26 MEM_MB_DATA21 C20 F18 MEM_MA_DATA21
MA1_ODT0 MB0_ODT0 MEM_MB0_ODT0 18 MB_DATA21 MA_DATA21
Updated on Rev2.0 TP46 MEM_MA1_ODT1 V19 W23 MEM_MB_DATA22 B24 B22 MEM_MA_DATA22
MA1_ODT1 MB0_ODT1 MEM_MB0_ODT1 18 MB_DATA22 MA_DATA22
TP47 Y26 MEM_MB1_ODT0 MEM_MB_DATA23 C24 C23 MEM_MA_DATA23
T20 MB1_ODT0 TP7 MEM_MB_DATA24 E23 MB_DATA23 MA_DATA23 F20 MEM_MA_DATA24
18 MEM_MA0_CS#0 MA0_CS_L0 MB_DATA24 MA_DATA24
U19 V26 MEM_MB_DATA25 E24 F22 MEM_MA_DATA25
18 MEM_MA0_CS#1 MA0_CS_L1 MB0_CS_L0 MEM_MB0_CS#0 18 MB_DATA25 MA_DATA25
TP48 U20 W25 MEM_MB_DATA26 G25 H24 MEM_MA_DATA26
To reverse SODIMM socket

MA1_CS_L0 MB0_CS_L1 MEM_MB0_CS#1 18 MB_DATA26 MA_DATA26
TP49 V20 U22 TP13 MEM_MB_DATA27 G26 J19 MEM_MA_DATA27
MA1_CS_L1 MB1_CS_L0 MEM_MB_DATA28 C26 MB_DATA27 MA_DATA27 E21 MEM_MA_DATA28
J22 J25 MEM_MB_DATA29 D26 MB_DATA28 MA_DATA28 E22 MEM_MA_DATA29
18 MEM_MA_CKE0 MA_CKE0 MB_CKE0 MEM_MB_CKE0 18 MB_DATA29 MA_DATA29
J20 H26 MEM_MB_DATA30 G23 H20 MEM_MA_DATA30
To normal SODIMM socket

18 MEM_MA_CKE1 MA_CKE1 MB_CKE1 MEM_MB_CKE1 18 MB_DATA30 MA_DATA30
MEM_MB_DATA31 G24 H22 MEM_MA_DATA31
N19 P22 MEM_MB_DATA32 AA24 MB_DATA31 MA_DATA31 Y24 MEM_MA_DATA32
18 MEM_MA_CLK1_P MA_CLK_H5 MB_CLK_H5 MEM_MB_CLK1_P 18 MB_DATA32 MA_DATA32
N20 R22 MEM_MB_DATA33 AA23 AB24 MEM_MA_DATA33
18 MEM_MA_CLK1_N MA_CLK_L5 MB_CLK_L5 MEM_MB_CLK1_N 18 MB_DATA33 MA_DATA33
TP50 E16 A17 TP14 MEM_MB_DATA34 AD24 AB22 MEM_MA_DATA34
TP51 F16 MA_CLK_H1 MB_CLK_H1 A18 TP15 MEM_MB_DATA35 AE24 MB_DATA34 MA_DATA34 AA21 MEM_MA_DATA35
TP52 Y16 MA_CLK_L1 MB_CLK_L1 AF18 TP16 MEM_MB_DATA36 AA26 MB_DATA35 MA_DATA35 W22 MEM_MA_DATA36
TP53 AA16 MA_CLK_H7 MB_CLK_H7 AF17 TP45 MEM_MB_DATA37 AA25 MB_DATA36 MA_DATA36 W21 MEM_MA_DATA37
P19 MA_CLK_L7 MB_CLK_L7 R26 MEM_MB_DATA38 AD26 MB_DATA37 MA_DATA37 Y22 MEM_MA_DATA38
18 MEM_MA_CLK2_P MA_CLK_H4 MB_CLK_H4 MEM_MB_CLK2_P 18 MB_DATA38 MA_DATA38
P20 R25 MEM_MB_DATA39 AE25 AA22 MEM_MA_DATA39
18 MEM_MA_CLK2_N MA_CLK_L4 MB_CLK_L4 MEM_MB_CLK2_N 18 MB_DATA39 MA_DATA39
MEM_MB_DATA40 AC22 Y20 MEM_MA_DATA40
3 18 MEM_MA_ADD[0..15] MEM_MB_ADD[0..15] 18 MB_DATA40 MA_DATA40 3
MEM_MA_ADD0 N21 P24 MEM_MB_ADD0 MEM_MB_DATA41 AD22 AA20 MEM_MA_DATA41
MEM_MA_ADD1 M20 MA_ADD0 MB_ADD0 N24 MEM_MB_ADD1 MEM_MB_DATA42 AE20 MB_DATA41 MA_DATA41 AA18 MEM_MA_DATA42
MEM_MA_ADD2 N22 MA_ADD1 MB_ADD1 P26 MEM_MB_ADD2 MEM_MB_DATA43 AF20 MB_DATA42 MA_DATA42 AB18 MEM_MA_DATA43
MEM_MA_ADD3 M19 MA_ADD2 MB_ADD2 N23 MEM_MB_ADD3 MEM_MB_DATA44 AF24 MB_DATA43 MA_DATA43 AB21 MEM_MA_DATA44
MEM_MA_ADD4 M22 MA_ADD3 MB_ADD3 N26 MEM_MB_ADD4 MEM_MB_DATA45 AF23 MB_DATA44 MA_DATA44 AD21 MEM_MA_DATA45
MEM_MA_ADD5 L20 MA_ADD4 MB_ADD4 L23 MEM_MB_ADD5 MEM_MB_DATA46 AC20 MB_DATA45 MA_DATA45 AD19 MEM_MA_DATA46
MEM_MA_ADD6 M24 MA_ADD5 MB_ADD5 N25 MEM_MB_ADD6 MEM_MB_DATA47 AD20 MB_DATA46 MA_DATA46 Y18 MEM_MA_DATA47
MEM_MA_ADD7 L21 MA_ADD6 MB_ADD6 L24 MEM_MB_ADD7 MEM_MB_DATA48 AD18 MB_DATA47 MA_DATA47 AD17 MEM_MA_DATA48
MEM_MA_ADD8 L19 MA_ADD7 MB_ADD7 M26 MEM_MB_ADD8 MEM_MB_DATA49 AE18 MB_DATA48 MA_DATA48 W16 MEM_MA_DATA49
MEM_MA_ADD9 K22 MA_ADD8 MB_ADD8 K26 MEM_MB_ADD9 MEM_MB_DATA50 AC14 MB_DATA49 MA_DATA49 W14 MEM_MA_DATA50
MEM_MA_ADD10 R21 MA_ADD9 MB_ADD9 T26 MEM_MB_ADD10 MEM_MB_DATA51 AD14 MB_DATA50 MA_DATA50 Y14 MEM_MA_DATA51
MEM_MA_ADD11 L22 MA_ADD10 MB_ADD10 L26 MEM_MB_ADD11 MEM_MB_DATA52 AF19 MB_DATA51 MA_DATA51 Y17 MEM_MA_DATA52
MEM_MA_ADD12 K20 MA_ADD11 MB_ADD11 L25 MEM_MB_ADD12 MEM_MB_DATA53 AC18 MB_DATA52 MA_DATA52 AB17 MEM_MA_DATA53
MEM_MA_ADD13 V24 MA_ADD12 MB_ADD12 W24 MEM_MB_ADD13 MEM_MB_DATA54 AF16 MB_DATA53 MA_DATA53 AB15 MEM_MA_DATA54
MEM_MA_ADD14 K24 MA_ADD13 MB_ADD13 J23 MEM_MB_ADD14 MEM_MB_DATA55 AF15 MB_DATA54 MA_DATA54 AD15 MEM_MA_DATA55
MEM_MA_ADD15 K19 MA_ADD14 MB_ADD14 J24 MEM_MB_ADD15 MEM_MB_DATA56 AF13 MB_DATA55 MA_DATA55 AB13 MEM_MA_DATA56
MA_ADD15 MB_ADD15 MEM_MB_DATA57 AC12 MB_DATA56 MA_DATA56 AD13 MEM_MA_DATA57
18 MEM_MA_BANK[0..2] MEM_MB_BANK[0..2] 18 MB_DATA57 MA_DATA57
MEM_MA_BANK0 R20 R24 MEM_MB_BANK0 MEM_MB_DATA58 AB11 Y12 MEM_MA_DATA58
MEM_MA_BANK1 R23 MA_BANK0 MB_BANK0 U26 MEM_MB_BANK1 MEM_MB_DATA59 Y11 MB_DATA58 MA_DATA58 W11 MEM_MA_DATA59
MEM_MA_BANK2 J21 MA_BANK1 MB_BANK1 J26 MEM_MB_BANK2 MEM_MB_DATA60 AE14 MB_DATA59 MA_DATA59 AB14 MEM_MA_DATA60
MA_BANK2 MB_BANK2 MEM_MB_DATA61 AF14 MB_DATA60 MA_DATA60 AA14 MEM_MA_DATA61
R19 U25 MEM_MB_DATA62 AF11 MB_DATA61 MA_DATA61 AB12 MEM_MA_DATA62
18 MEM_MA_RAS# MA_RAS_L MB_RAS_L MEM_MB_RAS# 18 MB_DATA62 MA_DATA62
T22 U24 MEM_MB_DATA63 AD11 AA12 MEM_MA_DATA63
18 MEM_MA_CAS# MA_CAS_L MB_CAS_L MEM_MB_CAS# 18 MB_DATA63 MA_DATA63
T24 U23
18 MEM_MA_WE# MA_WE_L MB_WE_L MEM_MB_WE# 18 18 MEM_MB_DM[0..7] MEM_MA_DM[0..7] 18
MEM_MB_DM0 A12 E12 MEM_MA_DM0
MEM_MB_DM1 B16 MB_DM0 MA_DM0 C15 MEM_MA_DM1
MEM_MB_DM2 A22 MB_DM1 MA_DM1 E19 MEM_MA_DM2
MEM_MB_DM3 E25 MB_DM2 MA_DM2 F24 MEM_MA_DM3
SOCKET_638_PIN MB_DM3 MA_DM3
MEM_MB_DM4 AB26 AC24 MEM_MA_DM4
MEM_MB_DM5 AE22 MB_DM4 MA_DM4 Y19 MEM_MA_DM5
MEM_MB_DM6 AC16 MB_DM5 MA_DM5 AB16 MEM_MA_DM6
MEM_MB_DM7 AD12 MB_DM6 MA_DM6 Y13 MEM_MA_DM7
CPU_VDDIO_SUS MB_DM7 MA_DM7
C12 G13
18 MEM_MB_DQS0_P MB_DQS_H0 MA_DQS_H0 MEM_MA_DQS0_P 18
B12 H13
18 MEM_MB_DQS0_N MB_DQS_L0 MA_DQS_L0 MEM_MA_DQS0_N 18
D16 G16
C16 G15
R107 A24 C22
2 18 MEM_MB_DQS2_P MB_DQS_H2 MA_DQS_H2 MEM_MA_DQS2_P 18 2
1.00K A23 C21
CPU_M_VREF_SUS F26 G22
DEL ACE (margining tool) header E26 G21
AC25 AD23
AC26 AC23
AF21 AB19
AF22 AB20
sensing point for AE16 Y15
R108 C109 C111 op-amp feedback AD16 W15
1.00K 470nF_6.3V 10nF C112 routed near CPU AF12 W12
1nF AE12 W13
PLACE CLOSE TO CPU
SOCKET_638_PIN
CPU_VDDR
Place close to socket
C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 C128
4.7uF 4.7uF 4.7uF 4.7uF 220nF 220nF 220nF 220nF 1nF 1nF 1nF 1nF 180pF 180pF 180pF 180pF
1 1

Title
S1G4 DDRIII MEMORY I/F
Custom 1.0
BM5016
A B C D E
5 4 3 2 1
+5VDUAL
R2990 10
D D
+3.3V
2
@C130
@C130 R1830 Updata on rev:1.2
1U_0402_16V7K 1K_0402_5%
2
PR238
NC_0R R146 CPU_PROCHOT#_VDDIO
CPU_VDDA_2.5_RUN 28 SB_PROCHOT#
1
2 1 0R R293
49 VDDA_EN_EC VDDA_PWRGD 8,17
NC_100_J
4
U2911 LAYOUT: ROUTE VDDA TRACE APPROX. 0R R169
R1829 49 EC_PROCHOT# Update on rev:1.1
PR237 NC_10K_0402_5% 50 mils WIDE (USE 2x25 mil TRACES TO
VCNTL
+3.3V 2 1 2 1 1 2
EN POK EXIT BALL FIELD) AND 500 mils LONG.
+2.5V_LDO R142 and Q110 is DNI, S1G4 does not support MEMHOT_L
UP7717ASU8_PSOP_8 U100D
100_J 3
VIN VOUT
6 800MA FB26 26R_600mA CPU_VDDA_RUN CPU_VDDIO_SUS
R1825 Keep trace from resisor to CPU within 0.6" F8 M11
5 F9 VDDA1 VSS W18 CPU_VDDIO_SUS
GND1
22K_0402_5% keep trace from caps to CPU within 1.2"
GND
NC VDDA2 RSVD11
1
7 1 2 AEP Head C183 C132 C133 C134 C135 3.9NF
FB
1
180pF 4.7UF 220nF 3.3NF CPU_CLKIN_SC_P TP33 A9 A6 CPU_SVC_R R143
100u
+
PC106
PC168 20 CPU_CLKP CLKIN_H SVC
1
<DEVICE> PC207 @ R173 CPU_CLKIN_SC_N TP34 A8 A4 CPU_SVD_R R141 10K
CLKIN_L SVD
9
22U_1206_6.3V R1824 1 2 169R R140 place them under CPU
20 CPU_CLKN
2
1
10K_0402_5% C136 3.9NF LDT_RST# TP41 B7 1K Q108
PWRGD TP42 A7 RESET_L 300R MMBT3904
27P_0402_16V7K LDT_STOP# TP43 F10 PWROK AF6 CPU_THERMTRIP#_VDDIO 2 3
LDTSTOP_L THERMTRIP_L
2
@ Note. LDTREQ_L may be left unconnected as CPU_LDT_REQ#_CPU TP87 C6 AC7 CPU_PROCHOT#_VDDIO
its function is not supported by the s1g4 LDTREQ_L PROCHOT_L AA8
CPU_SIC AF4 MEMHOT_L TP37
CPU_SID AF5 SIC CPU_THERMTRIP# 27
place them to CPU within 1.5" SID CPU_PROCHOT#_VDDIO 26
CPU_ALERT AE6 W7 CPU_THERMDC
ALERT_L THERMDC W8 CPU_THERMDA
Keep net PWRGD, LDT_STOP#, LDT_RST# no stub +3.3V THERMDA DEL SB_CPU_THRMDA/ SB_CPU_THRMDC
+1.8V R115 44.2R CPU_HTREF0 R6
+1.5V R116 44.2R CPU_HTREF1 P6 HT_REF0 NC_0R R171 H_THRMDC
+1.5V CPU_VLDT HT_REF1
C138 NC_100nF NC_0R R172 H_THRMDA Update on rev:1.1
R126 TP39 F6 W9 TP44
8 CPU_VDD0_RUN_FB_H VDD0_FB_H VDDIO_FB_H CPU_VDDIO_SUS_FB_H 9
R193 U4503 NC_4.7K TP40 E6 Y9 TP55 Thermdc and Thermda should be routed away to VRM,
8 CPU_VDD0_RUN_FB_L VDD0_FB_L VDDIO_FB_L
300R 1 NC VCC 5
R187 LDT_RST# 2 INA TP35 Y6 H6 TP54
crystal, etc. Customer should follow the MBDG.
26 CPU_LDT_RST# 8 CPU_VDD1_RUN_FB_H VDD1_FB_H VDDNB_FB_H CPU_VDDNB_RUN_FB_H 8 However, Guam is using TSI so this does not applies to Guam.
300R 3 GND 4 CPU_LDT_RST_HTPA# TP36 AB6 G6 TP56
8 CPU_VDD1_RUN_FB_L VDD1_FB_L VDDNB_FB_L CPU_VDDNB_RUN_FB_L 8
PWRGD OUT Y
26 CPU_PWRGD
C176 CPU_DBRDY G10
180pF NC_TC7SZ07F CPU_TMS AA9 DBRDY E10 CPU_DBREQ#
C337 DNI CPU_TCK AC9 TMS DBREQ_L
TCK route as differential
180pF CPU_TRST# AD9 AE9 CPU_TDO as short as possible
DNI CPU_VDDIO_SUS CPU_TDI AF9 TRST_L TDO
TDI testpoint under package
+1.5V Update on rev:1.1 TP4 CPU_TEST23_TSTUPD AD7 J7 CPU_TEST28_H_PLLCHRZ_P TP6
TEST23 TEST28_H H8 CPU_TEST28_L_PLLCHRZ_N TP8
R258 TP17 CPU_TEST18_PLLTEST1 H10 TEST28_L
C R191 TP19 CPU_TEST19_PLLTEST0 G9 TEST18 D7 CPU_TEST17_BP3 TP61 C
510R TEST19 TEST17
300R E7 CPU_TEST16_BP2 TP62
LDT_STOP# CPU_TEST25_H_BYPASSCLK_H E9 TEST16 F7 CPU_TEST15_BP1 TP63
23,26 CPU_LDT_STOP# TEST25_H TEST15
CPU_TEST25_L_BYPASSCLK_L E8 C7 CPU_TEST14_BP0 TP64
TEST25_L TEST14
TP21 CPU_TEST21_SCANEN AB8 C3 CPU_TEST7_ANALOG_T TP25 CPU_VDDIO_SUS
DEL R254 TP11 CPU_TEST20_SCANCLK2 AF7 TEST21
TEST20
TEST7
TEST10
K8 CPU_TEST10_ANALOGOUT TP26
510R TP9 CPU_TEST24_SCANCLK1 AE7
TP10 CPU_TEST22_SCANSHIFTEN AE8 TEST24 C4 CPU_TEST8_DIG_T TP27 CPU_DBREQ# R198 300R
PLL bypass debug option
TP12 CPU_TEST12_SCANSHIFTENB AC8 TEST22 TEST8 CPU_TEST27_SINGLECHAIN R147 NC_1K
TP18 CPU_TEST27_SINGLECHAIN AF8 TEST12
supports AC couple & DC bias
TEST27 C9 CPU_TEST29_H_FBCLKOUT_P TP23 R185 DNI 300R
TP22 CPU_TEST9_ANALOGIN C2 TEST29_H C8
TP20 CPU_TEST6_DIECRACKMON AA6 TEST9 TEST29_L R184
R138 TEST6 80.6R
0R A3 H18 CPU_TEST29_L_FBCLKOUT_N TP24
A5 RSVD1 RSVD10 H19 CPU_TEST21_SCANEN R148 1K
B3 RSVD2 RSVD9 AA7 CPU_TEST20_SCANCLK2 R149 1K
RSVD3 RSVD8 Route as 80ohm, diff
B5 D5 CPU_TEST24_SCANCLK1 R150 1K
C1 RSVD4 RSVD7 C5 CPU_TEST22_SCANSHIFTEN R151 1K
RSVD5 RSVD6 CPU_TEST12_SCANSHIFTENB R152 NC_1K
R184's value is TBD. CPU_TEST15_BP1 R153 DNI 300R
SOCKET_638_PIN CPU_TEST14_BP0 R154 DNI 300R
CPU_TEST18_PLLTEST1 R155 1K
CPU_TEST19_PLLTEST0 R156 1K
CPU_TEST23_TSTUPD R162 DNI 1K
CPU_DBRDY R166 DNI 300R
CPU_VDDIO_SUS
CPU_TEST10_ANALOGOUT R215 DNI 300R CPU_VLDT
R221 R220 R268

2.2K 2.2K 2.2K R147, R152 is installed ONLY when SCAN is enabled
R298, R295's value is TBD. R215, R185 internal ONLY
C110 C179 C336 R162 is TBD
DNI DNI DNI CPU_VDDIO_SUS
SCLK3 27
220pF NC_0R R327
220pF 220pF SDATA3 27
NC_0R R309
1
Q118 R298 R295 R325

3 2 MMBT3904 1K 1K 1K 1.5V
3.3V
1
D107
2 DEL SB-TSI HEADER
DEL SB-TSI HEADER RB501V-40 0R R294
CPU_SIC
1
B Q119 B
3 2 MMBT3904 CPU_SID
D106 0R R301 +1.5V
1
1 2
RB501V-40 Q117
3 2 MMBT3904 CPU_ALERT
0R R314
2.2K
+3.3VDUAL
TSI_CLK 49 1K 1K
R157 R158
R161 1K 1K R159 R160
TSI_DAT 49 TP31
0R DNI DNI
R163
DNI VID Override Circuit
TP28
0R DNI R132 8
U103
1 C139 NC_100nF
DEL AEP HEAD CPU_SVC_R
CPU_SVD_R
PWRGD
0R
0R
R194
R196
CPU_SVC
CPU_SVD
8
8
49 SCLK2 SCLK VDD CPU_PWRGD_SVID_REG 8
0R R192
0R DNI R133 7 2 H_THRMDA
R197NC_220R
R164NC_220R
49 SDATA2 SDATA D+ TP29
Note:
R165 DNI220R
6 3 TP30
49 SMBALERT# ALERT D- H_THRMDC To override VID,
5
GND THERM
4 C182 Remove R192, R194, R196, install R165
2.2nF_50V
set VID via SW100
N$325218
N$325219
NC_ADM1032ARMZ DNI
U103 is not used; Tek differential probing point
CPU thermal control is based on TSI by default. for normal operation

open all switches
BOOT VOLTAGE(VDD)
SVC SVD
(CPUVRM_PRO# (CPUVRM_PRO#
= VCC/GND) = OPEN)
0 0 1.1 1.1
0 1 1.0 1.2
1 0 0.9 1.0
1 1 0.8 0.8
VID OVERIDE TABLE (VDD)

DEL SCAN Connector
HDT pin24 can be VDDIO Level if only Purple Possum is used.
For old HDT tool, 3.3v level shift is required. However, Purple Possum can tolerance 3.3v.
A CPU_VDDIO_SUS A
TP84
CPU_DBREQ#TP32
CPU_DBRDYTP59
CPU_TCK TP60
CPU_TMS TP76
CPU_TDI TP77
CPU_TRST# TP81
CPU_TDO TP82
TP83
CPU_LDT_RST_HTPA#
TP85
Title
S1G4 CTRL & DEBUG
HDT Connector Size
D
Document Number Rev
1.0
BM5016
5 4 3 2 1
5 4 3 2 1
CPU_VDD_RUN
BOTTOM SIDE DECOUPLING
C140 C141 C142 C143 C144 C145 C146
22uF 22uF 22uF 22uF 220nF 10nF 180pF
CPU_VDD_RUN
D D
C147 C148 C149 C150 C151 C152 C153

22uF 22uF 22uF 22uF 220nF 10nF 180pF
U100F
AA4 J6
AA11 VSS1 VSS66 J8
AA13 VSS2 VSS67 J10 CPU_VDDNB_RUN CPU_VDDIO_SUS
AA15 VSS3 VSS68 J12
AA17 VSS4 VSS69 J14
AA19 VSS5 VSS70 J16
AB2 VSS6 VSS71 J18
AB7 VSS7 VSS72 K2 C175 C154 C155 C156 C157 C158 C159 C160
AB9 VSS8 VSS73 K7 22uF 22uF 22uF 22uF 22uF 220nF 220nF 180pF
AB23 VSS9 VSS74 K9
AB25 VSS10 VSS75 K11
CPU_VDD_RUN U100E CPU_VDD_RUN AC11 VSS11 VSS76 K13
AC13 VSS12 VSS77 K15
G4 P8 AC15 VSS13 VSS78 K17
H2 VDD_1 VDD_24 P10 AC17 VSS14 VSS79 L6
J9 VDD_2 VDD_25 R4 AC19 VSS15 VSS80 L8
J11 VDD_3 VDD_26 R7 AC21 VSS16 VSS81 L10
J13 VDD_4 VDD_27 R9 AD6 VSS17 VSS82 L12
J15 VDD_5 VDD_28 R11 AD8 VSS18 VSS83 L14
K6
K10
VDD_6
VDD_7
VDD_29
VDD_30
T2
T6
AD25
AE11
VSS19
VSS20
VSS84
VSS85
L16
L18
DECOUPLING BETWEEN PROCESSOR AND DIMMs
K12 VDD_8 VDD_31 T8 AE13 VSS21 VSS86 M7
K14
L4
VDD_9
VDD_10
VDD_32
VDD_33
T10
T12
AE15
AE17
VSS22
VSS23
VSS87
VSS88
M9
AC6
PLACE CLOSE TO PROCESSOR AS POSSIBLE
L7 VDD_11 VDD_34 T14 AE19 VSS24 VSS89 M17
L9 VDD_12 VDD_35 U7 AE21 VSS25 VSS90 N4 CPU_VDDIO_SUS
L11 VDD_13 VDD_36 U9 AE23 VSS26 VSS91 N8
L13 VDD_14 VDD_37 U11 B4 VSS27 VSS92 N10
L15 VDD_15 VDD_38 U13 B6 VSS28 VSS93 N16
M2 VDD_16 VDD_39 U15 B8 VSS29 VSS94 N18 C334
C C
M6 VDD_17 VDD_40 V6 B9 VSS30 VSS95 P2 C177 C162 C163 C164 C165 C166 C167 C168 C169 C170 C171 C172 C161 C4505
M8 VDD_18 VDD_41 V8 B11 VSS31 VSS96 P7 0.22uF 0.22uF 4.7uF 4.7uF 4.7uF 4.7uF 220nF 220nF 220nF 220nF 100nF 10nF 180pF 180pF 100nF
M10 VDD_19 VDD_42 V10 B13 VSS32 VSS97 P9
N7 VDD_20 VDD_43 V12 B15 VSS33 VSS98 P11
N9 VDD_21 VDD_44 V14 B17 VSS34 VSS99 P17
N11 VDD_22 VDD_45 W4 B19 VSS35 VSS100 R8 IF VDDIO plane is split, add two 0.22uf caps
CPU_VDDNB_RUN VDD_23 VDD_46 Y2 B21 VSS36 VSS101 R10
K16 VDD_47 AC4 B23 VSS37 VSS102 R16
M16 VDDNB_1 VDD_48 AD2 B25 VSS38 VSS103 R18
CPU_VDDNB_RUN 4A P16 VDDNB_2 VDD_49 CPU_VDDIO_SUS D6 VSS39 VSS104 T7
T16 VDDNB_3 Y25 D8 VSS40 VSS105 T9
V16 VDDNB_4 VDDIO27 V25 D9 VSS41 VSS106 T11
CPU_VDDIO_SUS VDDNB_5 VDDIO26 V23 D11 VSS42 VSS107 T13
H25 VDDIO25 V21 D13 VSS43 VSS108 T15
J17 VDDIO1 VDDIO24 V18 D15 VSS44 VSS109 T17
K18 VDDIO2 VDDIO23 U17 D17 VSS45 VSS110 U4 +5VDUAL
K21 VDDIO3 VDDIO22 T25 D19 VSS46 VSS111 U6 R2980 10
K23 VDDIO4 VDDIO21 T23 D21 VSS47 VSS112 U8
VDDIO5 VDDIO20 VSS48 VSS113
1
K25 T21 D23 U10
L17 VDDIO6 VDDIO19 T18 D25 VSS49 VSS114 U12 @PC152
@ PC152
M18 VDDIO7 VDDIO18 R17 E4 VSS50 VSS115 U14 1U_0402_16V7K Note.. VDDR must be 1.05v nominal to
VDDIO8 VDDIO17 VSS51 VSS116
2
M21 P25 F2 U16 support ddr3-1333. VDDR can be droped
M23 VDDIO9 VDDIO16 P23 F11 VSS52 VSS117 U18 to 0.9v for DDR3-800 and DDR3-1066 to
M25 VDDIO10 VDDIO15 P21 F13 VSS53 VSS118 V2 reduce power consumption
N17 VDDIO11 VDDIO14 P18 F15 VSS54 VSS119 V7
VDDIO12 VDDIO13 F17 VSS55 VSS120 V9
F19 VSS56 VSS121 V11 R529 0R VDDR_1.2_EN:
VSS57 VSS122 8,16 VDDA_PWRGD
SOCKET_638_PIN F21 V13 1 : VDDR =1.05V 1.75A
F23 VSS58 VSS123 V15 0: VDDR = 0.9V 1.25 A (Default)
VSS59 VSS124
4
F25 V17 C526 U2910
VSS60 VSS125 R1807 CPU_VDDR
H7 W6 2.2nF 10K_0402_5%
cpu_vddio_sus 3A
VCNTL
H9 VSS61 VSS126 Y21 DNI CPU_VDDIO_SUS 2 1 1 2 CPU_VDDRP
H21 VSS62 VSS127 Y23 EN POK PJ18
H23 VSS63 VSS128 N6 UP7717ASU8_PSOP_8 2 1
J4 VSS64 VSS129 3 6 2 1
VSS65 VIN VOUT
1
JUMP_43X118
GND1
5 @PC153
@ PC153
100u
+
PC154
SOCKET_638_PIN
GND
B
@PC201 <DEVICE> NC 7 NC_0.1U_0402_16V7K B
FB
2
22U_1206_6.3V
2
R532
R1806
9
100R Updata on rev:1.1
1 2
1.27K_0402_5%
PC151
1 2 0R R531
CPU_VDDR_SENSE 15
27P_0402_16V7K
1
@
R1805
10K_0402_5%
+3.3V
2
R535
C532 100nF 6.81K
3
R536
NC_10k Q501
2N7002E
R534 33R 1
26 VDDR_1.2_EN
C531
2
VDDR_1.2_EN: 150PF
1 : VDDR =1.05V 1.75A
0: VDDR = 0.9V 1.25 A (Default)
A A

Title
S1G4 PWR & GND
C 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
CPU_VDDIO_SUS CPU_VDDIO_SUS
100
105
106
111
112
117
118
123
124
100
105
106
111
112
117
118
123
124
75
76
81
82
87
88
93
94
99
75
76
81
82
87
88
93
94
99
15 MEM_MA_ADD[0..15] MEM_MA_DATA[0..63] 15 15 MEM_MB_ADD[0..15] MEM_MB_DATA[0..63] 15
J402 J401
MEM_MA_ADD0 98 5 MEM_MA_DATA0 MEM_MB_ADD0 98 5 MEM_MB_DATA0
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
MEM_MA_ADD1 97 A0 DQ0 7 MEM_MA_DATA1 MEM_MB_ADD1 97 A0 DQ0 7 MEM_MB_DATA1
MEM_MA_ADD4 92 A3/A4 DQ3 4 MEM_MA_DATA4 MEM_MB_ADD4 92 A3/A4 DQ3 4 MEM_MB_DATA4
D MEM_MA_ADD9 85 A8/A7 DQ8 23 MEM_MA_DATA9 MEM_MB_ADD9 85 A8/A7 DQ8 23 MEM_MB_DATA9 D
MEM_MA_ADD11 84 A10/AP DQ10 35 MEM_MA_DATA11 MEM_MB_ADD11 84 A10/AP DQ10 35 MEM_MB_DATA11
MEM_MA_ADD13 119 A12_BC# DQ12 24 MEM_MA_DATA13 MEM_MB_ADD13 119 A12_BC# DQ12 24 MEM_MB_DATA13
15 MEM_MA_BANK[0..2] A15/BA3 DQ15 15 MEM_MB_BANK[0..2] A15/BA3 DQ15
39 MEM_MA_DATA16 39 MEM_MB_DATA16
MEM_MA_BANK0 109 DQ16 41 MEM_MA_DATA17 MEM_MB_BANK0 109 DQ16 41 MEM_MB_DATA17
MEM_MA_BANK1 108 BA0/BA1 DQ17 51 MEM_MA_DATA18 MEM_MB_BANK1 108 BA0/BA1 DQ17 51 MEM_MB_DATA18
MEM_MA_BANK2 79 BA1/BA0 DQ18 53 MEM_MA_DATA19 MEM_MB_BANK2 79 BA1/BA0 DQ18 53 MEM_MB_DATA19
15 MEM_MA_DM[0..7] BA2 DQ19 15 MEM_MB_DM[0..7] BA2 DQ19
MEM_MA_DM0 11 DQ20 42 MEM_MA_DATA21 MEM_MB_DM0 11 DQ20 42 MEM_MB_DATA21
MEM_MA_DM1 28 DM0 DQ21 50 MEM_MA_DATA22 MEM_MB_DM1 28 DM0 DQ21 50 MEM_MB_DATA22
DM7 DQ28 58 MEM_MA_DATA29 DM7 DQ28 58 MEM_MB_DATA29
12 DQ29 68 MEM_MA_DATA30 12 DQ29 68 MEM_MB_DATA30
15 MEM_MA_DQS0_P DQS0 DQ30 15 MEM_MB_DQS0_P DQS0 DQ30
29 70 MEM_MA_DATA31 29 70 MEM_MB_DATA31
15 MEM_MA_DQS3_P 15 MEM_MB_DQS3_P
DDR3 SO-DIMM
DQS3 DQ33 DQS3 DQ33
DDR3 SO-DIMM
C 10 DQ38 142 MEM_MA_DATA39 10 DQ38 142 MEM_MB_DATA39 C
15 MEM_MA_DQS0_N DQS0# DQ39 15 MEM_MB_DQS0_N DQS0# DQ39
15 MEM_MA_DQS3_N
(Reverse) 15 MEM_MB_DQS3_N
(Reverse)
135 DQS3# DQ42 159 MEM_MA_DATA43 135 DQS3# DQ42 159 MEM_MB_DATA43
DQ47 163 MEM_MA_DATA48 DQ47 163 MEM_MB_DATA48
15 MEM_MA_CLK1_P CK0 DQ49 15 MEM_MB_CLK1_P CK0 DQ49
15 MEM_MA_CLK1_N CK0# DQ50 15 MEM_MB_CLK1_N CK0# DQ50
15 MEM_MA_CLK2_P CK1 DQ51 15 MEM_MB_CLK2_P CK1 DQ51
15 MEM_MA_CLK2_N CK1# DQ52 15 MEM_MB_CLK2_N CK1# DQ52
TP400 73 DQ53 174 MEM_MA_DATA54 TP402 73 DQ53 174 MEM_MB_DATA54
15 MEM_MA_CKE0 CKE0 DQ54 15 MEM_MB_CKE0 CKE0 DQ54
TP401 74 176 MEM_MA_DATA55 TP403 74 176 MEM_MB_DATA55
15 MEM_MA_CKE1 CKE1 DQ55 15 MEM_MB_CKE1 CKE1 DQ55
15 MEM_MA_RAS# RAS# DQ57 15 MEM_MB_RAS# RAS# DQ57
15 MEM_MA_CAS# CAS# DQ58 15 MEM_MB_CAS# CAS# DQ58
15 MEM_MA_WE# WE# DQ59 15 MEM_MB_WE# WE# DQ59
15 MEM_MA0_CS#0 S0# DQ60 15 MEM_MB0_CS#0 S0# DQ60
15 MEM_MA0_CS#1 S1# DQ61 15 MEM_MB0_CS#1 S1# DQ61
15 MEM_MA0_ODT0 ODT0 DQ63 15 MEM_MB0_ODT0 ODT0 DQ63
120 120 G1
15 MEM_MA0_ODT1 ODT1 15 MEM_MB0_ODT1 ODT1 NC3
208 G2
197 GND2 77 R401 4.7K 197 NC4 77
SA0 NC1 +3.3V SA0 NC1
201 122 201 122
SA1 NC2 125 MEM_MA_TEST TP57 SA1 NC2 125 MEM_MB_TEST TP58
B 200 TEST 205 200 TEST B
20,27 SDATA0 SDA NC 20,27 SDATA0 SDA
202 206 202 208
20,27 SCLK0 SCL NC3 20,27 SCLK0 SCL GND2
199 GND1
207
196 199 GND1
207
196
Standard
+3.3V +3.3V
VDDspd VSS51
VSS50
195 VDDspd VSS51
VSS50
195 Connector
30 190 30 190
15 MEM_MA_RST# RST# VSS49 15 MEM_MB_RST# RST# VSS49
VSS48
189
VSS48
189 1
198 185 198 185
19 MEM_MA_EVENT# EVENT# VSS47 19 MEM_MB_EVENT# EVENT# VSS47
184 184
VSS46 VSS46
1
2
3
1 179 1 179
5 4
6
7
8
MEM_M_VREF_SUS MEM_M_VREF_SUS
9
2
10
VREF VSS45 VREF VSS45

11
12
13
14
178 178
15
16
17
18
19
20
VSS44 VSS44
21
22
23 24
25
126 173 126 173

26
27
28
29
MEM_M_VREFCA MEM_M_VREFCA
30
31
VrefCA VSS43 VrefCA VSS43

32
CON_SODIMM200_STD_V1
33
34
35
172 172
36
37
38
39
40
203 VSS42 168 203 VSS42 168

MEM_VTT VTT1 VSS41 MEM_VTT VTT1 VSS41
41
42
43
44
C407C400 C408C401 204 167 C409C402 C418C403 204 167

45
46
47 48
49
50
51
VTT2 VSS40 VTT2 VSS40

52
53
54
55
0.01uf
1nF 0.01uf
1nF 162 0.01uf
1nF 0.01uf
1nF 162
56
57
58
59
60
61
VSS39 VSS39
62
Reverse
63
64
65
2 161 2 161
67 66
68
69
70
71
72
VSS0 VSS38 VSS0 VSS38

73
74
75
76
3 156 3 156
77
78
79
80
Connector
81
82

83 84
85
86
87
8 155 8 155
88
89
90
91
92
93

94
95
96
97
9 151 9 151
98
99
100
101
103 102
104

105
106
2
107
108
13 150 13 150
109
110
111
112
113
114

115
116
117
118
14 145 14 145
119 120
121
122
123
124
125

126
127
+3.3V
128
129
19 144 19 144
130
131
1 132
2 133
3 134
4 135
5

136
6 137
7 139 138
8 140
20 139 20 139
9 141
10 142
11 143
1
12 144
13 145
14 146
15

147
16 148
17 149
19 18 150
25 138 25 138
20 151
21 152
22 153
23 154
24 155
25 157 156
26

158
27 159
28
+3.3V
160
29 161
26 134 26 134
30 162
200
31 163
32 164
CON_SODIMM200_RVS_V1
199
33 165
34 166
35 36 167

37 168
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
38 169
39 170
40 171
31 133 31 133
172
173
175 174
176
177
178

179
180
181
182
32 128 32 128
183
184
41 185
43 42 186
44 187
45 188
46

189
47 190
48 191
49 192
50
C405
193 194
51 195
52 196
53 197
54 198
55 199
56 200
57
58
59 60
61
1uF
62
63
64
65
66
67
68
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
69
70
71
A A
72
73
74
75
76
77
79 78
80
81
82
C404 DDR3_SO-DIMM_SOCKET_1.5V_REVERSE DDR3_SO-DIMM_SOCKET_1.5V_REVERSE

83
84
85
86
87
88
89
90
91
92
1uF
93
94
95 96
97
98
99
100
101
102
103
FOXCONN_AS0A626_UASN_7F-2
104
105
106
107
108
109
110
111
112
113
FOXCONN_AS0A626_U2SN_7F-2
115 114
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133 134

135
136
137
138
139
140
141
142
143
144
145
146
147
148

149
151 150
152
153
154
155
156
157
158
159
160
161
162
163
164
199
165
166
Title
167
168
169 170
200 DDR3 SODIMMS: A/B CHANNEL

171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
187 186
188

189
190
191
192
193
194
195
196
197
198
Custom 1.0
199
200
BM5016
5 4 3 2 1
5 4 3 2 1
MEM_VTT MEM_VTT
D D
DNI DNI
C415 100nF C430 100nF
C414 100nF C431 100nF
DE-COUPLING FOR CHANNEL A SODIMM DE-COUPLING FOR CHANNEL B SODIMM
CPU_VDDIO_SUS
CPU_VDDIO_SUS
C594 C634 C640 C641 C642 C643 C480 C481 C482 C483 C484 C485
C450 C451 C452 C453 C454 C455 C595 C596 C597 C598 C628 C633 NC_100nF NC_100nF NC_100nF NC_100nF NC_100nF NC_100nF 100nF 100nF 100nF 100nF 100nF 100nF
100nF 100nF 100nF 100nF 100nF 100nF NC_100nF NC_100nF NC_100nF NC_100nF NC_100nF NC_100nF
DE-COUPLING FOR CHANNEL B SODIMM (ONE CAP PER POWER PIN)

DE-COUPLING FOR CHANNEL A SODIMM (ONE CAP PER POWER PIN)
C C
CPU_VDDIO_SUS MEM_VTT
CPU_VDDIO_SUS MEM_VTT
C502 C503 C506

C500 C501 C505 100uF_6.3V 100uF_6.3V 4.7uF
100uF_6.3V 100uF_6.3V 4.7uF
LAYOUT: PLACE CLOSE TO DIMMs
CPU_VDDIO_SUS
R420
1.00K
MEM_M_VREFCA
B B
MEM_VREF_SUS
CPU_VDDIO_SUS
R421
1.00K MEM_M_VREF_SUS
R409
1.00K
R410
1.00K
R404 R405
2.2K 2.2K R402 R403
1
2.2K 2.2K
3 2
27 CPU_MEMHOT# MEM_MA_EVENT# 18
Q401 MMBT3904
1
LAYOUT: PLACE CLOSE TO DIMMs

3 2
MEM_MB_EVENT# 18
Q402
A MMBT3904 A
+3.3V
R408
2.2K Bitland Information Techonogy Co.,Ltd.
R416
1
2.2K
Title
3 2 DDR3 SODIMM DECOUPLING
SB800_MEMHOT# 26
Q403 Size Document Number Rev
MMBT3904 Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
+3.3V CLK_VDD
FB1
1 2
Steward HZ0805E601R-00
C1 C7 C3 C4 C5 C6 C10 C8 C9 C11 C19

10uF 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 01.u 0.1u 0.1u 0.1u
0.1uF near the every power pin.
D D
U1A Place within 0.5" of CLKGEN

CLK_VDD R861 261R
11 42 CPU_CLKP_R R814 EXT 0R DNI
VDD_SRC_1 CPU_K8_0 CPU_CLKP 16
14 41 CPU_CLKN_R R875 EXT 0R
VDD_SRC_2 CPU_K8_0# CPU_CLKN 16
21 38
28 VDD_SB_SRC CPU_K8_1 37
33 VDD_ATIGCLK_1 CPU_K8_1#
36 VDD 32 NBGFX_CLKP_R R865 0R
VDD_A ATIGCLK_0 EXT NB_GFX_REFCLKP 23
40 31 NBGFX_CLKN_R R886 EXT 0R
VDD_CPU ATIGCLK_0# NB_GFX_REFCLKN 23
48 30 GFX_CLKP R864 EXT 0R
VDD_HTT ATIGCLK_1 PCIE_REFCLKP 31
52 29 GFX_CLKN R884 EXT 0R
VDD_REF ATIGCLK_1# PCIE_REFCLKN 31
56 26
VDD_48 ATIGCLK_2 25
ATIGCLK_2#
3
10 VSS_48 23 NBSLINK_CLKP_R
VSS_SRC_1 SB_SRC_0
R888 EXT 0R
NBLINK_RCLKP 23 Clock chip has internal serial terminations
15 22 NBSLINK_CLKN_R R882 EXT 0R
20 VSS_SRC_2 SB_SRC_0# 19 SBSRC_CLKP_R R890 EXT 0R
NBLINK_RCLKN 23 for differencial pairs, external resistors are
VSS_SB_SRC SB_SRC_1 SBSRC_CLKP 26
24
VSS_ATIGCLK_1 SB_SRC_1#
18 SBSRC_CLKN_R R883 EXT 0R
SBSRC_CLKN 26
reserved for debug purpose.
27
34 VSS_ATIGCLK_2 17
35 VSS SRC_0 16
39 VSS_A SRC_0# 13 PCIE_LAN_CLKP_R R889 0R
VSS_CPU SRC_1 EXT PCIE_LAN_CLKP 48
45 12 PCIE_LAN_CLKN_R R880 EXT 0R
VSS_HTT SRC_1# PCIE_LAN_CLKN 48
53 8 NB CLOCK INPUT TABLE
VSS_REF SRC_2 9
SRC_2# 7 PCIE_PE2_CLKP_R R833 0R NB CLOCKS RS740 RX780 RS780
SRC_3 EXT PCIE_PE2_CLKP 47
C819 22pF 6 PCIE_PE2_CLKN_R R874 EXT 0R
SRC_3# PCIE_PE2_CLKN 47
4
1
HT_REFCLKP
Y3 66M SE(SINGLE END) 100M DIFF 100M DIFF
C XTAL 14.31818MHz 14.318MHz HT_REFCLKN NC 100M DIFF 100M DIFF C
20pF / 30ppm Y_SMD3225

54 REFCLK_P
XTAL_IN
2
3
55 14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V)

C820 22pF XTAL_OUT REFCLK_N NC NC vref
47 NBHTREF_CLKP_R R835 EXT 0R
HTT_0/66M_0 HT_REFCLKP 23
46 NBHTREF_CLKN_R R847 EXT 0R GFX_REFCLK 100M DIFF 100M DIFF 100M DIFF(IN/OUT)*
CLK_VDD R872 HTT_0#/66M_1 HT_REFCLKN 23
43 2 Update on rev:1.2 GPP_REFCLK NC 100M DIFF NC or 100M DIFF OUTPUT
PD# 48MHz_0 1 48M_USB_1
48MHz_1 TP623
44 GPPSB_REFCLK 100M DIFF 100M DIFF 100M DIFF
8.2K RESTORE# 51 SEL_HT66
EXTCLK_CLK 4 REF_0/SEL_HTT66 50 REF1 R869 EXT NC_33R
SCL REF_1 SB_OSC 27
CLK_SDATA 5 49 NB_OSC_R R34 158R * RS780 can be used as clock buffer to output two PCIE referecence clocks
SDA REF_2 NB_OSC 23
By deault, chip will configured as input mode, BIOS can program it to output mode.
R877 0R CLK_CLK SB_OSC - 3.3v
18,27 SCLK0
SLG8LP625
R35 NB_OSC - 1.1V 158R/90.9R
90.9R
R34/R35 (value may change)
OSC_14M_NB
RS740 3.3V 33R serial
R876 0R CLK_SDATA RX780 1.8V 33R/43R
18,27 SDATA0
RS780 1.1V 200R/100R
CLK_VDD
R870
NB_OSC_R C14 10pF NC_8.2K 1 66 MHz 3.3V single ended HTT clock
EXT SEL_HTT66
0* 100 MHz differential HTT clock
REF1 C15 10pF SEL_HT66
1* 100 MHz non-spreading differential SRC clock
B B
SEL_SATA
0 100 MHz spreading differential SRC clock
R871 * default
8.2K
48M_USB_1 C18 NC_10pF EXT
SEL_HT66 C20 10pF
EMI Capacitor
A A

Title
EXTERNAL CLOCK GENERATOR
C 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
U200A
Y25 D24
14 HT_CPU_NB_CAD_H0 HT_RXCAD0P HT_TXCAD0P HT_NB_CPU_CAD_H0 14
Y24 PART 1 OF 6 D25
14 HT_CPU_NB_CAD_L0 HT_RXCAD0N HT_TXCAD0N HT_NB_CPU_CAD_L0 14
V22 E24
V23 E25
V25 F24
V24 F25
U24 F23
D U25 F22 D
T25 H23
HYPER TRANSPORT CPU I/F

T24 H22
P22 J25
P23 J24
P25 K24
P24 K25
N24 K23
N25 K22
AC24 F21
AC25 G21
AB25 G20
AB24 H21
AA24 J20
AA25 J21
Y22 J18
Y23 K17
W21 L19
W20 J19
V21 M19
V20 L18
U20 M21
U21 P21
U19 P18
U18 M18
T22 H24
14 HT_CPU_NB_CLK_H0 HT_RXCLK0P HT_TXCLK0P HT_NB_CPU_CLK_H0 14
T23 H25
14 HT_CPU_NB_CLK_L0 HT_RXCLK0N HT_TXCLK0N HT_NB_CPU_CLK_L0 14
AB23 L21
14 HT_CPU_NB_CLK_H1 HT_RXCLK1P HT_TXCLK1P HT_NB_CPU_CLK_H1 14
C AA22 L20 C
14 HT_CPU_NB_CLK_L1 HT_RXCLK1N HT_TXCLK1N HT_NB_CPU_CLK_L1 14
M22 M24
14 HT_CPU_NB_CTL_H0 HT_RXCTL0P HT_TXCTL0P HT_NB_CPU_CTL_H0 14
M23 M25
14 HT_CPU_NB_CTL_L0 HT_RXCTL0N HT_TXCTL0N HT_NB_CPU_CTL_L0 14
R21 P19
14 HT_CPU_NB_CTL_H1 HT_RXCTL1P HT_TXCTL1P HT_NB_CPU_CTL_H1 14
R20 R18
14 HT_CPU_NB_CTL_L1 HT_RXCTL1N HT_TXCTL1N HT_NB_CPU_CTL_L1 14
R200 301R HT_RXCALP C23 B24 HT_TXCALP R201 301R
HT_RXCALN A24 HT_RXCALP HT_TXCALP B25 HT_TXCALN
HT_RXCALN HT_TXCALN
RS880M A11 HF MVD
BOM 300
B B
DEL HTPA PROBE CONNECTOR FOR DEBUG( NB SIDE)
A A

Title
RS880M-HT LINK I/F
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
MXM3.0 need put the CAP on the motherboard.

MXM3.0 need put the CAP on the motherboard. Close to the MXM Slot
Close to the MXM Slot
U200B
31 GFX_RX0P_C D4 A5 C202 100nF_6.3V
GFX_RX0P GFX_TX0P GFX_TX0P_C 31
31 GFX_RX0N_C C4 PART 2 OF 6 B5 C203 100nF_6.3V
GFX_RX0N GFX_TX0N GFX_TX0N_C 31
31 GFX_RX1P_C A3 A4 C204 100nF_6.3V
31 GFX_RX1N_C B3 B4 C205 100nF_6.3V
31 GFX_RX2P_C C2 C3 C206 100nF_6.3V
31 GFX_RX2N_C C1 B2 C207 100nF_6.3V
D
31 GFX_RX3P_C E5 D1 C208 100nF_6.3V D
31 GFX_RX3N_C F5 D2 C209 100nF_6.3V
G5 E2 C210 100nF_6.3V
PCIE I/F GFX

31 GFX_RX4P_C GFX_RX4P GFX_TX4P GFX_TX4P_C 31
31 GFX_RX4N_C G6 E1 C211 100nF_6.3V
31 GFX_RX5P_C H5 F4 C212 100nF_6.3V
31 GFX_RX5N_C H6 F3 C213 100nF_6.3V
31 GFX_RX6P_C J6 F1 C214 100nF_6.3V
31 GFX_RX6N_C J5 F2 C215 100nF_6.3V
31 GFX_RX7P_C J7 H4 C216 100nF_6.3V
31 GFX_RX7N_C J8 H3 C373 100nF_6.3V
31 GFX_RX8P_C L5 H1 C218 100nF_6.3V
31 GFX_RX8N_C L6 H2 C217 100nF_6.3V
31 GFX_RX9P_C M8 J2 C220 100nF_6.3V
31 GFX_RX9N_C L8 J1 C219 100nF_6.3V
31 GFX_RX10P_C P7 K4 C222 100nF_6.3V
31 GFX_RX10N_C M7 K3 C221 100nF_6.3V
31 GFX_RX11P_C P5 K1 C224 100nF_6.3V
31 GFX_RX11N_C M5 K2 C223 100nF_6.3V
31 GFX_RX12P_C R8 M4 C226 100nF_6.3V
31 GFX_RX12N_C P8 M3 C225 100nF_6.3V
31 GFX_RX13P_C R6 M1 C228 100nF_6.3V
31 GFX_RX13N_C R5 M2 C227 100nF_6.3V
31 GFX_RX14P_C P4 N2 C230 100nF_6.3V
31 GFX_RX14N_C P3 N1 C229 100nF_6.3V
31 GFX_RX15P_C T4 P1 C232 100nF_6.3V
31 GFX_RX15N_C T3 P2 C231 100nF_6.3V
AE3 AC1
AD4 GPP_RX0P GPP_TX0P AC2
AE2 GPP_RX0N GPP_TX0N AB4
C AD3 GPP_RX1P GPP_TX1P AB3 C
AD1 GPP_RX1N GPP_TX1N AA2
PROBE TP254 GPP_RX2P GPP_TX2P
PROBE TP255 AD2 PCIE I/F GPP AA1
TP264 V5 GPP_RX2N GPP_TX2N Y1 GPP_TX3P_C C240 100nF_6.3V
48 PCIE_LAN_NB_RXP
48 PCIE_LAN_NB_RXN
TP265 W6 GPP_RX3P
GPP_RX3N
GPP_TX3P
GPP_TX3N
Y2 GPP_TX3N_C C241 100nF_6.3V
PCIE_NB_LAN_TXP 48
PCIE_NB_LAN_TXN 48
DEL header_1x3
U5 Y4
U6 GPP_RX4P GPP_TX4P Y3
U8 GPP_RX4N GPP_TX4N V1
U7 GPP_RX5P GPP_TX5P V2
GPP_RX5N GPP_TX5N
26 PCIE_SB_NB_RX0P TP258 AA8 AD7 A_TX0P_C C246 100nF_6.3V

SB_RX0P SB_TX0P PCIE_NB_SB_TX0P 26
26 PCIE_SB_NB_RX0N TP259 Y8 AE7 A_TX0N_C C247 100nF_6.3V
SB_RX0N SB_TX0N PCIE_NB_SB_TX0N 26
26 PCIE_SB_NB_RX1P TP260 AA7 AE6 A_TX1P_C C248 100nF_6.3V
26 PCIE_SB_NB_RX1N TP261 Y7 AD6 A_TX1N_C C249 100nF_6.3V
26 PCIE_SB_NB_RX2P TP256 AA5 PCIE I/F SB AB6 A_TX2P_C C250 100nF_6.3V
26 PCIE_SB_NB_RX2N TP257 AA6 AC6 A_TX2N_C C251 100nF_6.3V
26 PCIE_SB_NB_RX3P TP262 W5 AD5 A_TX3P_C C252 100nF_6.3V
26 PCIE_SB_NB_RX3N TP263 Y5 AE5 A_TX3N_C C253 100nF_6.3V
AC8 R208 1.27K +1.1V
PCE_CALRP(PCE_BCALRP) AB8 R209 2.0K
PCE_CALRN(PCE_BCALRN)
RS880M A11 HF MVD
Keep the impendance of PCIE lane to 85ohm +/-15% All PCIe lane shou route 8" max for Gen2 connector and max 12" for Gen2 on board devices
Including the A-link Guam has the Lasso lane over 8" due to the large board, should use shorter lasso calbe for Guam.
B
Customer need to follow the MBDG. B
RS880M Display Port Support (muxed on GFX)
GFX_TX0,TX1,TX2 and TX3

DP0
DEL PCIE MIDDLE BUS PROBE FOR DEBUG AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7

DP1
AUX1 and HPD1
A A

Title
RS880M-PCIE I/F
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
R210 0R NB_RST#_IN
24,26,31,49 A_RST#
+3.3V
Note:Regarding LDT_STOP# signal,It's required within B200 220R AVDD12 110MA
40ns skew for both assertion and de-assertion between C254
NB and CPU. +1.8V
2.2uF_4V
+1.8V
+1.8V
R213 0R 20MA AVDDDI
C255 U200C
DNI 100nF F12 A22
AVDD1(NC) TXOUT_L0P(NC) NB_LVDS_TX_L0P 43
D R277 C4506 R240 E12 PART 3 OF 6 B22 D
AVDD2(NC) TXOUT_L0N(NC) NB_LVDS_TX_L0N 43
300R 100nF 2.2K F14 A21
+1.8V AVDDDI(NC) TXOUT_L1P(NC) NB_LVDS_TX_L1P 43
U4504 G15 B21
1 NC VCC 5 B201 220R 4MA AVDDQ H15 AVSSDI(NC)
AVDDQ(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
B20
NB_LVDS_TX_L1N
NB_LVDS_TX_L2P
43
43
DEL THERMAL SENSOR
2 INA C257 H14 A20 TP200
16,26 CPU_LDT_STOP# AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) NB_LVDS_TX_L2N 43
3 GND 4 NB_LDT_STOP# 2.2uF_4V A19
OUT Y TP225 E17 TXOUT_L3P(NC) B19 TP203
TP204 F17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2)
F15 Y(DFT_GPIO2) B18
CRT/TVOUT
TC7SZ07F TP224
COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) A18
Termination resstors < 1 inch trace G18 TXOUT_U0N(NC) A17
R214 DNI 0R TP201
44 NB_VGA_R RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
R219 140R 1% ** G17 B17
R261 NC_1K+1.5V TP202 E18 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) D20
44 NB_VGA_G GREEN(DFT_GPIO1) TXOUT_U2P(NC)
R217 150R 1% F18 D21
TP205 E19 GREENb(NC) TXOUT_U2N(NC) D18
44 NB_VGA_B BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5)
1
R218 150R 1% F19 D19

BLUEb(NC) TXOUT_U3N(NC)
2 3 A11 B16 TP206
24,44 HSYNC# DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) NB_LVDS_TX_CLKLP 43
TP219 B11 A16 TP207
Q3641 24,44 VSYNC# DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) NB_LVDS_TX_CLKLN 43
Update on rev:1.1 F8 D16
NC_3904 44 DAC_SCL DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
TP223 E8 D17
44 DAC_SDAT DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) +1.8V
+1.1V R222 715R G14
PUT R330 ON TRACE DIRECTLY DAC_RSET(PWM_GPIO1) A13 15MA B202 220R
+1.8V B203 220R 65MA PLLVDD A12 VDDLTP18(NC) B13
B204 200R 20MA PLLVDD18 D14 PLLVDD(NC) VSSLTP18(NC)
PLLVDD18(NC)
PLL PWR
C261 C262 B12 A15 +1.8V
LVTM
C263 2.2uF_4V 2.2uF_4V PLLVSS(NC) VDDLT18_1(NC) B15 300MA B205 220R_2A
22uF B206 220R 20MA VDDA18HTPLL H17 VDDLT18_2(NC) A14
VDDA18HTPLL VDDLT33_1(NC) B14 C264 C265 C259
C B208 220R 120MA VDDA18PCIEPLL D7 VDDLT33_2(NC) 100nF 4.7UF 2.2uF_4V C
E7 VDDA18PCIEPLL1 C14
C266 C268 VDDA18PCIEPLL2 VSSLT1(VSS) D15
Change B204 to Resistor 2.2uF_4V 2.2uF_4V NB_RST#_IN D8 VSSLT2(VSS) C16
NB_PWRGD_IN A10 SYSRESETb VSSLT3(VSS) C18
3.9R(315003R900G) POWERGOOD VSSLT4(VSS)
PM
NB_LDT_STOP# C10 C20
NB_ALLOW_LDTSTOP C12 LDTSTOPb VSSLT5(VSS) E20
+1.1V ALLOW_LDTSTOP VSSLT6(VSS) C22
HT 100MHZ reference clock HT_REFCLKP C25 VSSLT7(VSS)
+3.3V R245 HT_REFCLKN C24 HT_REFCLKP
4.7K HT_REFCLKN
EXT NB_REFCLK_P E11
20 NB_OSC REFCLK_P/OSCIN(OSCIN)
NB_REFCLK_N F11 E9 R280 0R
CLOCKs
REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) NB_LCD_PWR_EN 43
R237 R236 F7 R281 0R
LVDS_BLON(PCE_RCALRP) NB_LCD_BKL_PWM 43
4.7K 4.7K Clock dif pair for NB_GFX_REFCLKP
R311 EXT 0R GFX_REFCLKP T2 G12 R282 0R
external graphics GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) NB_LCD_BKL_EN 43
R244 NB_GFX_REFCLKN
R312 EXT 0R GFX_REFCLKN T1
0R R238 I2C_DATA GFX_REFCLKN
43 NB_LCD_DDC_DATA 4.7K
Clock dif pair for general
TP228 GPP_REFCLKP U1 R226 R225 R228
EXT GPP_REFCLKP
0R R239 I2C_CLK purpose pcie devices TP229 GPP_REFCLKN U2 4.7K 4.7K 4.7K +3.3V
43 NB_LCD_DDC_CLK GPP_REFCLKN
Clock dif pair for NBLINK_RCLKP V4
SB and pcie devices NBLINK_RCLKN V3 GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN) R231 R229
I2C_CLK B9 NC_4.7K NC_4.7K
GFX_REFCLKP I2C_DATA A9 I2C_CLK D9 TP221
GFX_REFCLKN A8 I2C_DATA MIS. TMDS_HPD(NC) D10 TP230
B8 DDC_CLK0/AUX0P(NC) HPD(NC)
B7 DDC_DATA0/AUX0N(NC) D12 R243 0R
DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) SUS_STAT# 27
A7
R340 R341 DDC_DATA1/AUX1N(NC) AE8 0R R230 SUS_STAT#_R 24
B NC_4.7K NC_4.7K B10 THERMALDIODE_P AD8 0R R232 SB_NB_THRMDA 28 B
10 STRP_DATA STRP_DATA THERMALDIODE_N SB_NB_THRMDC 28
TP208 G11 D13 TEST_EN
RSVD TESTMODE
R259 150R RS880_AUX_CAL C8 R235
AUX_CAL(NC) 1.8K
+1.8V RS880M A11 HF MVD
R242
1K
20 NBLINK_RCLKP
R241 0R NB_ALLOW_LDTSTOP
26 ALLOW_LDTSTOP
20 NBLINK_RCLKN
NB_PWRGD_IN
51 NB_PWRGD_IN 20 HT_REFCLKP
20 HT_REFCLKN
20 NB_GFX_REFCLKP
20 NB_GFX_REFCLKN
PLACE R291, R292 CLOSE TO NB(R291, R292 IS FOR A11 SB800 ONLY)
DEL
RS880M UVD DEBUG HEAD
A RS880M JTAG A
8BIT DEBUG HEADER

Title
RS880M-SYSTEM I/F
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
U200D
PAR 4 OF 6
AB12 AA18
AE16 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA20
V11 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA19
AE15 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) Y19
AA12 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) V17
AB16 MEM_A4(NC) MEM_DQ4(NC) AA17
AB14 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA15
AD14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) Y15
D AD13 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) AC20 D
MEM_A8(NC) MEM_DQ8/DVO_D3(NC) DEL U202
SBD_MEM/DVO_I/F
AD15 AD19
AC16 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AE22
AE13 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AC18
AC14 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AB20
Y14 MEM_A12(NC) MEM_DQ12(NC) AD22
MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AC22
AD16 MEM_DQ14/DVO_D10(NC) AD21
AE17 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC)
AD17 MEM_BA1(NC) Y17
MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) W18
W12 MEM_DQS0N/DVO_IDCKN(NC) AD20
Y12 MEM_RASb(NC) MEM_DQS1P(NC) AE21
AD18 MEM_CASb(NC) MEM_DQS1N(NC)
AB13 MEM_WEb(NC) W17
AB18 MEM_CSb(NC) MEM_DM0(NC) AE19
V14 MEM_CKE(NC) MEM_DM1/DVO_D8(NC)
MEM_ODT(NC) AE23 15mA
IOPLLVDD18(NC) +1.8V
V15 AE24 +1.1V
W14 MEM_CKP(NC) IOPLLVDD(NC)
MEM_CKN(NC) AD23
AE12 IOPLLVSS(NC)
AD12 MEM_COMPP(NC) AE18 SPM_VREF
MEM_COMPN(NC) MEM_VREF(NC) STRAP_DEBUG_BUS_GPIO_ENABLEb
RS880M A11 HF MVD
R255 R260 3K +3.3V

23,44 VSYNC#
0R Enables the Test Debug Bus using GPIO.
R273 DNI 3K
1%
C RS880M C
1 Disable
0 Enable
DFT_GPIO1: LOAD_EEPROM_STRAPS
Selects Loading of STRAPS from EPROM
D201
RB501V-40 DNI 1 : Bypass the loading of EEPROM straps and use Hardware Default Values
2 1 0 : I2C Master can load strap values from EEPROM if connected, or use
23 SUS_STAT#_R A_RST# 23,26,31,49
default values if not connected
R279 DNI 3K
DEL SDRAM DDR3
B B
RS880M: Enables Side port memory
23,44 HSYNC#
R275 3K +3.3V RS880M:HSYNC#
R276 NC_3K Selects if Memory SIDE PORT is available or not

1 = Memory Side port Not available
0 = Memory Side port available
Register Readback of strap: NB_CLKCFG:CLK_TOP_SPARE_D[1]
A A

Title
RS880M-SPMEM/STRAPS
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
AE14
RS880M POWER TABLE
AC3
AC4
M11
AA4
AB5
AB1
AB7
AE1
AE4
AB2
D11
E14
E15
K14
L15
J15
J12
W1
W2
W4
W7
W8
M6
G1
G2
G4
G8
D3
D5
H7
R7
N4
R1
R2
R4
U4
A2
B1
E4
P6
V7
V8
V6
Y6
L1
L2
L4
L7
J4
U200F PIN NAME RS880M PIN NAME RS880M
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
RS880M A11 HF MVD
VDDHT +1.1V IOPLLVDD +1.1V
VDDHTRX +1.1V AVDD +3.3V
VDDHTTX +1.2V AVDDDI +1.8V
PART 6/6
D D
GROUND VDDA18PCIE +1.8V AVDDQ +1.8V
VDDG18 +1.8V PLLVDD +1.1V
VDD18_MEM +1.8V PLLVDD18 +1.8V
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VDDPCIE +1.1V VDDA18PCIEPLL +1.8V
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VDDC +1.1V VDDA18HTPLL +1.8V
VDD_MEM +1.8V/1.5V VDDLTP18 +1.8V
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VDDG33 +3.3V VDDLT18 +1.8V
IOPLLVDD18 +1.8V VDDLT33 NC
+1.1V
U200E 100R 100MHZ 3A +1.1V
R262 120R 2 A 100MHz 600MA VDDHT J17 A6 VDD_PCIE 2.5A R264
C K16 VDDHT_1 VDDPCIE_1 B6 C
L16 VDDHT_2 PART 5/6 VDDPCIE_2 C6
C296 C297 C301 C302 M16 VDDHT_3 VDDPCIE_3 D6 C304 C305 C298 C303 C309
4.7UF 100nF 100nF 100nF P16 VDDHT_4 VDDPCIE_4 E6 100nF 100nF 1uF_6.3V 1uF_6.3V 4.7UF
+1.1V R16 VDDHT_5 VDDPCIE_5 F6
T16 VDDHT_6 VDDPCIE_6 G7
VDDHT_7 VDDPCIE_7 H8
R271 120R 2 A 100MHz 700MA VDDHTRX H18 VDDPCIE_8 J9
G19 VDDHTRX_1 VDDPCIE_9 K9
C310 F20 VDDHTRX_2 VDDPCIE_10 M9
10uF_6.3V C312 C299 C313 E21 VDDHTRX_3 VDDPCIE_11 L9
100nF 100nF 100nF D22 VDDHTRX_4 VDDPCIE_12 P9
B23 VDDHTRX_5 VDDPCIE_13 R9
A23 VDDHTRX_6 VDDPCIE_14 T9
VLDT VDDHTRX_7 VDDPCIE_15 V9
R263 120R 2 A 100MHz 400MA 1.2V / 1.1V VDDHTTX AE25 VDDPCIE_16 U9
AD24 VDDHTTX_1 VDDPCIE_17 VCC_NB
C314 C317 C318 C319 C341 AC23 VDDHTTX_2 K12
4.7UF 100nF 100nF 100nF 100nF AB22 VDDHTTX_3 VDDC_1 J14
AA21 VDDHTTX_4 VDDC_2 U16 C320 C321 C322 C323 C324 C325 C326 C327 C328
Y20 VDDHTTX_5 VDDC_3 J11 100nF 100nF 100nF 100nF 100nF 100nF 100nF 10uF_6.3V 10uF_6.3V
W19 VDDHTTX_6 VDDC_4 K15
V18 VDDHTTX_7 VDDC_5 M12
POWER
U17 VDDHTTX_8 VDDC_6 L14
T17 VDDHTTX_9 VDDC_7 L11
R17 VDDHTTX_10 VDDC_8 M13
P17 VDDHTTX_11 VDDC_9 M15
M17 VDDHTTX_12 VDDC_10 N12
+1.8V VDDHTTX_13 VDDC_11 N14
B216 220R_2A 700MA VDDA18PCIE J10 VDDC_12 P11
B P10 VDDA18PCIE_1 VDDC_13 P13 B
C348 C329 C330 C331 C332 C333 K10 VDDA18PCIE_2 VDDC_14 P14
4.7UF 4.7UF 100nF 100nF 100nF 100nF M10 VDDA18PCIE_3 VDDC_15 R12
L10 VDDA18PCIE_4 VDDC_16 R15
W9 VDDA18PCIE_5 VDDC_17 T11
H9 VDDA18PCIE_6 VDDC_18 T15
T10 VDDA18PCIE_7 VDDC_19 U12
R10 VDDA18PCIE_8 VDDC_20 T14
Y9 VDDA18PCIE_9 VDDC_21 J16
AA9 VDDA18PCIE_10 VDDC_22
+1.8V AB9 VDDA18PCIE_11 AE10
R265 0R AD9 VDDA18PCIE_12 VDD_MEM1(NC) AA11
AE9 VDDA18PCIE_13 VDD_MEM2(NC) Y11
C339 U10 VDDA18PCIE_14 VDD_MEM3(NC) AD10
1uF VDDA18PCIE_15 VDD_MEM4(NC) AB10
10MA F9 VDD_MEM5(NC) AC10
G9 VDD18_1 VDD_MEM6(NC) +3.3V
25MA AE11 VDD18_2 H11 60MA R269 0R
AD11 VDD18_MEM1(NC) VDD33_1(NC) H12
VDD18_MEM2(NC) VDD33_2(NC) C342 C343
RS880M A11 HF MVD 100nF 100nF
A A
DEL FAN CIRCUIT

Title
RS880M-POWER
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
PLACE THESE PCIE AC

COUPLING CAPS CLOSE TO U600
U600A C847
C750 150PF NC_10PF
PCIE_RST#_C P1 SB800 Part 1 of 5 W2 PCI_CLK0_R R609 22R
PCIE_RST# PCICLK0 PCI_CLK0 47
23,24,31,49 A_RST# R600 33R L1 W1 PCI_CLK1_R R610 22R
A_RST# PCICLK1/GPO36 SMSC_CLK 30
PCI CLKS
W3 PCI_CLK2_R R611 22R
PCICLK2/GPO37 PCI_CLK2 30
C600 100nF_6.3V A_RX0P_C AD26 W4 PCI_CLK3_R R612 22R
22 PCIE_SB_NB_RX0P A_TX0P PCICLK3/GPO38 PCI_CLK3 30
C601 100nF_6.3V A_RX0N_C AD27 Y1 PCI_CLK4_R R613 22R
22 PCIE_SB_NB_RX0N A_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 30
C602 100nF_6.3V A_RX1P_C AC28
22 PCIE_SB_NB_RX1P A_TX1P
C603 100nF_6.3V A_RX1N_C AC29 V2 TP2816
D 22 PCIE_SB_NB_RX1N A_TX1N PCIRST# D
C604 100nF_6.3V A_RX2P_C AB29
22 PCIE_SB_NB_RX2P A_TX2P
C605 100nF_6.3V A_RX2N_C AB28
22 PCIE_SB_NB_RX2N A_TX2N +3.3V
C606 100nF_6.3V A_RX3P_C AB26 AA1
22 PCIE_SB_NB_RX3P A_TX3P AD0/GPIO0
C607 100nF_6.3V A_RX3N_C AB27 AA4
22 PCIE_SB_NB_RX3N A_TX3N AD1/GPIO1 AA3
TP650 AE24 AD2/GPIO2 AB1
22 PCIE_NB_SB_TX0P A_RX0P AD3/GPIO3
22 PCIE_NB_SB_TX0N TP651 AE23 AA5
TP652 AD25 A_RX0N AD4/GPIO4 AB2 R3614 R3615
PCI EXPRESS INTERFACES

22 PCIE_NB_SB_TX1P A_RX1P AD5/GPIO5 +3.3VDUAL
22 PCIE_NB_SB_TX1N TP653 AD24 AB6 NC_100K NC_100K
TP654 AC24 A_RX1N AD6/GPIO6 AB5
22 PCIE_NB_SB_TX2N TP655 AC25 AA6
TP656 AB25 A_RX2N AD8/GPIO8 AC2 MXM_PRESENT2# C3122 100nF
22 PCIE_NB_SB_TX3N TP657 AB24 AC3 MXM_PRESENT1# DNI
A_RX3N AD10/GPIO10 AC4
AD11/GPIO11
5
R601 590R 1% AD29 AC1
AD28 PCIE_CALRP AD12/GPIO12 AD1 1
PCIE_VDDR
R602 2.0K 1% PCIE_CALRN AD13/GPIO13 27 SB_GPIO_PCIE_RST#
AD2 R3612 R3613 4 R797 33R PCIE_RST# 27,31,36,47,48
C708 100nF_6.3V AA28 AD14/GPIO14 AC6 PCIE_RST#_C 2
47 PCIE_SB_PE2_TXP PROBE TP670 GPP_TX0P AD15/GPIO15 100K 100K
47 PCIE_SB_PE2_TXN PROBE TP671 C709 100nF_6.3V AA29 AE2
Y29 GPP_TX0N AD16/GPIO16 AE1 U3104 C749
PROBE TP668 GPP_TX1P AD17/GPIO17
3
PROBE TP669 Y28 AF8 NC7SZ08M5 150PF
Y26 GPP_TX1N AD18/GPIO18 AE3 Update on rev:1.1 DNI
Y27 GPP_TX2P AD19/GPIO19 AF1 TP2817
W28 GPP_TX2N AD20/GPIO20 AG1 R796 0R
J613 CLOSE TO U600 GPP_TX3P AD21/GPIO21
W29 AF2
GPP_TX3N AD22/GPIO22 AE9 PCI_AD23 TP2814
AD23/GPIO23 PCI_AD[27..23] 30
47 PCIE_PE2_SB_RXP TP662 AA22 AD9 PCI_AD24 R617 0R
GPP_RX0P AD24/GPIO24 VDDR_1.2_EN 17
47 PCIE_PE2_SB_RXN TP663 Y21 AC11 PCI_AD25 TP2815
TP660 AA25 GPP_RX0N AD25/GPIO25 AF6 PCI_AD26 TP2811 Updated on Rev2.0
TP661 AA24 GPP_RX1P AD26/GPIO26 AF4 PCI_AD27 TP2812
W23 GPP_RX1N AD27/GPIO27 AF3 PCI_AD28 TP2813
V24 GPP_RX2P AD28/GPIO28 AH2 PCI_AD29 R614 0R ALLOW_LDTSTOP
R798 NC_0R
C NOTE: SB8XX ONLY SUPPORTS 2 GPP GPP_RX2N AD29/GPIO29 SB800_MEMHOT# 19 C
W24 AG2
PORT 2 AND 3 IS NOT SUPPORTED. W25 GPP_RX3P AD30/GPIO30 AH3
GPP_RX3N AD31/GPIO31 AA8
PCI INTERFACE
CBE0# AD5
CBE1# AD8
CBE2# AA10 CPU_LDT_STOP#
R799 NC_0R
CBE3# AE8
FRAME# AB9
M23 DEVSEL# AJ3
20 SBSRC_CLKP PCIE_RCLKP/NB_LNK_CLKP IRDY#
20 SBSRC_CLKN P23 AE7
must share Pad with the serial resistor close to U800
PCIE_RCLKN/NB_LNK_CLKN TRDY# AC5

U29 PAR AF5 TEST PURPOSE ONLY
U28 NB_DISP_CLKP STOP# AE6
NB_DISP_CLKN PERR# AE4
T26 SERR# AE11
NOTE: The 0R serial resistor on SB CLK pair
T27 NB_HT_CLKP REQ0# AH5

NB_HT_CLKN REQ1#/GPIO40 AH4
REQ2#/CLK_REQ8#/GPIO41 TP274
V21 AC12 INTRUDER_ALERT#
R804 NC_0R
T21 CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42 AD12
CPU_HT_CLKN GNT0# AJ5
V23 GNT1#/GPO44 AH6 R771 0R
SLT_GFX_CLKP GNT2#/GPO45 PROBE PE_GPIO1 40
FOR EXT GRAPHICS T23 AB12 +3.3V
SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 AB11
CLKRUN# PCI_CLKRUN# 49
L29 AD7
L28 GPP_CLK0P LOCK# R809 R1821 10K_0402_5% +3.3V
GPP_CLK0N AJ6 20K PE_GPIO1 2 1
N29 INTE#/GPIO32 AG6 GPIO33 GUAM
N28 GPP_CLK1P INTF#/GPIO33 AG4 R1823 10K_0402_5%
GPP_CLK1N INTG#/GPIO34 AJ4 TP278 PE_GPIO0 2 1
M29 INTH#/GPIO35 R773 0R R808
GPP_CLK2P PROBE PE_GPIO0 31
FOR WIFI M28 20K
GPP_CLK2N BIMINI
B CLOCK GENERATOR B
T25
V25 GPP_CLK3P H24 R661 22R
FOR LAN GPP_CLK3N LPCCLK0 LPC_CLK0 30,49 FOR BIOS AUTO DETECTION(GUAM V.S. BIMINI)
H25 R662 22R
LPCCLK1 LPC_CLK1 30,47
L24 J27
GPP_CLK4P LAD0 LAD0 47,49
L23 J26
GPP_CLK4N LAD1 LAD1 47,49 +3.3VALW
LPC H29
LAD2 LAD2 47,49
P25 H28
GPP_CLK5P LAD3 LAD3 47,49
M25 G28
GPP_CLK5N LFRAME# LFRAME# 47,49
2
J25
P29 LDRQ0# AA18 R1808
P28 GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 AB19
GPP_CLK6N SERIRQ/GPIO48 SERIRQ 49 0_0402_5%
N26
GPP_CLK7P
1
N27
GPP_CLK7N G21 LBAT54CLT1G
ALLOW_LDTSTP/DMA_ACTIVE# ALLOW_LDTSTOP 23 D1
Updated on Rev2.0 T29 H21 CPU_PROCHOT#_VDDIO 16
T28 GPP_CLK8P PROCHOT# K19 0R R648 1
CPU_PWRGD 16
CPU
GPP_CLK8N LDT_PG G22 +RTCVCC

LDT_STP# CPU_LDT_STOP# 16,23
Updata on rev:1.2 TP606 J24 3
LDT_RST# CPU_LDT_RST# 16
R774 DNI 0R L25
14M_25M_48M_OSC RTCBAT1
+
2 +RTCVCC_EC
R1789 R1828
C694 27pF R763 0R C1 32K_X1 NC_0_0603_5% NC_0_0603_5%
Y15 32K_X1 4 2 1 2 1
25MHz 25M_X1 L26 C2 32K_X2 1
2 1 R651 25M_X1 32K_X2 2
RTC
+RTCVCC 3
PLACE THESE COMPONENTS CLOSE TO U600, AND
-
3 4 1M D2
RTCCLK B2 INTRUDER_ALERT# Update on rev:1.1
USE GROUND GUARD FOR 32K_X1 AND 32K_X2 C695 27pFY_5938 25M_X2 L27 INTRUDER_ALERT# B1 VBAT_IN R619 510R CONN2_R
25M_X2 VDDBT_RTC_G BM05_MIC_WAFER_2P Resered for EC and charger battery
32K_X1
SB_GPP DEVICE CLKREQ# SB800 A11 C645 C618
A NC_0.1uF
1uF R623 A
R605 20M 32K_X2 GFX_CLK MXM3.0 CLK_REQG# NC_100K FOR CMOS CLEAR
0 // 0
1 PE0 1
4
1
1
4
Y9 2 PE2 2 POWER EXPRESS SUPPORT

Y4 NC_32.7680KHZ 3 LAN 3
32.7680KHZ XS4_8038 4 PE1 4 PE_GPIO0 MXM RESET H: Enable Bitland Information Techonogy Co.,Ltd.
C616 C617
BM05_CLK_32_768M Notebook R&D Division
3
2
22pF 22pF 5 // 5 PE_GPIO1 MXM POWER ENABLE H: Enable

2
3
Title
6 PE3 6
PE_GPIO2 MODE SWITCH(BY NB) H:MXM L:NB SB8X0-PCIE/PCI/CPU/LPC/CLK
Update on rev:1.1 7 // 7 Size Document Number Rev
8 // 8 TMDS_HPD0 MXM HOT PLUG Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
U600D
R641 0R J2 A10
19 CPU_MEMHOT# PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC TP622
K1 Updata on rev:1.2
D3 RI#/GEVENT22# G19 R643 11.8K USB15 NA
F1 SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP 1%
DEL WIRELESS RADIO SWITCH
7,9,11,40,49,51 SLP_S3#
H1 SLP_S3# USB14 NA
9,11,46,49 SLP_S5# SLP_S5#
ACPI / WAKE UP EVENTS

49 PWR_BTN#_EC R702 EC 0R PWR_BTN# F2
PWR_BTN#
USB 1.1 USB MISC

H5
49,51 SB_PWRGD
G6 PWR_GOOD SB800 J10 USB13 NA
23 SUS_STAT# SUS_STAT# USB_FSD1P/GPIO186
SB_TEST0 B3 Part 4 of 5 H11
SB_TEST1 C4 TEST0 USB_FSD1N USB12 NA
TP607 TEST1/TMS
D SB_TEST2 F6 H9 USB11 NA D
R642 0R AD21 TEST2 USB_FSD0P/GPIO185 J8
49 EC_A20M# GA20IN/GEVENT0# USB_FSD0N
49 EC_KB_RST# R764 0R AE21
KBRST#/GEVENT1#
USB10 NA
49 EC_SCI# K2 B12
J29 LPC_PME#/GEVENT3# USB_HSD13P A12
49 EC_SMI# LPC_SMI#/GEVENT23# USB_HSD13N
H2
J1 GEVENT5# F11 USB9 NA
TP612 SYS_RESET#/GEVENT19# USB_HSD12P
H6 E11 USB8 3G PCIE Mini Slot
TP621 WAKE#/GEVENT8# USB_HSD12N
Update on rev:1.1 F3
IR_RX1/GEVENT20#
16 CPU_THERMTRIP# J6
THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD11P
E14 USB7 Blue Tooth
51 NB_PWRGD AC19 E12
NB_PWRGD USB_HSD11N USB6 Finger Print
RSMRST# G1 J12
RSMRST# USB_HSD10P J14 USB5 CAM
AD19 USB_HSD10N
AA16 CLK_REQ4#/SATA_IS0#/GPIO64 A13
CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD9P
26,31,36,47,48 PCIE_RST# 26 SB_GPIO_PCIE_RST# R795 0R AB21
SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD9N
B13 USB4 WIFI PCIE MINI SLOT
AC18
CLK_REQ0#/SATA_IS3#/GPIO60 USB3 USB PORT3
1
R784 NC_0R AF20 D13

40 MXM_PWR_EN SATA_IS4#/FANOUT3/GPIO55 USB_HSD8P USBP8 47
R682 AE19 C13
2 3 NC_0R CPU_THERMTRIP# R772 0R AF19 SATA_IS5#/FANIN3/GPIO59 USB_HSD8N USBN8 47 USB2 NC
42 SB_SPKR SPKR/GPIO66
18,20 SCLK0 AD22 G12 USB1 USB PORT1
USBP7 45
USB 2.0
AE22 SCL0/GPIO43 USB_HSD7P G14
18,20 SDATA0 SDA0/GPIO47 USB_HSD7N USBN7 45
C732 Q603 change to NC
47 SCLK1 SCLK1 F5
SCL1/GPIO227 USB0 USB PORT0
1uF 2N7002E 47 SDATA1 SDATA1 F4 G16
SDA1/GPIO228 USB_HSD6P USBP6 45
AH21 G18
R110 TP619 CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N USBN6 45
3
AB18
TP611 CLK_REQ1#/FANOUT4/GPIO61
1 Q3637 E1 D16
GPIO
36 MB_THERMB 49 KBC_LOW_BAT# IR_LED#/LLB#/GPIO184 USB_HSD5P USBP5 43
2021390400 13 SMARTVOLT2 AJ21 C16
SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD5N USBN5 43
2.2K H4
DDR3_RST#/GEVENT7#
2
C D5 B14 C
GBE_LED0/GPIO183 USB_HSD4P USBP4 47
D7 A14
GBE_LED1/GEVENT9# USB_HSD4N USBN4 47
+3.3V G5
K3 GBE_LED2/GEVENT10# E18
GBE_STAT0/GEVENT11# USB_HSD3P USBP3 46
CLKREQG# AA20 E16
CLK_REQG#/GPIO65/OSCIN USB_HSD3N USBN3 46
R625 2.2K SCLK0 J16
R626 2.2K SDATA0 H3 USB_HSD2P J18
R701 4.7K SUS_STAT# D1 BLINK/USB_OC7#/GEVENT18# USB_HSD2N
E4 USB_OC6#/IR_TX1/GEVENT6# B17
TP620 USBP1 46
USB OC
D4 USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P A17
+3.3VDual 46 USB_OCP3# USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N USBN1 46
R737 0R E8
TP618 USB_OC3#/AC_PRES/TDO/GEVENT15#
R5088 10K USB_OCP0#_P USB_OC2# F7 A16
TP617 USB_OC2#/TCK/GEVENT14# USB_HSD0P USBP0 46
R627 10K SCLK1 46 USB_OCP1# R734 0R E7 B16
TP616 USB_OC1#/TDI/GEVENT13# USB_HSD0N USBN0 46
R741 10K SDATA1 USB_OCP0#_P F8 Update on rev:1.1
TP615 USB_OC0#/TRST#/GEVENT12#
R5107 10K GBE_MDIO
R5108 10K GBE_PHY_INTR 46 USB_OCP0# R684 0R
R5109 NC_10KUSB_OC2#
R5110 10K USB_OCP1# JTAG MAPPING: AZ_BIT_CLK M3 D25
R5111 10K USB_OCP3# N1 AZ_BITCLK SCL2/GPIO193 F23
TCK = GEVENT14# 30 AZ_SDATA_OUT
L2 AZ_SDOUT SDA2/GPIO194 B26
42 AZ_SDATA_IN0 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 SCLK3 16
HD AUDIO
TDI = GEVENT13# M2
AZ_SDIN1/GPIO168 SDA3_LV/GPIO196
E26
SDATA3 162.2K 2.2K
R695 DNI 10K AZ_SDATA_IN0 TDO = GEVENT15# M1 F25
M4 AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197 E22 R705 R694
TMS = TEST1 AZ_SYNC N2 AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198 F22 10K 10K
AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199 GPIO199 30
R710 DNI 10K AZ_BIT_CLK RST# = GEVENT12# AZ_RST# P2
AZ_RST# EC_PWM3/EC_TIMER3/GPIO200
E21 GPIO200 30 R706 R698
C751 1 2 0402_NPO G24

NC_22P_50V_K_N GBE_COL T1 KSI_0/GPIO201 G25
AZ_RST# GBE_CRS T4 GBE_COL KSI_1/GPIO202 E28
42 AZ_RST#_CD R2115 33R
GBE_CRS KSI_2/GPIO203 STRAP pin to define
B L6 E29 B
R2105 33R AZ_BIT_CLK GBE_MDIO L5 GBE_MDCK KSI_3/GPIO204 D29 use LPC or SPI ROM
42 AZ_BIT_CLK_CD GBE_MDIO KSI_4/GPIO205
T9 D28 TEST2 TEST1 TEST0 TEST MODE DESCRIPTION
R2118 33R U1 GBE_RXCLK KSI_5/GPIO206 C29
42 AZ_SDATA_OUT_CD AZ_SDATA_OUT 30 GBE_RXD3 KSI_6/GPIO207
U3 C28
R2111 33R AZ_SYNC +3.3V T2 GBE_RXD2 KSI_7/GPIO208 0 0 0 None Nomal operation
42 AZ_SYNC_CD
GBE LAN
U2 GBE_RXD1 B28
T5 GBE_RXD0 KSO_0/GPIO209 A27 0 0 1 Reserved Reserved for ASIC debug
EMBEDDED CTRL
GBE_RXERR V5 GBE_RXCTL/RXDV KSO_1/GPIO210 B27
R2115 ,R2105 ,R2118,R2111 are placed close to SB800 GBE_RXERR KSO_2/GPIO211 +3.3VDual
R769 P5 D26 0 1 X Test mode Enable Test Mode
M5 GBE_TXCLK KSO_3/GPIO212 A26
NC_10K GBE_TXD3 KSO_4/GPIO213
P9 C26 1 X X Reserved Reserved for ASIC debug
CLKREQG# T7 GBE_TXD2 KSO_5/GPIO214 A24
20 SB_OSC GBE_TXD1 KSO_6/GPIO215
P7 B25 SB_TEST0 R686 NC_2.2K
R770 M7 GBE_TXD0 KSO_7/GPIO216 A25
P4 GBE_TXCTL/TXEN KSO_8/GPIO217 D24 SB_TEST1 R711 NC_2.2K
NC_10K TP605 GBE_PHY_PD KSO_9/GPIO218
M9 B24
+3.3VDual GBE_PHY_INTR V7 GBE_PHY_RST# KSO_10/GPIO219 C24
R639 NC_22K GBE_PHY_INTR KSO_11/GPIO220 B23 change to NC
RSMRST# 49 KSO_12/GPIO221
E23 A23
TP613 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222
E24 D22
EMBEDDED CTRL
TP614 PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223
F21 C22 SB_TEST2 R700 NC_2.2K
C621 G29 SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224 A22
TP610 FC_RST#/GPO160 KSO_16/GPIO225
NC_2.2uF_6.3V B22
D27 KSO_17/GPIO226
F28 PS2KB_DAT/GPIO189
F29 PS2KB_CLK/GPIO190
E27 PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
A SB800 A11 SB800 SB_TEST0,SB_TEST1,SB_TEST2 has internal 10K PD. A
R807 10K GBE_RXERR

R806 10K GBE_CRS
FOR IMC DEBUG R803 10K GBE_COL Bitland Information Techonogy Co.,Ltd.
Title
SB8X0-GPIO/USB/AZ/RGMII
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
SATA trace should use only 1via on the trace.

customers can use 2vias with GND via within 150mils of
signal via as long as they can ensure that their platform
meets SATA logo requirements. Return loss is expected
to get affected with 2 vias. AMD platforms are validated
with one via only
U600B
D D
C631 10nF SATA_TX0+ AH9 SB800 AH28
41 SATA_TX0+_C AJ9 SATA_TX0P FC_CLK AG28
41 SATA_TX0-_C
C632 10nF SATA_TX0-
SATA_TX0N Part 2 of 5 FC_FBCLKOUT
FOR SATA HD AF26
SATA_RX0- AJ8 FC_FBCLKIN
41 SATA_RX0-_C SATA_RX0N
SATA_RX0+ AH8 AF28
41 SATA_RX0+_C SATA_RX0P FC_OE#/GPIOD145 AG29
C636 10nF SATA_TX1+ AH10 FC_AVD#/GPIOD146 AG26
41 SATA_TX1+_C C637 10nF SATA_TX1- AJ10 SATA_TX1P FC_WE#/GPIOD148 AF27
41 SATA_TX1-_C SATA_TX1N FC_CE1#/GPIOD149 AE29
FOR SATA ODD FC_CE2#/GPIOD150
SATA_RX1- AG10 AF29
41 SATA_RX1-_C SATA_RX1N FC_INT1/GPIOD144
SATA_RX1+ AF10 AH27
41 SATA_RX1+_C SATA_RX1P FC_INT2/GPIOD147
AG12 AJ27
AF12 SATA_TX2P FC_ADQ0/GPIOD128 AJ26
SATA_TX2N FC_ADQ1/GPIOD129 AH25
AJ12 FC_ADQ2/GPIOD130 AH24
AH12 SATA_RX2N FC_ADQ3/GPIOD131 AG23
SATA_RX2P FC_ADQ4/GPIOD132 AH23
SATA PORTS DISTRIBUTION: FC_ADQ5/GPIOD133
AH14 AJ22
0, - 2.5 INCH DISK DRIVER AJ14 SATA_TX3P FC_ADQ6/GPIOD134 AG21
1, SATA ODD SATA_TX3N FC_ADQ7/GPIOD135 AF21
AG14 FC_ADQ8/GPIOD136 AH22
2,NOT USED AF14 SATA_RX3N FC_ADQ9/GPIOD137 AJ23
FLASH
3, NOT USED SATA_RX3P FC_ADQ10/GPIOD138 AF23
FC_ADQ11/GPIOD139
4 & 5, NOT USED AG17
SATA_TX4P FC_ADQ12/GPIOD140
AJ24
AF17 AJ25
SATA_TX4N FC_ADQ13/GPIOD141 AG25
PLACE SATA_CAL AJ17 FC_ADQ14/GPIOD142 AH26
AH17 SATA_RX4N FC_ADQ15/GPIOD143
SERIAL ATA
C RES VERY CLOSE SATA_RX4P C
AJ18
TO BALL OF U600 AH18 SATA_TX5P W5
Connect C7 and D8, then go to GND directly.
SATA_TX5N FANOUT0/GPIO52 W6
AH19 FANOUT1/GPIO53 Y9 SB_PROCHOT#_C
AJ19 SATA_RX5N FANOUT2/GPIO54
SATA_RX5P W7 DEL SB_CPU_THRMDA/SB_CPU_THRMDC
AVDD_SATA FANIN0/GPIO56 V9
R650 1% 1.0K SATA_CALP AB14 FANIN1/GPIO57 W8
R649 1% 931R SATA_CALN AA14 SATA_CALRP FANIN2/GPIO58 R759 10K
SATA_CALRN B6 TEMPIN0
TEMPIN0/GPIO171 A6 TEMPIN1 R644 0R
TEMPIN1/GPIO172 SB_NB_THRMDA 23
AD11 A5 MB_THRMDA_SB R729 0R
51 SATA_ACT# SATA_ACT#/GPIO67 TEMPIN2/GPIO173
3
B5 TEMPIN3
TEMPIN3/TALERT#/GPIO174 C7 TEMP_COMM 1 Q600
TEMP_COMM C700 C697 CMPT3904
To meet SB800 SCL1.02: A3 C662 390pF 390pF
HW MONITOR
VIN0/GPIO175
2
22pF C647 SATA_X1 AD16 B4 390pF
DNI SATA XTAL circuit's parts DNI Y6 SATA_X1 VIN1/GPIO176 A4 TEMP_COMM MB_THRMDC_SB
NC_25MHz VIN2/GPIO177 C5 R723 0R
2 1 R660 VIN3/GPIO178 A7 R676
3 4 1M VIN4/GPIO179 B7 GPIO180
VIN5/GPIO180 0R
DNI B8 10k DNI R709 0R SB_NB_THRMDC 23
22pF C648 Y_5938 SATA_X2 AC16 VIN6/GBE_STAT3/GPIO181 A8 R699 R738R740R758R751R739
DNI SATA_X2 VIN7/GBE_LED3/GPIO182 10K 10K 10K 10K 10K
R775 R777
10K 10K NOTE: ROUTE TEMP_COMM
SPI_DATAIN J5 G27
AS A 10MIL TRACE
SPI_DATAOUT E2 SPI_DI/GPIO164 NC1 Y2
SPI ROM
B SPI_CLK K4 SPI_DO/GPIO163 NC2 B

SPI_CS# K9 SPI_CLK/GPIO162
G2 SPI_CS1#/GPIO165 +3.3VDual
ROM_RST#/GPIO161
R666
0R SB800 A11
R726
20K
TEMPIN3
+3.3VDual D604 SD103AWS +3.3V

2 1 3.3V_SPI
R685: Normal R780 R672 C669 R665 R766

1K 10K 100nF 10K 10K R783
R685
0R U601 10K
1
R666: EXT Programmer SPI_CS# SPI_CS#_SEL 1 8 Q604
SPI_DATAIN 2 CE# VDD 7
3 SO HOLD# 6 SPI_CLK 3 2 SB_PROCHOT#_C
WP# SCK 16 SB_PROCHOT#
4 5 SPI_DATAOUT MMBT3904
GND SI
SST25VF016B-50-4C-S2AF
A A
SST SPI ROM
change to SPI mode

Title
SB8X0-SATA/IDE/HWM/SPI
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
PLACE ALL THE DECOUPLING CAPS ON

THIS SHEET CLOSE TO SB AS POSSIBLE.
+1.1V
+3.3V +3.3V_SB_R U600C VCC_SB_R
78mA Part 3 of 5 790mA WIDTH>=100MIL
R800 120R 100MHZ 2A AH1 SB800 N13 R762 120R 100MHZ 2A
D V6 VDDIO_33_PCIGP_1 VDDCR_11_1 R15 U600E D
Y19 VDDIO_33_PCIGP_2 VDDCR_11_2 N17
VDDIO_33_PCIGP_3
CORE S0
AE5 VDDCR_11_3 U13 C686 C685 C684 C679 C680
C670 C671 C672 C673 AC21 VDDIO_33_PCIGP_4 VDDCR_11_4 U17 1uF 1uF 10uF 100nF 100nF Y14 SB800 AJ2
22uF 100nF 100nF 100nF AA2 VDDIO_33_PCIGP_5 VDDCR_11_5 V12 Y16 VSSIO_SATA_1 VSS_1 A28
PCI/GPIO I/O
AB4 VDDIO_33_PCIGP_6 VDDCR_11_6 V18 AB16 VSSIO_SATA_2 VSS_2 A2
AC8 VDDIO_33_PCIGP_7 VDDCR_11_7 W12 AC14 VSSIO_SATA_3 VSS_3 E5
AA7 VDDIO_33_PCIGP_8 VDDCR_11_8 W18 AE12 VSSIO_SATA_4 VSS_4 D23
AA9 VDDIO_33_PCIGP_9 VDDCR_11_9 +1.1V_CKVDD +1.1V AE14 VSSIO_SATA_5 VSS_5 E25
AF7 VDDIO_33_PCIGP_10 AF9 VSSIO_SATA_6 VSS_6 E6
VDDIO_33_PCIGP_11 382mA VSSIO_SATA_7 VSS_7
AA19 K28 42R_4A B611 AF11 F24
VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K29 AF13 VSSIO_SATA_8 VSS_8 N15
+1.8V VDDAN_11_CLK_2 J28 AF16 VSSIO_SATA_9 VSS_9 R13
VDDAN_11_CLK_3 K26 C724 C723 C627 C676 C688 AG8 VSSIO_SATA_10 VSS_10 R17
CLKGEN I/O
WIDTH>=15MIL VDDAN_11_CLK_4 J21 AH7 VSSIO_SATA_11 VSS_11 T10
71mA VDDAN_11_CLK_5
1uF 100nF 100nF 1uF 22uF
VSSIO_SATA_12 VSS_12
0R R779 VDDIO_18_FC AF22 J20 AH11 P10
FLASH I/O
AE25 VDDIO_18_FC_1 VDDAN_11_CLK_6 K21 AH13 VSSIO_SATA_13 VSS_13 V11
AF24 VDDIO_18_FC_2 VDDAN_11_CLK_7 J22 AH16 VSSIO_SATA_14 VSS_14 U15
C714 C715 C716 C718 AC22 VDDIO_18_FC_3 VDDAN_11_CLK_8 Internal clock generator AJ7 VSSIO_SATA_15 VSS_15 M18
4.7uF 100nF 100nF NC_100nF VDDIO_18_FC_4 at least 30mil and with ferrite bead AJ11 VSSIO_SATA_16 VSS_16 V19
V1 0R R592 External clock generator AJ13 VSSIO_SATA_17 VSS_17 M11
+3.3V VDDRF_GBE_S thick trace and ferrite bead not requied AJ16 VSSIO_SATA_18 VSS_18 L12
POWER VDDIO_33_GBE_S
M10 VSSIO_SATA_19 VSS_19
VSS_20
L18
11mA A9 J7
B600 220R VDDPL_3.3V_PCIE AE28 B10 VSSIO_USB_1 VSS_21 P3
GBE LAN
VDDPL_33_PCIE K11 VSSIO_USB_2 VSS_22 V4
C608 C609 B9 VSSIO_USB_3 VSS_23 AD6
VSSIO_USB_4 VSS_24
PCI EXPRESS
2.2uF 100nF U26 L7 D10 AD4
+1.1V PCIE_VDDR DNI V22 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L9 D12 VSSIO_USB_5 VSS_25 AB7
V26 VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 D14 VSSIO_USB_6 VSS_26 AC9
690mA VDDAN_11_PCIE_3 VSSIO_USB_7 VSS_27
C B601 42R_4A VDDAN_11_PCIE V27 D17 V8 C
WIDTH>=50MIL V28 VDDAN_11_PCIE_4 M6 E9 VSSIO_USB_8 VSS_28 W9
C615 V29 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 P8 F9 VSSIO_USB_9 VSS_29 W10
C610 C613 C614 100nF C699 W22 VDDAN_11_PCIE_6 VDDIO_GBE_S_2 F12 VSSIO_USB_10 VSS_30 AJ28
22uF 1uF 1uF 100nF W26 VDDAN_11_PCIE_7 F14 VSSIO_USB_11 VSS_31 B29
DNI VDDAN_11_PCIE_8 F16 VSSIO_USB_12 VSS_32 U4
+3.3V C9 VSSIO_USB_13 VSS_33 Y18
VSSIO_USB_14 VSS_34
15mA G11
VSSIO_USB_15 VSS_35
Y10
VDDPL_3.3V_SATA AD14 WIDTH>=20MIL +3.3VALW_R +3.3VDUAL F18 Y12
B608 220R 49mA
GROUND
VDDPL_33_SATA A21 D9 VSSIO_USB_16 VSS_36 Y11
C704 AJ20 VDDIO_33_S_1 D21 R677 0R H12 VSSIO_USB_17 VSS_37 AA11
100nF C649 AF18 VDDAN_11_SATA_1 VDDIO_33_S_2 B21 H14 VSSIO_USB_18 VSS_38 AA12
SERIAL ATA
DNI 2.2uF AH20 VDDAN_11_SATA_4 VDDIO_33_S_3 K10 C683 C682 C681 H16 VSSIO_USB_19 VSS_39 G4
3.3V_S5 I/O
+1.1V AG19 VDDAN_11_SATA_2 VDDIO_33_S_4 L10 100nF 2.2uF 2.2uF H18 VSSIO_USB_20 VSS_40 J4
AVDD_SATA AE18 VDDAN_11_SATA_3 VDDIO_33_S_5 J9 DNI J11 VSSIO_USB_21 VSS_41 G8
VDDAN_11_SATA_5 VDDIO_33_S_6 VSSIO_USB_22 VSS_42
1350mA AD18
VDDAN_11_SATA_6 VDDIO_33_S_7
T6 J19
VSSIO_USB_23 VSS_43
G9
B606 42R_4A AE16 T8 K12 M12
VDDAN_11_SATA_7 VDDIO_33_S_8 K14 VSSIO_USB_24 VSS_44 AF25
C653 K16 VSSIO_USB_25 VSS_45 H7
WIDTH>=15MIL +1.1VDUAL K18 VSSIO_USB_26 VSS_46 AH29
C651 C652 1uF C654 C655 115mA
CORE S5
22uF 1uF 100nF 100nF F26 VDDCR_1.1V 0R R781 H19 VSSIO_USB_27 VSS_47 V10
A18 VDDCR_11_S_1 G26 VSSIO_USB_28 VSS_48 P6
A19 VDDAN_33_USB_S_1 VDDCR_11_S_2 VSS_49 N4
A20 VDDAN_33_USB_S_2 M8 15mAWIDTH>=20MIL C678 C677 Y4 VSS_50 L4
VDDAN_33_USB_S_3 VDDIO_AZ_S VDDIO_AZ EFUSE VSS_51
B18 1uF 1uF L8
+3.3VDUAL AVDD_USB B19 VDDAN_33_USB_S_4 A11 VDDCR_1.1V_USB D8 VSS_52
B20 VDDAN_33_USB_S_5 VDDCR_11_USB_S_1 B11 VSSAN_HWM
658mA
USB I/O
C18 VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 WIDTH>=15MIL +1.1VDUAL M19 M20
VDDAN_33_USB_S_7 58mA VSSXL VSSPL_SYS
B602 220R_2A C20 WIDTH>=15MIL B613 220R
C622 D18 VDDAN_33_USB_S_8 M21
47mA
VDDAN_33_USB_S_9 VDDPL_33_SYS VDDPL_3.3V
B C624 C623 C702 10uF_6.3V D19 P21 H23 B
+1.1VDUAL 1uF 1uF 10uF_6.3V D20 VDDAN_33_USB_S_10 L22
62mA C625 C692 C626 P20 VSSIO_PCIECLK_1 VSSIO_PCIECLK_14 H26
VDDAN_33_USB_S_11 VDDPL_11_SYS_S VDDPL_1.1V VSSIO_PCIECLK_2 VSSIO_PCIECLK_15
E19 10uF_6.3V 100nF 100nF M22 AA21
17mA
PLL
VDDAN_33_USB_S_12 F19 M24 VSSIO_PCIECLK_3 VSSIO_PCIECLK_16 AA23

VDDPL_33_USB_S VDDPL_3.3V_USB +3.3VDUAL VSSIO_PCIECLK_4 VSSIO_PCIECLK_17
M26 AB23
B604 220R at least 20mils wide 88MA VDDAN_1.1V_USB C11 D6 5mA P22 VSSIO_PCIECLK_5 VSSIO_PCIECLK_18 AD23
VDDAN_11_USB_S_1 VDDAN_33_HWM_S VDDAN_3.3V_HWM VSSIO_PCIECLK_6 VSSIO_PCIECLK_19
D11 P24 AA26
VDDAN_11_USB_S_2 L20 P26 VSSIO_PCIECLK_7 VSSIO_PCIECLK_20 AC26
VDDXL_33_S
VDDXL_3.3V 5mA B610 220R
VSSIO_PCIECLK_8 VSSIO_PCIECLK_21
C703 C701 T20 Y20
100nF 2.2uF T22 VSSIO_PCIECLK_9 VSSIO_PCIECLK_22 W21
SB800 A11 C611 C689 T24 VSSIO_PCIECLK_10 VSSIO_PCIECLK_23 W20
100nF 2.2uF_6.3V V20 VSSIO_PCIECLK_11 VSSIO_PCIECLK_24 AE26
DNI J23 VSSIO_PCIECLK_12 VSSIO_PCIECLK_25 L21
VSSIO_PCIECLK_13 VSSIO_PCIECLK_26 K20
VSSIO_PCIECLK_27
Part 5 of 5
To meet SB800 SCL1.02: SB800 A11
Separate ferrite bead is not
+1.5VDUAL +3.3VDUAL required for VDDPL_33_USB_S,
Del B603/600ohm bead.
VDDIO_AZ
VDDPL_3.3V +3.3V VDDPL_1.1V +1.1VDUAL VDDPL_3.3V_USB +3.3VDUAL VDDAN_3.3V_HWM
+3.3VDUAL
0R R589 B612 220R WIDTH>=15MIL
B609 220R B607 220R
0R NC_R588
A C748 C674 C675 C690 C696 C629 C630 C664 C668 A
2.2uF 2.2uF 100nF 2.2uF_6.3V 100nF 100nF 2.2uF_6.3V 100nF 2.2uF_6.3V
DNI DNI

Title
SB8X0-POWER & DECOUPLING
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
+3.3VDual +3.3VDual
VDDIO_AZ +3.3V +3.3V +3.3V +3.3V +3.3VDual +3.3VDual
R744
10K
OVERLAP COMMON PADS WHERE R752 R742 DNI R746 R782 R720 R748 R754
POSSIBLE FOR DUAL-OP RESISTORS. 10K 10K 10K 10K NC_10K NC_10K 10K 10K
DNI DNI change to installed INT R756
D 27 AZ_SDATA_OUT D
26 SMSC_CLK DEL JTAG HEADER
26 PCI_CLK2
26 PCI_CLK3
26 PCI_CLK4
26,49 LPC_CLK0
26,47 LPC_CLK1
27 GPIO200
27 GPIO199
R753 R755 R757

10K R743 R745 R747 R719 R721 R749 NC_2.2K 2.2K
NC_10K 10K 10K NC_10K 10K 10K
EXT change to SPI mode
change to NC
REQUIRED AZ_SDOUT SMSC_CLK PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 GPIO200 GPIO199
STRAPS
PULL LOW POWER ALLOW Watchdog USE non_Fusion EC CLKGEN
HIGH MODE PCIE Gen2 Timer DEBUG CLOCK MODE ENABLED ENABLED H,H = Reserved
DEFAULT Enabled STRAP DEFAULT DEFAULT
H,L = SPI ROM
C C
PULL PERFORMANCE FORCE Watchdog IGNORE EC CLKGEN L,H = LPC ROM (Default)
LOW MODE PCIE Gen1 Timer DEBUG FUSION DISABLED DISABLED
CLOCK MODE L,L = FWH ROM
Disabled STRAP
DEFAULT DEFAULT DEFAULT DEFAULT
DEBUG STRAPS
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
B B
26 PCI_AD[27..23]
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
Use 2.2K PD.
R793 R791 R789 R787 R785

2.2K 2.2K 2.2K 2.2K 2.2K
DNI DNI DNI DNI DNI
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
PULL USE PCI DISABLE ILA USE FC USE DEFAULT DISABLE PCI
HIGH PLL AUTORUN PLL PCIE STRAPS MEM BOOT
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

A A
PULL BYPASS ENABLE ILA BYPASS FC USE EEPROM ENABLE PCI

LOW PCI PLL AUTORUN PLL PCIE STRAPS MEM BOOT
Title
SB8X0-STRAPS
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
U4502A
COMPONENTS SHOWN ARE EXAMPLES ONLY
AND NOT NECESSARILY QUALIFIED
TP1
22 GFX_TX0P_C AF30 AH30 PCIE_TXP0 C267 100nF_6.3V

PCIE_RX0P PCIE_TX0P GFX_RX0P_C 22
D
22 GFX_TX0N_C AE31 AG31 PCIE_TXN0 C269 100nF_6.3V D
PCIE_RX0N PCIE_TX0N GFX_RX0N_C 22
22 GFX_TX1P_C AE29 AG29 PCIE_TXP1 C238 100nF_6.3V

TP2 PCIE_RX1P PCIE_TX1P GFX_RX1P_C 22
22 GFX_TX1N_C AD28 AF28 PCIE_TXN1 C239 100nF_6.3V
22 GFX_TX2P_C AD30 AF27 PCIE_TXP2 C242 100nF_6.3V

22 GFX_TX2N_C AC31 AF26 PCIE_TXN2 C243 100nF_6.3V
22 GFX_TX3P_C AC29 AD27 PCIE_TXP3 C244 100nF_6.3V

22 GFX_TX3N_C AB28 AD26 PCIE_TXN3 C245 100nF_6.3V
22 GFX_TX4P_C AB30 AC25 PCIE_TXP4 C256 100nF_6.3V

AA31 AB25 PCIE_TXN4 C258 100nF_6.3V
PCI EXPRESS INTERFACE

22 GFX_TX4N_C PCIE_RX4N PCIE_TX4N GFX_RX4N_C 22
22 GFX_TX5P_C AA29 Y23 PCIE_TXP5 C270 100nF_6.3V

22 GFX_TX5N_C Y28 Y24 PCIE_TXN5 C271 100nF_6.3V
22 GFX_TX6P_C Y30 AB27 PCIE_TXP6 C272 100nF_6.3V

22 GFX_TX6N_C TP3 W31 AB26 PCIE_TXN6 C273 100nF_6.3V
22 GFX_TX7P_C W29 Y27 PCIE_TXP7 C274 100nF_6.3V

22 GFX_TX7N_C V28 Y26 PCIE_TXN7 C279 100nF_6.3V
22 GFX_TX8P_C V30 W24 PCIE_TXP8 C280 100nF_6.3V

TP5 PCIE_RX8P PCIE_TX8P GFX_RX8P_C 22
22 GFX_TX8N_C U31 W23 PCIE_TXN8 C281 100nF_6.3V
22 GFX_TX9P_C U29 V27 PCIE_TXP9 C282 100nF_6.3V

22 GFX_TX9N_C T28 U26 PCIE_TXN9 C283 100nF_6.3V
22 GFX_TX10P_C T30 U24 PCIE_TXP10 C284 100nF_6.3V

22 GFX_TX10N_C R31 U23 PCIE_TXN10 C287 100nF_6.3V
22 GFX_TX11P_C R29 T26 PCIE_TXP11 C289 100nF_6.3V

22 GFX_TX11N_C P28 T27 PCIE_TXN11 C288 100nF_6.3V
22 GFX_TX12P_C P30 T24 PCIE_TXP12 C290 100nF_6.3V

22 GFX_TX12N_C N31 T23 PCIE_TXN12 C291 100nF_6.3V
C C
22 GFX_TX13P_C N29 P27 PCIE_TXP13 C292 100nF_6.3V

22 GFX_TX13N_C M28 P26 PCIE_TXN13 C293 100nF_6.3V
22 GFX_TX14P_C M30 P24 PCIE_TXP14 C295 100nF_6.3V

22 GFX_TX14N_C TP66 L31 P23 PCIE_TXN14 C294 100nF_6.3V
22 GFX_TX15P_C L29 M27 PCIE_TXP15 C300 100nF_6.3V

22 GFX_TX15N_C K30 N26 PCIE_TXN15 C306 100nF_6.3V
TP65 CLOCK
PCIE_REFCLKP AK30
20 PCIE_REFCLKP
20 the
For Park-S3: PCIE_REFCLKN
PWRGOOD pin
PCIE_REFCLKN AK32 PCIE_REFCLKP
PCIE_REFCLKN
must need to pull down to GND
CALIBRATION AND NOT NECESSARILY QUALIFIED
For M9X-S2/S3: This PWRGOOD pin Y22 R75 1.1V_1.0V_PWR
is not connected PCIE_CALRP 1.27K
N10 AA22 R74
PWRGOOD PCIE_CALRN 2.0K
R8185 PERST#_buf AL27

10K PERSTB
M9X-S2/S3 + Park-S3
+3VRUN
R3669
10K
D3613 NC_RB501V-40
1 2 0R
26,27,36,47,48 PCIE_RST#
D3614 NC_RB501V-40
26 PE_GPIO0 1 2
D3615 RB501V-40
23,24,26,49 A_RST# 1 2
Updata on rev:1.1
B B
A A

Title
Park-XT(PCI-E)
D 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
Updata on rev:1.1
U4502B
1.8V_REG
M93-S3/M92-S2 TXCAP_DPA3P
AF2 AND NOT NECESSARILY QUALIFIED
MEM_ID0 AE9 AF4
MEM_ID1 L9 DVCNTL_0/ DVPDATA_18 TXCAM_DPA3N
MEM_ID2 R645 R640 R646 N9 DVCNTL_1 / NC AG3
AE8 DVCNTL_2 / NC TX0P_DPA2P AG5
MEM_ID3
DVDATA_12 / DVPDATA_16 DPA TX0M_DPA2N
10K NC_10K NC_10K AD9
AC10 DVDATA_11 / DVPDATA_20 AH3
AD7 DVDATA_10 / DVPDATA_22 TX1P_DPA1P AH1
AC8 DVDATA_9 / DVPDATA_12 TX1M_DPA1N
D 10K R690 AC7 DVDATA_8 / DVPDATA_14 AK3 D
AB9 DVDATA_7 / DVPCNTL_0 TX2P_DPA0P AK1
AB8 DVDATA_6 / DVPDATA_8 TX2M_DPA0N
DVDATA_0 DVDATA_1 DVDATA_2 10K R689 AB7 DVDATA_5 / DVPDATA_6 AK5
AB4 DVDATA_4 DVPDATA_4 TXCBP_DPB3P AM3
H5TQ1G43BFR_12C 1 0 0 NC_10K R691 AB2 DVDATA_3 / DVPDATA_19 TXCBM_DPB3N
Y8 DVDATA_2 / DVPDATA_21 AK6
K4W1G646E_HC12 0 1 0 Y7 DVDATA_1 / DVPDATA_2 TX3P_DPB2P AM5
DVDATA_0 / DVPDATA_0 TX3M_DPB2N
DPB
AJ7
TX4P_DPB1P AH6
For M93-S3: Install All components in 1.8V_REG DVO TX4M_DPB1N
this Box EXCEPT Decoupling caps and Bead B2701 AK8
connecting to DPC_VDD18# BLM15BD121SN1 C7337 TX5P_DPB0P AL7
(B10095,C6136,C6137,C6140,R6268) C7338 C7339 TX5M_DPB0N
10uF M93-S3/M92-S2
1uF 100nF W6 FOR MXM DESIGN:
1.8V_REG V6 DPC_PVDD / DVPDATA_11
DPC_PVSS / GND M92-S2/M93-S3 PLACE RGB 150 Ohm TERMINATION
V4 RESISTORS CLOSE TO ASIC
AC6 DVPDATA_3/TXCCP_DPC3P U5
For PARK-S3: Install All components in this B2702
DPC_VDD18#1/DVPDAT10 DVPCNTL_2/TXCCM_DPC3N
BLM15BD121SN1 C7341 AC5 R_DAC1
Box INCLUDING Decoupling caps and Bead C7342 C7340 DPC_VDD18#2/DVPDAT23 W3
connecting to DPC_VDD18# 1.1V_1.0V_PWR 10uF AA5 DVPDATA_7 / TX0P_DPC2P V2
(B10095,C6136,C6137,C6140,R6268) 1uF 100nF AA6 DPC_VDD10#1/DVPDAT15 DVPDATA_1 / TX0M_DPC2N G_DAC1
B2703 DPC_VDD10#2/DVPDAT17 Y4
DVPCNTL_MV1 / TX1P_DPC1P W5
BLM15BD121SN1 DVPDATA_9 / TX1M_DPC1N B_DAC1
C7343 C7344 U1 AA3 Update on rev:1.1 1.8V_REG
W1 DPC_VSSR#1 / DVPCLK DVPDATA_13 / TX2P_DPC0P Y2
For M92-S2: DO NOT Install any Component C7345
DPC_VSSR#2 / DVPDAT5 DVPCNTL_1 / TX2M_DPC0N
10uF 1uF U3 R1265 R1266 R1267
in this Box. 100nF Y6 DPC_VSSR#3 / GND AA12 R1268 150R
AA1 DPC_VSSR#4 / GND VDDR4 / DPCD_CALR 150R 150R 150R AVDD
DPC_VSSR#5/ DVPCNTL_MV0 (1.8V@70mA AVDD)
B1
BLM15BD121SN1
DPC C91 C94 C96
10uF 100nF 1uF
43 SCL SCL R1
R3 SCL
43 SDA SDA
SDA I2C
MUST NOT be connected to AVSSQ (1.8V@45mA VDD1DI) VDD1DI
+3VRUN AM26 RB_DAC1 B2
GENERAL PURPOSE I/O R R_DAC1 44
+3VRUN AK26 RB_DAC1 BLM15BD121SN1
R8191 R78 U6 RB C95 C93 C92
36 GPIO0 GPIO_0
4.7K 4.7K U10 AL25 GB_DAC1 10uF 1uF 100nF
36 GPIO1 GPIO_1 G G_DAC1 44
R81 NC_10K GPIO7_BLON R1130 T10 AJ25 GB_DAC1
36 GPIO2 GPIO_2 GB
AC (Performance mode) = 3.3 V 10K R8214 U8
NC_0R
36 PBAT_SMBDAT GPIO_3_SMBDATA
R85 10K Battery saving mode = 0.0 V R8215 U7
NC_0R AH24 BB_DAC1
36 PBAT_SMBCLK GPIO_4_SMBCLK B B_DAC1 44
NC_0 T9 AG25 BB_DAC1 DO NOT INSTALL for M93-S3
49 AC_BAT# GPIO_5_AC_BATT BB
ADD +3VRUN TP231 T8 DAC1 (Use Only for M92-S2/ Park-S3)
C +3VRUN update on rev:1.1 T7 GPIO_6 AH26 TP232 C
36 GPIO5 43 GPIO7_BLON GPIO_7_BLON HSYNC HSYNC_DAC1 44
R1263 TP235 P10 AJ27 TP233
GPIO_8_ROMSO VSYNC VSYNC_DAC1 44
10K GPIO26_TCK +3VRUN P4 (1.8V@2mA A2VDDQ) A2VDDQ
36 GPIO9 GPIO_9_ROMSI
TP236 P2 B3
N6 GPIO_10_ROMSCK AD22 R84 BLM15BD121SN1 C97
36 GPIO11 GPIO_11 RSET
R1261 10K GPIO24_TRSTB N5 AVDD 499R 10uF C90 C89
36 GPIO12 GPIO_12
R1262 10K GPIO25_TDI R528 N3 AG24 100nF 1uF
36 GPIO13 GPIO_13 AVDD
100K TP238 Y9 AE22
R1264 10K GPIO27_TMS N1 GPIO_14_HPD2 AVSSQ VDD1DI
40 GPIO15 GPIO_15_PWRCNTL_0
TP240 M4 AE23
0 R1287 R6 GPIO_16_SSIN VDD1DI AD23
36,49 ThermINT GPIO_17_THERMAL_INT VSS1DI
TP241 W10 (1.8V@40mA VDD2DI) VDD2DI
R1288 NC_0 M2 GPIO_18_HPD3 B4
49 CTF GPIO_19_CTF M92-S2/M93-S3
P8 AM12 BLM15BD121SN1
40 GPIO20
TP237 P7 GPIO_20_PWRCNTL_1 R2 / NC AK12 C86 C87 C88
N8 GPIO_21_BB_EN R2B / NC 10uF 100nF 1uF
36 GPIO22
TP239 N7 GPIO_22_ROMCSB AL11
GPIO_23_CLKREQB G2 / NC AJ11
G2B / NC
AK10
GPIO24_TRSTB L6 B2 / NC AL9
JTAG DEBUG GPIO25_TDI L5 JTAG_TRSTB B2B / NC +3VRUN
PORT GPIO26_TCK L3 JTAG_TDI A2VDD
JTAG_TCK (3.3V@65mA A2VDD)
GPIO27_TMS L1 AH12 B5
K4 JTAG_TMS C / NC AM10
TP69 35mil GPIO28_TDO
JTAG_TDO DAC2 Y / NC
BLM15BD121SN1
R6219 AF24 AJ9 C82 C81 C80
10K TESTEN COMP / NC 10uF 1uF 100nF
+3VRUN R6220 AB13
NC_10K W8 GENERICA AL13
W9 GENERICB H2SYNC AJ13
38 TEST_EN_park 36 GENERICC GENERICC V2SYNC
W7
AD10 GENERICD VDD2DI
GENERICE_HPD4 AD19
1.8V_REG AC14 VDD2DI / NC AC19
HPD1 VSS2DI / NC
NOTE: Designs that do not include an EEPROM must still provide
A2VDD
AE20
access to the ROM interface signals for debug purposes
R82 A2VDD / NC A2VDDQ
220R AE17 NOTE: A 1MBits Serial EEPROM is required on
AC16 A2VDDQ / NC
VREFG AE19
Prototype GDDR5 Designs.
1.8V_REG B6 R83 A2VSSQ
470R_1000mA (1.8V@75mA DPLL_PVDD) DPLL_PVDD 110R C70
100nF AG13 R76
R2SET / NC 715R
C79 C76 C72
10uF 1uF 100nF M92-S2/M93-S3 M92-S2/M93-S3
AE6
DPLL_PVDD PLL/CLOCK DDC1CLK AE5
AF14 DDC1DATA
B AE14 DPLL_PVDD AD2 DDC1 AND AUX1 CAN BE JOINTED TOGETHER FOR DUAL DCC/AUX FUNCTION B
B7 DPLL_PVSS AUX1P AD4 REFER THE DATABOOK FOR DETAIL
(1.0V@125mA DPLL_VDDC) AUX1N
1.1V_1.0V_PWR 470R_1000mA (1.1V@150mA DPLL_VDDC) DPLL_VDDC DDC/AUX
AD14 AC11
DPLL_VDDC DDC2CLK AC13
C83 C85 C84 DDC2DATA DDC2 AND AUX2 CAN BE JOINTED TOGETHER FOR DUAL GPIO22
10uF 1uF 100nF XTALIN AM28 AD13 DCC/AUX FUNCTION
XTALOUT AK28 XTALIN AUX2P AD11 REFER THE DATABOOK FOR DETAIL
XTALOUT AUX2N
AE16
DDCCLK_AUX5P AD16
AC22 DDCDATA_AUX5N
AB22 NC#2/XO_IN AC1
NC#1/XO_IN2 DDC6CLK DDC6CLK 44
AC3
DDC6DATA DDC6DATA 44
Note:1
For M9x-S2/S3 XO_IN and XO_IN2 Pins are NC, can be gronded See note:1 AD20 For M92-S2 these Pins are NC
NC/DDCCLK_AUX3P AC20 For M93-S3/Park-S3: these Pins can be use as DDC_Aux
For Park-S3: XO_IN and XO_IN2 can be use as THERMAL NC/DDCDATA_AUX3N
3.3V CLK Input. These poins can be grounded if not T4
in use. 36 GPU_DPLUS DPLUS
T2
36 GPU_DMINUS DMINUS SERIAL EEPROM 512K/1M
1.8V_REG
(1.8V@20mA TSVDD) TSVDD R5
B8 AD17 TS_FDO
BLM15BD121SN1 AC17 TSVDD
C56 C55 C54 TSVSS
10uF 1uF 100nF M9X-S2/S3 + Park-S3
Note:2
This is an example circuit for clock divider to supply 1.8V
Clock input with 3.3V Clock Oscillator
XTALIN
22pF
1
4 2Y2
27_MHZ 1M
3
XTALOUT
22pF
A Y2 A
y_27m_3225

Title
Park-XT(Main IO)
D 1.0
BM5016
5 4 3 2 1
3 2 1
U4502E
AA27 A3
AB24 PCIE_VSS#1 GND#1 A30
AB32 PCIE_VSS#2 GND#2 AA13
AC24 PCIE_VSS#3 GND#3 / EVDDQ#2 AA16
AC26 PCIE_VSS#4 GND#4 AB10
AC27 PCIE_VSS#5 GND#5 AB15
C AD25 PCIE_VSS#6 GND#6 / EVDDQ#3 AB6 C
AD32 PCIE_VSS#7 GND#7 AC9
AE27 PCIE_VSS#8 GND#8 AD6
AF32 PCIE_VSS#9 GND#9 AD8
AG27 PCIE_VSS#10 GND#10 AE7
AH32 PCIE_VSS#11 GND#11 AG12
K28 PCIE_VSS#12 GND#12 AH10
K32 PCIE_VSS#13 GND#13 AH28
L27 PCIE_VSS#14 GND#14 B10
M32 PCIE_VSS#15 GND#15 B12
N25 PCIE_VSS#16 GND#16 B14
N27 PCIE_VSS#17 GND#17 B16
P25 PCIE_VSS#18 GND#18 B18
P32 PCIE_VSS#19 GND#19 B20
R27 PCIE_VSS#20 GND#20 B22
T25 PCIE_VSS#21 GND#21 B24
T32 PCIE_VSS#22 GND#22 B26
U25 PCIE_VSS#23 GND#23 B6
U27 PCIE_VSS#24 GND#24 B8
V32 PCIE_VSS#25 GND#25 C1
W25 PCIE_VSS#26 GND#26 C32
W26 PCIE_VSS#27 GND#27 E28
W27 PCIE_VSS#28 GND#28 F10
Y25 PCIE_VSS#29 GND#29 F12
Y32 PCIE_VSS#30 GND#30 F14
PCIE_VSS#31 GND#31 F16
GND#32 F18
GND#33 F2
GND#34 F20
M6 GND#35 F22
N11 GND#56 GND#36 F24
N12 GND#57 GND#37 F26
B GND#58 GND#38 B
N13 F6
GND#59 GND#39
GND
N16 F8
N18 GND#60 GND#40 G10
N21 GND#61 GND#41 G27
P6 GND#62 GND#42 G31
P9 GND#63 GND#43 G8
R12 GND#64 GND#44 H14
R15 GND#65 GND#45 H17
R17 GND#66 GND#46 H2
R20 GND#67 GND#47 H20
T13 GND#68 GND#48 H6
T16 GND#69 GND#49 J27
T18 GND#70 GND#50 J31
T21 GND#71 GND#51 K11
T6 GND#72 GND#52 K2
U15 GND#73 GND#53 K22
U17 GND#74 GND#54 K6
U20 GND#75 GND#55 T11
U9 GND#76 GND#85 R11
V13 GND#77 GND#86
V16 GND#78
V18 GND#79
Y10 GND#80
Y15 GND#81
Y17 GND#82 A32
Y20 GND#83 VSS_MECH#1 AM1
GND#84 VSS_MECH#2 AM32
VSS_MECH#3
A A
M9X-S2/S3 + Park-S3

Title
PARK-XT(Core_GND)
B 1.0
BM5016
3 2 1
5 4 3 2 1
MVDDQ
( for DDR2 and GDDR3: 1.8V@2.2A VDDR1) (For DDR3, MVDDQ = 1.5V@2.0A) U4502D
1.8V_REG
MEM I/O
PCIE PCIE_VDDR_PARK (1.8V@500mA PCIE_VDDR) L1
C5994 C5995 C5996 C6015 C5998 C5999 C6002 H13 AB23 220R_2A
1uF 1uF 1uF 1uF 100nF 100nF 100nF H16 VDDR1#1 PCIE_VDDR#1 AC23
H19 VDDR1#2 PCIE_VDDR#2 AD24
J10 VDDR1#3 PCIE_VDDR#3 AE24 C529 C528 C316 C315 C193 C194 C195 C192
J23 VDDR1#4 PCIE_VDDR#4 AE25 100nF 100nF 1uF 1uF 1uF 1uF 1uF 10uF
J24 VDDR1#5 PCIE_VDDR#5 AE26
J9 VDDR1#6 PCIE_VDDR#6 AF25
C6003 C6004 C6005 C6006 C6007 C6008 C6009 C6010 C6011 K10 VDDR1#7 PCIE_VDDR#7 AG26
D
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF K23 VDDR1#8 PCIE_VDDR#8 D
K24 VDDR1#9 1.1V_1.0V_PWR
VDDR1#10 (1.1V@2A PCIE_VDDC)
K9 L23
L11 VDDR1#11 PCIE_VDDC#1 L24
L12 VDDR1#12 PCIE_VDDC#2 L25
L13 VDDR1#13 PCIE_VDDC#3 L26 C524 C527 C514 C511 C545 C544 C512 C520
L20 VDDR1#14 PCIE_VDDC#4 M22 1uF 1uF 1uF 1uF 1uF 1uF 1uF 10uF
L21 VDDR1#15 PCIE_VDDC#5 N22
C6012 C5992 C6013 C5993 C6014 L22 VDDR1#16 PCIE_VDDC#6 N23
10uF 10uF 10uF 10uF 10uF VDDR1#17 PCIE_VDDC#7 N24
1.8V_REG PCIE_VDDC#8 R22
PCIE_VDDC#9 T22 VDDC
VDDC_CT LEVEL PCIE_VDDC#10 U22
SEE DATABOOK FOR REQUIRED EDP
TRANSLATION PCIE_VDDC#11 V22
(1.8V@17mA VDD_CT) PCIE_VDDC#12
B13 AA20
BLM15BD121SN1 AA21 VDD_CT#1 C173 C108 C137 C129 C358 C98 C510 C534 C107
AB20 VDD_CT#2 AA15 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V
C508 C509 C359 C504 C507 AB21 VDD_CT#3 CORE VDDC#1 N15
+3VRUN 10uF 1uF 1uF 100nF 1uF VDD_CT#4 VDDC#2 N17
VDDC#3 R13
M93-S3/M92-S2 VDDC#4 R16
POWER
AA17 VDDC#5 R18
VDDR3#1 VDDC#6
AA18
VDDR3#2 I/O VDDC#7
Y21 C565 C567 C566 C568 C556 C557 C558 C559 C564 C563
AB17 T12 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V
C523 C521 C522 C519 VDDR4 VDDR5 AB18 VDDR3#3 VDDC#8 T15
10uF 1uF 1uF 1uF VDDR3#4 VDDC#9 T17
V12 VDDC#10 T20
Y12 VDDR4#1 / VDDR5 VDDC#11 U13
U12 VDDR4#2 VDDC#12 U16
VDDR4#3 / VDDR5 VDDC#13 U18 C549 C548 C551 C550 C547 C553
VDDR4 AA11 VDDC#14 V21 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V
B14 For M9X-S3/ Park-S3: REMOVE R6274, Y11 NC#1 / VDDR4 VDDC#15 V15
BLM15BD121SN1 R6402,R6284 and INSTALL R8210 DVCLK / VDDR4 VDDC#16 V17
C178 C513 C536 V11 VDDC#17 V20
10uF 1uF 100nF U11 NC#3 / VDDR5 VDDC#18 Y13
NC / VDDR5 VDDC#20 Y16 C561 C560 C555 C552 C554 C546
VDDC#21 Y18 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S
VDDR5 VDDC#22 R21
C C
B16 VDDC#23 /BIF_VDDC U21
BLM15BD121SN1 MEM CLK VDDC#19/BIF_VDDC
C188 C537 C535 L17
10uF 1uF 100nF VDDRHA
L16 ISOLATED
VSSRHA CORE I/O
M13 VDDCI
PCIE_PVDD PLL VDDCI#1 M15
(1.8V@40mA PCIE_PVDD) VDDCI#2
B20 AM30 M16
BLM15BD121SN1 PCIE_PVDD VDDCI#3 M17
VDDCI#4 (0.95V-1.1V@(2-??)A VDDCI)
C191 C311 C308 M18 B23
10uF 1uF 100nF L8 VDDCI#5 M20
SPV10 MPV18 MPV18 VDDCI#6 M21 C7409 C7410 C533 0.9-1.1V @2A (DDR3) ??(GDDR5)
VDDCI#7 N20 C538 C539 C540
H7 VDDCI#8 Warning:Select the correct
SPV18 10uF_X6S 10uF_X6S 1uF 1uF 1uF 10uF_X6S
SPV18 Bead to support expected
C541 C543 C542 H8 VDDCI current. See databook
B2710 10uF 1uF 100nF SPV10 for details.
1.1V_1.0V_PWR SPV10
BLM15BD121SN1 J7
SPVSS
1.0V @100mA
For Park-S3: Connect 1.1V_1.0V_PWR to SPV10 ONLY BACK BIAS
For M9X-S2/S3: Connect VDDC to SPV10 ONLY +BBP M11
R8213 M12 BBP#1
VDDC BBP#2
0R
C181 C174
1uF 100nF
(DNI For M9X-S2/S3) M9X-S2/S3 + Park-S3
(For PARK-S3)
For PARK-S3:BAckBias(BBP#1
(1.8V@90mA SPV18) and #2) is not supported,
B2711 Connect to VDDC Rail
BLM15BD121SN1 SPV18
B B
C1361 C1362
1uF 100nF
B2712
470R_1000mA (1.8V@75mA MPV18)
MPV18
C1363 C1364
1uF 100nF
A A

Title
Park_XT(Power_and_NC)
C 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
1.8V_REG See Databook and Application note table for Voltage and Current requirements for each individual rail.
(1.8V@130mA )
B2713
DPA_VDD18 For M9X-S2/S3 , DPx_VDD10 = 1.1V
For Park-S3, DPx_VDD10 = 1.0V COMPONENTS SHOWN ARE EXAMPLES ONLY
D C7411 C7412 C7413 U4502G 1.1V_1.0V_PWR D
NOTE:4 10uF 1uF 100nF

AND NOT NECESSARILY QUALIFIED
DP E/F POWER DP A/B POWER
AG15 AE11 DPA_VDD18

DPE_VDD18#1 DPA_VDD18#1 Park-S3:110mA@1.0V
DPE_VDD18 AG16 AF11 B2714
(1.8V@20mA ) DPE_VDD18#2 DPA_VDD18#2 M9X-S2/S3:200mA@1.1V
B2715 DPA_VDD10
DPA_PVDD
AG20 AF6 DPA_VDD10 C7417 C7418 C7419
C7414 C7415 C7416 AG21 DPE_VDD10#1 DPA_VDD10#1 AF7
DPE_VDD10 DPE_VDD10#2 DPA_VDD10#2 10uF 1uF 100nF
10uF 1uF 100nF
AG14 AE1
AH14 DPE_VSSR#1 DPA_VSSR#1 AE3
AM14 DPE_VSSR#2 DPA_VSSR#2 AG1
AM16 DPE_VSSR#3 DPA_VSSR#3 AG6
AM18 DPE_VSSR#4 DPA_VSSR#4 AH5
DPE_VSSR#5 DPA_VSSR#5 Park-S3:110mA@1.0V
B2717
M9X-S2/S3:200mA@1.1V
DPB_VDD10
AF16 AE13 DPA_VDD18
AG17 DPF_VDD18#1 DPB_VDD18#1 AF13 C7423 C7424 C7425
DPF_VDD18 DPF_VDD18#2 DPB_VDD18#2
C 10uF 1uF 100nF C
AF22 AF8 DPB_VDD10

AG22 DPF_VDD10#1 DPB_VDD10#1 AF9
DPF_VDD10 DPF_VDD10#2 DPB_VDD10#2
Park-S3: TMDS/DP=110mA@1.0V : LVDS=120mA@1.0V
AF23 AF10 M9X-S2/S3: TMDS/DP=170mA@1.1V LVDS=100mA@1.1V
AG23 DPF_VSSR#1 DPB_VSSR#1 AG9 B2719
DPF_VSSR#2 DPB_VSSR#2 DPE_VDD10
AM20 AH8
AM22 DPF_VSSR#3 DPB_VSSR#3 AM6
LVDS Mode:1.8V@200mA AM24 DPF_VSSR#4 DPB_VSSR#4 AM8 C7429 C7430 C7431
DPF_VSSR#5 DPB_VSSR#5
(DP Mode:1.8V@130mA) 10uF 1uF 100nF
DPE_VDD18
C7432 C7433 C7434 R6227 150R AF17 AE10 R6226 150R

10uF 1uF 100nF DPEF_CALR DPAB_CALR
Park-S3: TMDS/DP=110mA@1.0V : LVDS=120mA@1.0V
M9X-S2/S3: TMDS/DP=170mA@1.1V LVDS=100mA@1.1V
AG18 DP PLL POWER AG8 B2720
DPE_PVDD DPE_PVDD DPA_PVDD DPA_PVDD DPF_VDD10
AF19 AG7
DPE_PVSS DPA_PVSS
B2721 (1.8V@20mA )
DPE_PVDD C7435 C7436 C7437
B 10uF 1uF 100nF B
DPF_PVDD AG19 AG10 DPA_PVDD
C7438 C7439 C7440 AF20 DPF_PVDD DPB_PVDD AG11
10uF 1uF 100nF DPF_PVSS DPB_PVSS
LVDS Mode:1.8V@200mA M9X-S2/S3 + Park-S3

(DP Mode:1.8V@130mA)
DPF_VDD18
NOTE:1: DPx_VDD18 and DPx_PVDD Rails can be join together and remove Decoupling Capacitors and BEAD for DPx_PVDD if
C7441 C7442 C7443
10uF 1uF 100nF signal integrity for DP lanes are OK.
NOTE:2: DPA_VDD10 / DPB_VDD10 and DPE_VDD10 / DPF_VDD10 Rails can be join together and remove Decoupling Capacitors and BEAD
B2722 (1.8V@20mA ) for one rail of each pair if signal integrity for DP lanes are OK. We also need to Change BEAD to minimum 400mA rating.
DPF_PVDD
NOTE:3: DPx_VDD18 Rails can be join together as shown in schematic for Dual -Link DVI or LVDS setting and remove Decoupling
C7444 C7445 C7446
10uF 1uF 100nF Capacitors and BEAD of any one rail of the pair if signal integrity for DP lanes are OK. We need atleast 500mA Bead to support
join rails.
A A
NOTE:4: Do not Install for M9X-S2/S3. INSTALL ONLY for
NOTE:4 PARK-S3. Other Notes can be apply as well. Bitland Information Techonogy Co.,Ltd.
Title
Park-XT(DP Power)
B 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
D D
Refer to the appropriate GPU

Databook for configuration strap
CONFIGURATION STRAPS RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
settings +3VRUN ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, X = DESIGN DEPENDANT
NA = NOT APPLICABLE
THEY MUST NOT CONFLICT DURING RESET
32 GPIO0 GPIO0 R96 NC_3K
STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
32 GPIO1 GPIO1 R97 3K
32 GPIO11 GPIO11 R92 10K TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING X
32 GPIO12 GPIO12 R95 NC_10K PIN STRAPS TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED X
32 GPIO13 GPIO13 R94 NC_10K BIF_GEN2_EN_A GPIO2 PCIE GEN2 ENABLED X
RSVD GPIO8 0
BIF_VGA_DIS GPIO9 VGA ENABLED 0
RSVD GPIO21 0
R102 NC_10K Updata on rev:1.1 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM X
32 GENERICC
ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT X X X
32 GPIO22 R73 NC_10K
VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS X
0
RSVD GENERICC 0
32 GPIO5 GPIO5 R101 NC_10K AUD[1] HSYNC AUD[1] AUD[0] XX
C AUD[0] VSYNC 0 0 No audio function C
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI
+3VRUN AMD RESERVED CONFIGURATION STRAPS

Provide pull-up pads for these straps - but do not populate. GPIOs functions on these signals must
not conflict with the pin strap at Reset
R331 R330 C285
2.2K 2.2K 100nF
+3VRUN H2SYNC GENERICC
Provide pull-up pads for these straps - but do not populate. GPIOs functions on these signals must
not conflict with the pin strap at Reset
U8 C286 2.2nF_50V
R274 0R 8 1
32 PBAT_SMBCLK SCLK VDD GPIO21_BB_EN
+3VRUN R329 0R 7 2
32 PBAT_SMBDAT SDATA D+ GPU_DPLUS 32
R8218 0R
6 3
ALERT D- GPU_DMINUS 32
PCIE_RST# R8219 NC_0R
26,27,31,47,48 PCIE_RST# DNI 5 4 R323 0R
GND THERM MB_THERMB 27
+3VRUN ADM1032ARMZ
R326 0R
ThermINT 32,49
B
R696
Optional External Thermal Sensor R324
R328 B
1
nc_10K 2.2K
Q64 2.2K
3 2 PBAT_SMBCLK
49 PARKXT_CLK
2N7002 +3VRUN
R697
DNI NC_0R
+3VRUN
Updata on rev:1.1
R693
1
nc_10K
Q65
49 PARKXT_DAT 3 2 PBAT_SMBDAT
2N7002
R657
NC_0R
Update on rev:1.1
A A

Title
MINI PCIE SLOT 1,2 (SB)
C 1.0
BM5016
5 4 3 2 1
3 2 1
LVDS Interface
R652 10K
C U4502F C
R653 10K
LVDS CONTROL AB11

VARY_BL BLON_PWM 43
AB12
DIGON DIGON 43
AH20
TXCLK_UP_DPF3P AJ19
TXCLK_UN_DPF3N
AL21
TXOUT_U0P_DPF2P AK20
TXOUT_U0N_DPF2N
AH22
TXOUT_U1P_DPF1P AJ21
TXOUT_U1N_DPF1N
AL23
TXOUT_U2P_DPF0P AK22
TXOUT_U2N_DPF0N
AK24
TXOUT_U3P AJ23
TXOUT_U3N
LVTMDP
AL15
TXCLK_LP_DPE3P TXCLK_L+ 43
AK14
TXCLK_LN_DPE3N TXCLK_L- 43
AH16
B TXOUT_L0P_DPE2P TXOUT_L0+ 43 B
AJ15
TXOUT_L0N_DPE2N TXOUT_L0- 43
AL17
TXOUT_L1P_DPE1P TXOUT_L1+ 43
AK16
AH18
TXOUT_L2P_DPE0P TXOUT_L2+ 43
AJ17
AL19
TXOUT_L3P AK18
TXOUT_L3N
M9X-S2/S3 + Park-S3
To MXM LVDS signals
A A

Title
Park-XT(DPEF_ LVDS)
B 1.0
BM5016
3 2 1
3 2 1
MDA[63..0]
39 MDA[63..0]
MAA[13..0]
39 MAA[13..0]
A_BA0
39 A_BA0
A_BA1
39 A_BA1
A_BA2
39 A_BA2
DQMA#[7..0]
39 DQMA#[7..0]
39 QSA#[7..0]
QSA#[7..0] DDR3 Memory
QSA[7..0]
39 QSA[7..0]
U4502C Interface
MDA0 K27 K17 MAA0
CLKA1 MDA1 J29 DQA_0 MAA_0 J20 MAA1
39 CLKA1 CLKA1# MDA2 H30 DQA_1 MAA_1 H23 MAA2
39 CLKA1# MDA3 H32 DQA_2 MAA_2 G23 MAA3
CLKA0 MDA4 G29 DQA_3 MAA_3 G24 MAA4
39 CLKA0 CLKA0# MDA5 F28 DQA_4 MAA_4 H24 MAA5
39 CLKA0# MDA6 F32 DQA_5 MAA_5 J19 MAA6
MEMORY INTERFACE
RASA0# MDA7 F30 DQA_6 MAA_6 K19 MAA7
C 39 RASA0# RASA1# MDA8 C30 DQA_7 MAA_7 J14 MAA8 C
39 RASA1# MDA9 F27 DQA_8 MAA_8 K14 MAA9
CASA0# MDA10 A28 DQA_9 MAA_9 J11 MAA10
39 CASA0# CASA1# MDA11 C28 DQA_10 MAA_10 J13 MAA11
39 CASA1# MDA12 E27 DQA_11 MAA_11 H11 MAA12
CSA0#_0 MDA13 G26 DQA_12 MAA_12 G11 A_BA2
39 CSA0#_0 MDA14 D26 DQA_13 MAA_13/BA2 J16 A_BA0
MDA15 F25 DQA_14 MAA_14/BA0 L15 A_BA1
CSA1#_0 MDA16 A25 DQA_15 MAA_15/BA1
39 CSA1#_0 MDA17 C25 DQA_16 E32 DQMA#0
MDA18 E25 DQA_17 DQMA_0 E30 DQMA#1
MDA19 D24 DQA_18 DQMA_1 A21 DQMA#2
CKEA0 MDA20 E23 DQA_19 DQMA_2 C21 DQMA#3
39 CKEA0 CKEA1 MDA21 F23 DQA_20 DQMA_3 E13 DQMA#4
39 CKEA1 MDA22 D22 DQA_21 DQMA_4 D12 DQMA#5
WEA0# MDA23 F21 DQA_22 DQMA_5 E3 DQMA#6
39 WEA0# WEA1# MDA24 E21 DQA_23 DQMA_6 F4 DQMA#7
39 WEA1# MDA25 D20 DQA_24 DQMA_7
MDA26 F19 DQA_25 H28 QSA0
MDA27 A19 DQA_26 RDQSA_0 C27 QSA1
MDA28 D18 DQA_27 RDQSA_1 A23 QSA2
MDA29 F17 DQA_28 RDQSA_2 E19 QSA3
MDA30 A17 DQA_29 RDQSA_3 E15 QSA4
MDA31 C17 DQA_30 RDQSA_4 D10 QSA5
MDA32 E17 DQA_31 RDQSA_5 D6 QSA6
MDA33 D16 DQA_32 RDQSA_6 G5 QSA7
MDA34 F15 DQA_33 RDQSA_7
MDA35 A15 DQA_34 H27 QSA#0
MDA36 D14 DQA_35 WDQSA_0 A27 QSA#1
MDA37 F13 DQA_36 WDQSA_1 C23 QSA#2
MDA38 A13 DQA_37 WDQSA_2 C19 QSA#3
MVDDQ = 1.5V FOR MDA39
MDA40
MDA41
C13
E11
A11
DQA_38
DQA_39
DQA_40
WDQSA_3
WDQSA_4
WDQSA_5
C15
E9
C5
QSA#4
QSA#5
QSA#6
DQA_41 WDQSA_6
DDR3 Memory MDA42
MDA43
MDA44
C11
F11
A9
DQA_42
DQA_43
WDQSA_7
H4
L18
QSA#7
NC ODTA0
MDA45 C9 DQA_44 ODTA0 K16 NC ODTA1 ODTA0 39
MDA46 F9 DQA_45 ODTA1 ODTA1 39
MDA47 D8 DQA_46 H26 CLKA0
MDA48 E7 DQA_47 CLKA0 H25 CLKA0#
MDA49 A7 DQA_48 CLKA0B
MDA50 C7 DQA_49 G9 CLKA1
MDA51 F7 DQA_50 CLKA1 H9 CLKA1#
MDA52 A5 DQA_51 CLKA1B
MDA53 E5 DQA_52 G22 RASA0#
PLACE MVREF DIVIDERS MDA54 C3 DQA_53 RASA0B G17 RASA1#
AND CAPS CLOSE TO ASIC MDA55 E1 DQA_54 RASA1B
MDA56 G7 DQA_55 G19 CASA0#
MVDDQ MDA57 G6 DQA_56 CASA0B G16 CASA1#
B MDA58 G1 DQA_57 CASA1B B
MDA59 G3 DQA_58 H22 CSA0#_0
R114 MDA60 J6 DQA_59 CSA0B_0 J22
DQA_60 CSA0B_1 Note 1 : Do not Install for M9X-S2/S3, Install 240 Ohms 0.5% Resistor for PARK-S3.
40.2R MDA61 J1
Ra MDA62 J3 DQA_61 G13 CSA1#_0
MDA63 J5 DQA_62 CSA1B_0 K13
MVREF DQA_63 CSA1B_1
K26 K20 CKEA0
Updata on rev:1.1 J26 MVREFDA CKEA0 J17 CKEA1
R122 C278 MVREFSA CKEA1
Rb 100R 100nF MVDDQ Note: 1 R117 243R
J25 G25 WEA0#
Note 2 :For M9X-S2/S3,J8 Pin Connect to VSS through 240 Ohms(0.5%) resistor.
MVDDQ NC_0R K7 MEM_CALRN0 WEA0B H10 WEA1# For Park-S3,J8 Pin Connect to VSS through 150 Ohms(1%) resistor for DPC_CALR
32 TEST_EN_park R118 Note:3 NC/TESTEN#2 WEA1B
J8 AB16
Note 3 :For M9X-92/93, K7 Pin (NC_MEM_CALRP1) is Not connected.
Note:2 150R R121 MEM_CALRP1/DPC_CALR PX_EN
R119 K25 For PARK-S3, K7 Pin (TESTEN#2) connect to TEST_EN Signal At AF24
40.2R R125 243R MEM_CALRP0
For M9X-S2/S3 Ra Note: 1
L10
DRAM_RST_G DRAM_RST G14
CLKTESTA K8 RSVD#2
DIVIDER RESISTORS DDR2/DDR3 GDDR3 CLKTESTB L7 CLKTESTA G20 MAA13
CLKTESTB RSVD#3 For PARK-S3 only
R123 C307 For M9X-S2/S3 with
MVREF TO 1.8V (Ra) 100R 40.2R Rb 100R 100nF M9X-S2/S3 + Park-S3 DDR3: this pin is
not in use.
MVREF TO GND (Rb) 100R 100R MVDDQ
DRAM_RST 39
R8229
NC_51.1R
For Park-S3 R8226 51R R8227 0R
DRAM_RST_G DRAM_RST QSA#[7..0] QSA#[7..0]
39 QSA#[7..0] 39 QSA#[7..0]
DIVIDER RESISTORS DDR2/DDR3 GDDR3 C7447 C7370 QSA[7..0] QSA[7..0]
39 QSA[7..0] 39 QSA[7..0]
R8228 C7371
MVREF TO 1.8V (Ra) 40.2R 40.2R 68PF 10K NC_100nF NC_100nF ODTA0 ODTA0
39 ODTA0 ODTA1 39 ODTA0 ODTA1
39 ODTA1 39 ODTA1
MVREF TO GND (Rb) 100R 100R
R8199 R8200
NC_51.1R NC_51.1R
A route 50ohms A
single-ended/100ohms diff
and keep short
Use this option ONLY
for Park-S3
Differential for testing and
DNI component for normal operation.

Title
Park-XT(MEM Interface)
C 1.0
BM5016
3 2 1
5 4 3 2 1
MVDDQ
MVDDQ
R216
MDA[63..0] 4.99K U13
38 MDA[63..0]
R224
4.99K U12 M8 E3 MDA30
MAA[13..0] H1 VREFCA DQL0 F7 MDA24
38 MAA[13..0] VREFDQ DQL1
M8 E3 MDA19 F2 MDA29
A_BA0 H1 VREFCA DQL0 F7 MDA17 R190 C347 MAA0 N3 DQL2 F8 MDA27
38 A_BA0 VREFDQ DQL1 A0 DQL3
A_BA1 F2 MDA21 4.99K 100nF MAA1 P7 H3 MDA25
38 A_BA1 DQL2 A1 DQL4
A_BA2 R189 C346 MAA0 N3 F8 MDA20 MAA2 P3 H8 MDA26
38 A_BA2 A0 DQL3 A2 DQL5
4.99K 100nF MAA1 P7 H3 MDA23 MAA3 N2 G2 MDA31
DQMA#[7..0] MAA2 P3 A1 DQL4 H8 MDA16 MAA4 P8 A3 DQL6 H7 MDA28
38 DQMA#[7..0] A2 DQL5 A4 DQL7
MAA3 N2 G2 MDA22 MAA5 P2
QSA#[7..0] MAA4 P8 A3 DQL6 H7 MDA18 MVDDQ MAA6 R8 A5
38 QSA#[7..0] A4 DQL7 A6
MAA5 P2 MAA7 R2 D7 MDA15
QSA[7..0] MAA6 R8 A5 MAA8 T8 A7 DQU0 C3 MDA11
38 QSA[7..0] A6 A8 DQU1
MAA7 R2 D7 MDA3 MAA9 R3 C8 MDA14
D MAA8 T8 A7 DQU0 C3 MDA7 R195 MAA10 L7 A9 DQU2 C2 MDA10 D
MVDDQ MAA9 R3 A8 DQU1 C8 MDA2 4.99K MAA11 R7 A10/AP DQU3 A7 MDA9
MAA10 L7 A9 DQU2 C2 MDA5 MAA12 N7 A11 DQU4 A2 MDA12
CLKA1 MAA11 R7 A10/AP DQU3 A7 MDA0 MAA13 T3 A12/BC DQU5 B8 MDA13
38 CLKA1 CLKA1# MAA12 N7 A11 DQU4 A2 MDA4 T7 A13 DQU6 A3 MDA8
38 CLKA1# R207 MAA13 T3 A12/BC DQU5 B8 MDA1 M7 A14 DQU7
CLKA0 4.99K T7 A13 DQU6 A3 MDA6 R203 C353 A15 MVDDQ
38 CLKA0 CLKA0# M7 A14 DQU7 4.99K 100nF
38 CLKA0# A15 MVDDQ M2 B2
38 A_BA0 BA0 VDD#B2
RASA0# N8 D9
38 RASA0# 38 A_BA1 BA1 VDD#D9
RASA1# M2 B2 M3 G7
38 RASA1# 38 A_BA0 BA0 VDD#B2 38 A_BA2 BA2 VDD#G7
R206 C349 N8 D9 K2
38 A_BA1 BA1 VDD#D9 VDD#K2
CASA0# 4.99K 100nF M3 G7 K8
38 CASA0# 38 A_BA2 BA2 VDD#G7 VDD#K8
CASA1# K2 N1
38 CASA1# VDD#K2 K8 J7 VDD#N1 N9
VDD#K8 38 CLKA0 CK VDD#N9
CSA0#_0 N1 K7 R1
38 CSA0#_0 VDD#N1 38 CLKA0# CK VDD#R1
J7 N9 K9 R9
38 CLKA0 CK VDD#N9 38 CKEA0 CKE VDD#R9 MVDDQ
K7 R1
38 CLKA0# CK VDD#R1
CSA1#_0 K9 R9
38 CSA1#_0 38 CKEA0 CKE VDD#R9 MVDDQ K1 A1
38 ODTA0 ODT VDDQ#A1
L2 A8
38 CSA0#_0 CS VDDQ#A8
K1 A1 J3 C1
38 ODTA0 ODT VDDQ#A1 38 RASA0# RAS VDDQ#C1
CKEA0 L2 A8 K3 C9
38 CKEA0 38 CSA0#_0 CS VDDQ#A8 38 CASA0# CAS VDDQ#C9
CKEA1 J3 C1 L3 D2
38 CKEA1 38 RASA0# RAS VDDQ#C1 38 WEA0# WE VDDQ#D2
K3 C9 E9
38 CASA0# CAS VDDQ#C9 VDDQ#E9
WEA0# 38 CLKA0 L3 D2 F1
38 WEA0# 38 WEA0# WE VDDQ#D2 VDDQ#F1
WEA1# E9 QSA3 F3 H2
38 WEA1# R233 VDDQ#E9 F1 QSA1 C7 DQSL VDDQ#H2 H9
56R QSA2 F3 VDDQ#F1 H2 DQSU VDDQ#H9
QSA#[7..0] 402 QSA0 C7 DQSL VDDQ#H2 H9
38 QSA#[7..0] DQSU VDDQ#H9 DQMA#3 E7 A9
QSA[7..0] R205 C421 DQMA#1 D3 DML VSS#A9 B3
38 QSA[7..0] DMU VSS#B3
56R 10nF DQMA#2 E7 A9 E1
ODTA0 check list 402 402 DQMA#0 D3 DML VSS#A9 B3 VSS#E1 G8
38 ODTA0 38 CLKA0# DMU VSS#B3 VSS#G8
ODTA1 Add a series resistor on the ODTA0 E1 QSA#3 G3 J2
38 ODTA1 and a pull-up resistor on the memory side. VSS#E1 G8 QSA#1 B7 DQSL VSS#J2 J8
QSA#2 G3 VSS#G8 J2 DQSU VSS#J8 M1
120R for dual rank DQSL VSS#J2 VSS#M1
QSA#0 B7 J8 M9
Add a series resistor on the ODTA1 DQSU VSS#J8 M1 VSS#M9 P1
and a pull-up resistor on the memory side. 38 CLKA1 VSS#M1 VSS#P1
M9 38 DRAM_RST T2 P9
R204 VSS#M9 P1 RESET VSS#P9 T1
56R T2 VSS#P1 P9 L8 VSS#T1 T9
38 DRAM_RST RESET VSS#P9 ZQ VSS#T9
402 T1
L8 VSS#T1 T9 R182
ZQ VSS#T9 Should be 240
R212 C420 243R B1
56R 10nF R180 Ohms +-1% VSSQ#B1 B9
402 402 243R B1 VSSQ#B9 D1
38 CLKA1# VSSQ#B1 VSSQ#D1
B9 D8
VSSQ#B9 D1 VSSQ#D8 E2
VSSQ#D1 D8 J1 VSSQ#E2 E8
C VSSQ#D8 E2 L1 NC#J1 VSSQ#E8 F9 C
J1 VSSQ#E2 E8 J9 NC#L1 VSSQ#F9 G1
L1 NC#J1 VSSQ#E8 F9 L9 NC#J9 VSSQ#G1 G9
J9 NC#L1 VSSQ#F9 G1 NC#L9 VSSQ#G9
L9 NC#J9 VSSQ#G1 G9 100-BALL
NC#L9 VSSQ#G9 SDRAM DDR3
100-BALL 23E22387MNG8
SDRAM DDR3
23E22387MNG8
BGA0_8mm10x16-100
MVDDQ MVDDQ
C498 C442 C7380 C7382

C354 C357 C355 C440 C423 C439 C424 C441 C7372 C7373 C7374 C7375 C7376 C7377 C7378 C7379
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_6.3V 10uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_6.3V 10uF_6.3V
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
For PARK-S3 with DDR3: Support MAA13-MAA0 Address or 128KX16 DDR3.

RANK1: 256MB/ 512MB DDR3 MVDDQ MVDDQ
R8201 R8202
4.99K U15 4.99K U16
PARK_XT ENG=750MHZ ,Mem=900MHZ DDR3
M8 E3 MDA34 M8 E3 MDA46
H1 VREFCA DQL0 F7 MDA39 H1 VREFCA DQL0 F7 MDA45
VREFDQ DQL1 F2 MDA33 VREFDQ DQL1 F2 MDA44
R8205 C7383 MAA0 N3 DQL2 F8 MDA37 R8203 C7384 MAA0 N3 DQL2 F8 MDA40
4.99K 100nF MAA1 P7 A0 DQL3 H3 MDA35 4.99K 100nF MAA1 P7 A0 DQL3 H3 MDA43
MAA2 P3 A1 DQL4 H8 MDA38 MAA2 P3 A1 DQL4 H8 MDA42
MAA3 N2 A2 DQL5 G2 MDA32 MAA3 N2 A2 DQL5 G2 MDA47
MAA4 P8 A3 DQL6 H7 MDA36 MAA4 P8 A3 DQL6 H7 MDA41
MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7
MVDDQ MAA6 R8 A5 MVDDQ MAA6 R8 A5
B MAA7 R2 A6 D7 MDA55 MAA7 R2 A6 D7 MDA57 B
MAA8 T8 A7 DQU0 C3 MDA50 MAA8 T8 A7 DQU0 C3 MDA60
MAA9 R3 A8 DQU1 C8 MDA53 MAA9 R3 A8 DQU1 C8 MDA59
R8204 MAA10 L7 A9 DQU2 C2 MDA51 R8206 MAA10 L7 A9 DQU2 C2 MDA62
4.99K MAA11 R7 A10/AP DQU3 A7 MDA52 4.99K MAA11 R7 A10/AP DQU3 A7 MDA56
MAA12 N7 A11 DQU4 A2 MDA49 MAA12 N7 A11 DQU4 A2 MDA61
MAA13 T3 A12/BC DQU5 B8 MDA54 MAA13 T3 A12/BC DQU5 B8 MDA58
T7 A13 DQU6 A3 MDA48 T7 A13 DQU6 A3 MDA63
M7 A14 DQU7 M7 A14 DQU7
R8207 C7385 A15 MVDDQ R8208 C7386 A15 MVDDQ
4.99K 100nF 4.99K 100nF
M2 B2 M2 B2
38 A_BA0 BA0 VDD#B2 38 A_BA0 BA0 VDD#B2
N8 D9 N8 D9
38 A_BA1 BA1 VDD#D9 38 A_BA1 BA1 VDD#D9
M3 G7 M3 G7
38 A_BA2 BA2 VDD#G7 38 A_BA2 BA2 VDD#G7
K2 K2
VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1
J7 VDD#N1 N9 J7 VDD#N1 N9
38 CLKA1 CK VDD#N9 38 CLKA1 CK VDD#N9
K7 R1 K7 R1
38 CLKA1# CK VDD#R1 38 CLKA1# CK VDD#R1
K9 R9 K9 R9
38 CKEA1 CKE VDD#R9 MVDDQ 38 CKEA1 CKE VDD#R9 MVDDQ
qs5/qs6
K1 A1 K1 A1
38 ODTA1 ODT VDDQ#A1 38 ODTA1 ODT VDDQ#A1
L2 A8 L2 A8
38 CSA1#_0 CS VDDQ#A8 38 CSA1#_0 CS VDDQ#A8
J3 C1 J3 C1
38 RASA1# RAS VDDQ#C1 38 RASA1# RAS VDDQ#C1
K3 C9 K3 C9
38 CASA1# CAS VDDQ#C9 38 CASA1# CAS VDDQ#C9
L3 D2 L3 D2
38 WEA1# WE VDDQ#D2 38 WEA1# WE VDDQ#D2
E9 E9
VDDQ#E9 F1 VDDQ#E9 F1
QSA4 F3 VDDQ#F1 H2 QSA5 F3 VDDQ#F1 H2
QSA6 C7 DQSL VDDQ#H2 H9 QSA7 C7 DQSL VDDQ#H2 H9
DQSU VDDQ#H9 DQSU VDDQ#H9
DQMA#4 E7 A9 DQMA#5 E7 A9
DQMA#6 D3 DML VSS#A9 B3 DQMA#7 D3 DML VSS#A9 B3
DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8
QSA#4 G3 VSS#G8 J2 QSA#5 G3 VSS#G8 J2
QSA#6 B7 DQSL VSS#J2 J8 QSA#7 B7 DQSL VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1
T2 VSS#P1 P9 T2 VSS#P1 P9
38 DRAM_RST RESET VSS#P9 38 DRAM_RST RESET VSS#P9
T1 T1
L8 VSS#T1 T9 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9
Should be 240 R181 Should be 240 R234
243R B1 243R B1
Ohms +-1% VSSQ#B1 B9 Ohms +-1% VSSQ#B1 B9
VSSQ#B9 D1 VSSQ#B9 D1
A VSSQ#D1 D8 VSSQ#D1 D8 A
VSSQ#D8 E2 VSSQ#D8 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3
23E22387MNG8 23E22387MNG8
MVDDQ MVDDQ

C7395 C7397 C7406 C7407 C7408 Notebook R&D Division
C7387 C7388 C7389 C7390 C7391 C7392 C7393 C7394 C7398 C7399 C7400 C7401 C7402 C7403 C7404 C7405 Title
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_6.3V 10uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_6.3V 10uF_6.3V 10uF_6.3V Park-XT( DDR3 Memory)
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 Size Document Number Rev
D 1.0
BM5016
5 4 3 2 1
COMPONENTS SHOWN ARE

For M9X-S2/S3 withEXAMPLES ONLYMAA12-MAA0
DDR3: Support AND NOT NECESSARILY QUALIFIED
Address or 64KX16 DDR3. MAA13 is NC
5 4 3 2 1
+VIN
PJ16
3A
VDDC_DCBATOUT 1 2 GPIO20(p8) GPIO15(n1) vddc R top R bot
0.1U_25V_M
+3.3VDual 0 0 0.9V 10Kohm 35Kohm
0603_X5R
1206_X5R
10U_25V_M
1
1
1206_X5R
10U_25V_M
PC181
PC178
PC182
Place these CAPS
close to FETs 0 1 0.95V 10Kohm 35K//140K=28 KOhm
2
5
SIR462DPT1-GE3
2
D
PR134 x x x x x
PQ46
100K_J PJ29
0402 4 G NC_1UH +-20% FDV0630-1R0M=P3 12A
D S D
PL18 1
1 2
2 VDDC 1 1 1.12V 10Kohm 35K//47K//140K=17.5 KOhm
1
1 2
1
2
3
PC180
49 PARK-XT_PGOOD JUMP_43X118
0.1U_25V_M 0.36UH_PCMC104T-R36MN1R17_30A_20%
PJ24
0603_X5R LS2_1040
NC_100P_50V_K
1 2 1 2 VDDC_OUT1 1 2 20A
1
PL19
0402_NPO
1
1
PR130
PC179
330U_2V_7.3x4.3
330U_2V_7.3x4.3
2
0R PR147 D
SIR464DP-T1-GE3
1
PU7 0603 3.3R PR129
1 11 3.3_J Iocp=22A
PQ54
+ +
PC114
PC115
0.1U_6.3V_K
PGOOD GND 0603
2
VDDC_TRIP2 10 VDDC_BST 4 G
0402_X5R
TRIP VBST 0603
2
GPOWER_EN 1 2 VDDC_EN 3 9 VDDC_DH S
EN DRVH
2
VDDC_VFB4 8 VDDC_PHASE
PC119
VFB SW
1
2
3
1
PR128 VDDC_RF5 7 PC118
NC_1U_10V_K
1K_F RF V5IN 6 VDDC_DL 1000P_50V_M

DRVL
0402 1
1
0402
0603_X5R
30K_F
0603_X7R
2
1
1
TPS51218DSCR/TPS51217 +5VDual
PC120
PR135
1
PC183
NC_100K_F
1U_10V_K PC159
2 0402
1K_F
PR127
2
0805_X5R
0402
PR136
2
2
4.7NF update on rev:1.1
1 2
PR125
0402_X5R
2 1 CPU_VDDIO_SUS
MVDDQ
0402 10K_F +3.3VDUAL +3VRUN
U68
2
PR126 SI4800BDY-T1-E3_SO8
2
4
35K PR137 +3VRUN U67 8 1
0402 47K 5 7 2
2
0402 PR138 6 3 6 3
2
140K 7 2 1 1 5
1
2
PC160 PR139 Updata on rev:1.1 1 1 8 1 C2162 C2155 1
0402
3 1
C 100P 10K C2160 C2176 C2179 C

1
1
0402_X5R 0402 10U_0805_10V4Z C496
1
PQ64 D 10U_0805_10V4Z SI4800BDY-T1-E3_SO8 2 2

1U_0603_10V4Z NC_0.1U_50V_K
2N7002-7-F +5VDUAL 2 2
10U_0805_10V4Z 2
10U_0805_10V4Z
1
2
1 GPIO20 32
S G
2
PR145
C2158
2
2
PC161 NC_3K
2
51P PR141 +3.3VDUAL R1793 2 1+3VRUN_GATE

2 1+1_5VRUN_GATE 1 2
0.1U_6.3V_K
0402 +VSB
3
0402_X5R 100K_0402_5% R1800 R1803
0402_X5R
10K
PQ65 D
0402 2 200K_0402_5% 200K_0402_5%
0.1U_0603_25V7K
1
2
2N7002-7-F PC158
D14
1
1 GPIO15 32 R1804 +5VDUAL
1
S G NC_100K_0402_5% 2
2
3
PR144 +3VRUN_GATE 3
2
6
NC_3K PR146 1K_F 0402 1 +1_5VRUN_GATE
0.1U_6.3V_K
1
1 2 Q3636B Q3636A R3691
0402_X5R
0402 49 VDDC_EN_EC
2
NC_RB751V-40D2911 Q3639A 5 100K

1 2 2 2 RUN_EN# BAT54S
PC155
26 PE_GPIO1
1
NC_RB751V-40D2912 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6 +5VDUAL SOT23 Updata on rev:1.1
4
1
27 MXM_PWR_EN 1 2
1
2
3
R1798 2N7002DW-T/R7_SOT363-6
+5VDUAL 100K_0402_5% R1799
R2978 10 100K_0402_5% Q3639B
2N7002DW-T/R7_SOT363-6 5 SLP_S3# 7,9,11,27,49,51
2
GPOWER_EN
1
1
4
@PC166
@ PC166
1U_0402_16V7K Q3640B Q3640A
2
updata on rev:1.1 5 2
2N7002DW-T/R7_SOT363-6
GPOWER_EN1 2 0R R2979 2N7002DW-T/R7_SOT363-6
PARK-XT_PGOOD 49
1
1
PR236 U2909
R1815
2k @PC198
@ PC198 NC_1K_0402_5%
VCNTL
0.22U_0402_16V7K 2 1 1 2 1.1V_1.0V_PWRP 1.1V_1.0V_PWR POWER EXPRESS SUPPORT

EN POK
2
CPU_VDDIO_SUS
UP7717ASU8_PSOP_8 PJ27 PE_GPIO0 MXM RESET H: Enable
B
3
VIN VOUT
6 2.6A 2
2 1
1 PE_GPIO1 MXM POWER ENABLE H: Enable B
1
R1812
1.0V
1
GND1
5 22K_0402_5% @PC205 @
@PC205 @PC206
PC206 JUMP_43X118
GND
NC 7 1 2 22U_0402_16V7K @PC195
@ PC195
NC_22U_0402_16V7K
FB
2
2
1
NC_0.1U_0402_16V7K +5VDUAL
PC165
2
1
<DEVICE> PC200 @ R2985 10

8
22U_1206_6.3V R1814 1 2
2
1
80.6K_0402_5%
@PC167
@ PC167
27P_0402_16V7K 1U_0402_16V7K
2
2
@
+3.3VDUAL
1
1
MVDDQ +3VRUN VDDC R1820
1
10K_0402_5% R1818
6
NC_1K_0402_5% U2905 @PC204 <DEVICE>
22U_1206_6.3V
VCNTL
2
2
R2986 0R 7 5 1.8V_REG
49 PARK-XT_PGOOD POK VIN
2
R3067 R3068 R3069 +1.8VP_REG 2A

100R 100R 100R PJ28
+5VDUAL MVDDQ 3 2 1
APL5912 VOUT1 4 2 1
VOUT R1816
3
1
8 PC203 JUMP_43X118
GND
D13 EN
vin1
Q3043 Q3044 Q3045 2 1 2 @ @PC202
@ PC202
<DEVICE>
R2984 10K 1 FB NC_0.1U_0402_16V7K
22U_1206_6.3V
PC163
2
1
1 1 1 3
15K_0402_5%
1
9
1
R3074 2N7002E 2N7002E 2N7002E GPOWER_EN R2993 0 2 R2992 R1817 1 2

10k @PC196
@ PC196 10K 12K_0402_5%
2
0.1U_0603_16V7K
BAT54S 68P_0402_16V7K
2
2
SOT23 update rev:1.1 @
Power Ctrl in Power Xpress mode

3
A Q3050 1.1V_1.0V_PWR 1.8V_REG A
GPOWER_EN
R2991 0R 1
2N7002E
R3070 R3072
2
100R 100R
3
Q3046 Q3047
1 1
FOR EG discharge 2N7002E 2N7002E Notebook R&D Division
Title
Park-XT(VDDC/MVDDQ/18REG)
2

C 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
SATA HDD Conn.

JSATA1
1
2 GND1
D 28 SATA_TX0+_C 3 HTX+ D
28 SATA_TX0-_C 4 HTX-
C635 10nF 5 GND2
28 SATA_RX0-_C HRX-
C644 10nF 6
28 SATA_RX0+_C HRX+
7
+3.3V GND3
R1727 NC_0R 8
9 VCC3.3_1
10 VCC3.3_2
+5V C1718 C1717 C1719 11 VCC3.3_3
NC_10uF NC_100nF NC_100nF 12 GND4
13 GND5
14 GND6
15 VCC5_1
C1721 C1720 C1722 16 VCC5_2
10uF 100nF 100nF 17 VCC5_3
R1726 0R 18 GND7
19 RESERVED
20 GND8 24
21 VCC12_1 GND11
22 VCC12_2 23
* Optional: immdiate spin up disable VCC12_3 NC2
C Need device to support C
C166D3-12204-L
sata_ld2122_srjl6
To support Mobile SATA ODD CONN@
through cable
SATA ODD_13P
2
S1
NPTH3
S2
28 SATA_TX1+_C S3
PTH2
28 SATA_TX1-_C S4
C638 10nF S5
28 SATA_RX1-_C
C639 10nF S6
28 SATA_RX1+_C
S7
P1
P2
P3
B
+5V P4 B
P5
P6
PTH1
NPTH4
C1727 C1728 C1726
10uF 100nF 100nF CN23
1
R1729
1K
suyin_127382fb
A A

Title
SATA HDD /ODD
B 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
+3.3V MIC2-VREFO R671 1 2 2.2K_J
1
C590 C575
1U_10V_K 0.1U_6.3V_K
1 2 MIC1
2
R313 0R 0805 220R-100MHZ_0603
1
C580 C573 C571 MIC2_R C764 1 2 L73 INT_MIC 1
1
C5193 10U_6.3V_M 0.1U_6.3V_K 0.1U_6.3V_K 2.2U_16V_K 2
NC_EGA10603V05A1-B
0.1U_10V_K A_GND
2
+5V MIC2_L C765 1 2 .
2
D +3.3V D
Layout Note: 2.2U_16V_K 0
2
C351 C577 R688 1 2
+3.3VDUAL 1 2
Place bypass caps very close to device.
10U_6.3V_M 0.1U_6.3V_K
VR4
1
R321 NC_00805 C883
2
1
1
1 2 C352 C579
0.1UF_50V_K
1
R310 0R 0805 10U_6.3V_M 0.1U_6.3V_K
2
1
1
+3.3V C591 C581
2
2
1U_10V_K 0.1U_6.3V_K A_GND
+3.3VDUAL 1 2 R302 A_GND
2
R322 NC_00805 0R FOX_JA9333L_B5S7_7F
0805 AUDIO JACK CONN_6P
1 2 Updata on rev:1.1 CN27
1
R318 0R 0805
2.5A MAX
1
1
C578 C582 R717 only needed if supply to VAUX_3.3 is 6
10U_6.3V_M 0.1U_6.3V_K CLASSD_5V HP_FRONT_L R815 1 2 4.9_J L87 220R-100MHZ_0603 HP_JACKL 1
removed during system re-start. 2
2
FILT_1.8V HP_FRONT_R R727 1 2 4.9_J L88 220R-100MHZ_0603 HP_JACKR 3
HP
1
C593 HP_DET 5
1
1
C576 C583 0.1U_6.3V_K C585 C584 C570 C572 C830 4
1
R717 10U_6.3V_M 0.1U_6.3V_K 0.1U_6.3V_K 0.1U_6.3V_K 10U_6.3V_M 10U_6.3V_M +3.3V C882
1000P_50V_K
NC_EGA10603V05A1-B
NC_EGA10603V05A1-B
NC_EGA10603V05A1-B
PTH2
PTH1
NPTH2
NPTH1
2
1000P_50V_K
2
8
7
10K_F
2
A_GND
2
2
18
26
29
27
28
12
15
17
3
2
7
2
U509
VR10
VR14
R679
VR12
27 AZ_RST#_CD
AVDD_HP
AVDD_5V
CLASSDREF
FILT_1.8
VAUX_3.3
VDD_IO
DVDD_3.3
FILT_1.65
AVDD_3.3
LPWR_5.0
RPWR_5.0
5.11K_F
1
C762 1 2 0402_NPO
1
NC_22P_50V_K_N 9
RESET#
1
Updata on rev:1.1
R1655 1 2 39.2K_FHP_DET
27 AZ_BIT_CLK_CD R680 2 0R 1 0402 5 36 SENSE_A
8 BIT_CLK SENSE_A R1656 1 2 10K_F MIC_DET
27 AZ_SYNC_CD SYNC
27 AZ_SDATA_IN0 R683 2 39_J 1 0402 SDATA_IN 6 SENSE_A
4 SDATA_IN FOX_JA9333L_B5S7_7F
27 AZ_SDATA_OUT_CD SDATA_OUT AUDIO JACK CONN_6P
C763 1 2 0402_NPO CN20
C NC_22P_50V_K_N 35 MIC2_R C
PORTB_R 34 MIC2_L 6
PORTB_L 33 MIC2-VREFO MIC_JACKL_LC880 1 2 R8181 2 100_F L89 220R-100MHZ_0603 MIC_JACKL 1
B_BIAS 2.2U_16V_K 2
PCBEEP 10
39
PC_BEEP C_BIAS
PORTC_R
32
31
30
MIC1_VREFO
MIC_JACKR_L
MIC_JACKL_L
MIC_JACKR_LC824 1 2
2.2U_16V_K
R8221 2 100_F L79 220R-100MHZ_0603 MIC_JACKR
MIC_DET
3
5
4
Mic
NC_S PORTC_L
1
C831 C881
NC_EGA10603V05A1-B
NC_EGA10603V05A1-B
PTH2
PTH1
NPTH2
NPTH1
38 MIC1_VREFO R767 1 2 2.2K_J
1000P_50V_K
1000P_50V_K
NC_EGA10603V05A1-B
GPIO0/EAPD#
8
7
MUTE_AMP# R678 2 0R 1 0402 EAPD 37
GPIO1/SPK_MUTE#
2
R768 1 2 2.2K_J A_GND
2
25
NC_DR
2
24
VR11
VR9
NC_DL
VR13
23 HP_FRONT_R
PORTA_R
1
40 22 HP_FRONT_L
DMIC_CLK PORTA_L
1
1
DMIC_1/2 21 AVEE
AVEE 20
FLY_N 19 C592 1 2 Updata on rev:1.1
FLY_P
EP_GND
1
1U_10V_K C589 C574
RIGHT+
RIGHT-
LEFT+
LEFT-
0.1U_6.3V_K 10U_6.3V_M
2
CX20671-11Z
SPEAKER
11
13
14
16
41
INT_SPK_R+
A_GND JSPK3
INT_SPK_R- INT_SPK_R+ R715 1 2 0R 0603 INT_SPK_R+_CN 1 5
INT_SPK_L- INT_SPK_R- R713 1 2 0R 0603 INT_SPK_R-_CN 2 1 G1 6
INT_SPK_L+ INT_SPK_L+ R712 1 2 0R 0603 INT_SPK_L+_CN 3 2 G2
INT_SPK_L- R716 1 2 0R 0603 INT_SPK_L-_CN 4 3
4
C821 1000P_50V_J 0402_NPO
C812 1000P_50V_J 0402_NPO
C822 1000P_50V_J 0402_NPO
C818 1000P_50V_J 0402_NPO

HEADER_4P
NC_EGA10603V05A1-B
NC_EGA10603V05A1-B
NC_EGA10603V05A1-B
NC_EGA10603V05A1-B
1
B B
2
2
2
VR18
VR17
VR16
VR15
C350
MUTE_AMP#
PCBEEP 1 2 D28 2 10 R1660 1 2 33_J BEEP# 49
1
0402
3
D27 2 10 R1661 1 2 100_J SB_SPKR 27

0.1U_6.3V_K 0402 Q39 D
2N7002-7-F
1
C766 1 R750 1 0R 2 0402 AMP_SHDW 49

NC_100P_50V_K R1667 R1662 R1650 S G
2
0402_X7R 10k 0402 0402

2
1 2
NC_4.7K_J NC_4.7K_J R673 Updata on rev:1.2 update on rev:1.1

0402
10K_J
2
update rev:1.1 R1646 0402

0R
1
0402
2
C848
1
0402_NPO 20.1U_50V_J
C851
A_GND GND
GP7
CLOSE_JUMP_40X50 1
0402_NPO 2NC_1000p_50V_J
1 2
C852
Updata on rev:1.1
GP6 1
0402_NPO 2NC_1000p_50V_J
CLOSE_JUMP_40X50 Reserved for EMI
1 2
C853
A GP5 A
CLOSE_JUMP_40X50 1
0402_NPO 2NC_1000p_50V_J
1 2
A_GND

Title
Audio (CODEC HP MIC)
C 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
CN5
+VIN BOARD SIDE CONN_40P
AS BM5959 CNS40_LCD_R1
+VIN R433
F2 L41 0R
1 2 DCBATOUT_L 1 2 LCDVCC_R 2 1 LCDVCC
3 1 2 4
3 4
1
2
C599 C620 32V_1A_0603 330R-100MHZ_0805 5 6 C587
5 6
1
1U_25V_M_B 0.1U_50V_K_B C612 C619 7 8 33P_50V_J C588
D
33P_50V_J 0.1U_50V_K_B L_CLKIN- 9 7 8 10 0.1U_10V_K D
9 10
2
1
L_CLKIN+ 11 12
11 12
2
13 14
L_RXIN0- 15 13 14 16
L_RXIN0+ 17 15 16 18
19 17 18 20
L_RXIN1- 21 19 20 22 +3.3V
L_RXIN1+ 23 21 22 24
25 23 24 26 +3.3V
L_RXIN2- 27 25 26 28
R278 R0402 NC_0R L_RXIN0+ R304 R0402 0R L_RXIN2+ 29 27 28 30
23 NB_LVDS_TX_L0P TXOUT_L0+ 37 29 30 1
R283 R0402 NC_0R L_RXIN0- R307 R0402 0R +V5AL_CAM 31 32 DISPOFF# 0_0402_5% C1911
23 NB_LVDS_TX_L0N TXOUT_L0- 37 31 32
USB20_CMOS_N6 33 34 1R1632 2
33 34 EC_LCD_BKL_PWM 49
R286 R0402 NC_0R L_RXIN1+ R308 R0402 0R USB20_CMOS_P6 35 36 DDCCLK NC_0_0402_5% 0.1U_0402_16V4Z
23 NB_LVDS_TX_L1P
R287 R0402 NC_0R L_RXIN1- R315 R0402 0R
TXOUT_L1+ 37 1.5A 37 35 36 38 DDCDATA 1R1633 2 2
23 NB_LVDS_TX_L1N TXOUT_L1- 37 37 38 BLON_PWM 37
39 40 NC_0_0402_5%
R289 R0402 NC_0R L_RXIN2+ R316 R0402 0R 39 40 1R1649 2
41
42
23 NB_LVDS_TX_L2P TXOUT_L2+ 37 NB_LCD_BKL_PWM 23
R299 R0402 NC_0R L_RXIN2- R317 R0402 0R
23 NB_LVDS_TX_L2N TXOUT_L2- 37
41
42
2
23 NB_LVDS_TX_CLKLP R300 R0402 NC_0R L_CLKIN+ R319 R0402 0R
23 NB_LVDS_TX_CLKLN TXCLK_L+ 37
R303 R0402 NC_0R L_CLKIN- R320 R0402 0R C586
TXCLK_L- 37
0.1U_10V_K
1
R567 1 2 0_EG DDCCLK
32 SCL
R568 1 2 0_EG DDCDATA
32 SDA
R565 1 2 0_IG DDCCLK
23 NB_LCD_DDC_CLK
R177 R0402 0R R566 1 2 0_IG DDCDATA
23 NB_LCD_DDC_DATA +3.3V
C C
R188 R0402 0R
CHK7
4 3 USB20_CMOS_P6
27 USBP5
1 2 USB20_CMOS_N6
27 USBN5 D18
D9 D10 2
nc_90ohm@100MHz,0.5A
1
DDCCLK 3
L4_0805
EGA10603V05A1-B EGA10603V05A1-B 1
ns ESDPAD_R0603 ESDPAD_R0603
ns ns
BAT54S
2
SOT23
GND
D26
2
DDCDATA 3
+3.3V 1
BAT54S
SOT23
U33
5
1 GND
49 BKOFF#
4 DISPOFF#
2
74AHC1G08DBV EC_LCD_BKL_PWM 1 2
3
0_IG C1907 220P_0402_50V7K

R167 R0402 DISPOFF# 1 2
23 NB_LCD_BKL_EN
0_PARK-S3 C1909 220P_0402_50V7K
R176 R0402
32 GPIO7_BLON
B B
+3.3VDUAL +3.3V
+5VDUAL R178
R434 47K C235
2 NC_0R1 Q20 SOT23 +V5AL_CAM 0.1uF/10V,X5R
R0402
4
+5V 2307 47K C0402
S
R435 500mA R135 R0402 3 G .
2 0R 1 2 3
S
LCDVCC D Q21
AO6409
1 G
Updata on rev:1.3 R168 C200 C237 TSOP6_0D95_1D6
5
6
2
1
10K 0.1uF/10V,X5R 0.1uF/25V,Y5V LCDVCC
R0402 C0603 R305 C0402
10K . 100 . 500mA
R174 R0402 Updata on rev:1.3
R0603
3
Q22
D
Q11 2N7002 Q23
2N7002 C260 R633 1 2 0_IG SOT23 2N7002
23 NB_LCD_PWR_EN
1 0.1uF/10V,X5R R636 1 2 0_PARK-S3 1 1 SOT23 C236
49 CAM_PWRON G 37 DIGON
S SOT23 C0402 0.1uF/10V,X5R
. C0402
2
R175 C201 R179 .

A 100K NC_0.1uF/25V,Y5V 100K A
R0402 C0402 R0402
.
Q21 2N7002DW Q13 Q14 2N7002 C185

1022

Title
LVDS CON
C 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
D D
CRT Connector +5V W=40mils

+R_CRT_VCC +CRT_VCC
D38 F1 W=40mils
3
+3.3V 1 2 1 2
D8 D11 D12 1N5819 1.1A_6VDC_FUSE

BAT54S BAT54S BAT54S SOD123 1
1 1 1 SOT23 SOT23 SOT23
2
Based on ref136 EACH ESD SUPPRESSION COMPONENT IS D C1927 C1930 C1933 C1914
decoupled with at least one 100nf to 470nf ceramic capacitor 0.1U_0402_16V4Z
100NF_0402_50V8J100NF_0402_50V8J100NF_0402_50V8J 2
2 2 2
JCRT1
6
CRT_R L900 47nH 1 2 CRT_R_2 11 RGND
L61 47NH_0805 1 ID0
7 Red
CRT_G L904 47nH 1 2 CRT_G_2 12 GGND
L63 47NH_0805 2 SDA
8 Green
CRT_B L902 47nH 1 2 CRT_B_2 13 BGND
L65 47NH_0805 3 Hsync
Blue
1
9
R1625 R1626 R1627 14 +5V
When use IG R1625 140 C1937
1 1
C1939 C1938
1
C1918
1 1
C1919 C1920
1 change to 82nH based
1 on e698 1 1
4 Vsync
When use EG R1625 150 140_0402_1% C1921 C1922 C1923 10 res
R1659 SGND
150_0402_1% 5.6P_0402_50V8J
5.6P_0402_50V8J 5.6P_0402_50V8J NC_5P_0402_50V8JNC_5P_0402_50V8J NC_5P_0402_50V8J 15
SCL
2
2 2 2 2 2 2 2 2 2 1 2 5
150_0402_1% 6P_0402_50V8J GND1
6P_0402_50V8J 6P_0402_50V8J GM@ GM@ GM@ 16
0_0402_5% 17 GND2
C 1 C
C1924 GND3
1 2 CRT_HSYNC_2
L4 27NH_0603_5% DZ11A91-SB261-7F
2 CONN@
+CRT_VCC 1 2 CRT_VSYNC_2 100P_0402_50V8J
1 2 L5 27NH_0603_5% 1 1 DSUB_12 fox_dz11a9_sb1dd
C1934 0.1U_0402_16V4Z C1926
1 2 C1925 1
C1928 0.1U_0402_16V4Z 4.7P_0402_50V8J 4.7P_0402_50V8J
2 2
U48 DSUB_15
CRT_HSYNC 2 5 C1936 2
A VCC R1657
100P_0402_50V8J 1
1 CRT_HSYNC_1 1 2
CE# C1929
3 4 100Pf_0402_50V8J
GND Y 27_0402_5% 2
74AHCT1G125 +CRT_VCC change to 12p based on reference video cicuit
SOT23_5 add two resisitance
Place closed to chipset R1663 AND R1664 pull-up 10k on park xt
+3.3V +3VRUN
U47 +CRT_VCC
2
CRT_VSYNC 2 5
A VCC R1666 R1665
1 IG_0_0402_5% EG_0_0402_5%
CE# R1658
3 4 1
CRT_VSYNC_1 2
GND Y
1
2
1
2K_0402_5%
74AHCT1G125 27_0402_5%
1
R1653 R1651
SOT23_5 2K_0402_5% 0_0402_1%_N11M
R1663 R1648 1 2
DDC6DATA 32
1
R1636 1 2 NC_30.1_0402_1%_IG 10K_0402_5%
23,24 VSYNC#
33_0402
G
GM@
2
R1644 1 GM@ 2 NC_30.1_0402_1%_IG R1668 1
DSUB_12 2 3 2
23,24 HSYNC#
S
B B
GM@ GM@ R1654 NC_0_0402_5%_IG
2 1
Q112 DAC_SDAT 23
R1635 1 2 CRT_VSYNC
30.1_0402_1%_N11M 2N7002
32 VSYNC_DAC1 R1664
SOT23 GM@
1
R1637 1 GM@ 2 CRT_HSYNC
30.1_0402_1%_N11M 1 2
32 HSYNC_DAC1
33_0402
G
GM@ R1669 1
DSUB_15 2 3 210K_0402_5% 2 1
DDC6CLK 32
R1652
S
GM@ 0_0402_5%-N11M
NC_0_0402_1%_IG
GM@
R1638 1 2 0_0402_5%_N11MCRT_B Q113 R1647 1 2
32 B_DAC1 Updata on rev:1.2 2N7002 DAC_SCL 23
R1640 1 GM@ 2 0_0402_5%_N11MCRT_G
Place closed to chipset SOT23
32 G_DAC1 GM@
R1641 1 GM@ 2 0_0402_5%_N11MCRT_R +CRT_VCC

32 R_DAC1
GM@
D16 D19
R1639 1 2 NC_0_0402_5%_IG 2 2
23 NB_VGA_B DSUB_12 3 3CRT_HSYNC_2
R1642 1 GM@ 2 NC_0_0402_5%_IG 1 1
23 NB_VGA_G
R1643 1 GM@ 2 NC_0_0402_5%_IG
23 NB_VGA_R BAT54S BAT54S
GM@ SOT23 SOT23
GND
GND
D17 D20
2 2
DSUB_15 3 3 CRT_VSYNC_2
A 1 1 A
BAT54S BAT54S
SOT23 SOT23
GND GND

Title
CRT
C 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
+3.3V
0.5A 220R-100MHZ_0603
+3.3V_S4 L74 C666
D NC_220R-100MHZ_0603 0.1uF/10V,X5R_BT D
L75 BT_CN1 C0402 R492 1 0_BT 2 R0603
1
87213-0800_BT
680P_50V_K
1
1
C390 C650 foxconn_hs6208e R491 1 0_BT 2 R0603
0603_X7R
2.2U_6.3V_M
1000pF/50V,X7R_BT CHK6
2
Updata on rev:1.3 0402_X5RC0402 NC_90ohm@100M0.33A
C393
1
2
l4_0805
2 3 4
3 USBP7 27
2 1
9 4 USBN7 27
10 5 BT_ACTIVE 47,49
6
2
Updata on rev:1.1
7 R0402
8 100K_BT
2 R445 1 2 R444 1 R486
BT_LED 47,51
NC_0 0
1
R0402 R0402
3
Q35
2N7002
BT En/Disable
1 SOT23
.
2
R442
100k
R0402
BLUE TOOTH
1
C C
BT Status LEDBlueToothLED
2010-5-20 update on rev:1.1
30mA +3.3V R439

0R
R437 +3.3V_S4 2 1
C392 2 NC_0R1
0.1uF/10V,X5R +3.3V_S4
C0402 R438 +3.3VDUAL Q24 SOT23
2 0R 1 NC_2307
2 0_J_FP 1
7
. CN11 500mA
R805 2 3
D
+3.3V_fp 6
SMDFIX1
NC_90R-100MHZ_0R35 5
1 G
4 3 USB_PP6_F 4 R202 C395
27 USBP6
1 2 USB_PN6_F 3 NC_10K NC_0.1uF/10V,X5R
27 USBN6
2 Finger Print C0603
L77 R0402
1 NC_10K .
1
2 1 R272 R0402
0_J_FP
SMDFIX2
ESD10 ESD9
R778 EGA1-0603-V05
3
EGA1-0603-V05 HEADER_6P_FP
8
ESDPAD_R0603 ESDPAD_R0603 D
Q12
NC_2N7002 C391
B update on rev:1.1 update on rev:1.1 FOXCONN_GB5RF060_1203_7F 2 1 1 NC_0.1uF/10V,X5R B
9,11,27,46 SLP_S5#
2
NC_0_J_FP G
S SOT23 C0402
need to be changed R786 .
2
C394 R211
NC_0.1uF/10V,X5R
NC_100K
C0402 R0402
.
Updata on rev:1.3
A A

Title
FP / BT / CIR
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
+5VDUAL
+5VDUAL
13
CN37
1
SMDFIX1
R728 1 2 0R C833 C834 1

0402 0.1U_16V_Y_Y 0.1U_16V_Y_Y 2
2
0402 0402 3
4
D R735 1 2 NC_0 5 D
9,11,27,49 SLP_S5#
0402 USB_PP4 6
27 USBP3
USB CON. 27 USBN3

USB_PN4 7
8
USB_PWR_EN_R
27 USB_OCP3# 9
C843 USB_PWR_EN_R 10
11
0402 0.1U_16V_Y_Y 12
1 2 SMDFIX2
+5VDUAL
FPC_12P
14
U27
1 8 USB_VCC1 USB_VCC1
2 GND OUT_3 7
3 IN_1 OUT_2 6
IN_2 OUT_1
1
C844 4 5 USB_OCP1# 27
1U_25V_M_B EN(EN#) OC#
0603 G545B2P8U_1.5A_Low
2
C842
1 2
0402 0.1U_16V_Y_Y
U28
1 8 USB_VCC0 USB_VCC0
2 GND OUT_3 7
R736 1 2 NC_0 3 IN_1 OUT_2 6
49 USB_PWR_EN IN_2 OUT_1 USB_OCP0# 27
0402 4 5
EN(EN#) OC#
G545B2P8U_1.5A_Low
C C
del R730
USB_VCC0
0R
5
R722 1 2 0603 CN18
L80 PTH1
USB_VCC0_R 1 VCC NPTH1
7
USB_PN0 1 2 USB_VD0-_F 2
27 USBN0 V-
USB_PP0 4 3 USB_VD0+_F 3
27 USBP0 V+
4 GND NPTH2
8
1
CAP8 C839 C837

NC_90R-100MHZ_0R35 PTH2
1
47U_6.3V_3528 + 0.1U_16V_Y 470P_50V_K_B C841
1
R732 1 1206
0R 2 6TPC47MB 0402_Y5V 0402_X7R D31 0.1U_16V_Y 020173MR004G565ZR
2
6
0603 NC1 0402_Y5V FL-5988
2
2
NC2
4 NC_RSB12JS2
6
del R733
1
1
C845 C846
NC_5P_50V_K_B NC_5P_50V_K_B
USB_VCC1 0402_X7R 0402_X7R
2
2
B B
R724
5
1 0R 2 0603 CN19
L78 PTH1
USB_VCC1_R 1 VCC NPTH1
7
USB_PN1 4 3 U_VD1-_F 2
27 USBN1 V-
USB_PP1 1 2 U_VD1+_F 3
27 USBP1 V+
4 GND NPTH2
8
1
CAP13 C838
NC_90R-100MHZ_0R35 PTH2
1
47U_6.3V_3528 + 470P_50V_K_B C840

3
1 1206 2 0603
0R 6TPC47MB 0402_X7R D30 0.1U_16V_Y 020173MR004G565ZR
1
6
R725 NC1 0402_Y5V FL-5988
2
NC2
NC_RSB12JS2
4
6
1
C850 C849
NC_5P_50V_K_B NC_5P_50V_K_B
0402_X7R 0402_X7R
2
A A

Title
USB/PW_SW CONN
Custom 1.0
BM5016
5 4 3 2 1
3 2 1
+3.3VDUAL
D23 D21
NC_EGA1-0603-V05 NC_EGA1-0603-V05
ESDPAD_R0603 C473 C465 ESDPAD_R0603
10uF/6.3V,X5R 0.1uF/10V,X5R +1.5V
+DATA3 1 2 +1.5V C0805 C0402 USB_PP4 1 2
D24 . . D22
NC_EGA1-0603-V05 NC_EGA1-0603-V05 C447 C464 C449 C463 C462
ESDPAD_R0603 ESDPAD_R0603 10uF/6.3V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
C470 C469 C468 C472 C471 +3.3V C0805 C0402 C0402 C0402 C0402
-DATA3 1 2 10uF/6.3V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R USB_PN4 1 2 . . . . .
C0805 C0402 C0402 C0402 C0402
. . . . . C466 C467 +V3.3S_PCIE
10uF/6.3V,X5R 0.1uF/10V,X5R
C0805 C0402
. . C444 C445
10uF/6.3V,X5R 0.1uF/10V,X5R
C0805 C0402
C C
. .
+V3.3AL_PCIE
C448 C446
10uF/6.3V,X5R 0.1uF/10V,X5R
MPCIE2 +3.3V +V3.3S_PCIE C0805 C0402
. .
1 2 +V3.3S_PCIE_3G R383 0R R0603 MPCIE1 +3.3V
WAKE# +3.3V_1
3 4 +1.5V R475 NC_0 R0402 1 2 R374 0R R0603
RSVD1 GND7 48,49 PCIE_WAKE_UP# WAKE# +3.3V_1 +1.5V
5 6 3 4
RSVD2 +1.5V_1 VSIM_VBB Updata on rev:1.3 RSVD1 GND7
7 8 R476 2K R0402 5 6
CLKREQ# RSVD13 45,49 BT_ACTIVE RSVD2 +1.5V_1
9 10 SIM_DATA PROBE TP268 7 8
GND1 RSVD14 CLKREQ# RSVD13
11 12 SIM_CLK 9 10
REFCLK- RSVD15 GND1 RSVD14
13 14 SIM_RESET 20 PCIE_PE2_CLKN 11 12
REFCLK+ RSVD16 REFCLK- RSVD15
15 16 UIM_VPP_R 20 PCIE_PE2_CLKP 13 14
GND2 RSVD17 R385 NC_0 R0402 REFCLK+ RSVD16
15 16
KEY GND2 RSVD17
17 18 KEY +3.3V
RSVD3 GND8 R3735 DNI 20K
19 20 +3.3VDUAL 17 18
RSVD4 W_DISABLE# WP_DISABLE# 49 PROBE TP266 RSVD3 GND8
21 22 PROBE TP267 19 20
GND3 PERST# RSVD4 W_DISABLE# WU_DISABLE# 49
2 0 1D3708
+3.3VDUAL PCIE_RST# 26,27,31,36,48
23 24 R388 NC_0 R0603 21 22 BUF_PLT_RST#
PER_N0 +3.3V_AUX +3.3V GND3 PERST# +V3.3AL_PCIE
25 26 26 PCIE_PE2_SB_RXN 23 24 R376 NC_0 R0603
PER_P0 GND9 R384 0R R0603 PER_N0 +3.3V_AUX
27 28 25 26 +1.5V +3.3V
GND4 +1.5V_2 26 PCIE_PE2_SB_RXP PER_P0 GND9
29 30 R412 NC_0 R0402 SCLK1 27 27 28 R380 0R R0603
GND5 SMB_CLK GND4 +1.5V_2
31 32 R413 NC_0 R0402 SDATA1 R386
27 0R R0402 29 30 R414 NC_0
R0402 SCLK1 27
PET_N0 SMB_DATA GND5 SMB_CLK
+V3.3S R289 NC 33
PET_P0 GND10
34 CHK2
26 PCIE_SB_PE2_TXN
31
PET_N0 SMB_DATA
32 R415 nc_0
R0402 SDATA1 R368 0R
27 R0402
NC_90ohm@100MHz0.33A
CHK1
35 36 -DATA3 L4_0805 33 34
GND6 USB_D- 26 PCIE_SB_PE2_TXP PET_P0 GND10 NC_90ohm@100MHz0.33A
4 3
USBN8 27 L4_0805
+3.3V 37 38 +DATA3 1 2 35 36 USB_PN4
RSVD5 USB_D+ USBP8 27 GND6 USB_D-
R391 NC_0 R0603 4 3 USBN4 27
B R389 NC_0 R0603 39 40 +3.3V 37 38 USB_PP4 1 2 USBP4 27
B
R400 0R R0603 RSVD6 GND11 R387 0R R0402 RSVD5 USB_D+
26,30 LPC_CLK1
R379 NC_0RR0603 41 42 LED_WIRELESS# R381 NC_ R0603 39 40
26 PCI_CLK0 RSVD7 LED_WWAN# RSVD6 GND11 R361 0R R0402
R285 NC_0RR0402 43 44 R382 NC_0 R0603 41 42
26,49 LFRAME# RSVD8 LED_WLAN# RSVD7 LED_WWAN#
R367 0R R0402 45 46 R306 NC_0 R0603 43 44 LED_WIRELESS# 51
26,49 LAD0 RSVD9 LED_WPAN# RSVD8 LED_WLAN#
R288 0R R0402 47 48 45 46 R362 0R R0402 BT_LED 45,51
26,49 LAD1 RSVD10 +1.5V_3 RSVD9 LED_WPAN# +1.5V
R378 0R R0402 49 50 47 48
26,49 LAD2 RSVD11 GND12 RSVD10 +1.5V_3
R375 0R R0402 51 52 +V3.3S_PCIE_3G 49 50 +V3.3S_PCIE
26,49 LAD3 RSVD12 +3.3V_2 RSVD11 GND12
53 54 51 52
GNDM1 GNDM2 RSVD12 +3.3V_2
NC1
NC2
53 54
GNDM1 GNDM2
NC1
NC2
55
56
PCIE MINI CARDW

R284 NC_0RR0402 Mini_Card_CONN
55
56
PCIE MINI CARD
Mini_Card_CONN
Update on rev:1.1 Change debuge port to 3G slot
VSIM_VBB
UC1 UC2
0.1uF/10V,X5R NC_0.1uF/10V,X5R USIMCON1
C0402 C0402 SIM
. . P1 P7 SIM_DATA
VCC I/O UC5 D15
SIM_RESET P2 P8 NC_22pF/10V,X5R NC_CM1293
UC3 RST NC2 C0402 UIM_VPP_R 1 4 SIM_DATA
NC_22pF/10V,X5R SIM_CLK P3 P9 . CH1 CH4 VSIM_VBB
C0402 UC4 CLK GND2 2 5
. NC_22pF/10V,X5R P4 P10 VSS VCC
C0402 NC1 GND3 SIM_RESET 3 6 SIM_CLK
. P5 CD CH2 CH3
GND1 CD SOT23-6
NC4
UIM_VPP_R P6 P11
UC6 VPP NC3
NC_22pF/10V,X5R SIM_CONN_5927
P12
C0402
.
A A

Title
Park-XT(Straps & Thermal)
Custom 1.0
BM5016
3 2 1
5 4 3 2 1
+3V_LAN +3V_LAN
DVDD
MPD connect to Main Power or RSTN for D3E
MDIO Single
applicaion, to AUX power otherwise.
0.1U_6.3V_K
0.1U_6.3V_K
NC_10U_10V_M
0.1U_6.3V_K
0.1U_6.3V_K
0.1U_6.3V_K
NC_10U_6.3V_M
MDIO5X
End = 50
1
1
Function
MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO6
R61
C34
C437
C438
C443
C196
C197
C427
Ohm
GND
MDIO5X 1 2 22_J MDIO5 R3 R4 R5 C2
0 NC NC NC Disable D3E
2
2
D NC NC 0 NC Enable D3E(1) D
NC 100K NC 0.1u Enable D3E(2)
+3.3VDUAL Pin#26 Pin#17 Pin#17 Pin#51 Pin#62 Pin#55 Pin#55
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
+3V_LAN U7
R832 0 1206
MDIO0
MDIO1
MDIO2
VDDIO1
MDIO3
MDIO4
MDIO5
GND4
MDIO6
MDIO7
VDDIO
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
1 2
+3.3V
0.1U_6.3V_K
0.1U_6.3V_K
0.1U_6.3V_K
0.1U_6.3V_K
0.1U_6.3V_K
0.1U_6.3V_K
NC_10U_6.3V_M
NC_10U_6.3V_M
1
1
R846NC_0R 1206
C426
C198
C199
C234
C428
C412
C413
C416
1 2 49 32 GND
50 LED0 GND3 31 MDIO13
LED1 MDIO13
2
2
51 30
update rev:1.1 DVDD VDD MDIO14
GND 52 29 CR1_LEDN +3V_LAN
Pin#38 Pin#38 Pin#45 Pin#27 Pin#59 Pin#59 Pin#2 Pin#11 MDI0+ 53 GND5 SMB_SDA/CR_LEDN 28 +3V_LAN
54 VIP_1 TESTN 27
JMC251
MDI0-
55 VIN_1 VDDIO2 26 Card_3V3
DVDD AVDD12 VDD1 DVDD
MDI1+ 56 25 (>20mil) R1360 NC_47K
57 VIP_2 VCC3O 24 +3.3VDUAL
JMC261
+3V_LAN MDI1- CR1_CD0N TP38
GND 58 VIN_2 CR_CD0N 23 CR1_CD1N +3.3V R1361
59 GND6 CR_CD1N 22 LAN_LED2 47K
AVDD33 SMB_SCL/LED2
1
+3V_LAN MDI2+ 60 21 PCIE_LAN_CLKREQ# TP86 R11 1 2 NC_0
LANXIN MDI2- 61 VIP_3(NC) CREQN 20 MPD R14 1 2 NC_100K Q1310
VIN_3(NC) MPD
1
62 19 PCIE_WAKE_UP#_LOM PCIE_WAKE_UP#_LOM 2 3
DVDD PCIE_WAKE_UP# 47,49
AS BM5960 2 Y7 4 R842 MDI3+ 63 AVDD12(NC) WAKEN 18 XRSTN 1 2 update rev:1.2
VIP_4(NC) RSTN
1
3 1 LANXOUT MDI3- 64 17 R63 0R +3V_LAN NC_2N7002E

VIN_4(NC) AVDDX DVDD
1
R811 R812 NC_1M_J C2
VDDREG
VDDX33
+3V_LAN U9 R810 NC_0.1U_6.3V_K R12 1 2 0R
AVDDH
2
1
GND1
GND2
XOUT
1 8 4.7K_J 4.7K_J C417 C425 R1302
CLKN
REXT
CLKP
0R Updated on Rev1.1
FB12
RXN
A0 VCC
RXP
TXN
2
TXP
2 7
XIN
25MHz 20P_50V_K nc_8.2K
0.1U_6.3V_K
LX
A1 WP
2
2
1
3 6 LAN_LED2 20P_50V_K
C419
A2 SCL
2
1
4 5 CR1_LEDN Y_5938 JMC261(10X10) 2 1
GND SDA PCIE_RST# 26,27,31,36,47
1
2
3
4
5
6
7
8
PCIE_LAN_CLKN 9
PCIE_LAN_CLKP 10
11
12
13
14
15
16
LQFP64-10X10 0 D1303
2
EEPROM_SOIC-8_2KB
LANXOUT
GND
REXT PTXPX C4351 2 0.1U_6.3V_K (>20mil)
PRXN
ARFB12
PCIE_LAN_NB_RXP 22
LANXIN
REGLX
1
PTXNX C4361 2 0.1U_6.3V_K
PRXP
PCIE_LAN_NB_RXN 22
GND
R841 PCIE_NB_LAN_TXN 22
PCIE_NB_LAN_TXP 22
12K_J
Card Reader +3V_LAN L2
2
+3V_LAN 4.7uH/5.5A/15mOHM DVDD
+3V_LAN
R8441 2 4.7K_J CR1_CD0N (>20mil) REGLX 1 2ARFB12
R8451 2 4.7K_J CR1_CD1N (>20mil) MHCI06030 (>20mil)
1
PCIE_LAN_CLKP C429 C433 update rev:1.2
20 PCIE_LAN_CLKP
1
Card_3V3 PCIE_LAN_CLKN C432 22U_6.3V_M 22U_6.3V_M
C434
C 20 PCIE_LAN_CLKN C
0.1U_6.3V_K 0.1U_6.3V_K
2
R836 1 2 10K_J MDIO4 update rev:1.2 closed to chip.
2
R839 1 2 10K_J MDIO6
R840 1 2 1K_J MDIO13
Pin#8 Pin#8 Pin#7 Pin#7
closed to chip.
27
28
L84 C757 1 2 0.01U_10V_K MDI2+ CN13
MDI0+ 2 23 TX0+ MDI2-
NC1
NC2
C759 NC_0.1U_10V_K
0402_X5R MDI0- 3 TD1+ MX1+ 22 TX0- R828 75_J 0402 MDI3+ CR1_CD0N 1 22 MDIO2
1 2 1 TD1- MX1- 24 RXCT 2 1 MDI3- MDIO6 2 CD_SD SD9# 21
C758 1 2 4 TCT1 MCT1 21 TXCT 2 1 0402 C747 1 2 0.01U_10V_K MDIO1 3 SD_WP MS10# 20 MDIO3
TCT2 MCT2 SD8# SD1#
1
NC_0.1U_10V_K 0402_X5R MDI1+ 5 20 TX1+ R823 75_J MDIO0 4 19 CARD_3V3
TD2+ MX2+ SD7# MS9#
1
MDI1- 6 19 TX1- R826 R813 5 18 MDIO5
MDI2+ 8 TD2- MX2- 17 TX2+ R830 R829 6 SD_WP_GND MS8# 17 MDIO4
C756 NC_0.1U_10V_K
0402_X5R MDI2- 9 TD3+ MX3+ 16 TX2- R817 75_J 0402 NC_49.9_F NC_49.9_F 7 SD6# SD2# 16 MDIO3
1 2 7 TD3- MX3- 18 2 1 NC_49.9_F NC_49.9_F MDIO4 8 MS1# MS7# 15 CR1_CD1N
TCT3 MCT3 MS2 MS6#
2
C752 1 2 10 15 2 1 0402 MDIO5 9 14
TCT4 MCT4 SD5# SD3#
2
0.1U_10V_K 0402_X5R MDI3+ 11 14 TX3+ R821 75_J MDIO1 10 13 MDIO2
MDI3- 12 TD4+ MX4+ 13 TX3- MDIO0 11 MS3# MS5# 12 CARD_3V3
TD4- MX4- MS4# SD4#
GND1
GND2
GND3
GND4
C754 C753
1
DVDD NC_1-1_350UH 0.1U_16V_Y 0.1U_16V_Y C410
1
G2453CG C411 NC_12P_50V_K_N
2
2
update rev:1.2 C733 NC_12P_50V_K_N 0402
23
24
25
26
2
1000pF/2000V 0402 CR009
2
C1206
1
2
.
R824
NC_0R RN25
update rev:1.1 1 2
0603
3 4
U41
1
5 6
MDI0+ 1 16 TX0+ 7 8
MDI0- 2 RD+ RX+ 15 TX0-
3 RD- RX- 14 RXCT 0x4
4 RDCT3 RXCT 13 RA0603_8
6 NC1 NC4 11 TXCT
MDI1+ 7 TDCT4 TXCT 10 TX1+ CHK16
MDI1- 8 TD+ TX+ 9 TX1- TX0+ 1 2 TRD0P_RJ45
5 TD- TX- 12 TX0- 4 3 TRD0N_RJ45
NC2 NC3
1
B B
1
R825 R816 H1631CG NC_90ohm@100M0.33A

R819 R827 l4_0805
NC_49.9_F NC_49.9_F TX1+ 1 2 TRD1P_RJ45
NC_49.9_F NC_49.9_F update rev:1.2 TX1- 4 3 TRD1N_RJ45
2
1
C755 0402
0.1U_16V_K_B
C734 0402
0.1U_16V_K_B
2
NC_90ohm@100M0.33A
CHK15
2
2
1
C760 C736 l4_0805

NC_0.1U_16V_Y NC_0.1U_16V_Y
J5
2
RJ45-C100N9
9 BM05_RJ45
Updata on rev:1.3 RN26 RJ45
1 2
3 4 TRD0P_RJ45 1 TX0+
5 6 TRD0N_RJ45 2 TX0- TX0+
7 8 TRD1P_RJ45 3 TX1+ TX0-
TRD2P_RJ45 4 TX2+ TX1+
TX2+
NC_0x4 TRD2N_RJ45 5 TX2- TX2-
RA0603_8 TRD1N_RJ45 6 TX1- TX1-
TRD3P_RJ45 7 TX3+ TX3+
CHK18 TRD3N_RJ45 8 TX3- TX3-
TX3- 1 2 TRD3N_RJ45
TX3+ 4 3 TRD3P_RJ45
NC_90ohm@100M0.33A
10
11
12
TX2- 1
l4_0805 2 TRD2N_RJ45
TX2+ 4 3 TRD2P_RJ45
NC_90ohm@100M0.33A
CHK17
l4_0805
A A

Title
LAN/CARD READER (JMC261)
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
+3.3VALW +3.3VDUAL
+RTCVCC_EC
7 EC_V3.3AL
2
Updata on rev:1.1
R431 L86
0R 120ohm@100MHz,500mA_0603 Resered for EC
2
R0805 R432 1 NC_0 2 R0805 0.1U_0402_16V4Z 0.1U_0402_16V4Z L83
1
1 1 C2157 1 1 2 2 C2058 120ohm@100MHz,500mA_0603R571
1
C2161 1000P_0402_50V7K NC_0_J
C2052 C2168 C2170
1000P_0402_50V7K R570 +3.3V
2 2 2 2 1 1
1
+3.3V 1 0_J 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1
2
Q3204 NC_2N7002 C2166 C2173 C2175
1
D KBC D
2 3 2
0.1U_0402_16V4Z 2 2
114
121
127
U511 0.1U_0402_16V4Z 0.1U_0402_16V4Z
26
50
92
74
11
3
IT8502E
2 1 EC_SCI#_EC ADC1 C569 1 2 3300pF/50V,X7R
27 EC_SCI#
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY6
AVCC
VCC
VBAT
R1747 0_0402_5% C0402
+3.3V
C2151 @
Q3203 NC_2N7002 NC_22P_0402_50V8J 10 24 BEEP#
26,47 LAD0 LAD0 PWM0/GPA0 BEEP# 42
1
2R1842 12 @ 1 NC_33_0402_5% 9 25 EC_LCD_BKL_PWM

26,47 LAD1 LAD1 PWM1/GPA1 EC_LCD_BKL_PWM 43
KBC 8 28 R549 0 R0402
26,47 LAD2 LAD2 PWM2/GPA2 CONTROL_FANOUT0 51
2 3 7 LPC PWM 29 0R R3262
26,47 LAD3 LAD3 PWM3/GPA3 KBC_LOW_BAT# 27
13 R3251
2 1 EC_SMI#_EC
26,30 LPC_CLK0
26,47 LFRAME#
6
22
LPCCLK
LFRAME#
47K Lid Switch
27 EC_SMI# 23,24,26,31 A_RST# LPCRST#/WUI4/GPD2
R1746 0_0402_5% 5
26 SERIRQ
EC_SMI#_EC 15 SERIRQ
ECSMI#/GPD4
(Hall Effect Switch)
EC_V3.3AL EC_SCI#_EC 23 +3.3VDUAL
+3.3V EC_A20M#_EC 126 ECSCI#/GPD3 7 EC_V3.3AL
KBRST 4 GA20/GPB5 108 GPB0
Updata on rev:1.1 Q3201 2N7002 2 1add r1743 EC_RST# 14 KBRST#/GPB6 RXD/GPB0 109 GPB1 C0402
WRST# TXD/GPB1
1
R1741 100K_0402_5% UART 123 NC_0.1UF/25V,Y5V

GPB2/CTX0 1V1_EN_EC 10 C517
KBC EC Output Signal! 119 2
GPC0/CRX0 CHG_ON 7
1
2 3 R569 C2104 1 2
2
1 NC_0_J 2 VU1 0.1U_0402_16V4Z R395 R394
3
1 EC_SPICLK 105 A180 R1888 NC_10K NC_10K DBCON2

2 1 KBRST D Q34 EC_SI_SPI_SO 103 FSCK 120 R548 1K R0402 PWRSW2# Update on rev:1.1 SOT23 1 NC_ACIN 4Pin
27 EC_KB_RST# SPI 100K_0402_5% R0402 R0402
R1744 NC_0_0402_5% C2060 EC_SO_SPI_SI 102 FMISO TMR0/WUI2/GPC4 124 1 2 LID_SW# 1 CNS4_R
NC_2N7002-7-F TIMER INT
FMOSI TMR1/WUI3/GPC6 VS+
2
1 EC_SPICS#/FSEL#
1U_0402_16V4Z 101 FLASH R1893 1k_0402_5%
32 CTF 2 FSCE# 1
1
+3.3V G S 2 LID_SW# GPB0
Output GPB1 2 5
1 3 6
2
Q3202 NC_2N7002 3
GND 4
1
1
SCANIN0 58 +3.3V
KSI0/STB# T191
KBC SCANIN1 59 TESD37
2 3 SCANIN2 60 KSI1/AFD# 66 1 C2112 2
KSI2/INIT# ADC0/GPI0 BAT_INT# 7 EGA10603V05A1-B
SCANIN3 61 67 PM_SLP_S3# 10P_0402_50V8J ESDPAD_R0603
KSI3/SLIN# ADC1/GPI1 SLP_S3# 7,9,11,27,40,51
2
2
SCANIN4 62 68
KSI4 ADC2/GPI2 PARK-XT_PGOOD 40 ns
27 EC_A20M# 2 1 EC_A20M#_EC SCANIN5 63 69 R1889
KSI5 ADC3/GPI3 ADAPT_OUVP 7
R1745 0_0402_5% SCANIN6 64 70 10K_0402_5%
KSI6 ADC4/GPI4 T192 ADC1 7
SCANIN7 65 71 BATT_OVP
KSI7 ADC5/GPI5 BATT_OVP 7
72 1 2 R1900 1
100K_0402_5%
ADC6/GPI6
1
15PFF/50V,NPO 73 board ID
C516 C0402 XOUT-EC SCANOUT0 36 ADC7/GPI7
KSO0/PD0
2
SCANOUT1 37 A/D D/A
Y5 SCANOUT2 38 KSO1/PD1 R1899
Y8 KSO2/PD2 KBMX
32.7680KHZ SCANOUT3 39 NC_10K_0402_5%
2 1 R227 1 2 SCANOUT4 40 KSO3/PD3 76
KSO4/PD4 DAC0/GPJ0 VDDA_EN_EC 16
3 4 NC_10M4 3 SCANOUT5 41 77
KSO5/PD5 DAC1/GPJ1 VDRAM_PWRGD 9
1
R0402 SCANOUT6 42
C BM05_CLK_32_768M SCANOUT7 43 KSO6/PD6 C
NC_32.7680KHZ SCANOUT8 44 KSO7/PD7
XS4_8038 SCANOUT9 45 KSO8/ACK# 106
KSO9/BUSY GPG0 CAM_PWRON 43
SCANOUT10 46 FAN
SCANOUT11 51 KSO10/PE 34
KSO11/ERR# PWM7/GPA7 AC_BAT# 32
SCANOUT12 52
15PFF/50V,NPO SCANOUT13 53 KSO12/SLCT
C515 C0402 XIN-EC SCANOUT14 54 KSO13 AC (Performance mode) = 3.3 V
DUAL RAILS ENABLE

SCANOUT15 55 KSO14 Battery saving mode = 0.0 V
KSO15
Del at88sc0104 circuit
. SCANOUT16 56
SCANOUT17 57 KSO16/GPC3
KSO17/GPC5 CIR
XOUT-EC 128 125 R544 1K R0402
PWRSW1# +3.3V
DUAL rails can be configured to be on at all times
XIN-EC 2 CK32K PWRSW/GPE4 35
CK32KE CLOCK
GPIO_WAKE WUI5/GPE5 17
VDDIO_SUS_EN_EC 9
VDDC_EN_EC 40 2N7002 Q3205
DUAL rails can also be configured to conserve power during S5 when operating from battery
LPCPD#/WUI6/GPE6
1
46 USB_PWR_EN 85 20 WL-SW
7 EC_V3.3AL
47 WP_DISABLE# 86 PS2CLK0/GPF0
PS2DAT0/GPF1
L80LLAT/WUI7/GPE7
GPE2/ISAS
83 R546 0 R0402 RSMRST# 27 KBC In this case DUAL rails can be configured to turn on only in response to a power button press
R3235 KBC 0R 87 3 2
51 KBC_GPIO77
88 PS2CLK1/GPF2
PS/2
the keyboard controller typically will control this funciton significantly reducing hardware
45,47 BT_ACTIVE PS2DAT1/GPF3
1 2 EC_SMB_CK0 TP_CLK 89 82 AMP_SHDW
PS2CLK2/GPF4 GPE1/ISAD AMP_SHDW 42
R1890 4.7K_0402_5% TP_DATA 90 84 2 1 EC_PROCHOT# 16
1 2 EC_SMB_DA0 PS2DAT2/GPF5 GPE3/ISCLK R1748 NC_0_0402_5%
IT8512JX
R1878 4.7K_0402_5% 7 BAT_CLK R3232 110

KBC 0R EC_SMB_CK0
7 EC_V3.3AL
7 BAT_DAT 111 SMCLK0/GPB3
R3221 KBC 0R EC_SMB_DA0 18 ACIN 7
Updata on rev:1.2 C2172 100P_0402_50V8J
16 TSI_CLK R3239 KBC 0R EC_SMB_CK1115 SMDAT0/GPB4 SM
RI1#/WUI0/GPD0 21 2 @ R1843 1 PCIE_WAKE_UP# 47,48
PCIE_WAKE#_EC BATT_OVP 2 1
16 TSI_DAT R3238 KBC 0R 116 SMCLK1/GPC1
EC_SMB_DA1 RI2#/WUI1/GPD1 1 0_0402_5%
2 C2156 100P_0402_50V8J
SMDAT1/GPC2 BUS T199 SMBALERT# 16
1 2 EC_SMB_CK1 112 R1919 NC_0_0402_5% ThermINT 32,36 ACIN 2 1
R1892 4.7K_0402_5% RING#/PWRFAIL#/LPCRST#/GPB7 16 1 1 2
16 SCLK2 PWUREQ#/GPC7 SLP_S5# 9,11,27,46
1 2 EC_SMB_DA1 16 SDATA2 R1918 1K_0402_5%
R1881 4.7K_0402_5% 107
GPG1/ID7 BAT_LED 51
93 19 R776 NC_0R
26 PCI_CLKRUN# CLKRUN#/GPH0/ID0/SHBM L80HLAT/GPE0 NB_VOL_DET 10
8 VRM_RUN_EC 94
95 CRX1/GPH1/ID1/BADDR0 100 BKOFF#
7 SHDN CTX1/GPH2/ID2/BADDR1 GPG2 BKOFF# 43
96 104
13 VDD_DUAL_EN GPH3/ID3 GPG6 MEM_VTT_EN 9
97 GPIO
7 ACOFF# GPH4/ID4 117 PARK_SCL R8220 0R PARKXT_CLK 36
R3231 0R 99 SMCLK2/GPF6 118 PARK_DATA R8221 0R
27,51 SB_PWRGD GPH6/ID6 SMDAT2/GPF7 PARKXT_DAT 36
SYSTEM_DUAL_PG 98
R547 0R R0402 48 GPH5/ID5 78 Updata on rev:1.1
27 PWR_BTN#_EC CHGVADJ 7
51 SB800_FANTACH0
47 WU_DISABLE#
1 2
WXMIT_OFF#
47
33
TACH1/GPD7
TACH0/GPD6
DAC2/GPJ2
DAC3/GPJ3
79
80
NUMBER LOCK_LED#
CAPS LOCK_LED#
CAPS LED/NUMBER LED
D46
1N4148WS
GINT/GPD5 DAC4/GPJ4
DAC5/GPJ5
81
SET_I 7 POWER SWITCH CONN
1
SOD323 30
PWM4/GPA4 CHARGER_LED 51
R430 31
+3.3VDUAL PWM5/GPA5 BTL_LED# 51
1
100K 32
PWM6/GPA6 AC_LED# 51
R0402 TESD31 TESD32
7
10,51 1V1DUAL_PWRGD NC_EGA10603V05A1-B
NC_EGA10603V05A1-B S_CN3
2
B R3073 0R R3029 ESDPAD_R0603

ESDPAD_R0603 NUMBER LOCK_LED# 1 B
2
SMDFIX1
7
47K S_CN2 CAPS LOCK_LED# 2
DNI R3031 KBC 0R
SYSTEM_DUAL_PG PWRSW2# ns ns 1 3
11,13 V3V5DUAL_PWRGD SMDFIX1 +5V
R3071 0R PWRSW1# 2 4
C3018 3 5
100nF 7 EC_V3.3AL 4 6
VCORE
SMDFIX2
1
5
AVSS
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
LID_SW# 1 2 6 TESD35 TESD34 FPC CONN_6P

SMDFIX2
8
R1897 NC_0_0402_5% NC_EGA10603V05A1-B
NC_EGA10603V05A1-B
LQFPS128_0D4_1D6 FPC CONN_6P ESDPAD_R0603
ESDPAD_R0603
12
1
27
49
91
113
122
75
2
update rev:1.1 ns ns aces_88511
1
2
1 TESD33 aces_88511
1
C2159 R1885 EGA10603V05A1-B

10K_0402_5% L85 ESDPAD_R0603
2
0.1U_0402_16V4Z @ 120ohm@100MHz,500mA_0603
2 ns
1
To TP/B Conn. KEY BOARD FLASH MEMORY 8M-bit WL SWITCH

+5V
0_0603_5% +VTP5S SCANOUT0 1 PAD~D

R1645 1 T149
7
S_CN1 SCANOUT1 1 T155 PAD~D

1 2 1 2 SCANOUT2 1 PAD~D +3.3VDUAL WL_SW1
SMDFIX1 3 T122
1
TP_CLK C2071 TP_CLK 2 SCANOUT3 1 T124 PAD~D sst-1221

TP_DATA 0.1U_0402_16V4Z TP_DATA 3 4 SCANOUT4 1 PAD~D sw_sst-1221
5 T126 EC_V3.3AL
LEFT_BTN# R1772 1 2 10_0402_5%
4 SCANOUT5 1 T151 PAD~D
6
2
1
RIGHT_BTN# R1773 1 2 10_0402_5%
5 SCANOUT6 1 T156 PAD~D
7
1
1 1 6 SCANOUT7 1 T123 PAD~D EC_SPICS#/FSEL#R1877 1 2 NC_10k_0402_5%

@ R545
SMDFIX2 8
TESD25
1 1 TESD26 C2072 SCANOUT8 1 T125 PAD~D EC_SPICLK R1876 1 2 NC_10k_0402_5%
@ 10K
C2068 C2073 9 SCANOUT9 1 PAD~D EC_SO_SPI_SI R1895 1 2 NC_10k_0402_5%
@ smdfix1 smdfix2 smdfix3
EGA10603V05A1-B EGA10603V05A1-B FPC CONN_6P T143 R0402
10
8
ESDPAD_R0603 C2069 ESDPAD_R0603100P_0402_50V8J 2 100P_0402_50V8J SCANOUT10 1 T152 PAD~D EC_SI_SPI_SO R1870 1 2 NC_10k_0402_5%
@
11
2
1
100P_0402_50V8J 100P_0402_50V8J SCANOUT11 1 T139 PAD~D
2 2ns ns 12 SCANOUT12 1 PAD~D
13 T141
Foxconn_hs6206e SCANOUT13 1 T142 PAD~D WL-SW
14 SCANOUT14 1 PAD~D EC_V3.3AL
15 T150
1
A +5V SCANOUT15 1 T157 PAD~D 1 2 C2169 1 2 0.1U_0402_16V4Z C3080 A
16 SCANOUT16 1 PAD~D R1891 0_0603_5% TESD2 330PF/50V,X7R
17 T130
SCANOUT17 1 T154 PAD~D C0402
NC_EGA1-0603-V05
18
2
SW4 SCANIN0 1 T140 PAD~D +SPI_VCC ESDPAD_R0603
19 EC_V3.3AL
6
1 2 TP_CLK SW5 STS_043_A SCANIN1 1 T147 PAD~D

20
6
R1883 4.7K_0402_5% STS_043_A 1 3 RIGHT_BTN# SCANIN2 1 T148 PAD~D U66

21
2
1 2 TP_DATA 1 3 LEFT_BTN# SCANIN3 1 T131 PAD~D EC_SPICS#/FSEL# 1 8
2822 CE# VDD
1
R1880 4.7K_0402_5% 2 4 SCANIN4 1 T144 PAD~D R1894 1 2 4.7K_0402_5% SPI_WP# 3 6 R1879 1

EC_SPICLK_R 2 0_0402_5%
EC_SPICLK
2723 WP# SCK
1
C2070 2 4 TESD28 SCANIN5 1 T153 PAD~D R1896 1 2 4.7K_0402_5% SPI_HOLD# 7 5 R1871 1 2 0_0402_5%
EC_SO_SPI_SI
TESD30 24 SCANIN6 1 PAD~D 4 HOLD# SI 2 R1873 1 2 0_0402_5%
EC_SI_SPI_SO
EGA10603V05A1-B T145
25 VSS SO
5
0.1U_0402_16V4Z EGA10603V05A1-B ESDPAD_R0603 SCANIN7 1 T158 PAD~D

26
2
ESDPAD_R0603 W25X80A
ns
2
ns FOXCONN_1BT002_0120L CNS26_1_R_UP
FOXCONN_1BT002_0120L ACES 88513
KBCON1
Title
EC(IT8502)
D 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Title
//
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
+3.3V
R3141
10K
NC_RB751V-40 +3.3V
D3146 1 2
11 1V5_PWRGD
DNI
RB751V-40 C3121 100nF
D3141 1 2 U515 SB/NB POWER GOOD CIRCUIT
10 +1.2V_PWRGD
5
NC_SN74AHC1G08DBV
1 VCC
4 R3138 0R
SB_PWRGD 27,49
2
NC_RB751V-40 GND
DNI
7,9,11,27,40,49 SLP_S3# D3140 1 2 C3125 R3947
3
D D
2.2uF_6.3V NC_100K,5%
RB751V-40 DNI R0402
49 KBC_GPIO77 D3150 1 2
R3137 0R
NC_RB751V-40
D3147 1 2
10,49 1V1DUAL_PWRGD +1.8V
RB751V-40 R3149
D3148 1 2 0R C3117 100nF
Updata on rev:1.2 11 1V8_PWRGD
DNI
NC_RB751V-40
5
D3149 1 2
8,10 VRM_PWRGD R3151 1
0R 4 R3147 33R
NB_PWRGD_IN 23
DNI 2 DNI
+1.8V U3102
3
NC7SZ08M5
DNI
R3152
300R
R3150 0R R3153 0R
27 NB_PWRGD
Updata on rev:1.2 +3.3VDUAL +5V
LED8
2
1 2 1 2 CHARGER_LED# SATA_LED (white)
R1791 500_0402_5% R1836
+5V NC_10K_0402_5%
HSMG-C-170/G R1851 LED2
1
C +5VDUAL SM_T_LED0603 2 1 1 2 SATA_LED# C
SATA_ACT# 28
LED7
1 2 1 2 BATT_AMB_LED# 500_0402_5% HSMG-C-170/G
R1790 500_0402_5% SM_T_LED0603 +5VDUAL
HSMG-C-170/G
SM_T_LED0603
2
R485 1 NC_0 2 R0402 BATT_AMB_LED# (white)
POWER_ON
+5VDUAL R1835
10K_0402_5%
R1826 LED6
3
KAL90@
1
Q29 2 1 1 2POWER_LED#
2N7002 AC_LED# 49
1 SOT23
49 BAT_LED 500_0402_5% HSMG-C-170/G
.
2
SM_T_LED0603
2
R484
100k
R0402
1
+5V R498 1 0 2 R0402 CHARGER_LED#
5
CN6
3
1
2 Q33
SB800_FANTACH0_1 3 NC_2N7002
R406 1 2 1k 4 1 SOT23
49 CONTROL_FANOUT0 49 CHARGER_LED
2
R0402 HEADER_4P .
2
D2
6
2
1N4148WS R497
B
NC_100k B
R0402
1
+3.3V
FOXCONN_HS8104E
1
R390
2.2K PWM FAN Conn WIFI/3G_LED
R0402 (white) D50 1 2 LRB751V LED_WIRELESS# 47
2
51R R3124 SB800_FANTACH0_1 +5V SOD323

49 SB800_FANTACH0 R1848 LED5
1
C486 2 1 1 2 WIFI_LED# D53 1 2 NC_LRB751V BTL_LED# 49

1000PF/50V,NPO SOD323 +5V
C0402
500_0402_5% HSMG-C-170/G
FOR EMI
2
1 R1858 2
SM_T_LED0603 NC_10K_0402_5%
KAL90@
LRB751V 1R1860 2
D54 1 2 10K_0402_5% BT_LED 45,47 POWER_LED# C2164 1 @ 2 100P_0402_50V8J
KAL90@
SOD323
update on rev:1.1 SATA_LED# C2165 1 @ 2 100P_0402_50V8J
H57 SATA_LED# POWER_LED# WIFI_LED# BATT_AMB_LED# CHARGER_LED#

H53 H54 H55 H56 WIFI_LED# C2163 1 @ 2 100P_0402_50V8J
1
TESD18 TESD24 TESD21 TESD23 TESD29 BATT_AMB_LED# C2167 1 @ 2 100P_0402_50V8J

EGA10603V05A1-B EGA10603V05A1-B EGA10603V05A1-B EGA10603V05A1-B EGA10603V05A1-B
HOLE ESDPAD_R0603 ESDPAD_R0603 ESDPAD_R0603 ESDPAD_R0603 ESDPAD_R0603
1
HOLE HOLE HOLE HOLE ns ns ns ns ns

1
HOLE_160X88 BTL_LED# C2171 1 @ 2 100P_0402_50V8J

HOLE_160X88 HOLE_160X88 HOLE_160X88 HOLE_160X88
ns
A A
ns ns ns ns
GND
GND GND GND GND
CHARGER_LED# C2178 1 @ 2 100P_0402_50V8J
H17 H46 H42 H45
H2 H48 H49 H50 H51 H24 H15 H44 H41 H52 H43 H47

HOLE HOLE HOLE HOLE Notebook R&D Division
1
1
HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE
1
HOLE_NP_4MM HOLE_NP_4MM HOLE_NP_4MM HOLE_NP_4MM Title

HOLE3MM_8MM HOLE3MM_8MM shape_hole8_3 HOLE3MM_8MM HOLE3MM_8MM shape_hole8_3 HOLE6MM_8MM shape_hole8_3 shape_hole8_3 shape_hole8_3 shape_hole8_3_2 HOLE_160X88 RESET/FAN/LED/POWERGOOD
ns ns ns ns Size Document Number Rev
ns ns ns ns ns ns ns ns ns ns ns ns C 1.0
GND GND GND GND
GND GND GND GND GND GND GND GND GND GND GND GND
BM5016
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Title
pull up resistor
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Title
change history
Custom 1.0
BM5016
5 4 3 2 1
5 4 3 2 1
+1.2V_PWRGD
+3.3VALW
+3.3VDUAL
V3V5_DUAL_PWRGD
3 PWRGD PWRGD
VCC_NB
EC TPS51125 +5VDUAL
LDO
1 2 ISL6228
IT8502 VDD_DUAL_EN
+1.1VDUALEN
+1.1VDUAL
SWITCH +1.1V VLDT
1.1V 2.5A
VCC_NB_EN 1.1V 2A
PWR_BTN#_EC
D
4 CPU_VDDIO_SUS
D
SLP_S5#
5 TPS51218 VRM_PWRGD
10 VRM_PWRGD
10
+3.3VDUAL
SB820 5
VTT +1.8V
CPU_VDDIO_SUS +1.5V
SLP_S3# LDO LDO 2.5A PWRGD
5 RT9199GP SLP_S3#
APL5912 1V8_PWRGD SWITCH VDDC
+1.8VEN PWRGD TPS51218 12.9A

+5VDUAL +5V VLDTEN
SLP_S3# SWITCH 7 CPU_VDDA_RUN
+3.3VDUAL +3.3V
LDO CPU_VDDIO_SUS
6 UP7707K3A- CPU_VDD_RUN 1.1V_1.0V_PWR
25_SOT89-3 VDDA_PWRGD
8 VDDA_PWRGD
PWRGD 9 LDO PWRGD 2.6A
EN UP7717ASU8
ISL6265 CPU_VDDNB_RUN
CPU_VDDIO_SUS MVDDQ
CPU_VDDIO_SUS
CPU_VDDR 3.7A
LDO 9 SWITCH For Park-XT-S3
VDDA_PWRGD
C
UP7717ASU8VDDR =1.05V 1.75A C
VDDR = 0.9V 1.25 A (Default)
+3.3VDUAL +3VRUN
0.3A
SWITCH
+1.8V 1.8V_REG
SLP_S3# 1.5A
SB 820M PE_GPIO1 APL5912
PWM/L/MOS
Power on Sequence required: POWER PWM L H_GATE L_GATE
HB90479MA0LFE
B 4.7uH20% 5.5A 40m B
+3.3VDUAL AO4468 AO4468
SMD-6.86x6.47x3.0mm 30V 11.6A RDS(ON)<22m(VGS=4.5V) 30V 11.6A RDS(ON)<22m(VGS=4.5V)
(+3.3V 8A) TI/TPS51125RGER
SB800: +5VDUAL
(+5V 8A)
VQFN24
HB90479MA0LFE
4.7uH20% 5.5A 40m
SMD-6.86x6.47x3.0mm
AO4468
30V 11.6A RDS(ON)<22m(VGS=4.5V)
AO4468
30V 11.6A RDS(ON)<22m(VGS=4.5V)
1, +3.3VDUAL ramp before +1.1VDUAL VCC_NB

(+1.1V 12A) ISL6228HRTZ-T
HB90109M00LFE
1.0H 20% 12A 10m
SMD-6.67.33.0mm
VISHAY/SI4172DY-T1-GE3
15A +/-20V 15m@4.5V SO-8pin
24A +/-20V 7.6m@4.5V SO-8pin
HB90479MA0LFE
2, +3.3V ramp before +1.8v VLDT
(+1.2V 4A)
TQFN-28 4.7uH20% 5.5A 40m
SMD-6.86x6.47x3.0mm
L/H intergrated (
HB90109M00LFE
3, +1.8V ramp before +1.1v VDDIO_SUS
(+1.5V 11A)
TPS51218
DSC
1.0H 20% 12A 10m
SMD-6.67.33.0mm
15A +/-20V 15m@4.5V SO-8pin
24A +/-20V 7.6m@4.5V SO-8pin
PHASE1
4, +3.3v ramp before +1.1v HB90479MA0LFE
4.7uH20% 5.5A 40m
VISHAY/SiR462DP-T1-GE3 VISHAY/SiR466DY-T1-E3/GE3(two)
30A +/-20V 0.01@4.5V PowerPAK SO-8pin 24.5A +/-20V 6.7m@4.5V SO-8pin
CPU_VDD_RUN PHASE2
5, +3.3VALW_R ramping down time > 300us (+1.375--1.5V 36A) ISL6265
QFN-48
SMD-6.86x6.47x3.0mm
HB90479MA0LFE
VISHAY/SiR462DP-T1-GE3 VISHAY/Si466DY-T1-E3/GE3(two)
30A +/-20V 0.01@4.5V PowerPAK SO-8pin 24.5A +/-20V 6.7m@4.5V SO-8pin
6, 50uS <= All power rails except +3.3VALW_R <= 40mS CPU_VDDNB_RUN
(0.9V 4A)
4.7uH20% 5.5A 40m
SMD-6.86x6.47x3.0mm
L/H intergrated (
7, 100uS <= +3.3VALW_R <= 40mS charger

ISL6251HAZ
SSOP24_25_150
HB90100MA0LFE
10uH20% IDC=4A DCR-Max=
71.2m SMD 6.86x6.47x3.0mm
AOS/AON7408
9.6A RDS(ON)<34m(VGS=4.5V DFN-8)
AOS/AON7702
20A RDS(ON)<14m(VGS=4.5V) DFN-8
RS880: LDO SWITCH

INPUT(V) OUTPUT(V) MOS
1, 0 <(+3.3V) - (+1.8v) < 2.1 VTT RT9199GP (+1.5V---0.75 1.5A)
+5VDUAL +5V AO4468 (8A)
CPU_VDDA_RUN APL5508_25DC_TRL SO789_3 (+3.3V---2.5V 500MA)
A
2, +1.8V ramp before +1.1v +1.8V APL5930 (+3.3V---1.8 1.5A)
+3.3VDUAL +3.3V AO4468 (8A) A
VLDT +1.1V JUMPER (4A)
3. +1.1V ramp before VCC_NB CPU_VDDR
+1.1VDUAL
APL5912
APL5930
(+1.5V---1.05V 4A)
(+3.3V---1.1V 500MA)
CPU_VDDIO +1.5V
_SUS
AO4468 (5A)

Title
Power sequence
C 1.0
BM5016
5 4 3 2 1

B465

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5 4 3 2 1

PRELIMINARY GUAM S1G4 SCHEMATIC DESIGN

Channel B UNBUFFERED DDR3

LVDS CON LVDS MUX RS880M

HyperTransport LINK0 CPU I/F

BATTERY CHAGER CPU CORE CPU MEMORY POWER

Bitland Information Techonogy Co.,Ltd.

CPU_VDDIO_SUS@9A CPU_VDDIO_SUS HD CODEC

+1.1V DUAL +1.1V

Power on Sequence required:

RS880: CPU_CLKP/N running

RC=~22ms VCC_NB should not ramp before 1.1v

VRM_PWRGD AND 1V8_PWRGD

Power button from EC to SB

Power button pressed

Bitland Information Techonogy Co.,Ltd.

EXTERNAL CLOCK MODE NB CLOCK INPUT TABLE

CLK_REQ in CLK GEN

PCIE_REFCLKP/N PCIE GFX PARK_XT(RS880M, 16 LANES) 25M Hz

AMD CPU_CLKP/N EXTERNAL AMD SB800

PCIE GPP I/F (RS880M, 1 LANE) JMC261 AZ_BIT_CLK

INTERNAL CLOCK MODE

SPI ROM & HEADER

FOR MASTER FOR RTC FOR SATA

25M Hz 32.768K Hz 25M Hz

1.5V TSI translate 3.3V TSI KBC

SID SDA3 (S5-S0)

SMBus Block Diagram

F24 SDATA0 SDA0

4-PIN CPU FAN mini MAX17009

THERM# CPU Thermal

G0 S0 C0 Running P-state transitions ON ON ON ON ON

G2 S5 OFF Soft-off ON ON ON OFF OFF

24 6251_DCIN 1 2 1.5A Isense_SYSN

PC143 C0402 C0603 C1206

PR175 PR176 PAK1212-8

R0402 1000pF/50V,X7R R0402 PL3

PC130 1 2 C0402 10uH/4A/68mOHM

PC126 1N4148WS PL11

1 2 PC131 1 2 C0402 6 C0402 LS2_1040

R0402 PR37 PR179 TPC60

NC_15.4K,1% PR49 50mOHM,1% NC_TestP

6.98K,1% C0402 PR181

R0402 PC129 2.2

R0402 1N4148WS/LMDL914T1G_SOD323-2~D 1N4148WS/LMDL914T1G_SOD323-2~D

R0402 7 1 2 ADC1 49 1 2 CELL PIN 3 GND VCC_358 LI-4CELLS :18.0V----BATT-OVP=2.001V

R0402 LM358DT_SO8 3ADPT_OUVP_DET 49 BATT_OVP 1 2 7

PR266 1 2 NC_100K,1% 133K,1% R0402 C0402

0.66V 400mA Input OVP : 22.3V

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Offset & VIN3

change from 16.2k to 16.5k SIR466DP-T1-GE3 SIR466DP-T1-GE3

2 1 1 R134 NC_10K_5% R130 16.2K_1%

Close to R170 10K_1%

R113 NC_0R X7R R38:Not Assembly

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Bitland Information Techonogy Co.,Ltd.

update on rev:1.1 PR114

RS880M VCC_NB 0.95V 1.1V N/A

SI4172DY-T1-GE3 0.95V 1.25V

PJ11 VCC_NBP 68nf_0603_50V7K When JU2903 is installed with a jumper

JUMP_43X118 LS2_1040 nc_0.01U_0402_25V7K

6TPC47MB 6TPC47MB @ 680P_0402_50V7K 2 1 2 1BST_VCC_NB

VLDT +1.1V C2147 C2177