sensors

Article
Enhanced Passive RF-DC Converter Circuit Efficiency
for Low RF Energy Harvesting
Issam Chaour 1,2, *, Ahmed Fakhfakh 3 and Olfa Kanoun 1
1 Chair of Measurement and Sensor Technology, Technische Universitt Chemnitz, 09126 Chemnitz, Germany;
olfa.Kanoun@etit.tu-chemnitz.de
2 National Engineering School of Sfax, University of Sfax, Sfax 3038, Tunisia
3 National School of Electronic and Telecommunication (ENETCom), Sfax 3018, Tunisia;
ahmed.fakhfakh@isecs.rnu.tn
* Correspondence: issam.chaour@etit.tu-chemnitz.de; Tel.: +49-371-5313-4399; Fax: +49-371-531-834-399

Academic Editor: Davide Brunelli

Received: 9 January 2017; Accepted: 6 March 2017; Published: 9 March 2017

Abstract: For radio frequency energy transmission, the conversion efficiency of the receiver is
decisive not only for reducing sending power, but also for enabling energy transmission over long
and variable distances. In this contribution, we present a passive RF-DC converter for energy
harvesting at ultra-low input power at 868 MHz. The novel converter consists of a reactive matching
circuit and a combined voltage multiplier and rectifier. The stored energy in the input inductor and
capacitance, during the negative wave, is conveyed to the output capacitance during the positive
one. Although Dickson and Villard topologies have principally comparable efficiency for multi-stage
voltage multipliers, the Dickson topology reaches a better efficiency within the novel ultra-low input
power converter concept. At the output stage, a low-pass filter is introduced to reduce ripple at
high frequencies in order to realize a stable DC signal. The proposed rectifier enables harvesting
energy at even a low input power from 40 dBm for a resistive load of 50 k. It realizes a significant
improvement in comparison with state of the art solutions.

Keywords: radio frequency energy transmission; RF-DC Converter; rectifier; power efficiency;
voltage multiplier; Villard topology; Dickson topology

1. Introduction
The use of energy harvesting technologies in wireless sensor networks (WSN) enables reducing
installation and maintenance efforts for autonomous systems [1]. It helps to overcome many challenges,
such as difficult direct access, flexible use, and working under harsh environmental conditions.
Nevertheless, in some cases, using only energy harvesting [2] is not sufficient because of the lack of
availability of ambient energy, aging effects, and changing ambient conditions.
Wireless power transmission provides a potential solution to support energy harvesting as an
additional source and is able to bridge a relatively long distance between a sensor node and its power
source [3]. The transmitted radio frequency (RF) power can reach a level of microwatts (W) to
milliwatts (mW) DC, which is a useful range for charging batteries or powering battery-free devices.
The main challenge of RF energy transmission is the low level of the received power and the
RF-DC power conversion efficiency (PCE). In this paper, we investigate possibilities to improve the
efficiency at the receiver side. In order to be able to convert RF energy even from low power ambient RF
sources, it is necessary to optimize the system design, especially for low RF energy density. Therefore,
we focus on the rectifier circuit, due to the interesting possibilities to reduce energy losses.
This paper is structured in three main sections. In Section 2, a short description of the related
challenges and solutions for RF power transmission is presented followed by a discussion on RF

Sensors 2017, 17, 546; doi:10.3390/s17030546 www.mdpi.com/journal/sensors

Sensors 2017, 17, 546 2 of 14

energy conversion and storage. Section 3 describes the Villard voltage rectifier circuit for RF-DC
converters and discusses the component selection. Finally, the novel approach for an RF-DC voltage
Sensors 2017, 17, 546 2 of 14
multiplier rectifier circuit is detailed, illustrating the simulation results and undertaking the proved
circuit performance.
energy conversion and storage. Section 3 describes the Villard voltage rectifier circuit for RF-DC
2. RF Energy
converters Conversion
and andcomponent
discusses the Storage selection. Finally, the novel approach for an RF-DC voltage
multiplier rectifier
RF transfer circuitsophisticated
requires is detailed, illustrating
circuits forthe simulation
conversion results
and andthe
storage undertaking theambient
available RF proved
circuit performance.
energy on the receiver side [4]. As shown in Figure 1, this can be reached by the optimization interface
between the rectenna (rectifying antenna), and typical storage unit for the WSN. The main aim is to
2. RF Energy Conversion and Storage
reach a high overall efficiency by minimizing discontinuities and signal reflections [5]. For that, a
reactive
RF matching circuit connects
transfer requires the antenna
sophisticated circuitsto
forthe rectifier under
conversion optimized
and storage operatingRF
the available conditions
ambient
[6].
energy on the receiver side [4]. As shown in Figure 1, this can be reached by the optimization interface
RF wave
between propagation
the rectenna models
(rectifying are available
antenna), to evaluate
and typical storagethe received
unit RF power.
for the WSN. The received
The main aim is to
power
reach a(Phigh
r) by overall
the antenna placed
efficiency byatminimizing
a distance Rdiscontinuities
from the transmitter antenna
and signal can be expressed
reflections as ina
[5]. For that,
Equation (1) [7]. circuit connects the antenna to the rectifier under optimized operating conditions [6].
reactive matching

Figure
Figure 1.
1. RF
RFenergy
energy harvesting
harvesting sensor
sensor design.
design.

RF wave propagation models are available 2

to evaluate the received RF power. The received
C 1 n R
P P G
power (Pr ) by the antenna placed at ar distanceG
t t rR from the transmitter
e antenna can be expressed as(1)
in
4 f R
Equation (1) [7].
 2   n
where Pt is the power transmitted P which C to
corresponds 1 input
the power to the transmitter antenna,
r = P G G
t t r eR (1)
Gt and Gr are, respectively, the gains of receiving4andf transmitting
R antennas, C is the speed of light,
and
where f isPtthe RF power
is the signal transmitted
frequency. which
is thecorresponds
effective decay coefficient
to the input powerin airto and is equal to antenna,
the transmitter 0.001. n
denotes the path loss exponent and is equal to 2 in free space. As it is shown P
Gt and Gr are, respectively, the gains of receiving and transmitting antennas, C is the speed of light,r depends on multiple
factors:
and f is the
the RFpower of frequency.
signal RF source,size/performance of receiving
is the effective decay antenna,
coefficient in air andtransmission frequency
is equal to 0.001. and
n denotes
the
the distance
path lossfrom the RFand
exponent source [8]. to 2 in free space. As it is shown Pr depends on multiple factors:
is equal
Since special regulations
the power of RF source, size/performanceexist for RF power transmission,
of receiving it makes
antenna, sense to use
transmission the freeand
frequency license
the
frequency
distance from bands,theorRFindustrial,
source [8].scientific, and medical bands (ISM). They should be classified as either
nonspecific short-range
Since special devices
regulations (SRD),
exist for RFwideband data transmission
power transmission, it makes systems,
sense toor useradio frequency
the free license
identification (RFID) applications [9,10]. For example, 867.6868 MHz
frequency bands, or industrial, scientific, and medical bands (ISM). They should be classified band is one of the RFID as
frequency ranges short-range
either nonspecific used in ultra-high frequency
devices (SRD), SRD applications.
wideband data transmissionFor this band,oritradio
systems, is allowed
frequencyto
transfer until 500
identification mW applications
(RFID) effective radiated
[9,10].power (ERP) in Europe
For example, 867.6868 withMHz200 band
kHz ofis coupling
one of thechannel
RFID
spacing [11].
frequency ranges used in ultra-high frequency SRD applications. For this band, it is allowed to transfer
untilMany
500 mW ruleeffective
parts specify RF power
radiated power (ERP)
transmission
in Europelimits in200
with terms
kHz ofof
ERP or equivalent
coupling channelisotropically
spacing [11].
radiated power (EIRP). ERP and EIRP are defined in linear terms as
Many rule parts specify RF power transmission limits in terms of ERP or equivalent the product of the antenna gain
isotropically
and the input
radiated power power.
(EIRP). ERP and EIRP are defined in linear terms as the product of the antenna gain
A lot of calculations
and the input power. and analyses are required to investigate the efficiency and performance of
RF power
A lot of calculations and approximate
transfer. After this study, itto
analyses are required is investigate
basic to note thethat increasing
efficiency and frequency
performance leads to
of RF
power transfer. After this approximate study, it is basic to note that increasing frequency leads to a
reduction in the received power level, hence, the decrease in the yield. To solve this problem, studying
 Sensors 2017, 17, 546 3 of 14
Sensors 2017, 17, 546 3 of 14
a reduction in the received power level, hence, the decrease in the yield. To solve this problem,
studying the rectification systems characterized by low power loss and high efficiency to recover the
the rectification systems characterized by low power loss and high efficiency to recover the maximum
maximum RF energy transmitted is needed.
RF energy transmitted is needed.
3. Basic Rectifier Circuit for RF Applications
3. Basic Rectifier Circuit for RF Applications
An impedance matching circuit between the received aerial and rectifier circuit is necessary to
An impedance matching circuit between the received aerial and rectifier circuit is necessary to
increase the voltage gain and further reduce reflection and transmission loss. For low-power and
increase the voltage gain and further reduce reflection and transmission loss. For low-power and
sensing applications, the main aim to satisfy after rectification is to recover the maximum amount of
sensing applications, the main aim to satisfy after rectification is to recover the maximum amount of
power and reduce the power loss caused by the rectifier circuit. Many investigations showed that
power and reduce the power loss caused by the rectifier circuit. Many investigations showed that
when the applied power is low, the rectifier circuit efficiency is also low. Therefore, in order to rectify
when the applied power is low, the rectifier circuit efficiency is also low. Therefore, in order to rectify
low RF signals at a high efficiency, it is interesting to improve the rectifier [12]. Power-conversion
low RF signals at a high efficiency, it is interesting to improve the rectifier [12]. Power-conversion
efficiency (PCE) or RF-to-DC conversion efficiency, is an important rectification metric for optimal
efficiency (PCE) or RF-to-DC conversion efficiency, is an important rectification metric for optimal
wireless power transmission [13] and is calculated as follow Equation (2):
wireless power transmission [13] and is calculated as follow Equation (2):
DC Output Power
PCE DCRF Output (2)
PCE = Incident Power Power
Reflected RF Power (2)
Incident RF Power Reflected RF Power
The voltage multiplier structure is considered for RF-DC power conversion system design
The voltage
because multiplier
it rectifies structure
peak-to-peak is considered
voltage for RF-DC
from the full-wave power
of the conversion
RF signal. system designare
Two configurations
because it rectifies peak-to-peak voltage from the full-wave of the RF signal. Two
arranged in a cascade using Schottky diodes to provide a passive voltage offset before rectification configurations are
arranged in a cascade using Schottky diodes to provide a passive voltage offset before
[14]. The conventional voltage multiplier rectifier forms a peak rectified by D1 and C2, while a voltage rectification [14].
The conventional
clamp is formed voltage D2. rectifier forms a peak rectified by D1 and C2 , while a voltage clamp
multiplier
by C1 and
is formed by C1
The circuit and D .
can 2be also called a voltage doubler, thereby, the output voltage is approximately
The circuit can be also called
twice the input voltage. The RF a voltage doubler,
input signal thereby, during
is rectified the outputthe voltage
positiveisalternative.
approximately Thetwice
stored
thevoltage
input voltage. The RF input signal is rectified during the positive alternative. The stored
on the input capacitor C1 during the negative alternative is transmitted to the output capacitor voltage on
theCinput capacitor C during the negative alternative is transmitted to the output
2 during the next 1positive alternative of the RF input signal. Thus, the voltage on C2 is roughly
capacitor C2 duringtwo
thetimes
next the
positive alternative of the RF input signal. Thus, the voltage on C 2 is
peak voltage of the RF source minus two times the turn on voltage of the diode [15].roughly two times the
peak voltage of the RF
One voltage sourcecircuit
doubler minuscantwo betimes the turn
extended to non voltage
stages of the diode
in cascade [15]. higher DC output
to achieve
voltage levels. In the Villard topology the stages are connected in series and higher
One voltage doubler circuit can be extended to n stages in cascade to achieve behaveDC output to
similarly
voltage levels.
batteries In the Villard
in cascade, topology
multiplying the stages
the output are Figure
voltage. connected in seriesaand
2 illustrates two behave similarly
stages Villard to
voltage
batteries in cascade, multiplying the output voltage. Figure 2 illustrates a two stages
multiplier circuit. Each Villard stage acts as a passive voltage shifter producing a DC offset voltage Villard voltage
multiplier circuit.
for the next Each Villard stage acts as a passive voltage shifter producing a DC offset voltage for
stage.
the next stage.

Figure
Figure Two-stage Villard
2. 2. Two-stage Villardand
andDickson
Dickson configuration
configuration for for a combined
a combined voltage
voltage multiplier
multiplier rectifier
rectifier circuit.
circuit.

TheThe stage
stage numberused
number usedininthe
therectifier
rectifierhas
has aa major influence on
on the
theharvesting
harvestingcircuit.
circuit.Since one
Since
rectifier
one rectifierstage
stagemay
mayyield
yieldto
toanan unused voltage and
unused output voltage andtoo
toomany
manyVillard
Villardstages
stages dampens
dampens thethe
multiplier effect by reducing the impedance reactive component. Thus, practical constraints oblige a
 Sensors 2017, 17, 546 4 of 14
Sensors 2017, 17, 546 4 of 14

limitation
multiplieron the permitted
effect by reducing stages due to the capacitor
the impedance parasitic effect
reactive component. of each
Thus, stage.constraints
practical Thus, the voltage
oblige a
can be increased
limitation on theby increasing
permitted the circuit
stages due to stage number,parasitic
the capacitor which increases the power
effect of each stage. loss.
Thus, the voltage
can The circuit isby
be increased efficient onlythe
increasing when the stage
circuit couplingnumber,capacitances (C1.1, C1.2the
which increases Cpower
1.n) areloss.
higher than the
connection capacity
The circuit to eachonly
is efficient circuit
whennode the(Ccoupling
2.1, C2.2C 2.n). In addition,
capacitances (C1.1the
, C1.2capacitors present
. . . C1.n ) are a high
higher than
parasitic capacitance
the connection capacityrelative to the
to each substrate.
circuit node (CTo 2.1 ,overcome
C 2.2 . . . C these
2.n ). In problems,
addition, Dickson
the proposed
capacitors presentthea
circuit presented
high parasitic in Figurerelative
capacitance 2 [16].toItthe is substrate.
characterized by an effective
To overcome voltage Dickson
these problems, multiplication
proposed with
the
relative low parasitic
circuit presented effects
in Figure [17].
2 [16]. It isAcharacterized
comparison by between
an effectivethe twovoltagearchitecture
multiplication topologies was
with relative
performed
low parasiticin [18].
effectsFor lowAvoltages,
[17]. comparison the between
two circuits offerarchitecture
the two similar performance.
topologies was performed in [18].
For low voltages, the two circuits offer similar performance.
4. Novel Approach for an RF-DC Converter Based on Voltage Multiplier Circuit
4. Novel Approach for an RF-DC Converter Based on Voltage Multiplier Circuit
The principal aim is energy harvesting from low RF density waves available at 868 MHz. The
received TheRFprincipal aim is energy
power generally rangesharvesting
from 0 to 30 from dBmlowrelative
RF density waves available
to transmitted power. We at 868 MHz.
propose
The received RF power generally ranges from 0 to 30 dBm relative
adding an inductor L in series with C1 (Figure 3) in order to store the energy in a magnetic field. to transmitted power. We propose
addingisanstored
Energy inductor
duringL in the
series with Ccycle
negative 1 (Figurewave 3) and
in order
returnedto store the energy
during in a magnetic
the positive one. The field. Energy
couple (L,
Cis1) stored
operatesduring
like antheadditional
negative cycle
powerwave source and returned
during during the
the positive positive [19].
alternation one. The
The power (L, C1 )
couplestored
inoperates like an additional
the inductance magneticpower source
field is givenduring
by thethe positive alternation
following [19]. The(3),
relation, Equation power storedofinthe
in terms the
i: magnetic field is given by the following relation, Equation (3), in terms of the current i:
inductance
current

didi
P=
P L
L ii
dt
(3)
(3)
dt

(a) (b) (c)

Figure
Figure3.3.(a)
(a)Novel
Novelapproach
approachforforaavoltage
voltagemultiplier
multipliercircuit;
circuit;(b)
(b)Equivalent
Equivalentcircuit
circuitduring
duringthe
thepositive
positive
wave; (c) Equivalent circuit during the negative wave.
wave; (c) Equivalent circuit during the negative wave.

4.1. Novel Approach for a Signal Voltage Multiplier Circuit

4.1. Novel Approach for a Signal Voltage Multiplier Circuit
To explain the principle of this approach, we have carried out a simulation of the circuit at low
To explain the principle of this approach, we have carried out a simulation of the circuit at low
frequency with standard elements using Simplorer software. Figure 4 illustrates the inductor voltage
frequency with standard elements using Simplorer software. Figure 4 illustrates the inductor voltage
and current during the transitional period.
and current during the transitional period.
The current passing through the inductor is always continuous. The potential of the inductor is
The current passing through the inductor is always continuous. The potential of the inductor
not proportional to the inductor current. The current passing through the inductor is constantly
is not proportional to the inductor current. The current passing through the inductor is constantly
charging and discharging. Therefore, the inductor generates an opposite voltage polarity in order to
charging and discharging. Therefore, the inductor generates an opposite voltage polarity in order
limit the current variation [20]. This potential can be used to charge the capacitances C1 and C2.
to limit the current variation [20]. This potential can be used to charge the capacitances C1 and C2 .
Current and voltage discontinuity, presented in Figure 4, is caused by the status variation of diodes
Current and voltage discontinuity, presented in Figure 4, is caused by the status variation of diodes D1
D1 and D2. The simulation results show the voltage behavior of the circuit elements for different time
and D2 . The simulation results show the voltage behavior of the circuit elements for different time
slots (Figure 5).
slots (Figure 5).
Sensors 2017, 17, 546 5 of 14
Sensors 2017, 17, 546 5 of 14

Figure 4. Current and voltage of the added inductor.

Figure 4. Current and voltage of the added inductor.

Figure 5. Voltage behavior of the rectifier circuit elements.

Figure 5. Voltage behavior of the rectifier circuit elements.

During
During phasephase is D
1, D2 1, 2 is blocked
blocked until until the condition
the condition givengiven by Equation
by Equation (4) is (4) is fulfilled:
fulfilled:

VC1VC>1
VV V V Ri
inin Vl l V Ri (4)

3CMarch 2017 and C2 are equal to 1 mF. The negative alternation of the input voltage (Vin equal 5
1 and C2 are equal to 1 mF. The negative alternation of the input voltage (Vin equal 5 V, the
V, the frequency
frequency is equalis equal to 1 crosses
to 1 kHz) kHz) crosses
D1 to D 1 to charge
charge the capacitor
the capacitor C1 the
C1 and andinductor
the inductor
L. We L.denote
We denote
that
that R is equal to 0.1 , which is the internal resistance, and V is equal to 0.8 V, which is
R is equal to 0.1 , which is the internal resistance, and V is equal to 0.8 V, which is the threshold
the threshold
voltage
voltage ofof the diodes. The
the diodes. The variation
variation of the inductor
of the inductor current
current ii causes
causes an
an opposite
opposite voltage
voltage polarity
polarity VVLL
across
across its
its terminals.
terminals. TheThe voltage
voltage V VC1 across C1 is determined by Equation (5):
C1 across C1 is determined by Equation (5):

V V V V Ri
C1 V in V l V Ri
VC1 = (5)
(5)
in l

During phase 2, D1 is blocked and the capacitance C1 discharges through D2 to charge the
capacitor C2. The voltage across C2 is determined by Equation (6):
Sensors 2017, 17, 546 6 of 14

During phase 2, D1 is blocked and the capacitance C1 discharges through D2 to charge the
Sensors 2017,C
capacitor 17,. 546
The
voltage across C2 is determined by Equation (6): 6 of 14
2

VC2V = V
C2 V +VVin +VVl V
C1 C1 in
Ri
V
l
Ri

(6)
(6)
The system
The system change
change the
the status
status from
from phase
phase 22 to
to another
another phase
phase when
when Equation
Equation (7)
(7) is
is fulfilled:
fulfilled:

VC>2 VC1
VC2 VC+1 V Vl lV
Vinin+V V
Ri
Ri (7)
(7)

During phase
During phase 3,
3, both
both diodes
diodes D D11and
andDD22areareblocked
blockedas aslong
longas asEquations
Equations(4) (4)and
and(7)
(7)are
areverified.
verified.
The
The charging cycle of C or C restarts again depending on the conditions established
cycle of C11 or C22 restarts again depending on the conditions established by Equations by Equations (4)
(4) or (7).
or (7). At At
thethe end,
end, thethe system
system C1 C
is stable.
is stable. C2Cmaintain
1 and
and 2 maintain thethe charge
charge level.
level.
The
The proposed
proposed approach
approach aims
aims toto ameliorate
ameliorate the the charging of capacitances C11 and and CC22 using
using the
the
opposite voltage polarity
opposite voltage polaritygenerated
generatedbyby thethe inductor
inductor L. Figure
L. Figure 6 shows
6 shows a comparison
a comparison between
between the
the classic
classic
voltagevoltage multiplier
multiplier circuit
circuit and theand theapproach.
novel novel approach.
The novelTheapproach
novel approach
providesprovides higher voltage
higher output output
voltage
(VC2 ) and(VC2 ) and exceeds
exceeds thevoltage
the classic classic voltage multiplier
multiplier circuit (Vcircuit (VC20
C20 ). The ). The establishing
system system establishing time is
time is reduced
reduced by the
by the same same inductor.
inductor. SimulationsSimulations
with variedwith variedvalues
inductor inductor values
show show
a better a better performance
performance for L equal
for L equal
to 0.023 mHto(Figure
0.023 mH6). (Figure 6).

Figure
Figure 6.
6. Comparison
Comparison between
between the the classic
classic voltage
voltage multiplier
multiplier (V
(VC20 ) and the novel approach with
C20 ) and the novel approach with
different inductor values (L, L1 = L + L, and L2 = L L corresponding
different inductor values (L, L1 = L + L, and L2 = L L corresponding to to
VC2V, C2
VC21
, V, C21
and, and
VC22).VC22 ).

The first sub-circuit of Figure 3 represents a second order system. The solution of its equations
The first sub-circuit of Figure 3 represents a second order system. The solution of its equations
leads to determine the charging expression of C1, as defined in Equation (8):
leads to determine the charging expression of C1 , as defined in Equation (8):
(V V s in ) V in c o s i
V C 1 ( t) e tt(Vh V s in ) c o s t (VV sin )Vin cos s in t
VC1 (t) = e (V V sin ) cos t + sin t + (8)
(8)
V s in ( in t ) V V sin(in t + ) V

Where
Where V V (Equation
(Equation(9)) and(Equation
(9))and (Equation(10))
(10))are,
are,respectively,
respectively, the
the amplitude
amplitude and
and the
the phase
phase ofof
the particular solution.
the particular solution.
Vin
V= q V (9)
V 2 2 2 in 2 2
C1 in R + (C1 Lin 12) (9)
C 2 2 R 2 C1 Lin 2 1
1 in
RC1 in
= arcsin q (10)
C 2 2 R2 + (C L 2 1)2

1 in RC 1 in
1 in
arcsin (10)
2

C12 in 2 R 2 C1 Lin 2 1

The damping coefficient is defined in Equation (11):
 Sensors 2017, 17, 546 7 of 14
Sensors 2017, 17, 546 7 of 14

R
(11):
The damping coefficient is defined in Equation (11)
2L
The comparison between the simulation and R
= the analytical expression validates the expression (11)
of VC1 during phase 1. For phase 2, C1 is discharging 2L and C2 is charging. From the simulation results,
VC1The
andcomparison
VC2 are characterized
between thewith the sameand
simulation slope
thebut in opposite
analytical sign (negative
expression validatesfor
theVexpression
C1 and positive
of
V C2). In order to determine the expression of the optimal inductor value from the expression of VC2
VC1 during phase 1. For phase 2, C1 is discharging and C2 is charging. From the simulation results,
max,
VC1 anditVis necessary to express the initial charge of C1 for phase 2. Since it is difficult to solve such
C2 are characterized with the same slope but in opposite sign (negative for VC1 and positive
equations with
VC2 ). In order multiple transcendental
to determine the expression functions, we propose
of the optimal inductortovalue
solvefrom
it with
the numerical
expressionmethods.
of VC2
After multiple simulations, with a varied input parameters, the result show that
max, it is necessary to express the initial charge of C1 for phase 2. Since it is difficult equal
for to in the
solve such
system has
equations a higher
with outcome.
multiple Where functions,
transcendental in is the pulse of the input signal and is defined in Equation
we propose to solve it with numerical methods.
(12):
After multiple simulations, with a varied input parameters, the result show that for equal in
the system has a higher outcome. Where in is the pulse 2of the input signal and is defined in
1 R
Equation (12): 2 (12)
s LC1 4 L
1 R 2
= 2 (12)
Based on these simulations results, it is LC
easy
1 to4L give an optimal expression estimation of L
(Equation (13)):
Based on these simulations results, it is easy to give an optimal expression estimation of L
(Equation (13)): 2 2
p 1 1C R in
2
L
1 + 1 C2 C 2 Rin in 2
2 2
(13)
L= (13)
2Cin 2

4.2.
4.2. Proposed
Proposed Signal
Signal Voltage
Voltage Multiplier
Multiplier Circuit
Circuit
The
The incident
incident RFRF signal
signal waves
waves captured
captured byby
thethe receiver
receiver antenna
antenna areare converted
converted into
into a DC
a DC signal
signal
byby a simple
a simple topology
topology based
based onon a voltage
a voltage multiplier
multiplier used
used forfor
thethe RF-DC
RF-DC converter
converter circuit.
circuit. The
The major
major
feature of this architecture is just to multiply the input voltage to its output
feature of this architecture is just to multiply the input voltage to its output terminal using the terminal using the
continuous
continuous voltage
voltage component
component of previous
of the the previousstagestage
addingadding
to thetorectified
the rectified RF of
RF signal signal of the
the next next
stage.
Thestage. The multiplier
multiplier circuit using
circuit is designed is designed using two
two zero-based zero-based
HSMS-2850 HSMS-2850
Schottky Schottky diodes
diodes characterized by
lowcharacterized by lowand
threshold voltage threshold voltage operating
high switching and high frequency
switching [21].operating frequency
The output voltage[21]. The output
depends on
thevoltage
storagedepends on the
capacitance. storage
The capacitance.
capacitors are chosen Thewith
capacitors
a lowerare chosen
value with athe
to reduce lower valuetime
charging to reduce
and
theofcharging
rise time speed
the switching and rise of the
of the switching
whole circuit. speed
Figureof the whole
7 presents circuit.
one Figure design
stage circuit 7 presents
tunedone
to stage
the
circuit design tuned to the unlicensed ISM band at 868 MHz. In order to
unlicensed ISM band at 868 MHz. In order to obtain good DC output and reduce ripples, a low pass obtain good DC output and
reduce
filter ripples, ainlow
is associated pass filter
cascade to theisRF-DC
associated in cascade
converter to The
circuit. the RF-DC
output converter
inductor andcircuit. The output
capacitor are
inductor and capacitor are chosen
chosen to filter the high frequencies. to filter the high frequencies.

Figure 7. Proposed single stage voltage multiplier RF-DC converter.

Figure 7. Proposed single stage voltage multiplier RF-DC converter.

A 50 k load is connected at the output to measure the outcome power and to visualize the
A 50behavior
circuit k load is connected
(Figure at the
8). The loadoutput
valueto
is measure the outcome
chosen relative to thepower
sensorand to visualize
node impedance theincircuit
a deep
behavior (Figure 8). The load value is chosen relative to the sensor node impedance in a deep
sleep state. For the operating frequency, the signal is well filtered with an attenuation of 40 dB. sleep
state. For the operating frequency, the signal is well filtered with an attenuation of 40 dB.
 Sensors
Sensors 2017,
2017, 17, 546
17, 546 8 of8814
of 14
Sensors 2017, 17, 546 of 14

Figure
Figure
Figure 8. Frequency
8. Frequency
8. Frequency response
response behavior
behavior
response of the
of the
behavior of the proposed
proposed rectifier
rectifier
proposed design.
design.
rectifier design.

4.3.4.3.
Simulations for for
Simulations
Simulations a Modified Voltage
a Modified Multiplier
Voltage Circuit
Multiplier Circuit
TheThe
modified
modified voltage doubler
voltage doublercircuit is simulated
circuit using
is simulated Advanced
using Design
Advanced System
Design (ADS)
System from
(ADS) from
Agilent. The ADS
Agilent. The
The ADS simulation
ADSsimulation employs
simulationemploys the
employsthe device
thedevice model
model
device of
model HSMS-2850
of HSMS-2850 Schottky
Schottky
of HSMS-2850 diode
diode
Schottky parameters
parameters
diode and
parameters
andand
achieved
achieved theresults
the
achieved results
the presented
presented
results inin
presented Figure
Figure 9.9. 9.
in Figure

(a) (a) (b)(b)

Figure 9. Simulation
Figure
Figure 9. Simulation
9. Simulationresults ofofthe
results
results proposed
ofthethe
proposed rectifier
proposed design.
rectifier
rectifier (a)Input
design.
design. (a) Input
(a) RFRF
Input wave
RF
wave form;
wave
form; (b) (b)
form; Output
(b)
Output Output
power
power after
power the
after rectifier
the circuit.
rectifier
after the rectifier circuit. circuit.

To To
discuss thethe
discuss RF-DC
RF-DC converter
converter circuit performances,
circuit performances, simulations
simulationswerewerecarried out.out.
carried TheTheresults
results
To discuss the RF-DC converter circuit performances, simulations were carried out. The results
presented in Figure 10 show the conversion efficiency for one and three multiplier
presented in Figure 10 show the conversion efficiency for one and three multiplier stages for variablestages for variable
presented in Figure 10 show the conversion efficiency for one and three multiplier stages for variable
input power
input powerfromfrom4040to to
20 20
dBm.
dBm.TheThe proposed
proposed design
designwith inductor
with inductoris compared
is compared to to
thethe
classic
classic
input power from 40 to 20 dBm. The proposed design with inductor is compared to the classic
voltage multiplier circuit without inductor for a resistive load of 50 k. The novel
voltage multiplier circuit without inductor for a resistive load of 50 k. The novel design reaches design reaches an an
voltage multiplier circuit without inductor for a resistive load of 50 k. The novel design reaches an
efficiency which
efficiency which is much
is much higher than
higher thanthethe
classic
classicvoltage multiplier
voltage multipliercircuit, especially
circuit, especially forforlowlow
input
input
efficiency which is much higher than the classic voltage multiplier circuit, especially for low input
power. With one stage, the novel design reaches greater efficiency, with a peak
power. With one stage, the novel design reaches greater efficiency, with a peak of 79%. With three of 79%. With three
power. With one stage, the novel design reaches greater efficiency, with a peak of 79%. With three
stages, thethe
stages, novel
noveldesign
design reaches
reaches83%83% peak efficiency.
peak TheThe
efficiency. novel RF-DC
novel RF-DC converter
converter circuit
circuitconsists of of
consists
stages, the novel design reaches 83% peak efficiency. The novel RF-DC converter circuit consists
diodes,
diodes,which
whichhavehavenonlinear
nonlinear component
component behavior.
behavior.In In
addition,
addition,thethe
circuit
circuitdesign
design itself exhibits
itself exhibits
of diodes, which have nonlinear component behavior. In addition, the circuit design itself exhibits
nonlinear effects due to the parasitic influence of the used elements. This implies that
nonlinear effects due to the parasitic influence of the used elements. This implies that the response the response of of
nonlinear
thethe
harvester effects
circuitdue to the
varies parasitic
with the influencepower
received of theamount
used elements.
deliveredThisbyimplies
the that theRF
antenna. response
input of
harvester circuit varies with the received power amount delivered by the antenna. RF input
the harvester
power variation circuit
does varies
not with the
correlate withreceived
thethe power
output amount
power delivered
of the by the
harvesting antenna. RF input power
circuit.
power variation does not correlate with output power of the harvesting circuit.
variation does not correlate with the output power of the harvesting circuit.
Sensors 2017, 17, 546 9 of 14
Sensors 2017, 17, 546 9 of 14
Sensors 2017, 17, 546 9 of 14

Figure 10.
Figure 10. Comparison
Comparison between
between the
the proposed
proposed rectifier
rectifier design efficiency and
design efficiency and the
the classic
classic voltage
voltage
Figure 10. efficiency.
multiplier Comparison between the proposed rectifier design efficiency and the classic voltage
multiplier efficiency.
multiplier efficiency.
The output load of the RF-DC converter circuit needs to be improved using harmonic balance in
The
The output load
output load ofof the
the RF-DC
RF-DC converter
converter circuit
circuit needs
needs to
to be
be improved
improved using
using harmonic
harmonic balance in
order to enhance the PCE. The output DC power is measured around 50 k resistive load.balance in
Figure 11
order
order to
to enhance
enhance the
the PCE.
PCE. The
The output
output DC
DC power
power is
is measured
measured around
around 50
50 k
k resistive load.
resistive load. Figure 11
Figure 11
illustrates the load influence on one stage RF-DC converter circuit PCE. The previous simulation
illustrates
illustrates the load
load influence on
on one stage RF-DC converter circuit PCE. The previous simulation
parametersthe influence
and a variable one
resistive stage
load are RF-DC
used to converter
investigatecircuit PCE.
the load The on
impact previous simulation
the PCE. Referred
parameters
parameters and
and a
a variable
variable resistive
resistive load
load are
are used
used to
to investigate
investigate the
the load
load impact
impact on
on the
the PCE.
PCE. Referred
Referred
to the sensor node impedance and according to sleep mode, the proposed RF-DC converter is loaded
to
to the sensor
sensor node
node impedance
impedance andand according
according to sleep mode,
mode, the
the proposed
proposed RF-DC
RF-DC converter
converter is
is loaded
bythe
50 k. to sleep loaded
by
by 50
50 k.
k.

Figure 11. Load influence on the signal stage modified voltage multiplier efficiency.
Figure 11.
Figure Load influence
11. Load influence on
on the
the signal
signal stage
stage modified
modified voltage
voltage multiplier
multiplier efficiency.
efficiency.
The novel designed RF-DC converter is capable to convert an RF wave to a DC signal and
The novel
achieving higherdesigned
efficiencyRF-DC
based converter
on passiveiselements.
capable Simulations
to convert anareRF wave to in
conducted a DC
ADSsignal
underand
the
achieving
achieving higher
higher efficiency
efficiency based
based on
on passive
passive elements.
elements. Simulations
Simulations are
are conducted
conducted
same scenarios in order to prove one voltage multiplier topology from Villard or Dickson in
in ADS
ADS under
under the
the
same
same scenariosinFigure
scenarios
configurations. in
orderorder
to12 to
prove provetheone
one voltage
shows voltage
multipliermultiplier
simulation topology
results topology
forfrom
twoVillardfrom
stages Villard
or Dickson or Dickson
configurations.
configuration
configurations.
compared to two Figure
stages12Villard
showsconfiguration.
the simulationTheresults
Dicksonfortopology
two stages Dickson
efficiency configuration
surpasses Villard
compared to two stages Villard configuration. The Dickson topology efficiency surpasses Villard
Sensors 2017, 17, 546 10 of 14

Figure 12 shows
Sensors 2017, 17, the
546 simulation results for two stages Dickson configuration compared to two stages
10 of 14
Villard configuration. The Dickson topology efficiency surpasses Villard topology efficiency all over
Sensors
topology2017,efficiency
17, 546 all over 10 as
of 14
the full input power range. The the full input
Dickson power range.
architecture The Dickson
is selected architecture
as a parallel is selected
capacitor configurationa to
reduceparallel capacitor
losses in configuration
each stage. to reduce losses in each stage.
topology efficiency all over the full input power range. The Dickson architecture is selected as a
parallel capacitor configuration to reduce losses in each stage.

Figure Comparison
12.12.
Figure Comparisonbetween Dicksonand
between Dickson andVillard
Villard topologies.
topologies.

Figure 12.
The number of RF-DC Comparison
converter between
stages has a Dickson andeffect
signficant Villard
ontopologies.
the circuit output power. The
The number of RF-DC converter stages has a signficant effect on the circuit output power.
voltage multiplier stages are reformed and arranged in cascade. The output power is directly
The voltage Themultiplier stages converter
number of RF-DC are reformed
stagesand
has arranged
a signficantineffect
cascade.
on theThe output
circuit
proportional to the stage number and the input power. However, practical constraints limit the
outputpower
power.isThedirectly
voltage multiplier
proportional stages are reformed and arranged in cascade. Thepractical
output power is directly
approved stages number and, therefore, the output power. Sweep input power parameters from 40 the
to the stage number and the input power. However, constraints limit
proportional to the stage number andthethe input power. However, practical constraints limitfrom
the
approved
to 20 stages
dBm wasnumber
used inand, therefore,
simulations with a output
variety power.
of stage Sweep
numbers input
frompower stages. Figure 13 40
1 to 11parameters
approved stages number and, therefore, the output power. Sweep input power parameters from 40
to 20 shows
dBm was the used
impact inof
simulations with a variety
the stages number on PCEof stage
and the numbers fromof1 the
output power to 11 stages.
new RF-DCFigure 13 shows
converter
to 20 dBm was used in simulations with a variety of stage numbers from 1 to 11 stages. Figure 13
circuit of
the impact design. Finally,
the stages the PCEonvariation
number PCE and becomes negligible.
the output powerHowever,
of the new when the stage
RF-DC number
converter circuit
shows the impact of the stages number on PCE and the output power of the new RF-DC converter
increases,
design. the efficiency curve shifts towards the higher input power region. This
Finally, the PCE variation becomes negligible. However, when the stage number increases, means an increase
circuit design. Finally, the PCE variation becomes negligible. However, when the stage number
of the power
the efficiency losses in the regionthe
of low input power.
increases,curve shifts
the efficiency towards
curve shifts higher
towardsinput powerinput
the higher region.
powerThis means
region. anmeans
This increase
an of the power
increase
lossesofinthe
the region of low input power.
power losses in the region of low input power.

Figure 13. Effect of the stage number on the power conversion.

Figure 13. Effect of the stage number on the power conversion.

Figure 13. Effect of the stage number on the power conversion.
Sensors 2017, 17, 546 11 of 14

4.4. Design
Sensors and546Experiment
2017, 17, Setup for a Modified Dual Stages Voltage Multiplier Circuit 11 of 14

Sensors
The 2017, 17, 546
receiver antenna is connected to the RF-DC converter block via a reactive matching 11 of 14
circuit
in order to
4.4. Design efficiently
and and load
Experiment and
Setup increase the voltage gain. This allows a decrease in the reflected signal
4.4. Design Experiment Setupforfora aModified
Modified Dual StagesVoltage
Dual Stages VoltageMultiplier
Multiplier Circuit
Circuit
and, therefore, losses. Figure 14 presents a two-stage voltage multiplier circuit. The return loss S11
The receiver antenna is connected to thethe
RF-DC
RF-DCconverter block via
via aa reactive
reactivematching
matching circuit in
parameterThe and receiver antenna
the circuit is connected
impedance aretomeasured converter
relative toblock
the input RF power at 10circuitdBm and
orderintoorder
efficiently
to load and
efficiently load increase
and thethe
increase voltage gain.
voltage gain.This
This allows
allows aadecrease
decrease in in
the the reflected
reflected signalsignal
the effective frequency matched to 50 .
and, therefore,
and, therefore,losses. Figure
losses. Figure1414presents
presentsaatwo-stage
two-stage voltage multiplier
voltage multiplier circuit.
circuit. TheThe return
return loss loss
S11 S11
parameter
parameter andcircuit
and the the circuit impedance
impedance areare measured
measured relative
relative totothe
theinput
inputRFRFpower
power at at
10
10dBm
dBmand and the
the effective
effective frequency frequency
matched matched
to 50 .to 50 .

Figure 14. Dual-stage proposed RFDC converter circuit.

Figure
Figure 14.14. Dual-stageproposed
Dual-stage proposed RFDC
RFDCconverter
convertercircuit.
circuit.
Experiment results prove that the circuit design runs at 868 MHz. The final modified RF-DC
Experiment results prove that the circuit design runs at 868 MHz. The final modified RF-DC
converter printed
Experiment
converter printedcircuit
results board
prove
circuit board(PCB),
that shown
the circuit
(PCB), in
showndesignin Figureruns
Figure 15,
atisis
15, 868 fabricated
MHz. The
fabricated using
using final
FR-4 FR-4 substrate.
modified
substrate. RF-DC
It It
contains
convertertwo
printed
contains layers,
two circuit one electrically
layers, board connects
(PCB), shown
one electrically connects the
in Figurepassive
the passive components
15, iscomponents
fabricated using and
and the the
FR-4 second
substrate.
second is a ground
It contains
is a ground
plane. A large
two layers,
plane. one deviation
electrically
A large between
deviation betweensimulation
connects the and
and experiment
passive components
simulation experiment results
andresults
the is is
second shown
is a ground
shown in Figure
in Figure plane. 15. This
A large
15. This
divergence
deviation is caused
divergence
between is causedby components
by components
simulation tolerances
tolerances
and experiment and
and the
results the parasitic
parasitic
is shown capacitance
incapacitance
Figure produced
15. produced
This bycircuit
by the
divergence the circuit
is caused
layout.
layout. PCB PCB
by componentslayers layers
andand
tolerances non-ideal
non-ideal
and the component
component behaviour generate
behaviour
parasitic capacitance generate
produced upper
bylosses,
upper losses,
the particularly,
circuit layout.for
particularly,PCB high
forlayers
high
frequency
frequency and
andcomponent
and non-ideal the low
the low input input power range.
powergenerate
behaviour range. The The
upper HSMS-2850
HSMS-2850 library model
library model
losses, particularly, is being
for highis beingsupplied
supplied
frequency for
and thefor
simulation
simulation to reflect
to reflect typical
typical baselineaspects.
aspects.Certain
Certain performance modulations miss the the
perfection
low input power range. Thebaseline
HSMS-2850 library model performance modulations
is being supplied miss
for simulation perfection
to reflect
compared to the real Schottky diode behavior. The model limitation and the sensitivity of Schottky
compared to theaspects.
typical baseline real Schottky
Certain diode behavior.modulations
performance The model limitation and the sensitivity
miss the perfection comparedoftoSchottky
the real
diode parameters to the ambient temperature produce a mismatch between the simulation and
diode parameters
Schottky diode to theThe
behavior. ambient
model temperature
limitation and produce
the a mismatch
sensitivity of between
Schottky diode theparameters
simulationtoand the
experimental results.
experimental results.
ambient temperature produce a mismatch between the simulation and experimental results.

Figure 15. Comparison between simulation and experimental PCE results of the proposed RFDC
converter.

Figure 15.
15. Comparison between
Comparison simulation
between and and
simulation experimental PCE results
experimental of the proposed
PCE results RFDC
of the proposed
RFDC converter.
converter.
Sensors 2017, 17, 546 12 of 14

Sensors 2017, 17, 546 12 of 14

At 10 dBm input power the measured PCE of the modified RF-DC converter is about 19.49%.
At 10 dBm
The proposed designinput power 19.43
provides the measured
W output PCEpower
of the modified
and around RF-DC
1 V converter is aboutThe
output voltage. 19.49%.
circuit
The proposed design provides 19.43 W output power and around 1 V output
achieves 26.21% of PCE at 6 dBm. It delivers 78.72 W and reaches 2 V output voltage. This means voltage. The circuit
theachieves
proposed 26.21% of PCE
modified at 6 dBm.
RF-DC It delivers
converter design 78.72
canW and reaches
power 2 V output
a diversity voltage. This means
of microcontrollers. Among
the proposed
them, modifiedwhich
the MSP430L092, RF-DCruns converter
with 0.9 design
V withcan6 power a diversity
W power of microcontrollers.
consumption in standby mode Among and
them, the MSP430L092, which runs with 0.9 V with 6 W
3 W in off mode. It consumes 45 A in active mode and works at 1.3 V [22]. power consumption in standby mode and
3 W in off mode.
In order It consumes
to evaluate 45 A in of
the efficiency active
the mode
proposedand works at 1.3 V
dual-stage [22]. we compare archived
design,
In order to evaluate the efficiency of the proposed
experimental results to the state of the art presented in [23]. LPD, presenteddual-stage design, we compare in [23],archived
is a low
experimental results to the state of the art presented in [23]. LPD, presented in [23], is a low power
power design harvester consisting of a seven-stage classic voltage multiplier circuit connected to
design harvester consisting of a seven-stage classic voltage multiplier circuit connected to a 100 k
a 100 k load. It operates at 915 MHz and employs Agilent HSMS-2852 Schottky diodes, which are
load. It operates at 915 MHz and employs Agilent HSMS-2852 Schottky diodes, which are used for
used for our proposed design. The setup results of the LDP, as published in [23], are presented in
our proposed design. The setup results of the LDP, as published in [23], are presented in Figure 16.
Figure 16. LPD-PCE is about 10% at 10 dBm input power and around 15% at 6 dBm. Consequently,
LPD-PCE is about 10% at 10 dBm input power and around 15% at 6 dBm. Consequently, this
this performance evaluation purpose shows a comparison of LPD-PCE and the proposed dual-stage
performance evaluation purpose shows a comparison of LPD-PCE and the proposed dual-stage
design.
design. TheTheproposed
proposeddual-stage
dual-stagedesign
design provides higher efficiency.
provides higher efficiency.TheTheperformance
performanceofof the
the proposed
proposed
dual-stage design stands out in the low power region where the LPD
dual-stage design stands out in the low power region where the LPD efficiency is low. The mainefficiency is low. The main
target of of
target this RFRF
this energy
energy harvesting
harvesting system
system is is
toto
yield
yieldenergy
energyofofa alow
lowRFRFdensity
densityarea.
area.TheTheincident
incidentRF
power in the energy harvesting case is very low. The input power range is
RF power in the energy harvesting case is very low. The input power range is limited and rarely limited and rarely exceeds
0 dBm for ambient RF energy harvesting. In [23] a comparison of LPD with
exceeds 0 dBm for ambient RF energy harvesting. In [23] a comparison of LPD with the commercial the commercial RF energy
harvester
RF energy from a Powercast
harvester from aP1100 is carried
Powercast P1100out. Figureout.
is carried 16 shows
Figure a16PCEshowsof P1100
a PCEacrossof P1100theacross
100 k
load
the[23].
100 The comparison
k load [23]. Thedemonstrates that the proposed
comparison demonstrates design
that the leads design
proposed to a higher
leadsPCEto athan thePCE
higher P1100
than the P1100
at low input power. at low input power.

Figure
Figure 16.16. Comparison
Comparison between
between PCE
PCE results
results of of
thethe proposed
proposed RF-DC
RF-DC converter,
converter, LPD
LPD prototype
prototype from
from [23],
[23],
and theand the commercial
commercial RF energy
RF energy harvester
harvester Powercast
Powercast P1100P1100
[23]. [23].

5. Conclusions
5. Conclusions
With energy harvesting and transfer, it is possible to recover micro-power, useful for powering
With energy harvesting and transfer, it is possible to recover micro-power, useful for powering
low-power wireless sensor nodes. In this work, a passive ultra-low RF-DC converter circuit design
low-power wireless sensor nodes. In this work, a passive ultra-low RF-DC converter circuit design
operating at 868 MHz is presented. It is capable of harvesting low ambient RF power levels using a
operating at 868 MHz is presented. It is capable of harvesting low ambient RF power levels using
novel multiplier circuit technique and high quality components to reduce parasitic effects and
a novel multiplier circuit technique and high quality components to reduce parasitic effects and
threshold voltages. New techniques are used for the modified voltage multiplier circuit. They consist
threshold voltages.
of including New techniques
an inductor arethe
in series with used for capacitance,
input the modifiedwhich
voltage multiplier
is able circuit.
to enhance Theyofconsist
the PCE the
of design.
including an inductor in series with the input capacitance, which is able to enhance the PCE of
the design.
The proposed RF-DC converter has a variable input power from 40 to 20 dBm according to the
received RF power and across a 50 k resistive DC load. Investigations show that the number of
Sensors 2017, 17, 546 13 of 14

The proposed RF-DC converter has a variable input power from 40 to 20 dBm according to the
received RF power and across a 50 k resistive DC load. Investigations show that the number of stages
leads to a high output power but, because of increased parasitic effects, the maximal efficiency remains
almost constant, and is shifted to the higher input power region. Experimental results present a large
divergence produced by PCB layer parasitic capacitance and the components tolerances. Results are
compared to state of the art solutions and show an outstanding potential of power conversion efficiency.

Acknowledgments: This work is part of the project Autonomous Intelligent Sensor Networks in Production (AIS)
(Ref. 100113366), Chemnitz University of Technology (TU-Chemnitz)-Germany, supported by the European Social
Fund (ESF) and Schsische AufbauBank (SAB).
Author Contributions: The author gratefully acknowledges the co-authors for their support and contribution to
this work. All the authors have given final approval of the version to be published. Issam Chaour contributed to
the main idea, Simulation and Experiment of this work; Ahmed Fakhfakh participated in the analytic model of the
proposed circuit and Olfa Kanoun participated in analysis and interpretation of the results and the paper structure.
Conflicts of Interest: The authors declare no conflict of interest.

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