JEDEC

STANDARD

Thermal Impedance Measurement for

Insulated Gate Bipolar Transistors
(Delta VCE(on) Method)

JESD24-12

JUNE 2004

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

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 JEDEC Standard No. 24-12
Page 1

THERMAL IMPEDANCE MEASUREMENTS FOR INSULATED GATE BIPOLAR

TRANSISTORS - (DELTA VCE(on) METHOD)

(From JEDEC board Ballot JCB-04-38, formulated under the cognizance of the JC-25 Committee on
Transistors.)

1 Scope

The purpose of this test method is to measure the thermal impedance of the IGBT (Insulated Gate
Bipolar Transistor) under the specified conditions of applied voltage, current and pulse duration.
The temperature sensitivity of the collector-emitter on voltage, VCE(on), is used as the junction
temperature indicator. This is an alternative method to JEDEC Standard No. 24-6.

2 Terms and definitions

The following symbols and terms shall apply for the purpose of this test method:

IM Emitter current applied during measurement of the collector-emitter ON voltage.

IH Heating current through the collector or the emitter lead.

VH Heating voltage between the collector and emitter.

PH Magnitude of the heating power pulse applied to the DUT in watts(W); the product
of IH and VH.

tH Heating time during which PH is applied.

VCE(on) Voltage-temperature coefficient of VCE(on) with respect to TJ; in mV/C.

K Thermal calibration factor equal to the reciprocal of VCE(on); in C/mV.

TJ Junction temperature in degrees Celsius (C).

TJI Junction temperature in degrees Celsius (C) before the start of the power pulse.

TJF Junction temperature in degrees Celsius (C) after the end of the power pulse.
JEDEC Standard No. 24-12
Page 2

2 Terms and definitions (contd)

TX Reference temperature in degrees Celsius (C).

TXI Reference temperature in degrees Celsius (C) before the start of the power pulse.

TXF Reference temperature in degrees Celsius (C) after the end of the power pulse.

VCE(on) Collector-emitter voltage in millivolts (mV).

VCE(on)i Collector-emitter voltage in millivolts (mV) before the start of the power pulse.

VCE(on)f Collector-emitter voltage in millivolts (mV) after the end of the power pulse.

VCE(M) Collector-emitter voltage during measurement periods.

VCE Collector-emitter voltage during heating period.

VGE Gate-emitter voltage used to drive the device during the heating period.

tMD Measurement delay time; is defined as the time from the removal of the heating
pulse, PH, to the start of the VCE(on) measurement.

tSW Sample window time during which the final VCE(on) measurement is made.

ZJX Transient junction to reference point thermal impedance in degrees

Celsius/watt(C/W). ZJX for a specified power pulse duration is:

(TJF TJI ) TX
ZJX =
PH

where: TX = the change in reference point temperature during the heating pulse
(for short heating pulses, such as at die attach evaluations, this term becomes
negligible)

RJX the value referred to as steady state thermal resistance. This is the condition where
the time of the heating pulses is sufficiently long that there is no change in the value
of ZJX, or where [(TJF TJI) TX] does not change.
 JEDEC Standard No. 24-12
Page 3

3 Apparatus

The apparatus for this test shall include the following:

3.1 A means for temperature measurements

The preferred method for measuring the case temperature is a thermocouple to measure a
consistent reference location. The preferred reference location is on the case under the heat
source, the IGBT die. The thermocouple wire should be AWG size 30; copper-constantan (type
T) is preferred to optimize temperature reading response. The junction thermocouple shall be
welded, not soldered or twisted, to form a bead. Proper mounting of the thermocouple to ensure
intimate contact to the reference is critical for system accuracy, which shall be 0.5 C.
Alternative methods to measure the referenced case temperature can be used, such as IR thermal
imaging, but these methods are usually less desirable economically. The method for temperature
measurement is not relevant to this test method as long as the accuracy of the temperature
measurement system is 0.5 C.

3.2 A setup for VCE(on) or K-factor calibration

A VCE(on) or K-factor calibration shall be determined using a controlled environment. A

recirculating bath or an oven that is capable of holding the case temperature during the device
calibration to within 1 C over a 25 C to 125 C range, the possible temperature range for
measuring the K-factor, can be used. A circuit, such as Figure 1, shall be used to make the
measurement to determine this K-factor. The current source used to generate IM shall have an
accuracy to 2% . The meter used to measure VCE(on) shall be capable of 1 mV resolution. The
VGE supply shall have an accuracy to 2%. The wires used to supply the device to current source
connections shall be sufficient to handle the measurement current (AWG 22 is sufficient to carry
up to 100 mA). A typical VCE(on) vs. Temperature curve will be similar to Figure 2.

IM VCE DUT
G
E
VGE

Figure 1 Simplified schematic for Rthjc measurement

JEDEC Standard No. 24-12
Page 4

3 Apparatus (contd)

3.3 A setup for thermal testing

Testing can be implemented using a circuit that allows the control of the test current, IH, and the
measurement current, IM, through the use of a high speed switching circuit. This circuit should
effectively measure the VCE(on) at IM during the pre-power application phase of the test. The
measurement will be held for later comparison to the post power measurement. Then the circuit
will switch to the high current mode and will set up the switches that control IH and VH during
the heating phase of the thermal testing. After the heating pulse is complete the circuit should
effectively measure the VCE(on) at IM as done during the pre-power application.

4 Measurement of the temperature sensitive parameter

4.1 VCE(on) versus temperature calibration

The required calibration of VCE(on) vs. TJ, or VCE(on), is accomplished by monitoring VCE(on)
and IM as the heat sink temperature (and thus the DUT temperature) is varied by external heating.
VGE shall be set at a condition that results in the DUT being full on. IM must be chosen so that
there is no significant self-heating but provides sufficient temperature sensitivity. This will be
dependent upon the DUT power dissipation, or the DUT die size (IM could be 1 mA or less for
smaller devices and upward of 100 mA for larger devices). It is prudent engineering practice to
generate this curve with more then 3 points. A typical calibration curve usually has a linear
relation over a 25 C to 125 C range, such as Figure 2.

500
VCE(mV)

200
@ IM

25 TJ(C) 125

Figure 2 Example of a calibration curve

 JEDEC Standard No. 24-12
Page 5

4 Measurement of the temperature sensitive parameter (contd)

4.1 VCE(on) versus temperature calibration (contd)

A suitable sample-and-hold voltmeter or oscilloscope shall be used to measure the collector-

emitter voltage at selected temperatures. VCE(on) shall be measured within 1 mV, or within
2% of VCE(on), which ever is less.

4.2 K-factor

A calibration factor, K (which is the reciprocal of the slope of the curve on Figure 2) can be
defined as:
T J 2 - T J1
K= C/mV
V CE 2 - V CE 1

It has been observed experimentally that the VCE(on) or K-factor variation for devices within a
given device type class is small. This should be verified. Usually a 10 to 12 piece sample from a
device lot can be measured. The average, KAV, and standard deviation (K), of the K-factor is
determined. If K is less than or equal to 3% of KAV, then KAV can be used. If K is greater than
3% of KAV, then all the devices in the lot need to be measured for their respective K-factor and
the individual values for the VCE(on) shall be used for the calculations of thermal resistance or
thermal response. As an alternative to using individual values of K, the manufacture may
establish internal limits unique to their product that ensures atypical product removal from the
population (lot-to-lot and within-the-lot). The manufacturer shall use statistical techniques to
establish the limits.

5 Test procedure

5.1 Calibration

K-factor determination shall be done per 4, being mindful of the constraints in 4.2.

5.2 Reference temperature point

The reference temperature point location must be specified and the temperature shall be
monitored using the requirements of 3.1. The reference point is usually chosen to be on the
bottom of the transistor case directly below the IGBT die. Alternatively, this reference point
should be as close to the thermal path generated by the die into the case (or the heat sink location
that is accessible) as practicable, so it reflects the effects of mounting the DUT in a real
application.
JEDEC Standard No. 24-12
Page 6

5 Test procedure (contd)

5.2 Reference temperature point (contd)

If it is determined that the temperature TX increases more than 5 % of the measured junction
temperature rise during the power pulse, then one of following options must be taken. The
heating pulse magnitude must be decreased. Or the DUT must be mounted to a temperature
controlled heat sink and temperatures must be measured properly to assure the TX requirement.
Or the calculated value of thermal impedance must be corrected to take into account the thermal
impedance of the reference point to the cooling medium (i.e., the heat sink).

Temperature measurements for monitoring, controlling and/or correcting for reference point
temperature changes are not required if the tH is short enough to ensure that the heat generated by
the DUT has not had time to propagate through the package. In this case typical values for tH are
10 ms to 100 ms dependent upon the package design and materials.

5.3 Steady state thermal resistance, RJX

Prior to the power pulse:

a) Establish the reference point temperature TXI.

b) Apply the gate voltage, VGE, needed to assure full conduction.
c) Measure the initial VCE(on)i at the specified IM.

Apply the power pulse

a) Verify VH, observe that there are no anomalies with the pulse.
b) Verify IH, observe that there are no anomalies with the pulse.
c) Verify that tH is great enough that the device is in a steady state condition.
d) Measure the TXF at the end of the power pulse.

Post Power Pulse

a) Apply the gate voltage, VGE, needed to assure full conduction.

b) Measure the VCE(on)f at the specified IM.
c) Establish the delay time, tMD. This can be used to extrapolate the actual TJF of the post
power pulse.
 JEDEC Standard No. 24-12
Page 7

5 Test procedure (contd)

5.4 Thermal response, ZJX

Prior to the power pulse:

a) Establish the reference point temperature TXI.

b) Apply the gate voltage, VGE, needed to assure full conduction.
c) Measure the initial VCE(on)i at the specified IM.

Apply the power pulse

a) Verify VH, observe that there are no anomalies with the pulse.
b) Verify IH, observe that there are no anomalies with the pulse.
c) Verify that tH is short enough that the device is not exceeding the conditions of paragraph 5.2
for a non-heat-sunk device. This can be done by measuring the TXF at the end of the power
pulse.

Post Power Pulse

a) Apply the gate voltage, VGE, needed to assure full conduction.

b) Measure the VCE(on)f at the specified IM.
c) Establish the delay time, tMD. This can be used to extrapolate the actual TJF of the post
power pulse.

5.5 Calculate thermal resistance, RJX , or thermal impedance, ZJX

a) The value of thermal resistance is calculated per the formula below:

RJX = {TJ / PH }{TX / PH}
= [({ VCE(on)f - VCE(on)I }/ VCE(on))/ PH ] {TX / PH} C/W
b) The value of thermal response is calculated per the formula below:
ZJX = {TJ / PH }
= ({ VCE(on)f - VCE(on)I }/ VCE(on))/ PH C/W
because the term {TX / PH} approaches 0 if the conditions for thermal response are met.

NOTE There are several semi-automated systems available today, because of the advances made in
computer controlled testing systems, that can do much of the data taking and calculations for the
procedures outlined in this section.
JEDEC Standard No. 24-12
Page 8

6 Test conditions and measurements

Typical waveforms are below

where VCE1 = VCE(on)i

VCE2 = VCE(on)f
DT = Delay time = tMD
PT = PH [tSW = the sampling window, (10 s) this value is not always fixed]

NOTE 1 Some test equipment may provide a VCE directly instead of VCE(on)i and VCE(on)f; this is
an acceptable alternative. Record the value of VCE.

NOTE 2 Some test equipment may provide ZJX directly instead of VCE(on)i and VCE(on)f for thermal
resistance calculations; this is an acceptable alternative. Record the value of ZJX.

NOTE 3 Alternative waveforms, as may be generated by ATE using the general principles of this
method, may be used.
 JEDEC Standard No. 24-12
Page 9

7 Test conditions and measurements to be specified and recorded

7.1 K factor calibration

7.1.1 Test conditions, Specify the following test conditions:

a) IM measuring current mA
b) Initial junction temperature C
c) Initial VCE voltage mV
d) Final junction temperature C
e) Final VCE voltage mV

7.1.2 K factor, Calculate K factor in accordance with the following equation:

K= TJ2 - TJ1 C/mV

VCE2- VCE1

K factor C/mV

7.2 Thermal transient and equilibrium measurements

7.2.1 Test conditions, Specify the following test conditions:

a) IM measuring current mA
b) IH heating current A
c) VH heating voltage V
d) tH heating time ms
e) tMD measurement time delay s
f) tSW sample window time s

7.2.2 Data, Record the following data:

a) VCE(on)i initial forward voltage V

b) VCE(on)f final forward voltage V

NOTE 1 Some test equipment may provide a VCE instead of VCE(on)i and VCE(on)f; this is an
acceptable alternative. Record the value of VCE.

NOTE 2 Some test equipment may provide direct display of calculated ZJX; this is an acceptable
alternative. Record the value of ZJX.)
JEDEC Standard No. 24-12
Page 10
Standard Improvement Form JEDEC JESD24-12

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