POWER PC

PowerPC (Performance Optimization with Enhanced RISC Performance

Computing) is a microprocessor architecture that employs reduced
instruction-set computing (RISC).It was developed jointly by
Apple, IBM, and Motorola. The three developing companies have made
the PowerPC architecture an open standard, inviting other
companies to build on it.

Developed at IBM, reduced instruction-set computing (RISC) is

based on studies showing that the simplest computer instructions
are the ones most frequently performed. Traditionally, processors
have been designed to accommodate the more complex instructions as
well. RISC performs the more complex instructions using
combinations of simple instructions. The timing for the processor
can then be based on simpler and faster operations, enabling the
microprocessor to perform more instructions for a given clock
speed.

What is a microprocessor?
A microprocessor is a computer processor which incorporates the
functions of a computer's central processing unit (CPU) on a single
integrated circuit (IC),[1] or at most a few integrated circuits.

A microprocessor, sometimes called a logic chip, is a computer

processor on a microchip.

The microprocessor contains all, or most of, the central processing

unit (CPU) functions and is the "engine" that goes into motion
when you turn your computer on. A microprocessor is designed to
perform arithmetic and logic operations that make use of small
number-holding areas called registers. Typical microprocessor
operations include adding, subtracting, comparing two numbers, and
fetching numbers from one area to another. These operations are
the result of a set of instructions that are part of the
microprocessor design. For example

When your computer is turned on, the microprocessor gets the first
instruction from the basic input/output system (BIOS) that comes
with the computer as part of its memory. After that, either the
BIOS, or the operating system that BIOS loads into computer memory,
or an application program is "driving" the microprocessor, giving
it instructions to perform.
POWER PC ARCHITECTURE

The PowerPC architecture provides an alternative to the popular

processor architectures from Intel, including the Pentium.
(Microsoft builds its Windows operating system offerings to run on
Intel processors, and this widely-sold combination is sometimes
called "Wintel".) The PowerPC was first used in IBM's RS/6000
workstation with its UNIX-based operating system, AIX, and in Apple
Computer's Macintosh personal computers. Today, PowerPC chips are
also used in diverse applications including internetworking
equipment, routers, telecom switches, interactive multimedia,
automotive control, and industrial robotics.

The POWER architecture incorporated lots of the RISC

characteristics:

fixed-length instructions,
register-to-register architecture,
simple addressing modes,
large general register file
Three-operand instruction format.

Additionally, it has other features more characteristic of more

complex ISAs (Industry Standard Architecture).

Designed to be superscalar- dispatched across three

independent units: branch, fixed-point arithmetic, and
floating point units. This allows out of order execution.
Compound instructions--updating the base register on a load
and store with the newly calculated effective address, thus
eliminating the need for extra add instructions required to
increment the index for array traversals.
Does not implement delayed branches- Instead the POWER
architecture uses a branch target buffer, and the now well
known branch folding technique.
Branching technique- The POWER architecture has eight
condition registers that are set by compare instructions.
One additional bit in the opcode of each instruction signaled
that instructions should be executed only under certain
conditions, a form of predicated execution.
PowerPC family.

There are different Power PC family as follows;

o PowerPC 601:
Medium sized and medium performance processor
Includes a more sophisticated branch unit
Capable to dispatch three out-of-order instructions per
cycle.
Up to 8 instructions per cycle can be fetched directly
into an eight-entry
instruction queue (IQ), where they're decoded before
being
dispatched to the execution core.

o PowerPC 603:
Smaller die size than the 601.
Smaller cache capable to dispatch three out-of-order
instructions per cycle.
PowerPC Registers.

PowerPC's application-level registers are broken into three

categories: namely

General purpose, Floating point and Special purpose

registers.

General-purpose registers (GPRs).

Flat-scheme of 32 general purpose registers.

Source and destination for all integer operations.
Address source for all load/store operations.
They also provide access to SPRs.

Floating-point registers (FPRs).

It can contain 32-bit and 64-bit signed and unsigned integer

values, as well as single-precision and double-precision floating-
point values.

Special-purpose registers (SPRs).

 The Fixed-Point Exception Register (XER) - used for
indicating conditions for integer operations, such as carries
and overflows.
The Floating-Point Status and Control Register (FPSCR) - 32-
bit register used to store the status and control of the
floating-point operations.
The Count Register (CTR) - used to hold a loop count that can
be decremented during the execution of branch instructions.
The Condition Register (CR)-32-bit register grouped into
eight fields, where each field is 4 bits that signify the
result of an instructions operation: Equal (EQ), Greater Than
(GT), Less Than (LT), and Summary Overflow (SO).
The Link Register (LR) contains the address to return to at
the end of a function call.

Overall design of power

pc.

Integer Execution Unit

Floating Point Unit
Load/Store Unit (LSU)
Branch Execution Units.
Memory Management Unit
Cache
Memory Unit.


International Business
Machines (IBM).

Introduction.

The IBM System/360 (S/360) was a mainframe computer system family

announced by IBM on April 7, 1964, and delivered between 1965 and
1978.[1] It was the first family of computers designed to cover the
complete range of applications, from small to large, both
commercial and scientific. The design made a clear distinction
between architecture and implementation, allowing IBM to release
a suite of compatible designs at different prices. All but the
incompatible model 44 and the most expensive systems used microcode
to implement the instruction set, which featured 8-bit byte
addressing and binary, decimal and (hexadecimal) floating-point
calculations.

System/360 was extremely successful in the market, allowing

customers to purchase a smaller system with the knowledge they
would always be able to migrate upward if their needs grew, without
reprogramming of application software or replacing peripheral
devices.

IBM products include hardware and software for a line of business

servers, storage products, custom-designed microchips, and
application software. Increasingly, IBM derives revenue from a
range of consulting and outsourcing services.

IBM has built another bridge between its old and new computing
systems with the announcement today of a versatile new System/360
for users of small and medium sized computers.

The System/360 Model 25 joins Models 20 and 30 to offer IBM 1400-

series users a wider choice in converting to System/360.

The Model 25 can operate as an IBM 1401, 1440, or 1460. It also

can process a full range of System/360 Model 30 jobs, both
scientific and commercial - - and users can convert to larger
System/360s without reprogramming.
 References.

1. IBM System/360 Principles of Operation (PDF). First Edition.

IBM. 1964. A22-6821-0.
2. IBM System/360 Component Descriptions - 2841 and Associated
DASD (PDF). Eighth Edition. IBM. December 1969. GA26-5988-7.
3. G. M. Amdahl, G. A. Blaauw, & F. P. Brooks,Architecture of
the IBM System/360
4. IBM Journal of Research and Development, April 1964.
5. IBM 2301 Drum Storage, Columbia University Computing History