Hard Disk Controller: the Disk Drives Brain and Body

James Jeppesen; Walt Allen; Steve Anderson; Michael Pilsl

Infineon Technologies; Memory Products, Network and Computer Storage

600 South Airport Road; Suite #205; Longmont, Colorado USA

(James.Jeppesen; Walt.Allen; Steve.Anderson; Michael.Pilsl) @infineon.corn

experienced rapid Unit (CPU), Buffer
integration as driven Memory, and CPU
by cost reductions. memory. See Figure
Abstract Moving from a six- 1 for a block diagram
chip design, the of a disk drive.
Integration of the Hard Disk current HDC
Controller (HOC) today has taken on solution is one chip.
an extensive amount of functionality. Future products will
2.1. Host
From the host interface, error integrate the Interface
correction code, disk sequencer, readwrite channel
microprocessor(s), servo control
into the HDC further The host interfaces
logic, buffer controller, to the
reducing the total primary function is to
embedded memory, the HDC has
become a true system on a chip. number of parts the provide a standard
Depending on the product, hard disk drive protocol for the Disk
embedded DRAM is used as (HDD) will require to Drive to talk to a host
bufferingfor data between the host perform its function. system. The host
and media and possibly for storing The paper system can be
controller firmware. By bringing all presented here will anything from a server
these blocks into one chip, pin or PC to a simple
look at the current
counts can be reduced and higher peripheral or
dataflow speeds can be obtained by scale of integration consumer product--
decreasing the interconnect delays. and the testability such as a printer or
However, the challenge for designers issues created by digital camera. There
is in test and verification of the this integration. exists a number of
design during development and distinct protocols in
production. the disk drive industry
2. HDC for performing this
Functional link. Some of the
1. Introduction
Block major interfaces are
Description ATA, SCSI, and Serial
Computer mass storage devices interfaces. The main
once took up an area about the size driver between
of a 2-drawer legal file cabinet back The Hard Disk selecting which
in the 1980s. A current drive produced Controller today is interface to use is cost
for digital cameras is smaller than a made up of the to performance. The
credit card, about the depth of a 3 % following common design trend for the
inch floppy, and holds at least 10 blocks: Host host interface is to
times the data-all at a reduced cost. Interface, Buffer have multiple
In 1995, a -400 MB drive cost nearly Controller, Disk interface blocks. Each
$500. Now, a 20 GB drive can be Sequencer, Error block supports a
bought for only $150. What has Correction Code particular host
enabled the manufacturers to achieve (ECC), protocol and has a
such changes? One area is system standard back end
integration. interface to the rest of
the HDC. This allows
Servo Control,
The hard disk controller (HDC) has Central Processing for maximum synergy
among designs.
Depending on the interface chosen raw signal control to
and the performance desired, the the bank of buffer
size of the host interface can vary memory. This
dramatically from a few thousand gates memory can be Static
to over a hundred thousand gates. Random Access
Memory (SUM),
Currently, the host interface is the Dynamic Random
only block that is covered by any kind Access Memory
of published industry standard--albeit (DRAM), or
many different public standards. Embedded memory.
These standards define physical Typically the host
transfers, required registers, and interface, disk
command sets. sequencer, ECC, and
CPU all need access
to this buffer memory.
2.2. Buffer Controller The buffer controller,
under some priority
The main function of the buffer scheme, will prevent
controller is to provide arbitration and these blocks from
0-7695-1200-
3/01$10.00 Q 2001 IEEE
colliding while
accessing the
memory buffer. This
block may also
contain logic to help
with the automation of
moving data to and
from the host. The
size of this block can
vary depending on the
number of memory
configurations
supported by a single
controller. The system
throughput and
performance can be
greatly affected by
this block.
262
Head Disk Assembly PCB
a normal name equipment
for the 8-bit data called, Servo
interface Writers.) The
between the user data
read/write sometimes must
channel and the be split on either
HDC. For a disk side of these
write operation, servo wedges.
the disk The disk
sequencer takes sequencer
user data, handles the split
appends data fields for
additional fields both read and
such as ECC write operations.
bytes, and Furthermore,
writes out the since the
newly formatted spinning disk
data to the cannot be
media interface throttled,
through the
NRZ pins. (NRZ
is defined as
I I
non-return to
zero.)
Servo Control 8 Conversely for a
disk read
Motor Control operation, the
disk sequencer
reads formatted
Demodulator data from the
NRZ pins and
converts it back
into user data
that is then sent
to the host
Figure 1. Hard interface. The
disk drive process is
complicated by
subsystem
the fact that disk
media has servo
2.3. Disk wedges written
Sequencer on it that cannot ATA,
be over written
by user data.
The main task of (Servo wedges, etc.
the disk typically 50-80
sequencer is to per revolution,
oversee and Variable Store
contain gain
manage the control
transfer of data information for
between the disk the readwrite
interface channel;
(referred to in cylinder/track
this paper as the location
NRZ pins) and information; and
the data buffer. head alignment
The term, NRZ, patterns. The
is defined as servo wedges
non-return to the data rate
are written at from and to the
zero. The NRZ the factory by
bus has become special disk must
remain constant. the ECC is one contains some
The sequencer is of the largest type of Cyclic
in charge of blocks of an Redundancy
pulling data from HDC controller. Check (CRC)
registers, data This block is function to keep
buffers, and the responsible for the probability of
ECC block at appending ECC miscorrection to
precise times in symbols to the an acceptably
a disk write user data and low level.
operation, and in also to check Current disk
charge of and, if needed, drives are
sending the NRZ correct the user specifying a
data to the data before it is nonrecoverable
correct blocks returned to the read error of 1 in
during a disk host. The ECC lOI4 bits read
read operation. size is greatly [2].
The disk affected by the
sequencer is chosen
2.5. Servo
often referred to correction
as the disk capable of the Control
formatter. hardware and
the amount of The servo
software control block
2.4. ECC intervention has a lot of
(Error required to different
Correction perform the definitions
correction.
Code) Along with ECC
depending on
the particular
syndromes, this implementation.
In terms of a block often In this paper,
single function,
263
multiple ways. Single
%bit, 16-bit, or 32-bit
the servo block refers
microprocessors and
to general logic used
Digital Signal Processors
in aiding the spinning (DSP) have been used,
of the discs and in the as well as combinations
positioning of the of these cores. These
actuator on the disc. It cores are used to control
does not refer to the the overall system or
power devices may have a very specific
necessary to drive the task. The CPU has the
spindle motors. This highest gate count of all
block is uniquely the logic blocks except
customized to the memory. It is also the
particular customers most complex from a
strategy for motion simulation and
control d the Head integration standpoint.
Disk Assembly (HDA).
Therefore, it is difficult 2.7. Buffer Memory
to standardize and
thus lends itself to an
The buffer memory is
Application Specific
used as a temporary
Standard Product
storage of the users
(ASSP) strategy.
data either on its way
to the disc or returning
2.6. CPU (Central to the host. This
Processing memory may also
Unit(s)) serve as variable
storage or even code
execution space for the
The CPU of the HDC CPU. This memory
can be implemented in
traditionally has been
made up of both
SRAM and DRAM.
The buffer memory
can be either external
or embedded within
the HDC. By
embedding the
memory, a higher
throughput to the buffer is
possible. However,
embedding the memory
increases the
integration and testing
difficulties.
2.8. CPU Memory
The CPU memory can
be made up of Read
Only Memory (ROM),
SRAMs, Flash, or
DRAMS. Also, any
combination of these
memory types can be
utilized in the product
design. This memory
is where the op-codes
for the CPU are stored
for execution.
Currently, some sort of
non-volatile memory is
required. However, the
use of volatile memory
to supplement the
non-volatile memory is
becoming standard.
The benefit of this
volatile memory is that
it can be changed
often, execution
performance
increased, and
manufacturing costs
reduced. If volatile
memory is available, it
quite often doubles as
code variable storage
for the CPU.
3. The Challenge
of Integration
Integration of more
and more HDC
functional blocks into
a single chip is not
without issues. While
integration can lead to
cost savings, if not
managed
appropriately, it can
lead to cost increases,
or even failure of the
project.
As each module was
integrated over the
years, the externally
observable connections
were no longer available
for test. This forced the
designer to find
alternative methods for
testability without adding
significant cost to the
final product. The
testability issues have
different objectives:
development tests for
the designer to prove
function; wafer tests
which ensure the die
was successfully
manufactured; final
assembly tests to verify
the customer receives a
functional part; and fnally
a means for the
customer to develop and
debug application
firmware/software on the
embedded
microprocessor. We will
now look at the process
for developing the
product in greater detail
and each of the
testability objectives.
3.1. Development
Phase
The development
phase sets the
objectives for the
project. Major concerns
include team make-up,
features required for
the product, and test
methodology from both
a producer and
customer viewpoint.
Team make-up has
implications on the
overall design
methodology. If multi-
sites are involved in the
design of the project,
functions must be
carefully chosen to
streamline the
utilization of the
resources within each
site. Often, more than
one geographical site
is utilized, which may
or may not extend
across international
borders, in the
development of
products. To control the
design process, version
control packages track
the updates to the
design as each
designer releases
their module for
general use. Without
version control, an
accidental bug placed
into the design can
take many man-hours
to locate and correct,
impacting all
engineers on the
team.
The definition of the
product takes on a new
dimension in an
integrated part. Defining
the features includes
package selection and
testing, which are all
required before design
can begin. How is this
different from the non-
integrated process?
Package selection
impacts the number of
pins available for
functional and testing
use. Heat dissipation
concerns limit features
based on cost of
packages needed to
handle the thermal load.
The non-integrated
design could use a chip
clip and a logic analyzer
as a testing plan. Of
course, the integrated
part has most module
interconnects hidden
from the outside world.
(We will look at testing
issues later in this
section.)
Once the definition and
design has been
completed, the
conversion to hardware
begins. Most of us have
seen HDL to netlist
flows. Highlighting some
important aspects of the
flow shown in Figure 2,
static timing analysis
(STA) and formal
verification have become
a very important step in
the

264
the netlist and HDL occur.
Once the netlist is laid out
and true timings are
development of the available. another flow is
highly integrated followed to verify the
HDC. STA is a fast results.
method of inspecting
the inter-module and
intra-module timings,
clock skew, and test b HDL 4
mode timings created
during synthesis.
From STA, more 4
exact timing
constraints can be
Functional Tests
produced to improve
the synthesis of the
netlist during
subsequent synthesis
operations. Formal
verification ensures
the HDL code
matches the netlist
created. Formal
verification is very
useful as patches to
 requirements. Since STA
and formal verification
are performed, the
running of functional
tests is not really
necessary to prove the
layout in design terms.

T
However, one should
perform these tests as
an extra measure of
confidence.
I1
Back-annotated

Netlist

Debug HDL to HDL design

hardware issues. 4
Adjust Layout
Static Timing
Debug netlist

Analysis
issues
Functional Tests

Verification between HDL and

L
correct

U Layoutnetlist

Functional Tests

Figure 2. HDL to
netlist flow.

In the layout flow

shown in Figure 3,
STA and formal .
Tests 1 Yes
verification are the Formal
main tools used to Verification between pre and

ensure the layout

meets the design
function and timing
correct

Back-annotated

Netlist Complete

I I

Figure 3. Layout to
release flow

3.2. Test point

of view

As referred to earlier
in this paper,
testability issues are
a main part of the
development phase.
Three points of view
need to be
considered when
planning testability.
First, the design
engineers must
formulate tests to
verify the
functionality of the
chip. Next, test
engineers need
wafer and
production tests to
verify that the silicon
was manufactured
correctly. Finally, the
customers
viewpoint needs to
be considered--both
for demonstrating a
quality
265
 dies have been
working part in the successfully produced
disk drive system and before packaging.
for creation and debug Wafer tests may
of application include scan vectors,
firmware. Each functional vectors,
viewpoint must be IDDQ current test, and
addressed to deliver a built in self-tests
product that meets or (BIST). Scan vectors
exceeds the are generated through
customers automatic test pattern
expectations in terms generation (ATPG)
of quality and ease of software tools. If the
application. designer has created
the design with
scanability in mind,
The designer of each over 90% of the logic
module within the can be tested through
HDC creates tests the ATPG patterns.
that verify the
functional aspect of
their design. These Once packaged, the
functional tests are viewpoint changes to
typically created for delivering a quality
use in a simulation product to the
environment. customer. As stated
However, many of earlier, the designer
these functional tests must have thought
have been converted through test
to run on a production methodologies to catch
tester. Thus, the parts that are marginal
designer must keep in or damaged through
mind only pins the packaging process.
exposed on the The designer must also
package should be consider the
used in the functional application in which the
tests created. Special product is intended to
test modes can be function. The designer
added to the design needs to add features
that change the to assist
configuration of the firmware/software
pins to expose engineers in
normally buried developing the HDC
signals. Care should into the final disk drive.
be taken to minimize Lets consider these
the creation of these closer.
modes. Each special
start up required to Even though a die has
enter test modes passed the test vectors
takes up time on the while part of a wafer, a
production tester. die may have marginal
Production test time is characteristics that will
a major factor in final cause it to fail under
part cost. stress. A standard
method for creating the
The next viewpoint stress is the burn in
addressed is the process. Special tests
production tester. are created to exercise
Once the design has the part during the burn
been transferred to a in process. The object
wafer, patterns are run of these tests is b
to determine which exercise as much logic
as possible while the about it? One familiar
part is exposed to the approach is to apply
stress. Once the burn Built-In-Self-Test (BIST)
in process is to memory devices. On
complete, tests are the old non-integrated
run to remove parts system, if one wrote an
that suffered from AAh to a memory
device, then read back
infant-mortality
an A8h, the faulty bit of
(failures caused by
the memory device or
the stress). CPU chip is clearly
evident. When it is
From the viewpoint of the shown that the Ash is
customer utilizing the evident at the pin of the
packaged part, one of memory device, replace
the first problematic the device. When the
items to become BIST fails, the memory
integrated was the or the BIST logic has a
microprocessor. As long
problem. If the BIST
as the external memory
bus is brought out to an
passes, and the CPU
external ROM device of
still fetches bad data,
some sort, the
interface logic should be
troubleshooting issues examined. One
are minimized drawback is that pattern
sensitivities may exist
with patterns that are not
because the primary tested in the BIST. This
interface and results in a BIST pass
partitioning of logic is condition, while system
viewable, probe-able, execution fails.
and therefore
analyzable. Now real Another employed
problems start when technique is the
any sort of memory, implementation of a test
such as embedded- multiplexor. This logic
code SRAM, is pulled dedicates a small
into the device, and number of pins to the
for pin savings, or presentation of a
timing margin, the predetermined subset of
designer chooses to important internal
eliminate this visibility. signals. This is
This visibility issue extensively used in
pertains to every testers to increase test
major integration coverage, while
decreasing test time.
carried out in the
However, if
modern system on a
systemdfirmware
chip. With integration, engineers are
the complexity incorporated in the
increases, the visibility process of choosing
decreases, and these signals, critical
system debug truly system debug visibility
becomes the can be achieved as well.
nightmare of the Drawbacks include not
firmware/systems/test having the necessary
engineers. signals to view the
particular bug of the day,
as well as having signals
that need to be
Now that we have examined together that
identified a root have different select
drawback to highly- settings for the
integrated chips, from multiplexor. Keep in
the troubleshooting mind, there can be
aspect, what can we do hundreds of internal
signals of interest, yet
only a handful of pins
for these signals to be
multiplexed out upon.
Therefore, it is
imperative to plan this
test strategy carefully.

One of the simplest

items to implement is
increased register
visibility from the CPU,
by the firmware.
Unfortunately, many
chips today are created
with write-only
registers. This hinders
firmware creation and
debug, while only
saving minimal logic
area. Another method
to increase visibility is
to insure that FIFOs are
readable from first cell
to last cell. As FIFOs
are often used as an
important part of the
partitioning interface
between logic blocks,
this functionality can be
used to isolate faulty
logic to the source
block. Visibility of state
machine states can be
a reward, as well. While
understanding a CPU
might not have the
resolution to capture
every phase, it can
show when state
machines receive
unexpected states and
end up in unexpected
places. Drawbacks
mainly include the
increased code space
and
266
 CO-verification, the
utilization of firmware
execution time, which
and hardware in a
alter the behavior of
system environment, is
many real-time growing in popularity.
systems . For The impetus comes
debugging time-critical primarily in making
fimctional areas, this parallel, the current
technique generally serial cycle of
should not be applied. developing hardware
and then developing
If a design is core firmware, in an effort to
limited, extra signals further reduce
can be brought out to development times.
While this has been
supplementary I/O
shown to reduce
pads. A secondary test development times in
package can be complex/expensive
chosen to present efforts, it should be
these signals to the viewed as another
outside world. Once mechanism for creating
debug is complete, the visibility of all nodes in
original production an integrated
package can be environment--nodes that
shipped with the just could not be seen
original die. If time and any other way.
cost constraints are
met, this can be an Even with these
extremely low risk techniques at hand,
methodology of management should
increasing visibility. schedule sufficient time
Along these lines, for increased testing and
even special ball grid debugging. No longer
array (BGA) can the engineer or
substrates have been technician just place a
produced to bring out test clip on the offending
microprocessor trace device and see the
functionality, creating
the visibility to track bug. Many of these
CPU flow and op-code techniques, can only
execution results. be applied in
conjunction with writing
On-Chip Debug specific code
Systems (OCDS) are segments. This
becoming available to process alone
manage the embedded increases time.
processor isibility Techniques such as co-
problems. Some verification increase
features existing today testing time and must
include on-the-fly be managed.
access to any memory
location or internal
register, real-time
hardware breakpoints, Increasing utilization of
virtually unlimited these techniques
software breakpoints, increases visibility; yet
and more. If your recoup costs, by
system includes this savings in pins,
capability, requirements packages, and
for external memory potential silicon spins.
bus visibility becomes a
low priority, in most
cases. 4. Conclusion
Integration has The authors wish to
brought the price of express our thanks to
the hard disk drive Chuck Gravelle for his
down for the editing efforts and
consumer. This paper Donna Ape1 for her
has shown how help in generating
designers have dealt figures used in this
with the integration in paper.
terms of testability and
design flow.
6. Literature
As integration continues
113 M. Pilsl and B.
to bring more
Rohfleisch (1999),
functionality into the
Embedded DRAMS for
HDC, designers will Hard Disk Drive (HDD)
need to manage the Controllers, DA C
testability issue. New Tutorial Presentation
methods for tackling the
three viewpoints
(designer, production, 99.
and customer) are
waiting to be found. [2] Seagate
Technology, Barracuda
ATA II Family Product
5.
Manual, Rev. B,
Acknowledgemen Seagate Technology,
t May 2000.

267