ELECTRONICS LAB

Department of Electrical and Electronics Engineering

Lab Manual
ELECTRONICS LABOROTARY
LIST OF EXPERIMENTS
1. Simplification, realization of Boolean expressions using logic
gates/ universal gates.
2. Realization of half/ full adder and half/ full subtractor using
logic gates.
3. Realization of parallel adder/subtractor using 7483 chip BCD to
EXCESS-3 code conversion and vice-versa, binary to gray code
conversion and vice- versa.
4. Design and testing ring counter/Johnson counter.
5. Design and testing of sequence generator.
6. Realization of 3bit counter as a sequential circuit and MOD- N
counter design using 7490, 74192, 74193.

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EXPERIMENT 1
STUDY OF LOGIC GATES
AIM: Simplification, realization of Boolean expressions using
logic gates/ universal gates.
APPARATUS REQUIRED:
Sl. No Name of the component IC Number
1 AND GATE 7408
2 OR GATE 7432
3 NOT GATE 7404
4 EXOR GATE 7486
5 NAND GATE 7400
6 NOR GATE 7402
7 EX-NOR GATE 74266
8 PATCH CORDS
9 TRAINE-KIT

THEORY:
Circuit that takes the logical decision and the process are called
logic gates. Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are
known as Universal gates.
AND GATE:
The AND gate performs a logical multiplication commonly known
as AND function. The output is high when both the inputs are high.
The output is low level when any one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as OR
function. The output is high when any one of the inputs is high.The
output is low level when both the inputs are low.

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NOT GATE:
The NOT gate is called an inverter. The output is high when the
input is low. The output is low when the input is high.

NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high
when both inputs are low and any one of the input is low .The
output is low level when both inputs are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high
when both inputs are low. The output is low when one or both
inputs are high.

X-OR GATE:
The output is high when any one of the inputs is high. The output is
low when both the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

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OR GATE:

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X-OR GATE:

SYMBOL: PIN DIAGRAM

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NAND GATE:

RESULTS: The different types of logic gates are studied.

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EXPERIMENT 2
DESIGN OF ADDER AND SUBTRACTOR
AIM: Realization of half/ full adder and half/ full subtractor using
logic gates.
Sl. No Name of the component IC Number
1 AND GATE 7408
2 OR GATE 7432
3 NOT GATE 7404
4 EXOR GATE 7486
5 NAND GATE 7400
6 NOR GATE 7402
7 PATCH CORDS
8 TRAINE-KIT

THEORY:

HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one
from the sum S and other from the carry c into the higher adder position.
Above circuit is called as a carry signal from the addition of the less
significant bits sum from the X-OR Gate the carry out from the AND gate.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of
Input it consists of three inputs and two outputs. A full adder is useful to add
three bits at a time but a half adder cannot do so. In full adder sum output
will be taken from X-OR Gate, carry output will be taken from OR Gate.

HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half
subtractor has two input and two outputs. The outputs are difference and
borrow. The difference can be applied using X-OR Gate, borrow output can
be implemented using an AND Gate and an inverter.

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FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a
full subtractor the logic circuit should have three inputs and two outputs. The
two half subtractor put together gives a full subtractor .The first half
subtractor will be C and A B. The output will be difference output of full
subtractor. The expression AB assembles the borrow output of the half
subtractor and the second term is the inverted difference output of first X-
OR.
HALF ADDER

(c) K-map of Half adder (d) Circuit Diagram

(e) Half adder using NOR gates

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(f) Half adder using NAND gates

FULL ADDER

(c) K-Map of full adder

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(d) Circuit Diagram

(e) Full adder using NAND gates

HALF SUBTRACTOR

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FULL SUBTRACTOR

(c) Kmap of full subtractor

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(d) Circuit Diagram for full subtractor

(e) Full subtractor using NOR gates

PROCEDURE:
I. Connections are made as shown in the circuit diagram
II. Logical inputs are given as per the circuit diagram
III. Observe the output and verify the truth table

RESULT:
The half adder, full adder, half subtractor and full subtractor circuits are
Designed, constructed and verified with the truth tables.

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EXPERIMENT 3
DESIGN AND IMPLEMENTATION OF CODE
CONVERTER
AIM: To design and implement 4-bit
a. Binary to gray code converter
b. Gray code to binary code converter
c. BCD to Excess-3 code converter
d. Excess-3 to BCD code converter
e. Realization of parallel adder/subtractor using 7483 chip
APPARATUS REQUIRED:
Sl. No Name of the component IC Number
1 AND GATE 7408
2 OR GATE 7432
3 NOT GATE 7404
4 EXOR GATE 7486
5 IC 7483
6 PATCH CORDS
7 TRAINE-KIT

THEORY:
The availability of large variety of codes for the same discrete
elements of Information results in the use of different codes by different
systems. A conversion circuit must be inserted between the two systems if
each uses different codes for same information. Thus, code converter is a
circuit that makes the two systems compatible even though each uses
different binary code.
The bit combination assigned to binary code to gray code. Since each
code uses four bits to represent a decimal digit. There are four inputs and
four outputs. Gray code is a non-weighted code.
The input variable are designated as B3, B2, B1, B0 and the output
variables are designated as C3, C2, C1, Co. from the truth table,
combinational circuit is designed. The Boolean functions are obtained from
K-Map for each output variable.

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A code converter is a circuit that makes the two systems compatible

even though each uses a different binary code. To convert from binary code
to Excess-3 code, the input lines must supply the bit combination of
elements as specified by code and the output lines generate the
corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean
Expressions derived by the maps. These are various other possibilities for a
logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.

LOGIC DIAGRAM
A. BINARY TO GRAY CODE CONVERTER

TRUTH TABLE:
Binary input Gray code output
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

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K-Map simplification

Binary to gray code code converter

B. GRAY CODE TO BINARY CONVERTER

Gray code Binary code

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
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K-Map Simplification

Gray to binary code converter

C. BCD TO EXCESS-3 CODE CONVERSION

TRUTH TABLE:

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K-Map simplification of BCD to EXCESS-3 conversion

Circuit diagram of BCD to EXCESS-3 conversion

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D. EXCESS-3 TO BCD CONVERSION

K-Map simplification of Excess-3 to BCD

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Circuit of Excess-3 to BCD conversion

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

E. REALIZATION OF PARALLEL ADDER/SUBTRACTOR USING

7483 CHIP

PIN DIAGRAM:

Here A1 A2 A3 A4 & B1 B2 B3 B4 &Cinare the inputs. S1S2S3S4&Coutare the

outputs.

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1) 4 BIT ADDER OPERATION

If control input Cin = 0, addition can be performed.
Ex a) if A1 A2 A3 A4 = 1100 Cin = 0
B1 B2 B3 B4 = 0011
Then sum, -------------------------
S1 S2 S3 S4 = 1111 and Cout = 0

Ex b) if A1 A2 A3 A4 = 1001 Cin = 1
B1 B2 B3 B4 = 1101
Then sum, -----------------------------
S1 S2 S3 S4 = 0111 and Cout = 1

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2) 4 BIT SUBTRACTION OPERATION USING ONES AND TWOS

COMPLEMENT METHOD.

I. 1s complement method

If Cin =1 subtraction can be performed.

Ex a) if A1 A2 A3 A4 = 1001
B1 B2 B3 B4 = 0011 by normal subtraction
Difference ,-------------------------------------
S1 S2 S3 S4 = 0110
In ones complement method
A1 A2 A3 A4 = 1100
B1 B2 B3 B4 = 1100 (1s complement of 0011)
End around carry , 0101
+1
If end around carry is 1, the result is positive. If there is no carry the
result is negative and is in 1s complement form.

Difference ,S1 S2 S3 S4 = 0110

II. 2s complement method:

2s complement method of subtraction can be performed, if S =1 and Cin= 1
A1 A2 A3 A4 = 1100
B1 B2 B3 B4 = 1101 (2s complement of 0011)

End around carry , 0110

+1
If end around carry is 1, the result is positive. If there is no carry the
result is negative and is in 2s complement form.
Difference, S1 S2 S3 S4 = 0110

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PROCEDURE:

1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Apply Minuend and subtrahend bits on A and B and cin=1.
5. Verify the results and observe the outputs.

RESULT: The Binary to gray, Gray to binary, BCD to excess-3, Excess-3 to

BCD code converter and parallel adder/subtractor using 7483 chip
Combinational circuits are constructed and their truth tables have been
checked.

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EXPERIMENT 4

DESIGN OF RING COUNTER/JHONSON COUNTER

AIM: To realize and study Ring Counter and Johnson counter.

APPARATUS REQUIRED:

Sl. No Name of the component IC Number

1 IC 7495
2 NOT GATE 7404
3 PATCH CORDS
4 TRAINE-KIT

THEORY: Ring counter is a basic register with direct feedback such that
the contents of the register simply circulate around the register when the
clock is running. Here the last output that is Q0 in a shift register is
connected back to the serial input. A basic ring counter can be slightly
modified to produce another type of shift register counter called Johnson
counter. Here complement of last output is connected back to the not gate
input and not gate output is connected back to serial input. A four bit
Johnson counter gives 8 state output.

RING COUNTER
CIRCUIT DIAGRAM:

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Right shift register using IC 7495

Left shift register using IC 7495

TRUTH TABLE:

CLOCK Q3 Q2 Q1 Q0
PULSES
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1

Waveforms of Ring counter

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PROCEDURE:
1. Make the connections as shown in the circuit diagram.
2. Connect mode control to switch and set mode to 1, load the input
D3,D2,D1,D0 to 1000 by giving 1 clock(clk2). For counter mode keep
mode to zero.
3. Apply clock pulses at clock 1 terminal and observe outputs.

JOHNSON COUNTER:

CIRCUIT DIAGRAM:

TRUTH TABLE:

CLOCK Q3 Q2 Q1 Q0
PULSES
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
8 0 0 0 0

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Waveforms of Johnson/Twisted ring counter

PROCEDURE :
1. Make the connections as shown in the circuit diagram.
2. Apply clock pulses at clock 1 terminal and observe outputs. [no need to
give the input]

RESULT: Ring and Jhonson counters are designed and verified with the
truth table

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EXPERIMENT-5

SEQUENCE GENERATOR

AIM: To design a sequence generator using IC 7495

COMPONENTS REQUIRED:

Sl. No Name of the component IC Number

1 IC 7495
2 IC 7486
3 PATCH CORDS
4 TRAINE-KIT

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PROCEDURE:

1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. By Keeping mode=1. Load the input A,B,C,D as in Truth Table 1st Row and give
a clock pulse
5. For count mode make mode = 0.
6. Verify the Truth Table and observe the outputs

RESULTS:

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EXPERIMENT-6
DESIGN OF COUNTERS
AIM: Realization of 3 bit counters as a sequential circuit and mod-N counter
design using 7490, 74192, 74193

APPARATUS REQUIRED:

SL.NO. NAME OF THE COMPONENT IC NUMBER

1 JK Flip Flop 7476
2 NAND GATE(3 pin) 7410
3 AND GATE 7408
4 OR GATE 7432
5 DECADE COUNTER 7490
6 DECADE UP/DOWN COUNTER 74192
7 MOD-16 COUNTER 74193
8 PATCH CORDS
9 TRAINER KIT

A.DESIGN OF DECADE COUNTER USING 7490

PIN DIAGRAM:

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TRUTH TABLE:
QD QC QB QA

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

0 0 0 0

MOD-7 COUNTER

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TRUTH TABLE:
QD QC QB QA

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 0 0 0

MOD-5 COUNTER

TRUTH TABLE:
QD QC QB QA

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 0 0 0

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B.DESIGN OF UP/DOWN COUNTER USING 74193

1. P1,P2,P3 and P0 are parallel data inputs2.

2. Q0,Q1,Q2 and Q3 are flip-flop outputs3.
3. MR: Asynchronous master reset4.
4. PL: Asynchronous parallel load(active low) input4.
5. TCd : Terminal count down output6.
6. TCu Terminal count up output

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I.DESIGN OF UP COUNTER FOR PRESET VALUE 0010, N=10

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II.DESIGN OF DOWN COUNTER FOR PRESET VALUE 0010, N=10

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C.DESIGN OF 74192
PROCEDURE:

Check all the components for their working.

Insert the appropriate IC into the IC base.

Make connections as shown in the circuit diagram.

Verify the Truth Table and observe the outputs.

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