Doc. No.

sngce/cse/fm/qb/16-17/cs203
Rev: 0
Sree Narayana Gurukulam College of Engineering,

Kadayiruppu
2016-2017

Department of Computer Science and Engineering

QUESTION BANK

Semester: 3

Sub Name & Code:CS203 Switching Theory And Logic Design

Faculty: JUSTY JAMESON

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Signature: Faculty: JUSTY JAMESON HOD:Prof. P JAYAKUMAR
 QUESTION BANK

2016-2017

Sub Name& Code:CS203 Switching Theory And Logic Design

Module 1
1. Convert the following binary number to its equivalent decimal numbers

a) 1101
b) 1011
c) 0.001101
d) 0.1101
e) 111011.101

2. Design a BCD to excess 3 code converter

3. Convert the decimal numbers to the equivalent binary number

a. 43

b. 0.4375

c. 2048.0625

4. Design a binary to gray code converter

5. What arw ASCII and EBCDIC codes ? Where are they used?

6. Give the binary ,BCD ,Excess -3 and gray code representation of the decimal
number 29

7. Find the value of x in the following:

(a) (847)10= (x)16

(b) (10110101)2 = (x)8
(c) (A3BH)16 = (x)10
8. Design a circuit for a 2 bit BCD to binary convertor, with the help of the function
tables.
9.

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Signature: Faculty: JUSTY JAMESON HOD:Prof. P JAYAKUMAR
 Module 2
1. What are universal gates?

2. State and prove DeMorgans Theorem

3. Simplify using K map:

i. A(ABC+ABC+ABC)
ii. F(w,x,y,z)=(0,1,2,4,5,6,8,9,12,13,14)
4. Reduce using Quine McCluskey method S=(1,2,4,5,6,8,9,12) + d(3,10,13,15).
Draw reduced prime implicants table and the minimal reduced circuit.

5. Simplify using Quine Mccluskey method f=(1,7,11,12,13,15)

6. Obtain the canonical SOP corresponding to f(a,b,c)=a+ab+bc

7. Convert the following to canonical forms:

(a) B+ABD+BC
(b) (+C)(A+B)(B+C)

Module 3
1. Explain Carry Look Ahead Adder

2. Explain with neat figure

(a) A Carry Save Adder

(b) Serial Adder

3. Explain with a neat figure a carry propagate adder

4. Explain the working of a comparator circuit.Design a comparator circuit to

compare two 2 bit numbers

5. What is a Multiplexer?

6. Show how a full adder can be converted to afull subtractor with the inclusion of
an inverter circuit

7. Design ahalf subtractor using only basic gates

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Signature: Faculty: JUSTY JAMESON HOD:Prof. P JAYAKUMAR
 8. Draw a half adder circuit using NOR gate only.

9. Using full adder blocks, represent the following 4-bit addition:

1111 + 1011

10. What is a full subtractor. Design the same using K-maps and draw the minimal
circuit.
11. With a neat block diagram ,explain a 4 bit carry look ahead adder
12. Design a gray to binary code convertor using 4:1 MUX. Draw the ciscuit diagram
and explain.

Module 4
1. Draw the circuit of the D-Flip-Flop using NAND gates

2. What is Race Around Condition ?How is it Eliminate?

3. Explain in detail , with neat diagram ,the working of master Slave JK Flip-Flop

4. A Sequential circuit has 2v flip-flop A and B , 2 inputs x and y and an output

z.The flip-flop input function and the circuit output function are follows:

JA=x B+yB; KA=xyB

JB=xA; KB=xy+A

Z=xyA+xyB

Obtain the logic diagram ,state table,state diagram and state equation.

5. Draw the circuit of a JK flip-flop using NAND gates.

6. Explain with neat figure the Master Slave JK flip flop

7. With neat figures explain :

i. D flip flop using NABD gates

ii. T flip flop using NAND gates
iii. Race around condition

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Signature: Faculty: JUSTY JAMESON HOD:Prof. P JAYAKUMAR
 8. A sequential circuit has 4 flip-flops A,B,C,D and input x.It is described by the
following state equations:

A(t+1)(CD+CD)x+(CD+CD)x

B(t+1)=A

C(t+1)=B

D(t+1)=C

i. Obtain the sequnce of states when x=1 starting from state ABCD=0001
ii. Obtain the sequence of states when x=0 starting from state ABCD=0000

9. What are the differences in the operation of master slave and edge triggered
flip-flops? Compare and contract their performances

10. Draw the circuit diagram of a master slave JK flip flop and show how the race
around condition is eliminated in it?

11. Write down the truth table and characteristic equation of SR flip-flop.

12. Distinguish between truth table and excitation table, taking JK flip flop as
example. How the excitation table can be derived from the truth table.

13. A network produces a 1 output if and only if the current input and the previous
three inputs correspond to either of the sequences 0110 or 1001. The outtput 1 is
to occur at the time of the fourth input of the recognised sequence. Outputs of
zero at all other time. Construct the state diagram.

14. Design a sequential machine with one input and one output line such that the
output becomes 1 when the input receives a sequence 101. Overlapping the
sequence is allowed. Use D flip flops.

Module 5
1. Explain the working of the Johnson counter

2. Explain the different type of the shift register and their application

3. Design an asynchronous binary 4-bit up counter

4. What is a Decade counter ?

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Signature: Faculty: JUSTY JAMESON HOD:Prof. P JAYAKUMAR
 5. Explain the working of the Asynchronous Decade counter

6. Design a 4 bit binary synchronous up counter

7. Explain with neat figures Ring conter and Johnson counter

8. Design a synchronous counter using K-maps:000,010,101,110 and repeat . The

undesired states 001,011,100 and 111 must always go to 000 on the next clock
pulse . Draw the circuit diagram.

9. How are shift-left or shift-right transfer registers built.

10. Construct a johnson counter for ten timing signals

11. With a neat diagram and waveform ,explain a 4 bit shift register with left/right
shift control and with parallel load control

12. Design a mod 77 synchronous counter by cascading two 4 bit binary counters.

Module 6
1. List the major difference between PAL and PLA

2. How divide overflow problem can be avoided?

3. Why should the sign of the remainder after a division be the same as the sign of
the dividend?

4. Design a BCD subtractor using PLA?

5. Design a 2x4 decoder in HDL?

6. Explain the algorithm for addition and subtraction of floating point numbers?

7. Give the syntax for input array declaration using VHDL?

8. Write the VHDL code for realizing 4:1 multiplexer?

9. The capacity of a 4Kx8 ROM is to be expanded to 16Kx8. Find the number of

chips required and the number of address lines in the expanded memory?

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Signature: Faculty: JUSTY JAMESON HOD:Prof. P JAYAKUMAR