Transistor

Modeling

eyewire

Andreas R. Alt, Diego Marti, and C.R. Bolognesi

S
mall-signal equivalent circuit (SSEC) models
prove indispensable to a broad range of activi
ties, ranging from the understanding of device
physics, the analysis of device performance,
the characterization and comparison of fabrica-
tion processes, the bottom-up construction of large-signal
models, the extraction of intrinsic noise parameters, and
the design of monolithic microwave integrated circuits
(MMICs). Because the SSEC model links the physical
structure of the device to its circuit behavior, it allows
analysis of the microwave performance as a function of
the device geometry. A physically representative model
can therefore be used for frequencies extending beyond
those of the measurement setup. One must keep in mind
that a model is only a physical approximation of a given
device, and the more we demand of a model, the more
likely we are to expose its various shortcomings. For
example, one can stress the limits of a model by extending
its frequency range or by applying it to dissimilar tech-
nologies; experience shows that with newer material sys-
tems, models tend to provide poorer fits to the measured
data. In the course of our work, we specifically investi-
gated differences brought about by different materials for
devices implemented with a given mask set.

Andreas R. Alt, Diego Marti, and C.R. Bolognesi (colombo@ieee.org) are with the Laboratory for
Millimeter-Wave Electronics of the Swiss Federal Institute of Technology, Zrich (ETH), 8092 Switzerland.

Digital Object Identifier 10.1109/MMM.2013.2248593

Date of publication: 7 May 2013

June 2013 1527-3342/13/$31.002013IEEE 83

Because the SSEC model links the
physical structure of the device to
its circuit behavior, it allows analysis
of the microwave performance as a
function of the device geometry.
There are several motivations behind the pres-
ent article. The first is to present a coherent view of
SSEC models, of the physical approximations they
involve, and of their limitations. This is no simple task
given the large and fragmented literature on SSEC
model extractions. For example, many model extrac-
tion methods make use of forward gate biases but the
question of how much forward gate bias is appropriate
is rarely, if ever, addressed. This is one of the unique
aspects of this article because it explicitly shows the
effects of bias on the extrinsic SSEC element extrac-
tion. Next, we review the development of SSEC in field
effect transistors (FETs) so that the casual reader can
get a sense of the logical structure of the models with-
out necessarily reading through the entire literature.
The comparison among different material systems
should prove helpful to both the graduate student set-
ting up for his first SSEC extractions and the experi-
enced engineer who, when transitioning to gallium
nitride (GaN) devices after several years of work with
gallium arsenide (GaAs) HEMTs, may be confronted
by less than satisfactory results with comfortable
methods that worked so well in the older technol-
ogy. Advanced readers who wish to understand more
subtle distinctions such as the effects of distributed
channel capacitances and resistances will also find
clarifications on these effects. In the final analysis, the
reader is provided with a general SSEC extraction pro-
cedure that allows direct comparisons between differ-
ent device types and fabrication technologies.
Small-Signal Equivalent Circuit Developments
Ever since the first frequently used FET lumped ele-
ment circuit models were presented by Dacey and Ross
in 1955 and Hower and Bechtel in 1973 [5], [6], there
has been ongoing work to further refine SSEC models
and their associated extraction methods for FETs and
HEMTs. The basic SSEC extraction method was pre-
sented by Minasian [7] for GaAs MESFETs in 1977 and
extended to determine the extrinsic resistances and
inductances from S-parameter data in a cold-FET con-
dition ^Vds = 0 h by Diamand and Laviron in 1982 [8].
In 1984, Curtice and Camisa [9] reported a procedure
for generating the equivalent circuit models for carrier-
mounted GaAs FETs that eventually led to the widely
used method introduced in 1988 by Dambrine et al. [10].
Dambrines method allowed a physically based deter-
mination of the extrinsic parameters and supplied an
analytical set of equations for the direct calculation of
84 June 2013
the seven intrinsic SSEC elements as a function of the
measurement frequency. Checking for the frequency
independence of each SSEC element provided a fast and
reliable method to verify the extracted element con-
sistency. Improvements and extensions to Dambrines
method were published by Berroth and Bosch [11] in
1990. Also in 1990 and 1991, the same group [12], [13]
extended the intrinsic SSEC by including the differen-
tial resistances of the gate-to-source and gate-to-drain
diodes as well as a series-resistance with the feedback
capacitance C gd ^R gsf, R gdf, and R gd h . Interesting work on
the parasitic capacitance and SSEC parameter extraction
was carried out at the same time by Anholt and Swirhun
[14], who explained the origin of parasitic capacitances
and showed how they should be modeled. Their latter
work in [15] emphasized the bias independent nature of
cold-FET extrinsic parameters.
Up to this point, all characterization methods relied
on strongly forward biased gate Schottky junctions in
order to extract the parasitic resistances and induc-
tances. This forward bias condition is applied in order
to eliminate the influence of the intrinsic RC paral-
lel networks and allow the extraction of the extrinsic
SSEC elements. In 1993, Tayrani et al. introduced a
new extraction method [16], which does not require
strongly forward biasing the gate Schottky junction.
This new method allowed the parasitic inductance and
resistance element extraction without large forward
gate currents which often lead to irreversible degrada-
tion of the gate electrode. In the same year, White and
Healy [17] suggested an improved equivalent circuit
under zero drain bias pinch-off conditions that cor-
rected the overestimated parasitic source and drain
capacitances due to the neglect of C ds in Dambrines
model [10].
In 1996 Rorsman et al. [18] presented a new cold-
FET extrinsic SSEC model including a Schottky series
resistance and enabling the extraction of the parasitic
resistances and inductances. Pads were modeled as a
r network, thus extending the model validity to higher
frequencies. The same work additionally pointed out
the importance of adding R gd for accurately modeling
the maximum stable gain (MSG), maximum available
gain (MAG), current gain ^h 21 h , and stability factor
(k) and presented exact equations for calculating the
intrinsic element values versus frequency.
In the same year, Reuter et al. [19] published an
extended intrinsic SSEC adding the capability of model-
ing impact ionization. By making extensive use of regres-
sion analysis, Miras and Legros [20] presented interesting
approaches for extracting the extrinsic elements of short-
gate InP HEMTs without strongly forward biasing the
gate Schottky junction and achieved excellent agreement
between measured and modeled data. However, their
work included some intrinsic SSEC elements as frequency-
dependent quantities, at the cost of increased complexity
and reduced physical interpretation.
 Besides the aforementioned contributions, fur-
ther model extensions and methods where proposed,
ranging from the use of neural networks to genetic
optimization algorithms to find suitable SSEC ele-
ment values fitting the measured device data
[21][30]. The well-known drawback of pure opti-
mization driven approaches is that they often make
extensive use of additional circuit elements and can
occasionally result in nonphysical SSEC values, due
to potential dependencies on the starting values, on
local minima, and on details of the chosen optimiza-
tion method.
With the continuing progress in the field of GaN
HEMTs, existing models and extraction methods were
adapted in order to take the GaN specific effects into
account [25]:
hightwo-dimensionalelectrongas(DEG) sic elements using only a small forward bias applied
densities
large conduction band discontinuity
piezoelectric and spontaneous polarization effects.
Due to the lack of native GaN substrates, GaN
HEMTs for RF and high-power applications are now
predominantly fabricated on silicon carbide (SiC)
or silicon (Si) substrates. While Si offers a somewhat
lower thermal conductivity, it is available in commer-
cial volumes and large wafer sizes at economically
competitive prices. However, GaN HEMTs grown on
Si-substrates can exhibit parasitic buffer effects origi-
nating from the [31]:
nitridization of Si in the initial stages of nitride
growth
unintentional contamination from the substrate
during growth.
GaAs-on-Si HEMTs suffered from similar effects,
and in 1996, Goto et al. [32] proposed the use of a simple
gate and drain extrinsic series RC-network in order to
model the reduced isolation in their proposed extrin-
sic circuit model. The approach was extended to two
RC-pairs at the gate, and three RC-pairs at the drain, by
Chumbes et al. in [31] who reported an accurate model
for GaN on leaky Si(111) substrates in 1999.
Another key consideration for GaN HEMTs is associ-
ated with the high-contact resistances originating from
the large conduction band discontinuity, as pointed out
by Gaska [33] in 1997. In the same year, Burm et al. [34]
showed that highly resistive contacts can be modeled
as transmission lines. In 2000, Chigaeva et al. [35] dem-
onstrated good agreement between simulation and
measurements when driving sufficiently high current
through the gate in order to diminish the influence of
the gate capacitance and therefore decrease the differ-
ential resistance.
Because high gate currents often lead to irrevers-
ible device degradation, significant effort was spent on
developing low gate bias model extraction techniques
for GaN HEMTs. Initially developed for AlGaAs/
GaAs HEMTs in 1999, Jeon et al. [36] reported the first
June 2013 85
The majority of SSEC model extraction
methods are based on the assumption
that the extrinsic and intrinsic circuits
can be partitioned.
extraction method able to extract the extrinsic ele-
ments in cold-FET mode below pinch-off. By describ-
ing the Schottky barrier and channel region by means
of a distributed RC-network, this method allows one
to determine the parasitics without forward biasing
of the gate and thus avoids any possible device deg-
radation. Based on this approach and simplifying the
equations obtained by neglecting the drain-source
capacitance C ds , Guang et al. [37] extracted the extrin-
to the gate of the AlGaN/GaN HEMT device. Also in
2006, work from Crupi et al. [38] treated the existence
of the channel capacitance in their approach, requir-
ing an iterative procedure to determine a suitable for-
ward bias condition, which is high enough to suppress
the channel resistance and low enough to not cause
significant current flow through the gate. A detailed
analytical extraction procedure also taking the drain-
source capacitance C ds into account, is reported by
Brady et al. in [39] from 2008. Their approach is also
based on the cold-FET technique of Jeon et al. [36],
in combination with the modified distributed chan-
nel model. Despite the good fit of the modeled and
simulated Z-parameters, some of the extracted results
e.g. the extracted channel resistance is tenfold overes-
timated compared to the specified sheet resistance of
300 X2 and reflects the difficulty of optimizer-driven
extraction procedures.
A series of extraction algorithms have been pre-
sented in [25][30], beginning with the report of a
15-element small-signal FET model in 1992, which
evolved to a 22-element distributed model for GaN
HEMTs on Si, which was later extended to a large-
signal model in 2011. The core of their approaches is
a hybrid optimization technique which determines
the starting values either from measurements or from
a genetic algorithm based procedure and then uses a
local optimization technique, to find the optimal value
of each element.
General Methods
The majority of SSEC model extraction methods are
based on the assumption that the extrinsic and intrin-
sic circuits can be partitioned. Moreover, in contrast
to intrinsic elements, the extrinsic SSEC elements are
assumed to be bias independent. Procedures there-
fore begin with the determination of the extrinsic
SSEC elements and follow by carefully removing (or
deembedding) their contributions from the measured
device data. Thereafter the intrinsic SSEC elements
 can be calculated, unless the used model involves
more equations than measured variables, as, for
example, the impact ionization model [19] does. In
this case, missing elements must be determined either
by additional measurements or through numerical fit-
ting methods.
An accurate extraction of the extrinsic elements
lays an essential foundation for successfully setting
up the SSEC representation of the device. Two main
approaches to determine the extrinsic SSEC elements
have proven successful:
the cold extraction technique, setting the tran-
sistor in the passive condition ^Vds = 0 V h in
order to determine the parasitics in reverse and/
or forward gate bias mode
the passive extraction technique, using pas-
sive test structures to independently determine
parasitics.
The passive extraction technique was first reported
by Wijnen et al. [40] in 1987 for use with BJTs and
represents the first use of a measured open dummy
structure for deembedding the parasitic pad elements.
The approach was significantly extended in both fre-
quency range and complexity by Cho and Burk [41] in
1991, and by other groups later [42][46]. While mostly
used for the deembedding of HEMT pads, open and
short structures may not be used to determine all
extrinsic SSEC elements. The reason is that the intrin-
sic device data can only be determined if the inter-
action between the extrinsic and intrinsic regions of
the device can be neglected. For most common device
types, and especially for GaN HEMTs, this assump-
tion of negligible source and drain resistances cannot
be made without introducing significant errors. In the
following section, we give an example of this circum-
stance and demonstrate that for the extraction of the
extrinsic parasitic capacitances the passive extraction
technique offers major advantages in terms of simplic-
ity and accuracy.
Lg Rg Cgd Rgd
G D
Cgs Vdg
Vgs Rds
-j~t
Rgs
Cpg2 Cpg1 gme V gs
Intrinsic
Rg, sub3
Rg, sub1 RsExtrinsic Rd, sub1
Rg, sub2
Ls
S
Figure 1. Proposed SSEC including both the extrinsic and intrinsic partitions.
The lower-frequency substrate losses are accounted by the R g/d, sub3 resistors in
the extrinsic (pad) circuit.
86 June 2013
Extraction of Small-Signal Equivalent
Circuit Extrinsic Elements
We first consider the extraction of the extrinsic part of
the SSEC. An accurate extrinsic equivalent circuit is
needed in order to obtain a physically representative
intrinsic SSEC because errors in the extrinsic network
ripple into the intrinsic element values, potentially
leading to misinterpretations of physical phenomena.
A key contribution of the present work is that our gen-
eral extrinsic model properly reproduces measured
characteristics for various possible degrees of buf-
fer layer conductivity, without invoking any a priori
knowledge of buffer layer properties. The proposed
complete SSEC including both the extrinsic and intrin-
sic partitions is shown in Figure 1. We next consider the
extraction of the various components of the extrinsic
network in detail.
Extrinsic Capacitances
Accurate determination of the extrinsic capacitances
is crucial for determining the exact SSEC. Incomplete
or exaggerated removal of the extrinsic capacitive cou-
pling influences the subsequently extracted elements
and thus introduces errors. There are two strategies to
determine the extrinsic capacitances:
conventional cold-FET extraction far below
pinch-off
passive extraction using a passive open structure.
In his original work, Dambrine explained [10] how
the input and output pad capacitances C pg and C pd
can be measured by suppressing channel conductivity
at zero drain bias with gate voltages below pinch-off.
In this state, the intrinsic gate capacitance and conduc-
tance are believed to be negligible. Because the induc-
tances and resistances can be neglected up to frequen-
cies of a few gigahertz, the three capacitances C pg , C pd,
and C b can be calculated from the imaginary parts of
the three Y-parameters Y11, Y22 , and Y12 = Y21, respec-
tively. In Dambrines cold-FET model, C b represents the
total depletion capacitance below the
gate (including fringing capacitances).
As White and Healy argued in [17],
Rd Ld the extrinsic capacitances are domi-
nated by the bond/probing pads.
Due to the typically nearly symmet-
rical pad layout and the similar imag-
Cds
Cpd1 Cpd2 inary parts of Y11 and Y22, nearly
equal extrinsic gate and drain capaci-
Rd, sub3 tance values are expected. White
and Healy showed that C pd in Dam-
Rd, sub2
brines [10] extrinsic model is consid-
erably overestimated, and they there-
fore introduced a corrected approach
preserving the symmetry of the
pinched-off device while accounting
for the neglected C ds in Dambrines
model. This was achieved with three
identical redefined capacitors C b which are associated
with the source, drain and gate to describe the total
depletion capacitance underneath the gate. A com-
parison of both methods swept against gate voltage for
a 2 # 0.1 # 50 m 2 AlInAs/GaInAs/InP HEMT with a
threshold of -0.2 V is presented in Figure 2, and for a
2 # 0.1 # 50 m 2 GaN/Si(111) HEMT with a threshold
of -3.2 V in Figure 3.
As can be seen from Figures 2 and 3, White and
Healys [17] approach leads to more similar and geo-
metrically interpretable values compared to Dam-
brines method. Extracted values at Vgs = - 2V for the
AlInAs/GaInAs/InP HEMT and Vgs = - 7V for the
GaN/Si(111) HEMT are listed in Table 1.
Despite White and Healys improvements, extracting
the extrinsic capacitances in a cold-FET pinch-off condi-
tion still involves three notable drawbacks:
It requires a well pinched-off device with low
gate leakage levels.
Large negative gate voltages must be applied to
reduce extraction dependence on gate voltage (see
C pd in Figure 3).
Conductive or imperfectly insulating buffer/sub-
strates cannot be taken into account.
In order to avoid the aforementioned drawbacks, a pas-
According to our experience, none
of the currently used extrinsic
capacitance models is capable of
reproducing the behavior of the
50 nm GaN on Si(111) open structure.
generally, with or without leakage, and accurately
model the imperfect extrinsic pad capacitances.
According to our experience, none of the currently
used extrinsic capacitance models is capable of repro-
ducing the behavior of the 50 m GaN on Si(111)
open structure as demonstrated in Figure 4. The fig-
ure shows that the measured S 11 on open dummy
pads varies significantly across technologies, accord-
ing to the residual conductivity of buffer layers, from
a nearly ideal behavior for opens on AlInAs/InP and
90
Cb, Dambrine Cb, White
80
Cpd, Dambrine Cpd, White
70 Cpg, Dambrine Cpg, White
Capacitance (fF)

sive open dummy structure can be used to determine 60

the extrinsic capacitance elements. This can either be 50
done through full-wave electromagnetic simulations, 40
as reported by Resca et al. in 2009 [47] or by measure- 30
ment as proposed by Goto [32] and Chumbes [31] in 20
1996 and 1999, respectively. Imperfections of the buffer 10
and the substrate can on the other hand only be deter- 0
-7 -6.5 -6 -5.5 -5 -4.5 -4 -3.5 -3-2.5
mined by actual measurements. Vgs (V)
For these reasons, our extrinsic SSEC model
includes resistors R g/d, sub3 to model the dc/low-fre- Figure 3. Bias dependence of pinch-off extraction on
quency substrate losses, in parallel with two resistor/ 2 # 0.1 # 50 m 2 GaN/Si(111) HEMT according to [10]
capacitor (RC) branches, in the gate and the drain cir- and [17].
cuits, as indicated in Figure 1. With this configura-
tion we are able to treat various buffers and substrates

0.1
0
-0.1
90
Cb, Dambrine Cb, White -0.2
80
S11 (dB)

Cpd, Dambrine Cpd, White -0.3

70
Capacitance (fF)

Cpg, Dambrine Cpg, White -0.4

60 -0.5
50 -0.6
-0.7
40
-0.8
30
-0.9
20 0 5 10 15 20 25 30 35 40
10 Frequency (GHz)
0
-2 -1.75 -1.5 -1.25 -1 -0.75 -0.5 -0.25 0 Open AlInsAs on InP Open GaN on Si (110)
Vgs (V) Open GaN on SiC Open GaN on Si (111)
Open InP (MOCVD)

Figure 2. Bias dependence of pinch-off extraction on

2 # 0.1 # 50 m 2 AlInAs/GaInAs/InP HEMT according Figure 4. Measured and modeled S 11 behavior of 50 m
to [10] and [17]. Open structures.

June 2013 87
 Table 1. Small signal equivalent circuit elements of 2 # 50 nm open.

Cpg1 Cpg2 Rgsub1 Rgsub2 Rgsub3 Cpd1 Cpd2 Rdsub1 Rdsub2 Rdsub3
(fF) (fF) (X) (k X ) (k X ) (fF) (fF) (X) (k X ) (k X )

GaN on SiC 10.1 2.1 35.2 87 49 10.0 5.3 26.0 46 63

GaN on

Si(110) 13.1 3.4 35.8 9.2 198 13.5 3.4 33.1 6.8 191

GaN on

Si(111) 12.7 116 27.7 2.6 14.8 13.4 122 26.7 2.5 14.8

AlInAs

on InP a 14.9 0.0 12.1 3 209 15.4 0.0 13.6 3 254

InP b 14.3 4.4 15.4 15.2 6.8 14.3 3.6 15.3 12.0 7.5

AlInAs a, e on InP 14.7 15.5

GaN on Si(111) e 12.7 13.7

Dambrine c AlInAs 14.6 35.9

White c AlInAs 14.6 16.8

Dambrine d GaN 13.7 35.1

White d GaN 13.7 19.4

a
350 nm thick MBE grown AlInAs on InP substrate.
b
InP is MOCVD grown and doped with Fe.
c
2 # 0.1 # 50 nm2 AlInAs/GaInAs/InP HEMT extracted in pinch-off (Vgs = -2 V) according to [10] and [17].
d
2 # 0.1 # 50 nm2 GaN/Si(111) HEMT extracted in pinch-off (Vgs = -7 V) according to [10] and [17].
e
Values from purely passive approach according to Wijnen et al. in [40].

GaN/SiC buffers with a highly insulating character,
to the more conductive behavior observed for GaN on
Si, with the highest conductivity seen for metalorganic
chemical vapor deposition (MOCVD) deposited lay-
ers. It is important to emphasize that this behavior has
nothing to do with the intrinsic transistor operation
(since it arises from an open pad dummy), but that it
must be separated and accurately modeled by the
extrinsic equivalent circuit. Unless this is properly
done, nonideal buffer effects will corrupt intrinsic SSEC
element values.
One should note that the GaN on Si(111) data
recorded in Figure 4 is not indicative of a pathologi-
cal technology: before the deembedding of the open/
short structures, HEMTs built on the same layer show
a maximum fT of 80 GHz with a simultaneous fmax
of 127 GHz (deembedded values of 111 and 135 GHz,
respectively). We have shown that GaN on Si(111)
material similar to that shown in Figure 4 is compat-
ible with the realization of low-loss transmission lines
up to 110 GHz [48].
It is apparent that extrinsic capacitance models
without resistors will not be able to account for the
low-frequency substrate losses: the model as proposed
by Crupi et al. [38] consisting of a parallel RC element
in series with another capacitor does not reproduce
the behavior shown in Figure 4. On the other hand,
our proposed extended extrinsic SSEC model is also
capable of modeling nearly ideal buffers and substrates
as shown in Figure 4 for the AlInAs on InP open dummy
structure. The physical origin of the proposed network
in the case of the GaN on Si can be understood by con-
sidering the metal/GaN/p-Si structure as behaving as
an n-i-p diode under RF or small-signal drive.
Rather than using different device conditions
(pinch-off, heavy forward bias, and peak g m, ext ) as
originally proposed by Chumbes [31] for determin-
ing network element values, we decouple the element
extraction from the device measurements by making
use of the separate open dummy structure illustrated
in Figure 5(a).
Such open/short structures are, in any case,
required for deembedding pads effects. Following
the described procedure, they allow an unambiguous
and unprecedentedly accurate determination of the
extrinsic circuit elements. Due to the under-determi-
nation of their characteristic set of equations, the ten
element values are obtained by optimization of the
modeled S-parameters. Optimization is implemented
using a modified Downhill Simplex method suitable

88 June 2013
for finding local minimas of multidimensional non- by White and Healy [17]. R g,sub2 and R d,sub2 account for
linear problem sets and capable of handling boundar- the buffer/substrate leakage and emphasize the high
ies, which were set to physically meaningful values. resistivity of SiC substrates compared to Si(111).
The starting values for C pg1 and C pd1 are calculated The lossless passive approach reported by Wijnen
with the measured S-parameters of the passive open et al. in [40] models the open structure entirely with
structure, in their Y-parameter representation, accord- one gate, one drain and one coupling capacitance. This
ing to White and Healys improved model [17]: approach leads to nearly identical (and symmetric) val-
ues when compared to our extracted element values for
1m ^Y11h + 2 $ 1m ^Y12h C pg1 and C pd1 .
C pg1 . , (1)
~ While the cold-FET (pinch-off) method of White
1m ^Y22 h + 2 $ 1m ^Y12 h and Healy [17] is still able to determine similar values
C pd1 . . (2)
~ for C pg1 the difficulty of accurately determining Cpd1
becomes apparent from the larger and less symmetric
Starting values for Rg,sub2 and Rd,sub2 are determined by values of C pd1 and its gate voltage dependence as illus-
evaluating (3) and (4) at low frequencies: trated in Figure 3.

R g,sub2 . 1 , (3)
0e ^Y11 + Y12 h f"0

R d,sub2 . 1 . (4)
0e ^Y22 + Y12 h f"0

Resistor values for R g,sub2 and R d,sub2 exceeding

100k X are set to infinity, and the corresponding Cpg2
and Cpd2 values are set to zero in order to disable the
particular branch when it is not required. Starting
values for the dc leakage resistors Rgsub3 and Rdsub3 are
calculated from (5) and (6) and account for the non-
(a) (b)
zero intersection of S11 and S22 with the Y-axis

R g,sub3 . s2z ^ S 11 h f"0 , (5) Figure 5. Structure (a) represents the used open and
R d,sub3 . s2z ^ S 22 h f"0 . (6) (b) short dummy structure. The dashed box in represents
the removed active device area.

Figure 4 compares the mea-

sured against the modeled data
of S11 showing good agree- DCg,ch = Cg,ch /n
ment for all studied substrate DRg,ch = Rg,ch . n
types. From the figure it can be DCch = Cch . n Rd Ld
concluded that even the leaky GaN DRch = Rch /n Cch DRg,ch D
on Si(111) behavior is modeled with
DCg,ch
high accuracy. S 22 shows almost Rch DRg,ch DCch DRch
identical behavior in data and fit-
ting accuracy. Plots in the Smith Lg Rg DCg,ch
DRch
DCch
chart showing also the imaginary G DRg,ch
part are omitted for clearer visibil-
ity. Extracted element values are DCg,ch
DRg,ch DCch DRch
listed in Table 1.
Cpd1
As becomes apparent from the Cpg2 Cpg1 Cpd2
Intrinsic DCg,ch
listed values, the extracted gate and Extrinsic
Rg,sub3 Rs Rd,sub1 Rd,sub3
drain pad capacitances C pg1 and Rg,sub1
C pd1 follow the expected behavior Ls Rd,sub2
Rg,sub2
in terms of the relative dielectric
constants f r of the various materi-
S
als involved (SiC: 9.7, Si: 11.9, InP:
12.4). This confirms the dominance Figure 6. Small-signal equivalent cold-FET circuit including gate and drain pad
of the pad layout geometry on the capacitance networks. The intrinsic partition is set up following the proposed model
extrinsic pad capacitance as stated of Jeon et al. [36].

June 2013 89
 Extrinsic Resistance and describing the cold-FET in any gate bias condition can
Inductances Extraction be described in means of Z-parameters as derived by
After subtracting the determined extrinsic capacitance Jeon et al. in [36] by (7)(9):
networks from the measured data in Y-parameter for-
mat according to (15), the measured data is transformed
R ch
to the Z-parameter format. Z 12 = Z 21 = R s + b 2
+
1 + ~ 2 C ch R2
Extrinsic element extraction is carried out following 1 4 44 2 4 44ch3
Term Re" Rch ,
the proposed cold-FET model of Jeon et al. [36], which 2 (7)
f R2 p
R ch C ch
uses a distributed approach to accurately describe the + j~ L s - b 2
,
1 + ~ 2 C ch
intrinsic channel and barrier regions, as illustrated in 1 4 44 2 4 44ch3
Term Im" Rch ,
the intrinsic part of Figure 6. R ch
In contrast to Jeons approach, we have not neglected Z 22 = R s + R d + 2
+
1 + ~ 2 C ch R2
the gate and drain pad capacitances, and after their 1 4 44 2 4 44ch3
Term Re" Rch ,
subtraction as described in the previous section, we 2 (8)
f R2 p
R ch C ch
+ j~ L s + L d - ,
extract the extrinsic elements above pinch-off for mul- 2
1 + ~ 2 C ch
1 4 44 2 4 44ch3
tiple Vgs. The equivalent circuit network capable of Term Im" Rch ,

R ch
Z 11 = R s + R g + a
1 + ~ 2 C 2ch R 2ch
1 4 44 2 4 44 3
Term Re" R ch ,
18
16 R g, ch
+ .
14 1 + ~ 2 C 2g, ch R 2g, ch
1 4 4 44 2 4 4 44 3
Term Re" R g,ch ,
12
Re(Z22) (X)

J C ch R 2ch N (9)
10 KL g + L s - a 2 2 2 O
K 1+~ C R
8 1 4 44 2 4ch44ch3O
K Term Im" R ch , O
6 + j~ K 2 O
K - C g, ch R g, ch O
4
K 1 + ~ 2 C 2g, ch R 2g, ch O
2 K 1 4 4 44 2 4 4 44 3 O
L Term Im" R g,ch , P
0
0 0.25 0.5 0.75 1 1.25 1.5
1/(Vgs - Vth) (V-1)
In the following subsections we present the rigor-
AlInAs/GaInAs/InP (Vgs = 0.6...1.0 V) ous determination of all individual element values.
GaN/Si (111) (Vgs = -0.5...-0.05 V)
GaN/Si (111) (Vgs = 0...2 V) Rch: Channel Resistance
Following the approach of Hower and Bechtel [6], and
including the modifications proposed by Berroth and
Figure 7. Determination of R s + R d from the real part Bosch [11], we determine the sum of Rs and Rd by plot-
of Z22 versus 1/(Vgs Vth) of 2 # 0.1 # 50 n m2 AlInAs/ ting the real part of Z22 at low frequencies (< 2 GHz)
GaInAs/InP HEMT and 2 # 0.1 # 50 n m2 GaN on
versus 1/ (Vgs - Vth), as shown in Figure 7.
Si(111) HEMT.
Interestingly, the real part Z 22 for the GaN device
shows a frequency independent discontinuous behav-
ior at Vgs = 0 V. Extractions for the sum of R s and Rd
6 carried out for negative Vgs yield 14.53 , while positive
AlInAs/ Vgs values yield 14.59 , respectively. Therefore, Rs + Rd
5
GaInAs/InP
GaN/Si (111)
is independent of the range chosen for extraction and
4
may be determined for gate voltages below 0 V. Values
Rch (X)

3 of Rs + Rd extracted for the AlInAs/GaInAs/InP HEMT

yield 3.67 X .
2
Inspection of the real part of Z 22 reveals that the
1 term Re{Rch} in (8) simplifies to Rch for low frequen-
cies. Making use of this relation and the previously
0
-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 determined sum of Rs and Rd, we calculate the chan-
Vgs (V) nel resistance Rch versus gate voltage for both device
types, as plotted in Figure 8.
Figure 8. Rch versus Vgs for 2 # 0.1 # 50 n m2 AlInAs/ The discontinuity at 0 V for the GaN-based HEMT is
GaInAs/InP HEMT and 2 # 0.1 # 50 n m2 GaN on a direct consequence of the discontinuous behavior of the
Si(111) HEMT. Z22 real part. This so far unreported behavior is considered

90 June 2013
to be trap/defect related, and potentially
induced by processing steps. Physical b
plausibility checks based on measured 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
10 2.5
sheet resistances and device/gate dimen- AlInAs/GaInAs/
vRs AlInAs/GaInAs/InP
sions yield a channel resistance of 0.64 X InP
8 GaN/Si (111) 2.0
for the GaN device (640 X/) and 0.27 X vR GaN/Si (111)
s b
for the InP device (273 X/), and are thus
in good agreement with the extracted 6 1.5

vRs (X)
Rs (X)
Rch values.
4 1.0
b, Rs, and Rd: Resistances
Mak i nguseoft heprev iously b
2 0.5
described term Re{Rch} relation in (7),
wedetermineR sindependenceof
b which should be considered a con- 0 0
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
stantwhichreflectsthedistributed
Vgs (V)
RC network underneath the gate into
account. We determine b here by sweep-
ing its value between zero and one, and Figure 9. Extrinsic source resistance versus gate voltage Vgs versus b
selecting the value which achieves a of 2 # 0.1 # 50 nm 2 AlInAs/GaInAs/InP and 2 # 0.1 # 50 nm 2 GaN
on Si(111) HEMT. The b value is selected to provide the flattest R s
maximally flat behavior of Rs versus gate
characteristic as a function of the gate voltage, using the standard deviation
voltage Vgs, as shown in Figure 9.
of R s as the deciding criterion.
A good criterion to judge the flat-
ness of the behavior is found to be the
standard deviation of Rs. Thus, b is
selected as the value when the stan- 4.0 8
dard deviation of Rs reaches its mini-
3.5 7
Rs, Rd AlInAs/GaInAs/InP (X)

mum, yielding 0.499 and 0.462 for the

Rs, Rd GaN/Si (111) (X)

AlInAs/GaInAs/InP and the GaN/ 3.0 6
Si(111) HEMTs, respectively. While the 2.5 5
value of b for the AlInAs/GaInAs/InP
HEMT agrees perfectly with the con- 2.0 4

ventionally used value of 0.5 [10], [20], 1.5 R s AlInAs/GaInAs/InP 3

[36], [39], the value of b for the GaN/ Rd AlInAs/GaInAs/InP
1.0 2
Si(111) is slightly lower, but still well Rs GaN/Si (111)
within the range of reported values for 0.5 Rd GaN/Si (111) 1
b ranging down to 0.41 as in the work 0.0 0
of Jeon et al. in [36]. These results indi- -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
cate that depending on the device type Vgs (V)
and processing parameters, b should
not simply be set to 0.5, but can rather Figure 10. Extracted source and drain resistance values Rs and Rd versus gate
be accurately determined during the voltage of 2 # 0.1 # 50 nm 2 AlInAs/GaInAs/InP and 2 # 0.1 # 50 nm 2
extraction process. GaN on Si(111) HEMT.
Having determined b and Rs, Rd can
now be calculated as a function of the gate voltage, from eter to fit here, since Rs, Rd, and Rch have already been
the real part of (7) and (8), yielding the results as plotted determined. This is particularly important because
in Figure 10. trying to simultaneously fit all the above-mentioned
variables can yield to an apparent tenfold increase
Cch: Channel Capacitance in channel resistance (which is most likely not physi-
As pointed out by Crupi et al. [38] and by Brady et al. cally based). The resulting channel capacitances ver-
[39], the channel capacitance is generally not negligi- sus gate voltage of the cold-FET biased HEMTs are
ble, and under certain cold-FET bias conditions, it can plotted in Figure 11.
become particularly high. In order to determine Cch we Comparing both plotted channel capacitances it is
make use of the dispersive behavior in the real part of interesting to note that the GaN/Si(111) device again
Z 22 that is dominated by the interaction with the chan- shows a discontinuous behavior at Vgs = 0 V. This
nel resistance. In contrast to the approach of Brady et time the step is in the opposite direction compared to
al. [39], the channel capacitance Cch is the only param- the channel resistance Rch. While the capacitance of

June 2013 91
 the GaN device sets on a lot earlier it increases almost
5.0 linearly and is quickly overtaken by the quadratic
4.5 increase of the InP device, once Vgs is increased by a
4.0 AlInAs/GaInAs/InP
GaN/Si (111)
few hundred millivolts above threshold. The influence
3.5 of Cch on the extraction error is discussed in detail in
3.0
Cch (pF)

the Cch Dependent Error Analysis section.

2.5
2.0
1.5 Ls, Ld: Inductances
1.0 After calculating the bias-dependent term Im{Rch} in
0.5 (7) and (8), and removing their contributions from the
0 imaginary parts of Z 12 in (7) and Z 22 in (8), Ls and Ld are
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
determined from the slope of the remaining imaginary
Vgs (V)
parts. Preceding multiplication of Z 12 and Z 22 imagi-
nary parts with ~, and the evaluation towards higher
Figure 11. Cch versus Vgs for 2 # 0.1 # 50 nm 2 AlInAs/ frequencies help to reduce frequency dependence
GaInAs/InP HEMT and 2 # 0.1 # 50 nm 2 GaN on
due to capacitive effects and/or incomplete capacitive
Si(111) HEMT.
deembedding. The resulting source and drain extrinsic
inductance values for both HEMT types
are plotted in Figure 12. As expected, the
10 60 extracted inductances are largely bias
Ls AlInAs/GaInAs/InP independent above threshold.
8 Ld AlInAs/GaInAs/InP 55
Ls GaN/Si (111) Cg, ch, Lg: Schottky Barrier
6 Ld GaN/Si (111) 50 Capacitance and Gate Inductance
Ld (pH)
Ls (pH)

The imaginary part of Z 11 in (9) reveals

that three unknown variables a, C g, ch and
4 45
Rg, ch are involved in the determination of
the extrinsic gate inductance L g . While a
2 40 is conventionally set to 1/3 [10], [20], [36],
[39], the maximum contribution of the a #
0 35 Term Im{Rch} in (9) to the imaginary part
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 of Z 11 is found to be in the range of 0.1%.
Vgs (V) Due to its negligible contribution, we use
the conventionally set value of 1/3 and
Figure 12. Extracted inductance values of Ls and Ld versus gate voltage of determine the optimal value of a later on.
2 # 0.1 # 50 nm 2 AlInAs/GaInAs/InP and 2 # 0.1 # 50 nm 2 GaN on The fitting equation can therefore be sum-
Si(111) HEMT. marized as (10), which yields Lg, c1 and c2

2
~^L g + L sh -
1 $ ~C ch R ch
3 1 + ~ 2 C 2ch R 2ch
60 100 (10)
- ~c 1 2 0 1m ^ Z 11h .
1 + c2 ~
55 80

Fitting coefficients c1 and c2 are solved

50 60 for the Schottky barrier capacitance Cg, ch.
Cg,ch (fF)
Lg (pH)

Due to the strong decrease of the real part

45 40 of Z11, as shown in [20, Fig. 3(a)], it is dif-
Lg AlInAs/GaInAs/InP
ficult to accurately extract the Schottky
Cg,ch AlInAs/GaInAs/InP
40 20 barrier resistance Rg, ch using fitting proce-
Lg GaN/Si (111)
dures. Therefore Rg, ch is extracted with a
Cg,ch GaN/Si (111)
different method explained in the follow-
35 0
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 ing subsection. Extracted gate inductance
Vgs (V) values and Schottky barrier capacitance
values versus gate voltage are plotted
Figure 13. Extracted gate inductance Lg and gate-channel capacitance inFigure13.Asanticipated,thegate
Cg,ch values versus gate voltage of 2 # 0.1 # 50 nm 2 AlInAs/GaInAs/InP inductance is largely independent of bias
and 2 # 0.1 # 75 nm 2 GaN on Si(111) HEMT. above threshold.

92 June 2013
Rg, ch: Schottky Barrier Resistance ditions of the gate, as the dc-results only in that region
The strong decrease in the real part of Z 11, as shown in coincide with the RF-extracted results.
[20, Fig. 3(a)], leads to difficulties in accurately extract-
ing the Schottky barrier resistance Rg, ch with fitting a, R g: Gate Resistance
algorithms. We therefore exploit the following charac- Similar to the approach for determining b , we make
teristic of the real part of Z 11 summarized in (11): use of the bias independence of the extrinsic gate
resistance Rg in (9). In order to determine a, it is swept
R g, ch
0e ^Z 11h - a
R ch between zero and one, and its final value selected
2 2
- 0 const.
1 + ~ 2 C ch R ch 1 + ~ 2 C 2g,ch R 2g, ch as the one yielding a maximally flat behavior of Rg
(11) 1 4 44 2 4 44 3 1 4 4 44 2 4 4 44 3
Term Re" R ch , Term Re" R g, ch , versus gate voltage. This approach simultaneously
yields the values of the extrinsic gate resistance Rg as
Because the maximum contribution of the a # Term plotted in Figure 16.
Re{Rch} to the real part of Z 11 can be estimated to be
less than 2%, we can initially use the conventional
value of a = 1/3. All other variables in (11) except Rg,
ch have previously been determined. Making use of its
10
definition, we sweep Rg, ch and monitor the behavior

Re (Z11) - a Term Re {Rch} -

Rg,ch = 18.7 kX
versus frequency as illustrated in Figure 14. 5

Term Re {Rg,ch} (X)

The value of Rg, ch yielding a maximally flat behavior
0
of (11) versus frequency is then selected as the Schottky
barrier resistance. A good criterion to judge the flat- -5
behavior is again found to be the standard deviation
-10
over the frequency range. Thus Rg, ch is selected as the
value when the standard deviation of (11) reaches its -15
minimum. The resulting Schottky barrier resistances
-20
for both HEMT types and their gate currents are plotted 10 15 20 25 30 35 40
versus gate voltage in Figure 15 and denoted Rg, ch, extr. Frequency (GHz)
Interestingly, the RF-extracted Schottky barrier
resistance of the AlInAs/GaInAs/InP HEMT is found Figure 14. Representative sweep of Rg, ch from 0.1 k
to be three times higher compared to the GaN on Si(111) to 100 k in 0.1 k steps until expression (11) becomes
HEMT. Due to the lower forward gate current of the maximally constant versus frequency, yielding the desired
GaN device this behavior is contrary to the expected value of Rg, ch.
behavior when determining the barrier
resistance from the gate current, as is com-
monly done according to (12)
25 4.5
nk B T 4.0
R g, ch, calc = , (12)
qI g 20 3.5
3.0
where n is the gate diode ideality factor, k B
Igs (mA/mm)
Rg,ch (kX)

15 2.5
the Boltzmann constant, T the device tem- 2.0
perature in Kelvin, q the electron charge,
10 1.5
and Ig the gate current. We believe that
1.0
the reasons can be attributed to bulk and
5 0.5
surface defects present in all GaN devices
as stated by Morko [49]. Another reason 0.0
responsible for lowering the RF-barrier 0 -0.5
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
resistance compared to the dc-extraction
Vgs (V)
may be the presence of interfacial lay-
ers at the gate-semiconductor junction as Rg,ch, extr AlInAs/GaInAs/InP Rg,ch, extr GaN/Si (111)
described by Wang et al. in [50] or Rohdin et Rg,ch, calc AlInAs/GaInAs/InP Rg,ch, calc GaN/Si (111)
al. in [51]. The behavior differences shown Igs AlInAs/GaInAs/InP Igs GaN/Si (111)
in Figure 15 for the dc and RF-extraction
results only begin to disappear for very
strong forward biasing of the gate. This Figure 15. Schottky barrier resistance Rg, ch versus gate voltage and gate
behavior proves the dc-extraction approach current of 2 # 0.1 # 50 nm 2 AlInAs/GaInAs/InP and 2 # 0.1 # 50 nm 2
only valid for very strong forward bias con- GaN on Si(111) HEMT.

June 2013 93
In contrast to Jeons approach, we 15.0
have not neglected the gate and Rg,dc = 155 X/mm
12.5
drain pad capacitances, and after

Gate Resistance (X)

10.0
their subtraction, we extract the
extrinsic elements above pinch-off 7.5

for multiple Vgs. 5.0

2.5

Selecting a as the value producing minimum stan- 0

0 25 50 75 100 125 150
dard deviation of Rg yields values of 0.22 and 0.26 for Gate Width (nm)
the AlInAs/GaInAs/InP and the GaN/Si(111) HEMTs,
respectively. Both values slightly deviate from the con- Figure 17. Measured end-to-end T-gate resistance values
ventionally used value of 1/3 [10], [20], [36], [39], but they of 100-nm foot length, 200-nm foot height, 500-nm head
are comparable to the value of 0.2 for a as determined length and 400-nm head height passivated dual gate process
in the work of Jeon et al. in [36]. Figure 16 also illus- monitor structures yielding 155 /mm for the AlInAs/
trates the increase in unevenness of Rg towards large GaInAs/InP device.
Vgs, or increasing gate current. From Figure 15 and (9),
it becomes apparent that the rapidly dropping Schottky safe for devices but it also ensures more accurate extrac-
barrier resistance is responsible for this behavior as all tion results.
other variables in the real part of Z11 remain constant Because of the electrical similarity of the extrinsic
over this bias range. Thus the appropriate bias range resistance Rg and the intrinsic resistance Rgs, it is dif-
to choose is the bias regime before the Schottky bar- ficult to accurately separate the unique individual val-
rier resistance begins to significantly drop (Figure 15). ues, as discussed by Patterson et al. [52]. In order to
As the drop in the Schottky barrier resistance coin- obtain a more reliable value for Rg, we therefore also
cides with the increase in gate current, the optimum carried out dc end-to-end measurements, as suggested
bias regime can already be chosen during the mea- by Chen and Kumar in [53]. Following this approach,
surement. For the present devices, this regime corre- and extending it by the number of parallel gate fingers
sponds to a maximum gate current of 0.25 mA/mm for NF, Rg can be expressed as
both HEMT types. Limiting the maximum gate cur-
rent during measurement not only makes this method l $ Wg
R g = R g, dc $ as long as m & W g . (13)
3 $ NF

With m being the wavelength at maximum

a operating frequency, Wg the width of a sin-
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 gle gate finger, Rg, dc the normalized mea-
10 2.5
AlInAs/GaInAs/ sured end-to-end metallization dc resistance
vRg AlInAs/GaInAs/InP
InP while l accounts for the skin effect over
8 vRg GaN/Si (111) GaN/Si (111) 2.0 the frequency range of interest (l $ 1) . As
shown by Rohdin et al. in [54], the skin effect
6 1.5 only becomes significant above 400 GHz for
vR (X)

a
Rg (X)

T-gates and 150 /mm normalized end-to-

g

end gate metallization resistances. Below

4 1.0
this frequency, l can be set to unity.
a Typical values extracted from our pro-
2 0.5 cess monitors for passivated double gate
structures with 100-nm gate footprints,
0 0 200-nm foot heights, 500-nm head widths
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
and 400-nm head heights are plotted
Vgs (V)
in Figure 17. The inset in Figure 17 shows
the layout of the process monitors used
Figure 16. Extrinsic gate resistance versus gate voltage Vgs versus a of for Rg, dc measurements.
2 # 0.1 # 50 nm 2 AlInAs/GaInAs/InP and 2 # 0.1 # 50 nm 2 GaN Making use of (13) with the measured
on Si(111) HEMT. The a value is selected to provide the flattest Rg dcend-to-endmetallizationresistances
characteristic as a function of the gate voltage, using the standard deviation of 155 X /mm for the 2 # 0.1 # 50 nm 2
of Rg as the deciding criterion. AlInAs/GaInAs/InP HEMT, the calculated

94 June 2013
value of end-to-end Rg results in
Table 2. Extrinsic SSEC elements of a 2 # 50 m AlInAs/GaInAs/InP
1.29 X compared to 1.62 X as
HEMT and a 2 # 50 m GaN/Si (111) HEMT.
extracted using the presented for-
ward bias cold-FET method. This Ls (pH) Ld (pH) Lg (pH) Rs ( X ) Rd ( X ) Rg ( X )
slightly lower value of Rg has been
explained by Rohdin et al. in [54] AlInAs/ 4.36 53.55 50.06 1.65 2.07 1.62 a
GaInAs/ InP
and is referred to as the interfacial
gate resistance as it scales with the AlInAs 3.52 50.99 47.07 0.02 0.27 0.28
contact area of the gate. The inter- 250
passive b
facial gate resistance value for the
AlInAs/GaInAs/InP HEMT results GaN/Si(111) 1.58 46.64 48.84 6.81 7.74 5.02 a
in 0.5 # 108 X -cm2 and is rather low 2 V+1 V
compared to the values described by GaN/Si(111) 1.63 46.73 48.99 6.77 7.77 5.03 a
Rohdin as ranging from 9 # 108 to 2 V+0 V
6 # 106 X -cm2. The differences can GaN/Si(111) 1.50 46.44 48.51 6.89 7.67 5.00 a
most likely be attributed to the use 0 V+1 V
of a platinum to InP Schottky contact GaN/Si(111) 4.07 51.21 46.04 0.01 0.41 0.31
sintered to the AlInAs layer, instead 250
of the direct platinum to AlInAs con- passive b
tact used by Rohdin et al., and to the a
Extracted with forward bias cold-FET method.
b
Values from purely passive approach, making use of the Short dummy structure, as illustrated in Figure 4(b).
different extraction method used to
extract the Rg.
In contrast the 2 # 0.1 # 50
2
nm GaN HEMT on Si(111) with a smaller gate cross from the imaginary parts and the resistances from
section area exhibits a dc end-to-end metallization the real parts of the deembedded short dummy struc-
resistance of 267 /mm resulting in a Rg value of 2.23 ture Z-parameters. The process of deembedding the
X compared to the cold-FET method extracted Rg of short dummy structure Z-parameters is done by
5.03 X . The resulting interfacial gate resistance for preceding subtraction of the open Y-parameters in
the GaN on Si(111) amounts to 2.49 # 10 7 X -cm 2. Y-parameter notation with subsequent transformation
In order for Rg to account only for the extrinsic gate into Z-parameters. Comparing these values listed in
metallization, the extractions used in this work exclu- Table 2, it becomes obvious that while the inductances
sively rely on values determined from dc end-to-end still show reasonable values considering the short is
measurements from this point on. not a perfect match of the device the resistances will
only represent the short dummy structure metalliza-
Extrinsic Values tion and completely neglect the contact and access
Table 2 summarizes the extrinsic parameter values resistances present in the devices. For GaN devices
extracted with the method presented above for a 2 # the resulting errors become even larger due to the
50 nm AlInAs/GaInAs/InP HEMT and a 2 # 50 for higher contact resistances. While proving perfectly
nm GaN on Si(111) HEMT.
The extracted values result from averag-
ing a few hundred millivolts above thresh-
old to the gate voltage at which a gate cur- 0.10 1.0
DRd DRd Error
rent of 0.25 mA/mm is reached. For the
AlInAs/GaInAs/InP HEMT, this range 0.08 DRs DRs Error 0.8
DRg Error
DRd, DRs, DRg (X)

spans 0.250.75 V; for the GaN HEMT on Si DRg

(111), the range extends from -2 V to +1 V. 0.06 0.6
Error (%)

For comparison, we also report the values

extracted using only positive gate voltages in 0.04 0.4
the range from 0 V to +1 V, and only nega-
tive voltages from -2 V to 0 V. With Table 1,
0.02 0.2
all extrinsic elements used in the Extraction
of Small-Signal Equivalent Circuit Extrinsic
0 0
Elements section are now known. There is -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
little sensitivity to the bias range. Vgs (V)
In order to compare to the commonly
used purely passive method, we addi- Figure 18. Extrinsic resistance differences and errors made by neglecting
tionally extracted the inductance values Cch versus gate voltage Vgs of 2 # 0.1 # 50 nm 2 GaN on Si(111) HEMT.

June 2013 95
 suitable for removing the effects of the
2.5 50 pads this method is not suitable for
DLd Ld Error removing extrinsic device components
2.0 DLs Ls Error 40 and subsequent determination of the
DLd, DLs, DLg (pH) DLg Lg Error intrinsic values.
1.5 30

Error (%)
Cch Dependent Error Analysis
Because of the high electron sheet densi-
1.0 20
ties in GaN channels, the channel capaci-
tance Cch has been suggested to have a sig-
0.5 10 nificant impact on the extraction process,
as stated in the works of Crupi et al. [38]
0 0 and Brady et al. [39]. The effect of channel
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
capacitance can now be explicitly deter-
Vgs (V)
mined by setting Cch to zero in the extrac-
tion and comparing to the previously
Figure 19. Extrinsic inductance differences and errors made by neglecting Cch determined extrinsic element values.
versus gate voltage Vgs of 2 # 0.1 # 50 nm 2 GaN on Si(111) HEMT.
Figure 18 plots the maximum extrin-
sic resistance difference resulting from
the channel capacitance of the GaN on
0.16 4.0 Si(111) device to the left and the result-
0.14 DRd DRd Error 3.5 ing relative error to the right Y-axis. In
DRs DRs Error contrast to the inductance difference the
0.12 3.0 resistance differences as well as the errors
DRd, DRs, DRg (X)

DRg DRg Error

0.1 2.5 remain stable over a wide gate bias range.
Error (%) In the region of interest, resistance differ-
0.08 2.0
ence values remain below 0.07 and the
0.06 1.5 respective errors below 0.7 %.
0.04 1.0
Figure 19 plots the maximum extrin-
sic inductance difference resulting from
0.02 0.5 the channel capacitance of the GaN on
0 0 Si(111) device to the left, and the result-
-0.25 0 0.25 0.5 0.75 1 ing relative error to the right Y-axis.
Vgs (V) Inductance difference as well as error
decrease with increasing forward bias.
Figure 20. Extrinsic resistance differences and errors made by neglecting Cch While the drain and gate inductance
versus gate voltage Vgs of 2 # 0.1 # 50 nm 2 AlInAs/GaInAs/InP HEMT. errors stabilize in the range of 0.53%,
the source inductance error reaches a
minimum around 25%.
Figure 20 plots the maximum extrin-
2.5 50
sic resistance difference resulting from
DLd Ld Error
the channel capacitance of the AlInAs/
2.0 DLs Ls Error 40 GaInAs/InP device to the left, and
DLg Lg Error the resulting relative error to the right
DLd, DLs, DLg (pH)

1.5 30 Y-axis. In the region of interest, resis-

Error (%)

tance difference values remain below

0.14 and the errors below 3.5 %.
1.0 20
Figure 21 plots the maximum extrin-
sic inductance difference resulting from
0.5 10 the channel capacitance of the AlInAs/
GaInAs/InP HEMT to the left and
the resulting relative error to the right
0 0
-0.25 0 0.25 0.5 0.75 1 Y-axis. Similar to the GaN device, the
Vgs (V) largest error is attributed to the source
inductance while the largest inductance
Figure 21. Extrinsic resistance differences and errors made by neglecting Cch difference is found with the drain induc-
versus gate voltage Vgs of 2 # 0.1 # 50 nm 2 AlInAs/GaInAs/InP HEMT. tance. The drain and gate inductance

96 June 2013
errors stabilize in the range of 0.23%, whereas the The four most commonly used
source inductance error reaches a minimum between
7 and 15%. methods to determine the intrinsic
Comparing the errors made by neglecting Cch element values versus frequency are
between the AlInAs/GaInAs/InP and the GaN/Si(111) due to Dambrine [10], Berroth [11]
devices, we observe that the errors are comparable. It can
be concluded that it is just as important to consider the [13], and Rorsman [18].
channel capacitance for non-GaN devices.
signal current gain (h21) and stability factor (k). Equa-
Small-Signal Equivalent Circuit tions from [18] yield:
Extraction of Intrinsic Elements
C gd = 1
~1m ^ Y 12 h
-1
Subtraction of the Extrinsic Elements
Once the extrinsic elements are determined accord- C gs = -1
~1m c m
ing to the Extraction of Small-Signal Equivalent Cir- 1
Y11 + Y12
cuit Extrinsic Elements section, they can be removed
1m ^Y12 + Y22 h
from the measured S-parameters according to (14) C ds =
~
(17) resulting in the intrinsic Y-parameters. The
obtained intrinsic Y-parameters are the basis for the R gs = 0e c 1
m
Y11 + Y12
further calculation of the intrinsic element values.
R ds = 1
0e ^Y12 + Y22 h
; E
S 11,meas S 12,meas

S 21,meas S 22,meas ^Y12 - Y21 h^Y11 + Y12 h
gm =
1m ^Y11 + Y12 h
0 S " Y (14) r
- phase ^Y12 - Y21 h
R V 2
SY11.meas - j~C pg1 W
x=
- ~
1 + j~C pg1 R g,sub1 + phase ^Y11 + Y12 h
S W
S Y12,meas W
j~C pg2 1
S - W
S1+ j~C pg2 R g,sub2 R g,sub3 W
S j~C pd1 W R gd = - 0e c 1 m . (18)
S Y22,meas- -W Y12
S 1 + j~C pd1 R d,sub1 W
S Y21,meas W
j~C pd2
SS - 1 W Intrinsic elements extracted according to the model
1 + j~C pd2 R d,sub2 R d,sub3 W
T X of Rorsman for a 2 # 0.1 # 50 nm 2 AlInAs/GaInAs/InP
0 Y " Z (15) HEMT biased at Vds = 0.5 V and I ds = 15 mA are pre-
sented in Figure 22.
Figure 23 displays the intrinsic elements extracted
Z 11 - R s - R g - j~ ^L s + L g h
= G
Z 12 - R s - j~L s according to the model of Rorsman for 2 # a 0.1 # 50 nm 2
Z 21 - R s - j~L s Z 22 - R s - R d - j~ ^L s + L d h

0 Z " Y (16)
140 1.6

; E .(17)
Y11,intr Y12,intr
120 Cgs Rgs 1.4
Y21,intr Y22,intr
Cgs, Cds, Cgd, (fF), gm (mS),

100 Cds Rds 1.2

Cgd Rgd
Rds, Rgs, Rgd (X)

The four most commonly used 80 1.0

x (ps)

gm x
methods to determine the intrinsic 60 0.8
element values versus frequency are
40 0.6
due to Dambrine [10], Berroth [11]
[13], and Rorsman [18]. For the subse- 20 0.4
quent extraction, we have applied the 0 0.2
model of Rorsman because it includes
-20 0
the intrinsic resistance Rgd in order 0 5 10 15 20 25 30 35 40
to account for the nonzero real part Frequency (GHz)
of Y12, and thus improves the model-
to-measurement degree of agreement Figure 22. Calculated intrinsic element values according to Rorsman [18] for
of the maximum stable gain (MSG), a 2 # 0.1 # 50 nm 2 AlInAs/GaInAs/InP HEMT biased at Vds = 0.5 V and
maximum available gain (MAG), small Ids = 15 mA.

June 2013 97
 Table 3. Intrinsic SSEC elements of 2 # 50 m HEMTs.

Cgd (fF) Cgs (fF) Cds (fF) Rgs ( X ) Rds ( X ) Rgd ( X ) gm (mS) x (ps) vsat (cm/ n s) dgc (nm)

AlInAs/ 16.6 58.9 39.6 0.6 62 22.4 123.3 0.17 25 c 21 d

GaInAs/
InP a
GaN/Si 10.7 49.7 24.4 1.6 175 68.5 44.3 0.25 10 c 23 d
(111) b
a
Example extraction of 2 # 0.1 # 50 nm2 AlInAs/GaInAs/InP HEMT biased at Vds = 0.5 V and Ids = 1.5 mA.
b
E xample extraction of 2 # 0.1 # 50 nm2 GaN on Si(111) HEMT biased at Vds = 0.5 V and Vds = -2.25 V.
c
Determined according to method of Enoki et al. in [55].
d
Effective gate to channel distance n as specified by epi-manufacturer: + 220 nm for the AlInAs/GaInAs/InP and + 22nm for the GaN/Si devices.

GaN on Si(111) HEMT biased at

200 2.2 Vds = 5 V and Vgs = 2.25 V.
180 2.0 Most of the parameters are
160 1.8 stable over significant portions
Cgs, Cds, Cgd, (fF), gm (mS),

Cgs Rgs
140 1.6 of the measurement frequency
Cds Rds
Rds, Rgs, Rgd (X)

120 1.4 range. After averaging the

Cgd Rgd
100 1.2 resulting intrinsic values over

x (ps)
gm x
80 1.0 the frequency range in which
60 0.8 they are most constant we obtain
40 0.6 a set of frequency independent
20 0.4 intrinsic SSEC element values as
0 0.2 listed in Table 3.
-20 0.0
0 5 10 15 20 25 30 35 40
Intrinsic Element
Frequency (GHz)
Optimization
The extracted intrinsic SSEC ele-
Figure 23. Calculated intrinsic element values according to Rorsman [18] for a 2 #
ment values produced by aver-
0.1 # 50 nm 2 GaN/Si(111) HEMT biased at Vds = 5 V and Vgs =-2.25 V.
aging over frequency prove
stable and already quite precise.
Because it is tedious to choose
90 4 the optimum frequency range
120 60 for achieving the best possible
3 fit, we implemented a modified
S12 of GaN on Si(111)
S21 of GaN on Si(111) downhill simplex algorithm to
150 2 Calculated Elements minimize an objective function
Optimized Elements and find the optimum SSEC
intrinsic values.
1
# 20 Our procedure considers the
extrinsic SSEC element values
0.2

0.5

1.0

2.0

5.0

0.0 3 fixed because they have been

determined by independent
S11 of GaN on Si(111) measurements and averaged
S22 of GaN on Si(111) over several bias points, lead-
Calculated Elements
- j5.0 ing to very stable values. This
Optimized Elements
leaves only the intrinsic val-
ues for optimization and limits
the number of variables to be
- j0.5 - j2.0 optimized. Additionally, the
risk of trapping in local optima
- j1.0 and the probability of con-
verging to nonphysical model
Figure 24. Measured, calculated and optimized S11, S22, S12, and S21 of 2 # 0.1 # 50 nm 2 parameters are reduced when
GaN on Si(111) HEMT biased at Vgs = -2.25 V and Vds = 5 V from 140 GHz. fewer elements are considered

98 June 2013
 Table 4. Calculated and optimized intrinsic SSEC elements.

Cgd (fF) Cgs (fF) Cds (fF) Rgs ( X ) Rds ( X ) Rgd ( X ) gm (mS) x (ps)

AlInAs/ GaInAs calculateda 16.6 58.9 39.6 0.6 62.1 22.4 123.3 0.17
AlInAs/ GaInAs optimizeda 16.3 58.2 39.8 0.0 61.2 19.3 125.0 0.01
b
GaN/ Si (111) calculated 10.7 49.7 24.4 1.6 175 68.5 44.3 0.25
GaN/ Si (111) optimizedb 10.7 49.4 24.3 1.7 172 66.7 44.6 0.26
a 2
Example extraction of 2 # 0.1 # 50 nm AlInAs/GaInAs/InP HEMT biased at Vds = 0.5 V and Ids = 1.5 mA.
b
E xample extraction of 2 # 0.1 # 50 nm2 GaN on Si(111) HEMT biased at Vds = 0.5 V and Vgs = 0.5 V.

in the optimization process

[30], [52]. 90
6
The principal procedure is
120 60
based on removing the extrin-
sic parameters from the mea- 4
sured data as described in
S12 of AlInAs/GaInAs/InP
the Small-Signal Equivalent 150 S21 AlInAs/GaInAs/InP
Circuit Extraction of Intrinsic Calculated Elements
Elements section and com- 2
Optimized Elements
paring the resulting mea-
sured intrinsic S-parameters # 20
0.2

0.5

1.0

2.0

5.0
with the calculated intrinsic 0.0 3
S-parameters of the SSEC
S11 of AlInAs/GaInAs/InP
intrinsic model. In order to
S22 AlInAs/GaInAs/InP
further prevent trapping into Calculated Elements
a local minimum, care is Optimized Elements - j5.0
taken in setting up the objec-
tive function to minimize the
nonlinear and multidimen-
sional optimization problem.
The final objective function, - j0.5 - j2.0
yielding a single scalar value,
- j1.0
is set up of multiple compo-
nents, chosen to allow the
2
final elements to reproduce Figure 25. Measured, calculated and optimized S11, S22, S12, and S21 of 2 # 0.1 # 50 nm
the measured device behav- AlInAs/GaInAs/InP HEMT biased at Vds = 0.5 V and Ids = 15 mA from 1 to 40 GHz.
ior as exact as possible. It con-
sists of the S-parameter errors denoted in (19) as the intersection with the logarithmically scaled fre-
quency axis:
N
DS ij = / S intr,
ij, n
meas
- S intr,calc
ij, n
n=1 DfT = f Tintr,meas - f Tintr,calc . (21)
i, j = 1 , 2 ; n = 1, 2, f, N. (19)
The fourth part presented in (22) is the MSG error:
where N is the total number of frequency data points.
N
The second contribution to the objective function is the
small signal current gain error enabling precise cut-off
DMSG = / MSG intr,meas
n - MSG intr,calc
n
n=1
frequency extractions and presented in (20): n = 1, 2, f, N. (22)

N Additional weighting of important contributors

DH 21 = / H intr,meas
21, n - H intr,calc
21, n n = 1, 2, f, N .(20) emphasizes their importance by favoring their mini-
n =1
mization. The sum of these weighted components
forms the final objective function as formulated in (23):
The third part is the error in cut-off frequency
extraction determined by fitting a line with 20 dB f total = DS 11 + DS 12 + 5 $ DS 21 + DS 22

slope to the small-signal current gain and calculating + DH 21 + 10 $ DfT + DMSG. (23)

June 2013 99
 A detailed comparison of the calculated and opti-
mized intrinsic parameters is listed in Table 4.
Comparing the S-parameter error resulting from
the calculated and the optimized intrinsic element val-
ues according to the error defined in (24):
N
intr,calc 2
2
/ intr,meas
S ij, n - S ij, n
Error = 100 $ / n=1
N
i, j = 1
/ intr,meas 2
S ij, n
n=1
i, j = 1, 2 n = 1, 2, f, N,
yields an error decrease from 2.8% to 2.5% for the AlI-
nAs/GaInAs/InP HEMT and 1.8% to 1.7% for the GaN
on Si(111) HEMT.
The small element value improvements the opti-
mizer is able to achieve confirm the values obtained by
calculation and the chosen frequency ranges for aver-
aging the intrinsic values. Plots comparing the mea-
sured S-parameters with the calculated and optimized
S-parameters demonstrate the good agreement of the
extracted values for both the GaN on Si(111) in Figure24
as well as the AlInAs/GaInAs on InP HEMT in Fig-
ure25. Especially for the leaky GaN on Si(111) substrate
the extrinsic capacitance network shows its advantages
in modeling the behavior of S11 and S22 very precisely.
Conclusion
A detailed review of the HEMT SSEC models was
given. A new extrinsic SSEC was then introduced
to properly describe pad capacitances on various
substrates and buffer materials, regardless of their
residual conductivity. The new model was then com-
pared to the classic methods of Dambrine et al. [10]
and White and Healy [17], both of which make use of
the cold-FET pinch-off conditions, and its advantages
were pointed out. We also presented a robust, accu-
rate, rigorous, nondestructive method for determining
the remaining extrinsic elements. A straightforward
method was next presented to reliably extract the
Schottky barrier resistance Rg, ch as well as the distrib-
uted channel parameters a and b which prove to be
device/technology dependent. The difference between
end-to-end dc and the forward bias cold-FET method
for the determination of the extrinsic gate resistance
Rg was examined. Additionally, this work provided the
first assessment of the errors caused when neglecting
the cold-FET channel capacitance. The full SSEC model
extraction was then demonstrated at typical bias points
for 2 # 0.1 # 50 nm2 AlInAs/GaInAs HEMTs and GaN
HEMTs on Si(111).
Finally, we have verified that a further numerical
optimization of the extracted intrinsic element val-
ues only leads to a slight improvement of the fit to
experimental S-parameter data, confirming the accu-
racy and robustness of the approach described in the
present article.
100 June 2013
Acknowledgments
The authors must first and foremost thank Dr. Hans
Rohdin from Avago Technologies for his extensive edi-
torial comments in the preparation of this manuscript.
We also acknowledge the ETH Zurich FIRST Labora-
tory personnel for its support in device fabrication, and
Hansruedi Benedickter for measurement assistance.
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