UNIT I

PART A
1. Define a Digital systems?
Electronic system is most reliable when designed for two state operation and this
binary system is said to be use of in digital system.
2.What is a Decimal Number system?
A Decimal Number system has a radix (or) (Base, r=10) and uses symbol 0,19.
(Eg) : (237)10
3.Give the Algorithm to perform subtraction using rs complement?
The subtraction of two positive numbers (M-N) both of base r may be done as follows :
1. Add the number M to the rs complement of the Number N.
2. Inspect the result obtained in step 1 for and end carry.
3. It end carry occurs discard it.
4. If end carry does not occur, take the rs complement of the number obtained in
step I & place a negative sign in front of it.
4.Define Minterms and Maxterms?
Minterm-It is a standard SOP term which contains all the literals either in
normal from or complement form. (Eg): AB, AB,AB,AB.
Maxterm-It is the standard POS term which contains all the literal either in
normal from or complement form. (eg) : A+B, A+B, A+B, A+B
5.What do you mean by canonical form?
The Representation of Boolean function in SOP or POS from (i.e.) each term in
the expression must contain all the literals of the function either in normal form
or complement form.
6.State Duality principle?
According to principle of duality "Dual of one expression isobtained by replacing
AND (.)withOR(+) and OR with AND togetherwith replacement of 1 with 0 and 0
with 1.
For example: consider the expression A+B=0. The dual of this expression is
obtained by replacing + with . and 0 by 1. i.e., A.B=1 is dual of A+B=0
7.What are the different classification of binary codes?
1. Weighted Code
2. Non Weighted Code
3. Reflective Code
1
 4. Sequential Code
5. Alphanumeric Code
6. Error Detecting and Correcting Code.
8.What is meant by weighted and non-weighted coding?(Nov/Dec 2015)
Weighted codes obey their positional weighting principle. Each bit has position weight.
(Eg) 8421, 2421.
Non weighted binary codes are not positional weighted.
(Eg) : Excess 3 code, Gray code.
9.What is an excess 3 codes?
Excess 3 code the name itself implies it gives the excess 3 if the given decimal
number in binary from. An excess 3 code is obtained by adding 3 with the
original number. Most of the application operation in digital computers.
10.What is cyclic Redundancy check?
The CRC is abit checking method used to detect the data error when
transmitted through the network. The transmitted and received bits are cross
checked.
11.Define Distributive Law?
A(B+C) AB + AC
The distribution law states that ORing several variables and ANDing the result with a single
variable is equivalent to AND ing the result with a single variable with each of the several
variable and them ORing the product.
12.What is gray code?
It is a binary code in which each successive number differs in only one bit
position. It is a non-weighted code and an arithmetic cove.
13.What is Alphanumeric Code?
As most of the computers & their peripherals process both alphabetic and
numeric information several coding techniques have been invented that
represent this alphanumeric information as a series of 1S and 0s. Such codes
are called as Alphanumeric codes.
14.What are Error Detecting codes?
Digital system should be accurate to the digit. So detecting errors are very
important.
The simplest technique for detecting errors is that of adding an extra bit known
as pavity bit. These codes are called a s error detecting codes.
15.What is an Universal Gate? Why?

2
 All Logic gates can be implemented using NAND and NOR gates only. Hence
they are known as universal gates.
16.What is K Map?
An arrangement of cells representing the combination of literals or variable in
the Boolean expression & used for a systematic simplification of the expression.
This K Map method gives us a systematic approach for simplifying a Boolean
expression. This method first proposed by veitch and modified by Karnaugh,
hence it is known as the veitch Diagram or the karnaugh map.
17.What is called as dont care conditions?
In some logic circuits, certain input conditions never occur; therefore the
corresponding output never appears.
In such cases, the output level is not defined; it can be either HIGH or LOW.
These output levels are indicated by X ord in the truth table and are called as
dont care output or dont care conditions or incompletely specified functions.
18.What is called as bit & byte?
Each binary digit in binary system is commonly known as bit.
Each bit is number system makes 1 byte.
19.What is the use of dont care conditions?
A circuit designer is free to make the output for any dont condition either a 0
or a 1 in order to produce the simplest output expression.
It is not always advisable to put dont cases as 1S. It is taken as 0, since it is
not helping anyway to reduce the expression.
It is important to decide which dont cases to change to 0 & which to 1 to
produce the best K-map grouping.
20.State Demorgans theorem?
Demorgan suggested 2 theorems. That form an important part of Boolean Algebra.
They are.

1. AB = A+B => The complement of a product is equal to the sum of the complements.
2. A+B = A B => The complement of a sum is equal to the product of the
complements.
21.Write the abbreviation for ASC11 & EBCD1C codes?
1. ASCII => American Standard code for information Interchange
2. EBCD1C => External Binary Code Decimal Interchange code.

3
22.What are the disadvantages of K-Map?(or) What are the limitations of Karnaugh
map?
The Disadvantages of K Map are
1. For more than 4 input variables, K Map is complex to solve.
2. Redundant terms cannot be avoided in Kmap.
23.Encode (2345)10 number in BCD & Excess -3 ?
BCD equivalent:0010 0011 0100 0101
Excess 3 equivalent:0101 0110 0111 1000
24.Covert decimal number 214 to its Octal equivalent?

25.Convert decimal number 35.45 to Octal number.

26.Convert (475.25)8 to its decimal equivalent?

27.Convert (615)8 to its hexadecimal equivalent?

Octal to Binary: 6 /1 / 5
110 /001 / 101
Binary to Hexadecimal:
0001 / 1000 / 1101 => 18D
Ans = 18DH
28.Determine the value of base x, if

4
 (211)x = (152)8
2x2+x+1 = 82x1+5x8+2
2x2+x+1 = 106
2x2+x-105 = 0
(x-7) (2x+15) = 0
x=7
Hence: (211)7 = (152)8
29.Convert the following Number to Decimal.

30.Convert the following Numbers to Hexadecimal NoS.

31.Convert (2101)3 to base 5 Number ?

5
32.Convert decimal no 0.1289062 to its hex equivalent.
0.1289062 x 16 = 2.0625
0.0625 x 16 = 1.0
Ans = (0.21)16
33.Find 2S complement of (10100011)2.
Given No: X = 10100011
1S comp of x = 01011100
+ 1
2S comp : 01011101
34.What ate the advantages of 1S complement subtraction?
1. The 1S complement subtraction can be accomplished with an binary adder.
Therefore this method is useful in arithmetic logic circuits.
2. The 1S complement of a number is easily obtained by inverting each bit in the
number.
35.Given the two binary numbers.
x = 1010100, y = 1000011, perform the subtraction, (a) x-y & (b) y-x using 1S
complement.
a) X-y => 1010100 1000011
X = 1010100
1S comp = 0111100 +
Sum = 10010000
1 +
x-y = 0010001
b) Y-X
Y = 1000011
1S comp of = 0101011 +
1101110
Y-X =>-(1S comp of 1101110) => -0010001

6
36.Given the two binary numbers x = 1010100 y = 1000011, perform the a) x-y b)y-x
using 2S complement.
a) x y
2S comp of y = 0111100
+ 1
0111101
x = 1010100
2S of y = 0111101 +
0010001
Ans = 0010001

b) y x
2S comp of x = 0101011
+ 1
0101100
y = 1000011
2S comp of x = 0101100 +
1101111
y-x => - (2S comp of 1101111)
=> - 0010001
37.subtract 72532 3250 using 10S complement
x = 72532
y = 03250
10S comp of y = 96750
X = 72532
10S comp y = 96750 +
=69282 (Carry in omitted if x>y)
Ans: 69282

38.Subtract using 10S complement of nos: 98 100.

x = 98
y = 100
10S comp of y = 900
x = 98
10S comp of y = 900 +

7
 998
The result is in complemented from
10S comp of 998 is 2. Add negative sign
98 100 => -2
Ans : -2.
39.Subtract (0101)2 from (1011)2
1 01 1
- 0 1 0 1
= 0 1 1 0
40.Simplify the following using De Morgan's theorem [((AB)'C)'' D]'
[((AB)'C)'' D]' = ((AB)'C)'' + D' [(AB)' = A' + B']
= (AB)' C + D'
= (A' + B' )C + D'
41.Reduce A.A'C
A.A'C = 0.C [A.A' = 1]
=0
42.Reduce A(A + B)
A(A + B) = AA + AB
= A(1 + B) [1 + B = 1]
= A.
43.Reduce A'B'C' + A'BC' + A'BC
A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C
= A'C' + A'BC [A + A' = 1]
= A'(C' + BC)
= A'(C' + B) [A + A'B = A + B]

44.Reduce AB + (AC)' + AB'C(AB + C)

AB + (AC)' + AB'C(AB + C) = AB + (AC)' + AAB'BC + AB'CC
= AB + (AC)' + AB'CC [A.A' = 0]
= AB + (AC)' + AB'C [A.A = 1]

8
45.Simplify the following expression Y = (A + B)(A + C' )(B' + C' )
Y = (A + B)(A + C' )(B' + C' )
= (AA' + AC +A'B +BC )(B' + C') [A.A' = 0]
= (AC + A'B + BC)(B' + C' )
= AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC'
= AB'C + A'BC'
46.Show that (X + Y' + XY)( X + Y')(X'Y) = 0
(X + Y' + XY)( X + Y')(X'Y) = (X + Y' + X)(X + Y' )(X' + Y) [A + A'B = A + B]
= (X + Y' )(X + Y' )(X'Y) [A + A = 1]
= (X + Y' )(X'Y) [A.A = 1]
= X.X' + Y'.X'.Y
=0 [A.A' = 0]
47.Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC
ABC + ABC' + AB'C + A'BC=AB(C + C') + AB'C + A'BC
=AB + AB'C + A'BC
=A(B + B'C) + A'BC
=A(B + C) + A'BC
=AB + AC + A'BC
=B(A + C) + AC
=AB + BC + AC
=AB + AC +BC ...proved
48.Convert the given expression in canonical SOP form Y = AC + AB + BC
Y = AC + AB + BC
=AC(B + B' ) + AB(C + C' ) + (A + A')BC
=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC
=ABC + ABC' +AB'C + AB'C' [A + A =1]
9
19.Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x(y'z' + yz).
By applying De-Morgan's theorem.
F1' = (x'yz' + x'y'z)' = (x'yz')'(x'y'z)' = (x + y' + z)(x + y +z')
F2' = [x(y'z' + yz)]' = x' + (y'z' + yz)'
= x' + (y'z')'(yz)'
= x' + (y + z)(y' + z')
50.Simplify the following expression
Y = (A + B) (A + C) (B + C)
= (A A + A C + A B + B C) (B + C)
= (A C + A B + B C) (B + C)
=ABC+ACC+ABB+ABC+BBC+BCC
=ABC
51.Convert A3BH and 2F3H into binary and octal respectively.
A3BH =1010 0011 10112
2F3H =0010111100112 =13638
52.State and prove Idempotent law in Boolean algebra.
i)A+A=A ii)A.A=A
I)A+A=A; if A=1,1+1=1
If A=0,0+0=0
ii)A.A=A ;if A=1,1.1=1
if A=0,0.0=0
53.Define cyclic prime implicant and redundant prime implicants?
When each column in the prime implicant selection chart has two or more dots,
the chart is known as prime implicant.
The prime implicants which are not selected to get the solution are called
redundant prime implicants.
54.Simplify the following expression:
1.ABC+AB+ABC=B(AC+A+AC)
=B(A(C+C)+A)
=B(A+A)
=B(1)=B
2.(X+Y) (X+Y)
XX+XY+XY+YY
X+XY+XY=X+X(Y+Y)
=X+X(1)

10
 =X
55. convert (101101.1101)2 to decimal and hexadecimal form.
Decimal

Ans: (45.8125)10

Hexadecimal
0010 / 1101.1101
2/ D. D
Ans: (2D.D)16
56.Obtain 3-level NOR-NOR implementation for f(a,b,c,d,e,f)=[ab+cd]ef

57.Realize F=AB+AB using minimum universal gates.

11
58. Draw the logic diagram for X = AB+BC

59.Write the Boolean expression for the o/p of the system shown.

12
60.Implement F = (AB+AB)(C+D) with only NOR gate.

61. Write the Boolean function of an XOR gate give its truth table ?.

Truth Table
Input Output
A B Y=A B
0 0 0
0 1 1
1 0 1
1 1 0
62.What are the application of Demorgan Theorem.
a. Convert max term-to-min term or min term-to-max term form
b. Examine two different logic diagrams that perform same logic function.

13
63.Realize an OR gates using NAND gates?

64. prove that a+ab = a+b

a+ab = a+ ab +ab [since a=a+ab]
= a+b(a+a)
= a+b [since a+a=1]
Thus proved
65.Convert (0.6875)10 to binary(April/May 2015)
0.6875 x 2 = 1.375 1
0.3750 x 2 = 0.750 0
0.7500 x 2 = 1.500 1
0.5000 x 2 = 1.000 1
This process gives the binary number 0.1011. The zero before the decimal point is assumed
because the number is obviously less than 1.
66.Prove the following using Demorgans Law.
[(X+Y)+(X+Y)]=X+Y
Solution:
[(X+Y)+(X+Y)]= X.Y+X.Y
Apply Function
= [X.Y+X.Y]
= (X+Y) .(X+Y) [X.X=X]
= X+Y Thus proved.
67.Implement AND gate using only NOR Gate.(Nov/Dec 2014)

14
68.Find the octal equivalent of hexadecimal number i)AB.CD and ii)DC.BA
Hexadecimal numberA- 1010
B->1011
C->1100
D->1101
i) (010101011 . 110011010)2to (253.632)8

ii)(011011100.101110100)2to (334.564)8
69.Convert (126)10 to octal number and binary number.(Nov/Dec 2015)

Decimal to octal conversion Decimal to binary conversion

Ans: 176. Ans:1111110

70.What is meant by multilevel gate network.(May/June 2016)

A number of gates cascaded in series between a network input and output is referred to as
the number of levels of gets .We dont count inverters as a level.Sum-of-products form and
product-of-sums form are two-level gets network.

15
 UNIT-II
1. Define combinational logic
When logic gates are connected together to produce a specified output for certain
specified combinations of input variables, with no storage involved, the resulting
circuit is called combinational logic.
OR
Combinational logic circuit is a logic circuit which output depends the present input
only. It is constructed using logic gates only but it does not have memory element.
2.Give the design procedure for combinational circuits.
i. The problem definition
ii. Determine the number of available input variables & required O/P variables.
iii. Assigning letter symbols to I/O variables
iv. Obtain simplified Boolean expression for each O/P using k-map.
v. Obtain the logic diagram.
3.What are the differences between sequential and combinational logic circuits?

S.No combinational logic Sequential logic

In sequential circuits the output
In combinational circuits the output
variables dependent not only on
1 variables are all time dependent on the
present variables but also on the past
combination of input variables.
history of input variables.
Memory input is not required in Memory input is required to store the
2
combinational circuits. past history in sequential circuits.
Combinational circuits are easy to Sequential circuits are harder to
3
design. design.
Parallel adder is a combinational
4 Serial adder is a sequential circuit.
circuit.
They are slower than the
5 These are faster in speed.
combinational circuit.

4.Define half adder and full adder

The logic circuit that performs the addition of two bits is a half adder.
The circuit that performs the addition of three bits is a full adder.
5.Give the truth table or half adder.
Inputs Outputs

16
 A B Sum(S) Carry(C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
6.Give the truth table of full-adder.
Inputs Output
A B Cin Sum(S) Carry-out(cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
7.What is Binary parallel adder?
A binary parallel adder is a digital function that produces the arithmetic sum of two
binary numbers in parallel.
8.From the truth table of a half adder derive the logic equation
Sum S = A B
Carry C = A B
Where A and B are the inputs
9.From the truth table of a half subractor, derive the logic equation
Difference D = XY
Borrow (B) = X1 . Y
Where X and Y are the inputs
10.From the truth table of a full adder derive the logic equation
Sum (S) = X Y Z
Carry (C) = XY + YZ + XZ
Where X, Y and z are the inputs
11.What is binary decoder?
A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2n outputs lines.
12.What is BCD adder?
17
 A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit
also in BCD.
13.What is Magnitude Comparator?
A Magnitude Comparator is a combinational circuit that compares two numbers, a
and B and determines their relative magnitudes.
14.Define Encoder.
An encoder has 2n or less than 2n input lines and n output lines. In encoder the
output lines generate the binary code corresponding to the input value.
15.What is priority Encoder?
A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if 2 or more inputs are equal to 1 at the same time, the input having the
highestpriority will take precendence.
16.Define multiplexer?
Multiplexer is a digital switch. If allows digital information from several sources to be
routed onto a single output line based on the selection lines.

17.What is Demultiplexer ?
A Demultiplexer is a circuit that receives information on a single line and transmits
this information on one of 2n possible output lines

18.What is code conversation?

If two systems working with different binary codes are to be synchronized in operation,
then we need digital circuit which converts one system of codes to the other. The
process of conversion is referred to as code conversion.
18
19.What is code converter?
It is a circuit that makes the two systems compatible even though each uses a
different binary code. It is device that converts binary signals from a source code to its
output code. One example is a BCD toXs3 converter.
20.What do you mean by analyzing a combinational circuit?
The reverse process for implementing a Boolean expression is called as analyzing a
combinational circuit. (ie) the available logic diagram is analyzed step by step and
finding the Boolean function
21.Give the applications of Demultiplexer.
i. If finds its application in Data transmission system with error detection.
ii. One simple application is binary to Decimal decoder.

22.Mention the uses of Demultiplexer.

Demultiplexer is used in computers when a same message has to be sent to different
receivers. Not only in computers, but any time information from one source can be fed
to several places.
23.Give another name for Multiplexer and Demultiplexer.
Multiplexer is other wise called as Data selector.
Demultiplexer is otherwise called as Data distributor.
24.What is the function of the enable input in a multiplexer?
The function of the enable input in a MUX is to control the operation of the unit.
25.What is priority encoder?
A priority encoder is an encoder that includes the priority function.
The operation of the The priority encoder is such that if two or more inputs are
equal to 1 at the same time, the input having the highest priority will take
precedence.
26.Can a decoder function as a Demultiplexer?
Yes. A decoder with enable can function as a Demultiplexer if the enable line E is
taken as a date input line A and B are taken as selection lines.
27.List out the applications of multiplexer?
The various application of multiplexer are
a. Data routing.
b. Logic function generator.
c. Control sequencer.

19
 d. Parallel-to-serial convertor
28.List out the applications of decoder?
The applications of decoder are
a. Decoder are used in counter system
b. They are used in analog to digital convertor.
c. Decoder outputs can be use to drive a display system.
29.List out the application of comparators?
The following are the applications of comparator
a. Comparator are used as a part of the address decoding circuitry in computers to
select a specific input/output device for the storage of data.
b. They are used to actuate circuitry to drive the physical variable towards the
reference value.
c. They are used in control applications.
30.Define Half subtractor.
Half Subtractor is used for subtracting one single bit binary number from another single bit
binary number.The truth table of Half Subtractor is shown below.

31. Define decoder.

A decoder is a device which does the reverse operation of an encoder, undoing the
encoding so that the original information can be retrieved.
32.What is look ahead carry generator.
The delay generated by an N-bit adder is proportional to the length N of the two
numbers X and Y that are added because the carry signals have to propagate from one
full-adder to the next.
For large values of N, the delay becomes unacceptably large so that a special solution
needs to be adopted to accelerate the calculation of the carry bits.
This solution involves a "look-ahead carry generator" which is a block that
simultaneously calculates all the carry bits involved.
20
33.Define parity generator/checker.
An error is detected if the checked parity does not correspond with the one
transmitted. The circuit that generates the parity bit in the transmitter is called a
parity generator.
The circuit that checks the parity in the receiver is called a parity checker.
34.What is binary multiplier?
A binary multiplier is an electronic circuit used in digital electronics, such as
a computer, to multiply two binary numbers. It is built using binary adders
35.Define demultiplexer.
A demultiplexer, sometimes abbreviated dmux, is a circuit that has one input and
more than one output. It is used when a circuit wishes to send a signal to one of many
devices. This description sounds similar to the description given for a decoder, but a
decoder is used to select among many devices while a demultiplexer is used to send a
signal among many devices.
36.Draw the diagram of parity checker.

37.Define full subtractor.

The full-subtractor is a combinational circuit which is used to perform subtraction of
three bits. It has three inputs, X (minuend) and Y(subtrahend) and Z (subtrahend) and
two outputs D (difference) and B (borrow).
38.Difference between encoder and decoder.
An encoder is a device, circuit, transducer, software program, algorithm or person that
converts information from one format or code to another, for the purposes of
standardization, speed, secrecy, security, or saving space by shrinking size.
A decoder is a device which does the reverse of an encoder, undoing the encoding so
that the original information can be retrieved. The same method used to encode is
usually just reversed in order to decode.
39.What is parity bit?
A parity bit, or check bit is a bit added to the end of a string of binary code that
indicates whether the number of bits in the string with the value one is even or odd
21
 Parity bits are used as the simplest form of error detecting code.
There are two variants of parity bits: even parity bit and odd parity bit.
40.How will you build a full adder using two half adder and a OR gate?

Implementation of full adder using two half adders and a OR gate is given below.

41.Draw the Logic diagram of 4-bit gray-to-binary converter.

Logic diagram of 4-bit gray-to-binary converter

42.What are the applications of Decoder?
1. Decoder can be used to implement combinational circuit.
2. It can be used to convert BCD into seven segment code.
3. It is used in memories to select particular register.
43. Write the truth table for 4:1 MUX for m(1,3,5,6)?

Minterms A B C F
0 0 0 0 0
1 0 0 1 1
2 0 1 0 0
3 0 1 1 1
4 1 0 0 0

22
 5 1 0 1 1
6 1 1 0 1
7 1 1 1 0

44.Draw the block diagram and truth table for 2 to 4 decoder.

Inputs Outputs
Enable A B Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

45.Implement the following boolean function using 4: 1 multiplexer,

F (A, B, C) = m (1, 3, 5, 6).
Solution:
Variables, n= 3 (A, B, C)
Select lines= n-1 = 2 (S1, S0)
2n-1 to MUX i.e., 22 to 1 = 4 to 1 MUX
Input lines= 2n-1 = 22 = 4 (D0, D1, D2, D3)
Implementation table:
Apply variables A and B to the select lines. The procedures for implementing the function are:
i. List the input of the multiplexer
ii. List under them all the minterms in two rows as shown below.
The first half of the minterms is associated with A and the second half with A. The given
function is implemented by circling the minterms of the function and applying the following
rules to find the values for the inputs of the multiplexer.
1. If both the minterms in the column are not circled, apply 0 to the corresponding input.
2. If both the minterms in the column are circled, apply 1 to the corresponding input.

23
 3. If the bottom minterm is circled and the top is not circled, apply C to the input.
4. If the top minterm is circled and the bottom is not circled, apply C to the input.

46.Implement the function G=m(0,3) using a 2x4 decoder (May/June 2014)

47.Write the differences between Decoder and Demultiplexer?

Decoder
1. Decoder is a many inputs to many
output device.
2. There are no selection lines.
Demultiplexer
1. Demultiplexer is a one input to many
outputs device.
2. The selection of specific output line is
controlled by the value of selection lines.

48. What are the differences between Multiplexer and Decoder?

1. Multiplexer has several data input lines and a single output line.
2. Decoder has n input lines and 2n output lines.
3. The selection of particular input line is controlled by set of selection lines in Multiplexer.
4. Decoder activates one of the output line depending on the input combination.
49. State the applications of multiplexer?
1. It is used as data selector to select one out of many data inputs.
2. It is used to implement combinational logic circuit.
3. Used in time and frequency multiplexing systems.
4. Used in A/D and D/A converters.
5. Used in data acquisition systems.

24
 UNIT-III
PART-A
1. Define sequential logic circuit.
In sequential circuit the output variables dependent not only on the present input
variables but they also depend up on the past history of these input variables. It
consists of logic circuit and memory element.
2. What is the classification of sequential circuits?( Jan 11)
The sequential circuits are classified on the basis of timing of their signals into two
types. They are,
1). Synchronous sequential circuit.
2). Asynchronous sequential circuit.
3. Define Flip flop. (May 11)
The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1
or 0 until directed by an input signal to change its state.
4. What are the different types of flip-flop? (May 11)
There are various types of flip flops. Some of them are mentioned below they are,
i. RS flip flop
ii. SR flip flop
iii. D flip flop
iv. JK flip flop
v. T flip flop
5. What is the operation of RS flip flop?
When R input is low and S input is high the Q output of flip-flop is set.
When R input is high and S input is low the Q output of flip-flop is reset.
When both the inputs R and S are low the output does not change
When both the inputs R and S are high the output is unpredictable.
Or

Flip flop inputs Present Next State name

state state
R S Q Q+
0 0 0 0 Not change
0 0 1 1
0 1 0 1 Set
0 1 1 1

25
 1 0 0 0 Reset
1 0 1 0
1 1 0 X Indeterminate
1 1 1 X condition

6. What is the operation of D flip-flop?

In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if
D=0, the output is reset.
or
output of D flip-flop is same as input
Flip flop input Present state Next state
D Q Q+
0 0 0
0 1 0
1 0 1
1 1 1
Same Q+ =D
7. What is the operation of JK flip-flop?
When K input is low and J input is high the Q output of flip-flop is set.
When K input is high and J input is low the Q output of flip-flop is reset.
When both the inputs K and J are low the output does not change
When both the inputs K and J are high it is possible to set or reset the flip-
flop (ie) the output toggle on the next positive clock edge.
Flip flop inputs Present Next State name
state state
J K Q Q+
0 0 0 0 No change
0 0 1 1
0 1 0 1 Set
0 1 1 1
1 0 0 0 Reset
1 0 1 0
1 1 0 1 Toggle
1 1 1 0 condition

26
8. What is the operation of T flip-flop?
T flip-flop is also known as Toggle flip-flop.
When T=0 there is no change in the output.
When T=1 the output switch to the complement state (ie) the output toggles.
Or
Flip flop input Present state Next state
T Q Q+
0 0 0
0 1 0
1 0 1
1 1 1

9. Define race around condition.

In JK flip-flop output is fed back to the input. Therefore change in the output results
change in the input. Due to this in the positive half of the clock pulse if both J and K
and high then output toggles continuously. This condition is called race around
condition.
10. What is edge-triggered flip-flop?
The problem of race around condition can solved by edge triggering flip flop. The term
edge triggering means that the flip-flop changes state either at the positive edge of the
clock pulse and it is sensitive to its inputs only at this transition of the clock.
11. What is a master-slave flip-flop?
A master slave flip-flop consists of two flip-flops where one circuit serves as a master
and the other as a slave.
12. Define rise time and fall time.
The time required to change the voltage level from 10% to 90% is known as rise time
(tr).
The time required to change the voltage level from 90% to 10% is known as fall time
(tf).
13. Define skew and clock skew.
The phase shift between the rectangular clock waveforms is referred to as skew and
the time delay between the two clock pulses is called clock skew
14. Define setup time.

27
 The setup time is the minimum time required to maintain a constant voltage levels at
the excitation inputs of the flip-flop device prior to the triggering edge of the clock
pulse in order for the levels to be reliably clocked into the flip flop.
It is denoted as tsetup.
15. Define hold time.
The hold time is the minimum time for which the voltage levels at the excitation inputs
must remain constant after the triggering edge of the clock pulse in order for the levels
to be reliably clocked into the flip flop. It is denoted as thold.
16. Define propagation delay.
A propagation delay is the time required to change the output after the application of
the input.
17. Define registers.(Jan11)
A register is a group of flip-flops flip-flop can store one bit information. So an n-bit
register has a group of n flip-flops and is capable of storing any binary
information/number containing n-bits.
18. Define shift registers.
The binary information in a register can be moved from one stage to other stage within
the register or into or out of the register upon application of clock pules. This type of
registers called shift registers.
19.Difference betweenCombinational&SequentialCircuits.

S.No Combinational Circuits SequentialCircuits

1 Theoutputatalltimesdependsonl Theoutputnot onlydependsonthe
yonthepresentcombinationofinp presentinput
utvariables. butalsodependsonthepast
2 MemoryunitisnotRequired. Memoryunitisrequiredtostorethepast
historyinputvariables.
3 Clockinputisnotneeded. historyof inputvariable.
Clockinputisneeded.
4 FasterinSpeed. SpeedisSlower.
5 Easytodesign. Difficult to design.
6 Eg:Mux,Demux,Encoder, Eg:ShiftRegister,Counters.
Decoder,Adders,Subtractors.

19. What do you mean by present state?

The information stored in the memory elements at any given time defines the present
state of the sequential circuit.
20. What do you mean by next state?

28
 The present state and the external inputs determine the outputs and the next state of
the sequential circuit.
21. Define synchronous sequential circuit
In synchronous sequential circuits, signals can affect the memory elements only at
discrete instant of time.
22. Define Asynchronous sequential circuit?
In asynchronous sequential circuits change in input signals can affect memory
element at any instant of time
23. Give the comparison between synchronous & Asynchronous sequential circuits?
Synchronous sequential circuits Asynchronous sequential circuits
Memory elements are clocked flip-flops Memory elements are either unlocked flip-
flops or time delay elements.
Easier to design More difficult to design
Speed of operation is limited by its clock No limitation
24.What is fundamental mode sequential circuit?
Input variables changes if the circuit is stable
Input are levels, not pulses
Only one input can change at a given time
25. What is meant by clocked sequential circuits? ( April 13 )
Sequential circuits use current input variables and previous input variables by
storeing the information and putting back into the circuit on the next clock (activation)
cycle.
26. What are pulse mode circuit?
-inputs are pulses
-width of pulses are long for circuit to respond to the input
-pulse width must not be long that it is still present after the new state is reached
27. What are the significance of state assignment?
In synchronous circuit-state assignments are made with the objective of circuit
reduction Asynchronous circuits-its objective is to avoid critical races
28. When do race conditions occur?
Two or more binary state variables change their value in response to the change in i/p
variable
29. What is non critical race?
-Final stable state does not depend on the order in which the state variable changes
-Race condition is not harmful

29
30. What is critical race?
-final stable state depends on the order in which the state variable changes
-race condition is harmful
31. When does a cycle occur?
-asynchronous circuit makes a transition through a series of unstable state
32. What are the different techniques used in state assignment?
-shared row state assignment
-one hot state assignment
33. What are the steps for the design of asynchronous sequential circuit?
-construction of primitive flow table
-reduction of flow table
-state assignment is made
-realization of primitive flow table
34. What is hazard?
-unwanted switiching transients
1 hazard?
-output goes momentarily 0 when it should remain at 1
0 hazards?
-output goes momentarily 1 when is should remain at 0
dynamic hazard?
-output changes 3 or more times when it changes from 1 to 0 or 0 to 1
cause for essential hazards?
-unequal delays along 2 or more path from same input
35.State the excitation table of JK flipflop.(May/June 2016)
Present Next
Input
State State
Qn Qn+1 J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0

36.Mention the differences between edge triggering and level triggering.

Level triggering:The output state is allowed to change according to input when active
level is maintained at the enable input.

30
 Edge triggering:the output responds to the changes in the input only at the positive
or negative edge of the clock pulse at the clock input.
37.What are the ApplicationsofFlip-Flop?
1.Used as a memoryElement.
2.Used as a DelayElement.
3.Used as abasic building block in sequential circuits such as counter and
registers.
4.DataTransfer.
5.Frequency Division& Counting
38.What are the applications of shift register ?(April/May 2014)
Shift register act as asequence generator
Used in delay lines.
Used in counters.
Used as amemory element
39. Define merger graph.
The merger graph is defined as follows. It contains the same number of vertices as the
state table contains states. A line drawn between the two state vertices indicate each
compatible state pair. It two states are incompatible no connecting line is drawn.
40. Define state table.
For the design of sequential counters we have to relate present states and next states.
The table, which represents the relationship between present states and next states, is
called state table.
41. Define total state
The combination of level signals that appear at the inputs and the outputs of the
delays define what is called the total state of the circuit.
42. Define primitive flow table: (Jan11)
It is defined as a flow table which has exactly one stable state for each row in the
table. The design process begins with the construction of primitive flow table.
43. What are the types of asynchronous circuits?
1. Fundamental mode circuits
2. Pulse mode circuits
44. What are races?
When 2 or more binary state variables change their value in response to a change in
an input variable, race condition occurs in an asynchronous sequential circuit. In case
of unequal delays, a race condition may cause the state variables to change in an
unpredictable manner.
45. Define non critical race.
31
 If the final stable state depends on the order in which the state variable changes, the
race condition is not harmful and it is called a non critical race.
46. Define critical race?
If the final stable state depends on the order in whichthe state variable changes, the
race condition is harmful and it is called a critical race.
47. What is a cycle?
A cycle occurs when an asynchronous circuit makes a transition through a series of
unstable states. If a cycle does not certain a stable state, the circuit will go from one
unstable to stable to another, until the inputs are changed.
48. Write a short note on pulse mode circuit.
Pulse mode circuit assumes that the input variables are pulses instead of level. the
width of the pulses is long enough for the circuit to respond to the input and pulse
width must not be so long that it is still present after the new state is reached.
49. Define the term counter. (April 13)
A counter is used to count pulse and give the output in binary form.A register that
goes through a prescribed sequence of states upon the application of input pulses is
called a counter.
50. State ripple counter( Jan 11)
A ripple counter is nothing but an asynchronous counter, in which the output of the
flip -flop change state like a ripple in water

UNIT-IV
PART-A
1.Define ROM.
Read only memory is a device that includes both the decoder and the OR gate within a
single IC package. We can read the data only.
2.Give the types of ROM
i. Masked ROM
ii. Programmable read only Memory
iii. Erasable Programmable Read only memory
iv. Electrically Erasable Programmable Read only Memory.
3.What are the different types of RAM?
The different types of RAM are
1. Static RAM
2. Dynamic RAM
32
4.What are the types of arrays in RAM?
RAM has two type of array namely,
a. Linear array
b. Coincident array
5.What do you mean by DRAM?
The dynamic RAM (DRAM) is an operating mod, which stores the binary information in
the fprm of electric charges on capacitors. The capacitors are provided inside the chip
by MOS transistors.
The stored charges on the capacitors tend to discharge with time and the capacitors
must be tending to discharge with time and the capacitors must be tending to
discharge with time and the capacitors must be periodically recharged by refreshing
the dynamic memory.
DRAM offers reduced power consumption and larger storage capacity in a single
memory chip.
6.Explain SRAM? [JANUARY 2011]
Static RAM (SRAM) consists of internal latches that store the binary information. The
stored information remains valid as long as the power is applied to the unit.
SRAM is easier to use and has shorter read and write cycle. The memory capacity of a
static RAM varies from 64 bit to 1 mega bit.
7.Differentiate volatile and non-volatile memory?
Volatile Memory Non-volatile Memory
This volatile memory cell lose stored It retains should information when power
information when power is turned off. is turned off.
E.g. SRAM and DRAM E.g. Magnetic disc an ROM

8.What are the advantages of RAM?

The advantages of RAM are
a. Non-destructive read out
b. Fast operating speed
c. Low power dissipation
d. Economy
9. Define bit, byte and word
The smallest unit of binary data is bit.
Data are handled in a 8 bit unit called byte.
A complete unit of information is called a word which consists of one or more bytes.

33
10.How many words can a 168 memory can store?
A 168 memory can store 16,384 word of eight bits each
11.Define address of a memory.
The location of a unit of data in a memory is called address.
12.What is Read and Write operation?
The Write operation strokes data into a specified address into the memory and
the Read operation takes data out of a specified address in the memory.
13.Why RAMs are called as Volatile?
RAMs are called as volatile memories because RAMs lose stored data when the
power is turned OFF.
14.Define static RAM and dynamic RAM
Static RAM use flip flop as storage elements and therefore store data indefinitely
as long as dc power is applied.
Dynamic RAMs use capacitors as storage elements and cannot retain data very
long without capacitors being recharged by a process called refreshing.
15.What is meant by ROM?
A read only memory (ROM) is a device that includes both the decoder and the OR
gates within a single IC package. It consists of n input lines and m output lines.
Each bit combination of the input variables is called an address.
Each bit combination that comes out of the output lines is called a word. The
number of distinct address possible with n input variables is 2n.
16.What are the types of ROM? [NOVEMBER 2013]
1. PROM
2. EPROM
3. EEPROM
17.Define CPLD.[APRIL/MAY 2012]
A complex programmable logic device (CPLD), as the name suggests, is a much more
complex device than any of the programmable logic devices.
A CPLD may contain circuitry equivalent to that of several PAL devices linked to each
other by programmable interconnections.
18.What is meant by PROM?
PROM (Programmable read Only Memory) it allows user to store data or program.
The user can below fuses by passing around 20 to 50mA of current for the period
5 to 20s. the blowing of fuses is called programming of ROM.

34
 The PROMs are one time programmable. Once programmed, the information is
stored permanent.
19.Define Memory Unit[November 2013]
A memory unit is a device to which binary information is transferred for storage and
from which information is retrieved when needed for processing.
20.What is meant by EPROM?
EPROM (Erasable Programmable Read Only Memory) EPROM use MOS circuitry.
They store 1s and 0s as a packet of charge in a buried layer of the IC chip.
We can erase the stored data in the EPROMs by exposing the chip to ultraviolet light
via its quartz window for 15 to 20 minutes.
It is not possible to erase selective information. The chip can be reprogrammed.
21.What is RAM?
Random Access Memory. Read and write operations can be carried out.
22.Define address and word.
If a ROM, each bit combination of the input variable is called on address. Each bit
combination that comes out of the output lines is called a word.
23.What is meant by flow table? [January 2011]
The tables we will try to obtain are transition tables and flow tables (more or less
the same thing as a state table in synchronous circuit design). We can also use
state diagrams to describe asynchronous circuits.
24.Define the term PAL [April 2013]
The PAL is a programmable logic device with a fixed OR array and a
programmable AND array. Because only the AND gates are programmable, the
PAL is easier to program than, but is not as flexible as, the PLA. Figure 7.16
shows the logic configuration of a typical PAL with four inputs and four outputs.
Each input has a bufferinverter gate, and each output is generated by a fixed OR
gate.
There are four sections in the unit, each composed of an ANDOR array that is
three wide, the term used to indicate that there are three programmable AND
gates in each section and one fixed OR gate.
Each AND gate has 10 programmable input connections, shown in the diagram
by 10 vertical lines intersecting each horizontal line.
The horizontal line symbolizes the multipleinput configuration of the AND gate.
One of the outputs is connected to a bufferinverter gate and then fed back into
two inputs of the AND gates.

35
25.What is programmable logic array? How it differs from ROM?
In some cases the number of dont care conditions is excessive, it is more
economical to use a second type of LSI component called a PLA. A PLA is similar
to a ROM in concept; however it does not provide full decoding of the variables
and does not generates all the minterms as in the ROM.
26.What is mask programmable?
With a mask programmable PLA, the user must submit a PLA program table to
the manufacturer.
27.What is field programmable logic array?
The second type of PLA is called a field programmable logic array. They user by
means of certain recommended procedures can program the EPLA.
28.List the major difference between PLA and PAL
PLA PAL
Both AND and OR arrays are AND arrays are programmable OR arrays
programmable are fixed
Complex Costlier than PAL Cheaper and Simpler
29.Define PLD.
Programmable Logic Devices consist of a large array of AND gates and OR gates
that can be programmed to achieve specific logic functions.
30.Give the classification of PLDs.
PLDs are classified as
Programmable Read Only Memory (PROM),
Programmable Logic Array(PLA),
Programmable Array Logic (PAL) and
Generic Array Logic (GAL)
31.Define PLA
PLA stands for Programmable Logic Array. The PLA is a PLD that consists of a
programmable AND array and a programmable OR array.
32.Define PAL
PAL is Programmable Array Logic. PAL consists of a programmable AND array and a
fixed OR array with output logic.
33.What are the terms that determine the size of a PAL?
The size of a PLA is specified by the
Number of inputs
Number of products terms

36
 Number of outputs
34.What does PAL 10L8 specify?
PAL Programmable Logic Array
10 Ten inputs
L Active LOW Output
8 Eight Outputs
35.What is CPLD?
CPLD are Complex Programmable Logic Devices. They are larger versions of
PLDs with a centralized internal interconnect matrix used to connect the device
macro cells together.
36.Why was PAL developed?
PAL is a PLD that was developed to overcome certain disadvantages of PLA, such as
longer delays due to additional fusible links tthat result from using two Programmable
arrays and more circuit complexity.
37. Why the input variables to a PAL are buffered?
The input to a PAL are buffered to prevent loading by the large number of AND gate
inputs to which available or its complements can be connected.
38.Define FPGA.
FPGA stands for Field Programmable Gate Array, which is the next generation in
programmable logic devices.
The Word field refer to the ability of the gate arrays to be programmed for a specific
function by the end user.
The word arrar indicates a series of columns and rows of gate that can be programmed
by the end user.
39.List the configurable elements in the FPGA architecture.
Three types of cinfrigurable elements:
1. A perimeter of Input Ouptut Blocks(IOBs)
2. A core array of Confrigurable Logic Blocks(CLBs)
3. Resources for Interconnection.
40.How is identified location in a EEPROM Programmed or erased?
Since it is electrically erasable memory, by activating particular row and column it is
possible that individual can be programmed or erased.

37
 UNIT-V
PART-A
1. What is Verilog?
Verilog is a general purpose hardware descriptor language. It is similar in syntax to
the C programming language. It can be used to model a digital system at many levels
of abstraction anging from the algorithmic level to the switch level.
2. What is use of Verilog HDL?
Verilog HDL is a general purpose hardware description language that is easy to learn
and easy to use. It is similar in syntax to the C programming language. Designers
with C programming experience will find it easy to learn Verilog HDL.
3. What are the design methodologies in Verilog HDL?
There are two Design methodologies are adopted in Verilog HDL.
(A) Top-down Design

(B) Bottom up Design

4. What are the various modeling used in Verilog?

1. Gate-level modeling
2. Data-flow modeling
3. Switch-level modeling
5. What is the structural gate-level modeling?

38
 Structural modeling describes a digital logic networks in terms of the components that
wake up the system. Gate-level modeling is based on using primitive logic gates and
specifying how they are wired together.
6. What are the value sets in Verilog?
Verilog supports four levels for the values needed to describe hardware referred to
as value sets.
Value levels Condition in hardware circuits
0 Logic zero, false condition
1 Logic one, true condition
X Unknown logic value
Z High impedance, floating state
7. What are identifiers?
Identifiers are names of modules, variables and other objects that we can reference
in the design. Identifiers consists of upper and lower case letters, digits 0 through
9, the underscore character(_) and the dollar sign($). It must be a single group of
characters. Examples: A014, a, b, in_o, s_out
8. What are the types of gate arrays in ASIC?
1) Channeled gate arrays
2) Channel less gate arrays
3) Structured gate arrays
9. Give the classifications of timing control .
Methods of timing control:
1. Delay-based timing control
2. Event-based timing control
3. Level-sensitive timing control
Types of delay-based timing control:
1. Regular delay control
2. Intra-assignment delay control
3. Zero delay control
Types of event-based timing control:
1. Regular event control
2. Named event control
3. Event OR control
4. Level-sensitive timing control

39
10. Define modules.
A module can be an element or a collection of lower-level design blocks.
Typically, elements are grouped into modules to provide common functionality that is
used at many places in the design.
A module provides the necessary functionality to the higher-level block through its
port interface (inputs and outputs), but hides the internal implementation.
11. What is Switch-level modeling?
Verilog allows switch-level modeling that is based on the behavior of MOSFETs.
Digital circuits at the MOS-transistor level are described using the MOSFET
switches.
12. Define Instances.
A module provides a template from which you can create actual objects.
When a module is invoked, Verilog creates a unique object from the template. Each
object has its own name, variables, parameters, and I/O interface.
The process of creating objects from a module template is called instantiation, and the
objects are called instances.
13. What are the two distinct components of Simulation?
(a) Design Block
(b) Stimulus block
14. What is mean by stimulus block?
The stimulus block can be written in Verilog. A separate language is not required to
describe stimulus.
The stimulus block is also commonly called a test bench. Different test benches can be
used to thoroughly test the design block.
Two styles of stimulus application are possible. In the first style, the stimulus block
instantiates the design block and directly drives the signals in the design block. In
Figure a, the stimulus block becomes the top-level block.
It manipulates signals clk and reset, and it checks and displays output signal q.

40
15. List out the lexical conventions in Verilog HDL.
(A) White space
(B) Commands
(C) Number Specification
(D) Operators
(E) Strings
(F) Identifier and Keywords
(G) Escaped Identifier
16. What are the different types of datatype in Verilog HDL?
(a) Value Set
(b) Nets
(c) Registers
(d) Vectors
(e) Integer, Real and Time Register Data types
(f) Arrays
17. Define array
Arrays are collection of storing same data items. Arrays are allowed in Verilog for reg,
integer, time, real, realtime and vector register data types.
Multi-dimensional arrays can also be declared with any number of dimensions.
Arrays of nets can also be used to connect ports of generated instances.
Each element of the array can be used in the same fashion as a scalar or vector net.
Arrays are accessed by < array_name>[<subscript>].
For multi-dimensional arrays, indexes need to be provided for each dimension.
18. Give the different arithmetic operators?
41
 Operator symbol Operation performed Number of operands
* Multiply Two
/ Divide Two
+ Add Two
- Subtract Two
% Modulus Two
** Power (exponent) Two
19. What are system tasks?
All system tasks appear in the form $<keyword>. Operations such as displaying on the
screen, monitoring values of nets, stopping, and finishing are done by system tasks.
20. Define Displaying information
$display is the main system task for displaying values of variables or strings or
expressions. This is one of the most useful tasks in Verilog. Usage: $display(p1, p2,
p3,....., pn); p1, p2, p3,..., pn can be quoted strings or variables or expressions. The
format of $display is very similar to printf in C. A $display inserts a newline at the end
of the string by default. A $display without any arguments produces a newline.
21. Write a example code for Display a string
// Display the string quotes
$display(Hello Verilog World);
-- Hello Verilog World
// Display value of current simulation time 230
$display($time);
22. Give the different bitwise operators.
Operator symbol Operation performed Number of operands
~ Bitwise negation One
& Bitwise and Two
| Bitwise or Two
^ Bitwise xor Two
^~ or ~^ Bitwise xnor Two
~& Bitwise nand Two
~| Bitwise nor Two
23. What is mean by ports?
Port provide the interface by which a module can communicate with its environment.
For example, the input/output pins of an IC chip are its ports. The environment can

42
 interact with the module only through its ports. The internals of the module are not
visible to the environment. This provides a very powerful flexibility to the designer.
24. How to declare a Port?
All the ports in the list of ports must be declared in the module. Ports can be declared
as follows:
Verilog Keyword Type of Port
Input input port
Output output port
Inout bidirectional
port.

25. What are gate types in Verilog? What are gate primitives in Verilog HDL?
(a) AND
(b) OR
(c) XOR
(d) NAND
(e) NOR
(f) XNOR
26. What is Buf/Not Gates?
Buf/Not gates have one scalar input and one or more scalar outputs. The last
terminal in the port list is connected to the input. Other terminals are connected to
the outputs.
Two basic buf/not gate primitives are provided in Verilog.
Buf not
27. What is Gate Delays?
In real circuits, logic gates have delays associated with them. Gate delays allow the
Verilog user to specify delays through the logic circuits. Pin-to-pin delays can also be
specified in Verilog.
28. What is Rise Delay?
The rise delay is associated with a gate output transition to a 1 from another value.

43
29. What is Fall delay?
The fall delay is associated with a gate output transition to a 0 from another value.

30. What is continuous assignments?

A Continuous asssignment is the most basic statement in dataflow modeling, used to
drive a value onto a net. This assignment replaces gates in the description of the
circuit and describes the circuit at a higher level of abstraction. The assignment
statement starts with the keyword assign.
31. What are operator types?
Operator Type Operator symbol Operation Number of
Performed Operands
* Multiplication Two
/ Divide Two
+ Addition Two
Arithmetic
- Subtract Two
% Modulus Two
** Power(exponent) Two
Logical ! Logical negation One
&& Logical and Two
|| Logical Or Two
Relational > Greater than Two
< Less than Two
>= Greater than or Two
<= equal Two
Less than or
equal
Equality == Equality Two
!= inequality Two
=== case equality Two
!== case inequality Two
Bitwise ~ Bitwise One
& negation Two
| Bitwise and Two
^ Bitwise or Two
^~ or~^ Bitwise XOR Two
Bitwise xnor
Shift >> Right Shift Two
<< Left Shift Two
>>> Arithmetic right Two
<<< shift Two

44
 <<< Arithmetic left
shift
Concatenation { } Concatenation Any
number
Replication { { } } Replication
Any
number
Conditional ?: Conditional Three
32. What are the types of conditional statements?
1. No else statement
Syntax: if ([expression]) true statement;
2. One else statement
Syntax: if ([expression]) true statement;
else false-statement;
3. Nested if-else-if
Syntax : if ( [expression1] ) true statement 1;
else if ( [expression2] ) true-statement 2;
else if ( [expression3] ) true-statement 3;
else default-statement;
33. What is behavioral Modeling?
A behavioral description expresses a digital circuit in terms of the algorithms it
implements.
A behavioral description does not necessarily include the hfardware implementation
details.
Behavioral modeling is used in the initial stages of a design process to evaluate
various design-related trade-offs. Behavioral modeling is similar to C programming in
many ways.
34. What are structure procedures?
Structured procedures initial and always form the basis of behavioral modeling. All
other behavioral statements can appear only inside initial or always blocks.
An initial block executes once; an always block executes continuously until
simulation ends.
35. Difference between task and function.
FUNCTIONS TASKS

A function can enable another A Task enable other tasks and function
function but not another task

45
 Function always execute in O Tasks may execute in non-zero
simulation time simulation time.

Function does not contain any delay, Tasks may contain delay, event or
event or timing control statements timing control statements.

Functions must have at least one Tasks may have zero or more
input argument. They can have more arguments of type input, output or
than one input inout

Function always return a single value. Tasks do not return with a value, but
They cannot have output or input can pass multiple values through
arguments. output and input arguments.

36. What are gate primitives?

Verilog supports basic logic gates as predefined primitives. Primitive logic function
keyword provides the basics for structural modeling at gate level. These primitives
are instantiated like modules except that they are predefined in verilog and do not
need a module definition. The important operations are and, nand, or, xor, xnor,
and buf(non-inverting drive buffer).
37. Give the two blocks in behavioral modeling.
1. An initial block executes once in the simulation and is used to set up initial
conditions and step-by-step data flow.
2. An always block executes in a loop and repeats during the simulation.
38. Define DataTypes?
Verilog has net and reg data types representing wires and variables, respectively.
The net type represents data carriers such as interconnecting wires, gate outputs,
and busses.
The reg data type represents variables that hold the value they are assigned until
they are overwritten.
39. Define Wait Construct.
The wait statement is used as a level-sensitive control.
The syntax is: wait (expression) statement.
The processor waits when the expression is FALSE. When the expression is
TRUE, the statement is executed.
40. What are the different types of blocks and Verilog HDL?
Sequential and parallel are two types of blocks.
Sequential blocks are specified by keywords begins and end. Parallel blocks are
expressed by keywords fork and join.

46