Volume 50, Number 4, 2016 Your Engineering Resource for Innovative Design

4 Improper Power Sequencing in Op Amps: Analyzing the Risks

10 Complete Gas Sensor Circuit Using Nondispersive Infrared (NDIR)
21 Whats Up with Digital DownconvertersPart 2
36 PLC DCS Analog Input Module Design Breaks Barriers in Channel-to-Channel Isolation and Density
41 Next-Generation SAR ADC Addresses Pain Points of Precision Data Acquisition Signal Chain Design

27 Fully Automatic Self-Calibrated

Conductivity Measurement System

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 In This Issue

4 Improper Power Sequencing in Op Amps: Analyzing the Risks

This article explains how to analyze the effects of improper power supply sequencing in
circuits containing operational amplifier ICs to avoid damaging circuit components.

10 Complete Gas Sensor Circuit Using Nondispersive Infrared (NDIR)

This article gives the technical details of a circuit that is a complete thermopile-based gas
sensor using the NDIR principle. This circuit is optimized for CO2 sensing, but can also
accurately measure the concentration of a large number of gases by using thermopiles with
different optical filters.

19 RAQ: Because Mr. Ohm Said So

In my system the SPI interface for the ADC is returning 0xFF for every read. What could
be wrong?

21 Whats Up with Digital DownconvertersPart 2

This article takes a closer look at the decimation filtering and applies it to the example that was
discussed in Part 1 of the article. In addition, it explores Virtual Eval, which incorporates the
ADIsimADC engine into a new and revamped software simulation tool.

27 Fully Automatic Self-Calibrated Conductivity Measurement System

This article describes a completely self-contained, microprocessor controlled, highly accurate
conductivity measurement system that is ideal for measuring the ionic content of liquids, water
quality analysis, industrial quality control, and chemical analysis.

34 RAQ: Amplifier RF: Think Before You Choose!

My system design requires a large amplifier gain, can I just use a large feedback resistor?

2 Analog Dialogue Volume 50 Number 4

 36 PLC DCS Analog Input Module Design Breaks Barriers in
Channel-to-Channel Isolation and Density
This article discusses the need for isolation in the process control analog input module and
the traditional approaches to achieving it. It also outlines an alternative high density, easy to
design, channel-to-channel isolation analog input module architecture.

41 Next-Generation SAR ADC Addresses Pain Points of Precision Data

Acquisition Signal Chain Design
This article discusses the common pain-points encountered in designing a precision data
acquisition signal chain and how to address them using the next generation of 16-/18-bit,
2 MSPS precision successive approximation register (SAR) ADCs. The new SAR ADC technology
reduces signal chain complexity, and enables higher channel density while pushing the
performance level higher.

46 RAQ: Precision Current Outputs Are Easy to Make

How do I design a circuit with an accurate current output into a nonlinear load resistance?

Jim Surber, Editor

Jim became editor of Analog Dialogue in
May of 2015, when the preceding editor,
Scott Wayne, decided to retire. Jim has
been with Analog Devices for 40+ years,
starting with a company called Computer
Labs, a maker of high speed data
converters, which was acquired by ADI in 1978.
Jim has worked in production test, applications
engineering, product line marketing, and, most recently,
marketing communications. He enjoys writing and has
published several technical articles in various magazines
down through the years. Residing in Greensboro, North
Carolina, Jim enjoys spending time with his family on
frequent mountain outings.
You can reach him at jim.surber@analog.com or at
(336) 605-4365.
Analog Dialogue is a technical magazine created and
published by Analog Devices. It provides in-depth design
related information on products, applications, technology,
software, and system solutions for analog, digital, and
mixed-signal processing. Published continuously for 49
yearsstarting in 1967it is produced as a monthly online
edition and as a printable quarterly journal featuring article
collections. For history buffs, the Analog Dialogue archive
includes all issues, starting with Volume 1, Number 1, and
three special anniversary editions. To access articles, the
archive, the journal, design resources, and to subscribe, visit
the Analog Dialogue homepage, analogdialogue.com.

Analog Dialogue Volume 50 Number 4 3

Improper Power Sequencing in Op Amps:
Analyzing the Risks
By David Guo

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Introduction
In systems with multiple supply voltages, operational amplifier power
supplies must be established simultaneously with or before any input
signals are applied. If this doesnt happen, overvoltage and latch-up
conditions can occur.
However, this can sometimes be a difficult requirement to meet in real-
world applications. This article takes a look at the activity of op amps in
different power sequence situations (see Table 2), analyzes possible
issues, and presents some suggestions.
Table 1 shows the results of all AD8616 pins in such conditions. Before V+
is applied, the voltage at the V+ pin and OUT pins is negative. This may
not damage the op amp, but if these signals are connected to terminals
on other chips that havent been fully powered (for example, assuming
the ADC uses the same V+, and its power pin normally tolerates only
0.3 V minimum voltage), the chips may suffer damage. A similar issue
will happen if V+ is powered up before V.
Table 2 highlights some possible situations in power sequencing.

Power Sequencing Issues Can Vary V+ V+

IN A IN B
There are a number of different scenarios where power sequencing issues OUT A OUT B
10 k +IN A A 10 k +IN B B
may arise. For example, in one customer application, an AD8616 can
be configured as a buffer, the input is 0 V before power supplies are 3 V 3 V
established (Figure 1), and the negative supply is powered on before the AD8616 AD8616

positive supply (negative power is present and positive power is absent). Figure 1. AD8616 test circuit with 3 V V applied and V+ absent.

Table 1. AD8616 Pins Voltage with 3 V V Applied and V+ Absent

Pin1: OUTA Pin2: INA Pin3: +INA Pin4: V Pin5: +INB Pin6: INB Pin7: OUTB Pin8: V+

1.627 1.627 0.959 3.000 0.959 1.627 1.627 1.627

Table 2. Possible Situations in Power Sequencing

IN V+ V Amplifier Power with Load Amplifier Out with Load

Floating Present Absent No No

Case 1
Floating Absent Present No No

0V Present Absent No No
Case 2
0V Absent Present No No

Positive or negative Present Absent No No

Case 3
Positive or negative Absent Present No No

Positive or negative Present Absent Yes No

Positive or negative Present Absent No Yes
Case 4
Positive or negative Absent Present Yes No
Positive or negative Absent Present No Yes

4 Analog Dialogue Volume 50 Number 4

Electrostatic Discharge (ESD) Diodes Within Op Amps
Electrostatic discharge can also result in an overvoltage event. Most op
amps have an internal ESD diode to prevent electrostatic ESD events.
ESD diodes can provide a key to analyzing activity when either V+ or V is
absent. Figure 2 is a simplified block diagram of the ADA4077/ADA4177.
Table 3 shows the ADA4077-2/ADA4177-2s typical drop voltage of internal
ESD diodes and back-to-back diodes. Notice that back-to-back diodes
are placed between the two input terminals of the op amps to clamp the
maximum differential input signal.
V+
Also note that when DMM is used to measure D5/D6 of the ADA4077-2, it
shows no diode between the two input terminals. In fact, there are two series
of resistors before the back-to-back diodes to limit input current smaller than
10 mA. The internal resistors and back-to-back diodes limit the differential
input voltage to Vs to prevent a base-emitter junction breakdown.
For the ADA4177, OVP cells are integrated for robustness. They are placed
before the ESD diodes and back-to-back diodes, so its hard to measure
these diodes by DMM. The output ESD diodes of ADA4177 can be measured.

V+
Evaluation Setup
Figure 3 is used to measure the activity of the op amp. Channel A and
D3 V+
IN Channel B are each configured as a buffer, and the Channel B noninverting
V+ D4 D7 input is connected to the GND by a 100 k resistor. By making V+ absent
D5 D6 OUT
D1 D8
(V present) or V+ present (V absent), the input and power-related vari-
V
+IN ables can be measured by the ampere and voltage meters. By analyzing
D2 V these variables, we can determine the current flow path.
ADA4077
V

V ISY+ A V
V+ IOUT 100 k
A V+
V+
V+
IN A V+ IN B
D3 V+
OUT A OUT B
IN OVP IB+ A B
V+ +IN A 100 k +IN B
D4 D7
A
D5 D6 OUT V V 3 V
D1 D8 V
+IN OVP
D2 V
ISY A V
ADA4177
V

V
Figure 3. Setup for power sequencing test.
Figure 2. ADA4077/ADA4177 simplified block diagram.
Case 1: Input Is Floating
Table 3. Internal Diode of an Op Amp Table 4 shows the results of a floating input and one absent supply. When V
is present and V+ is absent, there is a negative voltage at the V+ pin. When
ADA4077 ADA4177 V+ is present and V is absent, there is a positive voltage at the V pin.
D1 0.838 Unknown
D2 0.845 Unknown Testing the ADA4077-2 and ADA4177-2 reveals similar results. No large
D3 0.837 Unknown
currents are observed at the input pins and power pins, and the op amp
with floating input remains safe when a power rail is absent.
D4 0.844 Unknown
D5 Unknown Unknown
Case 2: Input Is Grounded
D6 Unknown Unknown
Table 5 shows the results when the input is grounded. Note for IB+, a
D7 0.841 0.849
negative value means the current flow out of the +IN terminal. For IOUT,
D8 0.842 0.849 a negative value means the current flow out of the IN terminal.

Table 4. ADA4077-2/ADA4177-2 Results with Floating Input

Condition V+ V ISY+ (mA) ISY (mA) IB+ (mA) IOUT (mA) IN (V) OUT (V)
ADA4077-2 All power 15 15 1.02 1.01 0.00005 0.00007 0.001 0.008
V+ absent 13.1 15 0 0.12 0.00001 0.001 13.73 14.42
V absent 15 13.06 0.15 0 0.00001 0.001 12.93 13.62
ADA4177-2 All power 15 15 0.98 0.96 0.00001 0.00002 0 0.001
V+ absent 14.26 15 0 0.14 0.00002 0.00137 13.77 13.78
V absent 15 12.96 0.14 0 0.00001 0.00039 12.26 12.31

Table 5. ADA4077-2/ADA4177-2 Results with Grounded Input

Condition V+ V ISY+ (mA) ISY (mA) IB+ (mA) IOUT (mA) IN (V) OUT (V)
ADA4077-2 All power 15 15 1.01 1 0.00005 0.00001 0 0.019
V+ absent 0.846 15 0 2.30 2.300 1.60 0.017 2.68
V absent 15 0.847 1.78 0 1.758 1.064 0.012 2.116
ADA4177-2 All power 15 15 0.98 0.96 0.00001 0.00002 0 0
V+ absent 11.99 15 0 9.3 9.300 0.200 0.068 11.98
V absent 15 1.848 1.84 0 1.823 0.067 0.013 1.851

Analog Dialogue Volume 50 Number 4 5

Taking ADA4077-2 with V+ absent as an example, V+ is clamped to the VIN
voltage by an ESD diode.
XX VIN is connected to V+ via an ESD clamp diode, so when VIN is 0 V, V+
is 0.846 V.
XX Current flow path loop: as per the red path shown in Figure 4, 0.7 mA
current flows from GND (+IN) to V+. 1.6 mA current flows from GND
(+IN) through an internal resistor, D5 and the feedback path between
IN and OUT, then the current flows into the output terminal. Finally the
two currents (0.7 mA and 1.6 mA) combine to flow to 15 V, and the
combined current flows back to GND (+IN).
Results are similar between the ADA4177-2 and ADA4077-2. Note that
within the ADA4177-2, D1 is implemented by an emitter base of a lateral
PNP transistor. The transistor routes the overvoltage current away from the
V+ to the V. The ADA4177 circuit in Figure 4 shows 9.1 mA current flow
from V+ back to V, and combined with 0.2 mA current in the feedback
path, results in a 9.3 mA current flow to 15 V, then the current flows back
to GND.
No large currents are observed at the input pins and power pins for either
the ADA4077-2 or the ADA4177-2 (Table 5). These op amps can withstand
any order of PU sequencings in a gain of 1 with +IN grounded.
Case 3: With Input
A positive or negative signal (+10 V or 10 V) is applied to the +IN terminal
when one power is absent. Table 6 shows no large current, so these op
amps can withstand any order of PU sequencings in a gain of 1 with +IN
grounded for a short duration.
The current flow path analysis is similar with Case 2 (0 V input), refer to
Figure 5.

V+ V+
1.6 mA 0.2 mA

V+ V+

D3 V+ D3 V+
IN IN OVP
0.846 V V+ D7 V+ D7
D4 11.99 V D4
0.7 mA OUT D5 D6 9.1 mA OUT
D1 15 V D5 D6 D8 2.68 V 9.1 mA D1 D8 11.98 V
0.7 mA
+IN +IN OVP
D2 15 V D2 V
2.3 mA 9.3 mA
0V ADA4077 2.3 mA 0V ADA4177 9.3 mA
15 V V

15 V 15 V

Figure 4. ADA4077/ADA4177 current path when V+ is absent (input grounded).

V+ V+
1.65 mA 0.11 mA

V+ V+

D3 V+ D3 V+
IN IN OVP
9.14 V V+ D7 V+ D7
D4 9.09 V D4
D5 D6 0.75 mA OUT D5 D6 8.75 mA OUT
9.99 V D1 15 V D8 7.3 V 9.92 V 8.75 mA D1 D8 9.06 V
0.75 mA
+IN +IN OVP
D2 15 V D2 V
2.4 mA 8.86 mA
ADA4077 2.4 mA ADA4177 8.86 mA
15 V V

15 V 15 V
Figure 5. ADA4077/ADA4177 current path when V+ is absent (10 V input).

Table 6
Condition V+ V ISY+ (mA) ISY (mA) IB+ (mA) IOUT (mA) IN (V) OUT (V)
ADA4077-2 All power 15 15 1.03 1.01 0.00098 0.00003 10 9.97
V+ absent and positive input 9.14 15 0 2.4 2.396 1.653 9.99 7.3
V+ absent and negative input 10.83 15 0 2.41 2.308 1.651 10.02 12.66
V absent and positive input 15 10.83 1.81 0 1.689 1.055 10.02 12.09
V absent and negative input 15 9.15 1.77 0 1.759 1.031 9.99 7.88
ADA4177-2 All power 15 15 1.02 1 0.00099 0.00009 9.99 9.97
V+ absent and positive input 9.09 15 0 8.86 8.866 0.113 9.92 9.06
V+ absent and negative input 12.33 15 0 4.31 4.18 0.039 10.02 12.32
V absent and positive input 15 11.42 1.33 0 1.2 0.056 9.99 11.43
V absent and negative input 15 8.33 1.51 0 1.492 0.062 9.97 8.32

6 Analog Dialogue Volume 50 Number 4

Case 4: With Input and with Load at Power/Output
In a real application, the op amp circuit may work with another circuit.
For example, the op amps output may drive a load, or the op amps power
supply may also power other circuits. This can cause a problem.
In this test, a 47 resistor is connected between the output and GND or
the absent power pins and GND. Table 7 shows the test results for the
ADA4077. Large currents are highlighted in red. Three possible situations
can pose risks, assuming V+ is absent:
XX Situation 1: When the input is 10 V and the load of OUT is 47 , the
output is 1.373 V. When there is a 23 mA current flow out of the op
amps output pin (refer to Figure 6) the current path is:
Input signal source supply 30.2 mA current
24 mA current flow through D1 to V+, and 6.2 mA current flow
through D5 and feedback path to OUT
24 mA current from V+ is divided to 1 mA (to V) and 23 mA
(to OUT)
29.2 mA current flows through 47 load to GND
The current needs to be limited. By adding a 1 k resistor at +IN, the input
current is decreased to 6.8 mA.
XX Situation 2: When the input is 10 V and the load of V+ is 47 , 170 mA
current flows into the ADA4077-2 and flows out of V+ pin to a 47
power load. 170 mA current will burn the internal diode and dam-
age the chip. By adding a 1 k resistor at +IN, the input current is
decreased to 8.9 mA. Figure 7 shows the current flow path.

Table 7. ADA4077 with Load at Output Pin or Absent Power Pin

ADA4077-2 Condition IN (V) V+ V ISY+ (mA) ISY (mA) IB+ (mA) IOUT (mA) OUT (V)
V+ absent Vo or V+ no load/positive input 9.99 9.14 15 0 2.4 2.396 1.653 7.3
Vo 47 to GND 9.98 8.77 15 0 1.00 30.22 6.174 1.373
Vo 47 to GND and 1 k 9.98 2.389 15 0 0.76 6.828 2.104 0.284
V+ 47 to GND 9.59 8.01 15 170 5.05 175 5.0 6.06
V+ 47 to GND and 1 k 9.94 0.295 15 6.27 2.69 8.96 2.69 1.876
Vo or V+ no load/negative input 10.02 10.83 15 0 2.41 2.308 1.651 12.66
Vo 47 to GND 9.97 3.226 15 0 48.6 4.65 4.885 2.501
Vo 47 to GND and 1 k 10.02 10.83 15 0 14.30 2.284 1.629 0.563

V+ V+
6.2 mA 2.1 mA

V+ V+

D3 V+ D3 V+
IN IN
8.77 V V+ D7 2.389 V V+ D7
D4 D4
D5 D6 OUT D5 D6 OUT
D1 15 V D8 23 mA 1.373 V 9.98 V +IN D1 15 V D8 3.9 mA 0.284 V
+IN 24 mA 4.7 mA
29.2 mA

15 V 47 1 k 15 V 47

6 mA
30.2 mA D2 6.8 mA D2
9.98 V ADA4077 1 mA ADA4077 0.8 mA
15 V 15 V

15 V 15 V

Figure 6. ADA4077 current path when V+ is absent (10 V input and 47 output load).

5.0 mA V+ 47 2.69 mA V+ 47

170 mA 6.27 mA
V+ V+

D3 V+ D3 V+
IN IN
8.01 V V+ D7 0.295 V V+ D7
D4 D4
D5 D6 OUT D5 D6 OUT
D1 15 V D8 6.06 V 9.94 V D1 15 V D8 1.876 V
+IN 170 mA 6.27 mA

D2 5.0 mA 15 V D2 15 V
175 mA 8.96 mA
ADA4077 5.0 mA ADA4077 2.69 mA
15 V 15 V

15 V 15 V

Figure 7. ADA4077 current path when V+ is absent (10 V input and 47 power load).

Analog Dialogue Volume 50 Number 4 7

XX Situation 3: When input is negative (10 V) and the load of OUT is 47
(refer to Figure 8), there is a 48 mA current that flows through the
chip. This will generate a 48 mA (2.5 V + 15 V) = 0.6 W power
dissipation. Considering the ADA4077-2s 158 C/W JA , the junction
temperature is 94.8 higher than the ambient temperature. If there are
two channels or there is a heavier load, the junction temperature may
be higher than 150, and the chip may be damaged.
XX Instead of adding a current-limiting resistor at the input, the resistor
should be added at the output.
XX When V+ is present and V is absent, the same phenomena will hap-
pen. By adding external resistors to limit the current, the circuit can
be more robust.
For ADA4177-2, only Situation 3 applies. When there is a large negative
input and a heavy load at the output at the same time and when V+ is
absent and there is 53 mA current flow through the chip, the power dissi-
pation may be increased and the junction temperature is increased (refer
to Figure 9). By adding a 1 k resistor at the output, the risk can be avoided.
Of the two op amps, the ADA4177-2 is more robust than the ADA4077-2. It is
a preferred choice for applications that require both precision and robustness.
Other Op Amp Activity in Power Sequencing
Among op amps, there are varying implementations of diodes, resistors,
and OVP cells. Some op amps have no internal OVP cells, some have no
back-to-back diodes. A different implementation will produce different
results if one power supply is absent. In addition, different op amp designs
can produce different results.
For example, the ADA4084-2 has no internal current-limiting resistor or OVP
cells, and it has ESD diodes connected to the power supply and back-to-back
diodes. Table 9 and Figure 10 show the results when V+ is absent and there
is 10 V input. The ADA4084s activity and current path are similar to those of
the ADA4077-2 and ADA4177-2 (discussed previously in Case 3). However,
because the ADA4084 has no internal resistor or OVP cell to limit the current,
60 mA current will flow into the chip, which may cause damage.

V+ V+
4.9 mA 1.6 mA

V+ 3.226 V V+

D3 0.3 mA V+ V+
D3
IN IN
V+ D7 10.83 V V+ D7
D4 OUT D4 OUT
D5 D6 0.3 mA 2.501 V D5 D6 0.7 mA
D1 15 V D8 48.3 mA D1 15 V D8 1 k
+IN 0.7 mA
+IN
53.2 mA

47 13.6 mA 12 mA 47
D2 4.6 mA 15 V D2 15 V
10.02 V

2.3 mA
9.97 V

ADA4077 ADA4077 14.3 mA

15 V 15 V

15 V 15 V
Figure 8. ADA4077 current path when V+ is absent (10 V input and 47 output load).

V+ V+
2.63 mA 0.15 mA

V+ 3.2 V V+ 10.4 V

D3 0.16 mA V+ D3 0.15 mA V+
OVP IN OVP
V+ D4 D7 OUT V+ D4 D7 OUT 0.428 V
D5 D6 0.16 mA 2.543 V D5 D6 0.15 mA
9.97 D1 D8 10.00 D1 D8 1 k
+IN OVP 51.37 mA +IN OVP 8.95 mA
V 47 54 mA V 9.1 mA 47
D2 D2
2.47 mA
ADA4177 51.53 mA ADA4177 9.10 mA
V V

V V

Figure 9. ADA4177 current path when V+ is absent (10 V input and 47 output load).

V+ V+
51.9 mA
V+
V+
D3 V+
D3 V+
IN
V+ D7 IN
D4 8.71 V V+ D4 D7
D5 D6 OUT
D1 D8 D5 D6 8.2 mA OUT
9.56 V 8.2 mA D1 D8 7.99 V
+IN
D2 +IN
V
D2 V
ADA4084 60.1 mA ADA4084
V 60.1 mA
V
V
15 V
Figure 10. ADA4084 current path when V+ is absent (10 V input).

8 Analog Dialogue Volume 50 Number 4

Table 8. ADA4177 with Load at Output Pin or Absent Power Pin
ADA4177-2 Condition IN (V) V+ V ISY+ (mA) ISY (mA) IB+ (mA) IOUT (mA) OUT (V)

V+ absent Vo or V+ is floating and negative input 10.02 12.33 15 0 4.31 4.18 0.039 12.32

Vo 47 to GND 9.97 3.218 15 0 51.53 2.473 2.632 2.543

Vo 47 to GND and 1 k 10 10.4 15 0 9.10 0.003 0.147 0.428

Table 9
ADA4084-2 Condition V+ V I+ (mA) I (mA) IB+ (mA) IOUT (mA) IN (V) OUT (V)

All power 15 15 1.38 1.37 0.001 0.0001 10 9.98

V+ absent and positive input 8.71 15 0 60.1 60.102 51.89 9.56 7.99

In system applications, different op amps, different topology (such as
noninverting amplification, inverting amplification, and difference amplifi-
cation), different load, and external connections can be implemented.
If one power supply is absent, the risks need to be evaluated. This article
can provide guidance on setting up the evaluation circuit (Figure 2), how
to analyze the current path, and evaluate the potential risks.
We tested three ADI op amps in a power supply absent application
(ADA4084-2, ADA4077-2, and ADA4177-2). When integrated with internal
resistors, the ADA4077-2 proved to be very robust. The ADA4177, when
integrated with an OVP circuit, delivered the best robustness. In applications
where the power may be absent, and external current-limiting resistors cant
be added, the ADA4177 is recommended to avoid degrading the precision.

Summary
To avoid overvoltage or latch-up situations, operational amplifier power
supplies must be established simultaneously. General guidelines are:
XX During the Power On sequence, turn on the supply first, then apply a
signal at the input
XX During the Power Off, turn off the input signal first, then turn off the
power supply
In real-world applications, these guidelines may be difficult to adhere to.
This can cause problems, especially when there is an input signal, and
designers need to properly evaluate the risk. An effective solution is try to
limit the input current of the op amp so it is within the specifications in the
data sheet. Adding a current-limiting resistor at the input and output can
help in applications where power cant be supplied at the same time.
References
ADA4077 data sheet. Analog Devices, Inc.
ADA4177 data sheet. Analog Devices, Inc.
Arkin, Michael and Eric Modica. Robust Amplifiers Provide Integrated
Overvoltage Protection. Analog Dialogue, Volume 46, Number 1, 2012.
Blanchard, Paul and Brian Pelletier. Using ESD Diodes as Voltage Clamps.
Analog Dialogue, Volume 49, Number 10, 2015.
For more information on the ADA4177 and ADA4077, see the product
pages and data sheets here: ADA4177 and ADA4077.

David Guo
David Guo [david.guo@analog.com] is a product applications engineer for
ADIs linear products. He started working in the China Central Application Also by this Author:
Center of ADI as an applications engineer in 2007 and transferred to the Low Power, Unity-Gain
Precision Amplifier Group as an applications engineer in June, 2011. Since Difference Amplifier
Implements Low Cost
January 2013, David has worked as an application engineer in ADIs Linear
Current Source
Product Department, where he is responsible for the technical support of
products including precision amplifiers, instrumentation amplifiers, high Volume 45, Number 2
speed amplifiers, current sense amplifiers, multipliers, references, and
rms-to-dc products. David earned his bachelors and masters degree in
mechano-electronic engineering from Beijing Institute of Technology.

Analog Dialogue Volume 50 Number 4 9

Complete Gas Sensor Circuit
Using Nondispersive Infrared (NDIR)
By Robert Lee and Walt Kester

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Introduction
Nondispersive infrared (NDIR) spectroscopy is often used to detect gas and
measure the concentration of carbon oxides (for example, carbon monoxide
and carbon dioxide). An infrared beam passes through the sampling chamber,
and each gas component in the sample absorbs some particular frequency
of infrared. By measuring the amount of absorbed infrared at the appropriate
frequency, the concentration of the gas component can be determined. The
technique is said to be nondispersive because the wavelength that passes
through the sampling chamber is not prefiltered and instead the optical filter
is in front of the detector to eliminate all light except the wavelength, which
the selected gas molecules can absorb.
The circuit shown in Figure 1 is a complete thermopile-based gas sensor
using the NDIR principle. This circuit is optimized for CO2 sensing, but can
also accurately measure the concentration of a large number of gases by
using thermopiles with different optical filters.
The printed circuit board (PCB) is designed in an Arduino shield form factor
and interfaces to the EVAL-ADICUP360 Arduino-compatible platform board.
The signal conditioning is implemented with the AD8629 and the ADA4528-1
low noise amplifiers and the ADuCM360 precision analog microcontroller,
which contains programmable gain amplifiers, dual, 24-bit, - analog-to-
digital converters (ADCs), and an ARM Cortex-M3 processor.
ADC3
ADC0
15 nF
47 k
220 3.3 V
AD8629 ADC1
8.2 nF
15 nF
47 k
The thermopile sensor is composed of a large number of thermocouples
connected usually in series or, less commonly, inparallel. The output
voltage of the series connected thermocouples depends on the temperature
difference between the thermocouple junctions and the reference
junctions. This principle is called the Seebeck effect after its discoverer,
Thomas Johann Seebeck.
The circuit uses the AD8629 op amp to amplify the thermopile sensor
output signals. The relatively small output voltage of the thermopile (from
hundreds of microvolts to several millivolts) requires high gain with very
low offset and drift to avoid dc errors. The high impedance (typically
84 k) of the thermopile requires low input bias current to minimize
errors, and the AD8629 bias current is only 30 pA typical. The very low
drift with time and temperature eliminates additional errors once the
temperature measurement has been calibrated. A pulsed light source
synchronized with the ADC sampling rate minimizes the errors caused by
low frequency drift and flicker noise.
The AD8629 only has 22 nV/Hz voltage noise spectral density at 1 kHz,
which is less than the thermopile voltage noise density of 37nV/Hz.
The AD8629 also has a very low current noise spectral density of 5fA/Hz
typical at 10 Hz. This current noise flows through the 84 k thermopile
and only contributes 420 pV/Hz at 10Hz.
7 V to 12 V
EVAL-ADuCM360-ARDZ
ADP7105
VIN
VOUT
P1.3 EN/UVLO
Sense
To ADuCM360
Muxes, PGAs, ADCs
SS
GND
C6
10 nF

220

AD8629 ADC2
3.3 V
8.2 nF Dual Thermopiles with
R3 Optical Filters and Thermistor Lamp
510 k
5V
R4 0V
130 k
CO2
3.3 V
200 mV
R7
5.1 k 3.3 V
CO2 CO2
R9
330
ADA4528-1

Figure 1. NDIR gas sensing circuit (simplified schematic: all connections and decoupling not shown) circuit description.

10 Analog Dialogue Volume 50 Number 4

With the 200 mV common-mode voltage buffered by low noise amplifier
ADA4528-1, the NTC and thermopile signal output meets the requirements
of the ADuCM360 buffered mode inputAGND + 0.1 V to approximately
AVDD 0.1 V for ADuCM360 ADC buffered mode input. The CN-0338
Arduino shield board can be compatible with other types of Arduino-
A thermopile consists of a series connection of a large number of thermo-
couples, as shown in Figure 3. Compared to a single thermocouple, the
thermopile generates much higher thermoelectric voltage.
Radiation

compatible platform board with single-input ADCs only. Active Junctions

(Heated by Radiation)

The circuit chopping frequency can be 0.1 Hz to 5 Hz, selected by software.

The ADP7105 low dropout regulator generates a stable 5V output voltage Thermocouples

to drive the lamp, and is turned on and off by the ADuCM360. The soft start
feature of the ADP7105 eliminates the in-rush current when cold starting
the lamp. Reference Junctions at Reference Temperature

The ADuCM360 includes dual, 24-bit, - ADCs for simultaneous sampling
of a dual element thermopile at programmable rates of 3.5Hz to 3.906 kHz.
The data rate in the NDIR system is limited from 3.5 Hz to 483 Hz for best
noise performance.
Thermopile Detector Theory of Operation
To understand the thermopile, it is useful to review the basic theory
of thermocouples.
If two dissimilar metals are joined at any temperature above absolute zero,
there is a potential difference between them (their thermoelectric EMF or
contact potential), which is a function of the temperature of the junction
(see the thermoelectric EMF circuit in Figure 2).
V
Figure 3. Thermopile constructed of multiple thermocouples.
In the NDIR application, pulsed and filtered IR light is applied to the series
connected active junctions; the junctions are therefore heated, which in
turn generates a small thermoelectric voltage. The temperature of the ref-
erence junction is measured with a thermistor.
Many gases have permanently or nonpermanently separated centers of
positive and negative charge. The gases are able to absorb specific fre-
quencies in the infrared spectrum, which can be used for gas analysis.
When infrared radiation is incident on the gas, the energy states of atoms
vibrating in the molecules change in discrete steps when the wavelength
of the infrared matches the molecules natural frequencies or resonances.

If the two wires are joined at two places, two junctions are formed (see the
thermocouple connected to load in Figure 2). Ifthe two junctions are at
different temperatures, there is a net EMF in the circuit, and a current flows
determined by the EMF and the total resistance in the circuit (see Figure 2).
If one of the wires is broken, the voltage across the break is equal to the
net thermoelectric EMF of the circuit, and if this voltage is measured, it can
be used to calculate the temperature difference between the two junctions
(see the thermocouple voltage measurement in Figure 2). Remember
that a thermocouple measures the temperature difference between two
junctions, not the absolute temperature at one junction. The temperature at
For a majority of IR gas sensing applications, the identities of the target
gases are known; therefore, there is little need for gas spectrometry. How-
ever, the application must deal with a certain amount of cross sensitivity
between different gases if their absorption lines overlap.
Carbon dioxide has a very strong absorption band between 4200nm and
4320 nm, as shown in Figure 4.
1017
1018

the measuring junction can be measured only if the temperature of the other
Absorption Intensity (cm/mol)

1019
junction (often called the reference junction or the cold junction) is known.
1020
However, it is not so easy to measure the voltage generated by a ther- 1021
mocouple. Suppose that a voltmeter is attached to the first thermocouple
measurement circuit (see the practical thermocouple voltage measurement 1022

showing cold junction in Figure 2). The wires attached to the voltmeter 1023
form further thermocouples where they are attached. If both these addi-
tional junctions are at the same temperature (it does not matter what 1024

temperature), the law of intermediate metals states that they make no net 1025
contribution to the total EMF of the system. If they are at different tem-
peratures, they introduce errors. Because every pair of dissimilar metals in 1026
1500 2000 2500 3000 3500 4000 4500 5000 5500
contact generates a thermoelectric EMFincluding copper/solder, kovar/ Wavelength (nm)
copper (kovar is the alloy used for IC lead frames), and aluminum/kovar Figure 4. Absorption spectrum of carbon dioxide (CO2).
(at the bond inside the IC)the problem is even more complex in practical
circuits, and it is necessary to take extreme care to ensure that all the The available output range of IR sources and the absorption spectrum
junction pairs in the circuitry around a thermocouple, except for the mea- of water also govern the choice of the sensing wavelengths. Water shows
surement and reference junctions themselves, are at the same temperature. strong absorptions below 3000nm and also between 4500 nm and
Copper Copper
Metal A Metal A R Metal A Metal A Metal A Metal A V Metal A
V1 V2
I T3 T4
Thermoelectric
V1 T1 EMF V1 T1 T2 V2 V1 T1 T2 V2 V1 T1 T2 V2
Metal B Metal B Metal B Metal B
R = Total Circuit Resistance
I = (V1 V2) R V = V1 V2, IF T3 = T4

Thermoelectric EMF Thermocouple Thermocouple Practical Thermocouple

Connected to Load Voltage Measurement Voltage Measurement
Showing Cold Junction
Figure 2. Thermocouple principles.

Analog Dialogue Volume 50 Number 4 11

8000 nm. Any attempt to sense gas spectral lines in these regions is For the active detector output, there is a corresponding output voltage
subject to strong interference if moisture (high humidity) is present with change, V0 V:
the target gas. Figure 5 shows the absorption spectrum of carbon dioxide
overlaid with the absorption spectrum of water. (All absorption data was (V0 V ) ( I0 I ) I
FA = = =1
taken from the HITRAN database). V0 I0 I0
1017
where:
1018 FA is the fractional absorbance.
V0 is the output in zero gas.
Absorption Intensity (cm/mol)

1019
V is the output in target gas.
1020

1021
Rearranging and combining the previous two equations gives:

1022 FA = 1 e klx
1023
If k and l are held constant, FA can be plotted against x as shown in Figure 6
1024 (where kl = 115, 50, 25, 10, and 4.5). The value of FA increases with c, but
1025
eventually saturates at high gas concentrations.
1.2
1026
1500 2000 2500 3000 3500 4000 4500 5000 5500 FA = 1 eklx
Wavelength (nm)
1.0
Figure 5. Absorption spectrum of carbon dioxide overlaid with water.
kl = 115

Fractional Absorbance
0.8
If IR light is applied to a dual thermopile detector fitted with a pair of optical kl = 50
filters so that one filter is centered on 4260nm and the other on 3910 nm, kl = 25
the concentration of carbon dioxide can be measured from the ratios of the 0.6

two thermopile voltages. The optical filter that resides within the absorption kl = 10
channel serves as the detection channel and the optical filter that resides 0.4
outside the absorption spectrum serves as the reference channel. Measur-
ing errors caused by dust or diminishing radiation intensity are removed 0.2
by the use of the reference channel. It is important to note that there are kl = 4.5
no gas absorption lines at 3910nm, making this the ideal location for the 0
reference channel. 0 2 4 6 8 10
CO2 Volume Gas Concentration (%)
Thermopiles used in NDIR sensing have relatively high internal resistance Figure 6. Typical fractional absorbance for kl = 4.5, 10, 25, 50, 115.
and 50 Hz/60 Hz power-line noise can couple into the signal path. The ther-
mopile can have source impedances of about 100k causing the thermal This relationship implies that for any fixed setup, the ability to resolve a
noise to dominate the system. For example, the thermopile detector change in gas level is better at low concentrations than at high concentra-
chosen in the Figure 1 system has a voltage noise density of 37 nV/Hz. tions. However, k and l can be adjusted to provide the optimum absorbance
By maximizing the amount of signal coming from the detector and using for the required range of gas concentration. This means that long opti-
less gain in the circuit, it is possible to ensure the best performance of the cal paths are more suited for low gas concentrations, and short optical
gas measuring system. paths are more suited for high gas concentrations.

The best way to maximize the signal from the thermopile detector is to use The following describes a two-point calibration procedure necessary
a sample chamber with high reflective properties, which ensures that the to determine the kl constant using the ideal Beer-Lambert equation.
detector absorbs the radiation emitted from the source and not the cham- If b = kl, then:
ber itself. Using a reflective chamber to reduce the amount of radiation
absorbed by the chamber can also reduce the amount of power consumed I
by the system because a less powerful radiation source can be used. FA = 1

I0

Beer-Lambert Law for NDIR Gas Absorption FA = 1 e bx

The infrared intensity on the active detector decreases according to the
exponential relationship called the Beer-Lambert Law:
I = I0 e klx
The first part of the calibration requires applying low concentration CO2
gas (or pure nitrogen, which is 0% concentration of CO2 gas) to the
sensor assembly:

XX ACTLOW is the peak-to-peak output of the active detector in low concen-

where: tration gas.
I is the intensity in target gas.
I0 is the intensity in zero gas.
XX REFLOW is the peak-to-peak output of the reference detector in low
k is the absorption coefficient for the specific gas and filter combination. concentration gas.
l is the equivalent optical path length between the lamp and detectors. XX TLOW is the temperature of the low concentration gas.
x is the concentration of the gas.

12 Analog Dialogue Volume 50 Number 4

The second part of the calibration requires applying CO2 gas of a known Variations in the optical path length and light scattering require the addition
concentration (xCAL) to the assembly. Usually, the xCAL concentration level is of a power term, c, for accurately fitting the equation to the actual absorp-
chosen to be the maximum value of the concentration range (for example, tion data.
0.5% vol. for the industrial air quality range).
The value of the b and SPAN constants also depend upon the range of
XX ACTCAL is the peak-to-peak output of the active detector in the calibra- concentration measured. The typical concentration ranges are as follows:
tion gas of concentration xCAL.
XX Industrial air quality (IAQ): 0 to 0.5% vol. (5000ppm). Note that CO2
XX REFCAL is the peak-to-peak output of the reference detector in the
concentration in ambient air is approximately 0.04% vol., or 400 ppm.
calibration gas of concentration xCAL.
XX Safety: 0 to 5% vol.
The following two simultaneous equations in two unknowns (I0 and b) can
then be written: XX Combustion: 0 to 20% vol.
XX Process control: 0 to 100% vol.
ILOW = I0 eb(xLOW)
The exact values of b and c for a particular system are usually determined
ICAL = I0 eb(xLOW) by taking a number of data points for FA vs. the concentration, x, and then
using a curve fitting program.
Solving the two equations for I0 and b:
For a given system where the b and c constants have been determined,
xLOW the value of ZERO and SPAN can be calculated using the two-point
ACTLOW ACTLOW REFCAL xCAL xLOW calibration method.
I0 = ZERO =

REFLOW REFLOW ACTCAL The first step in the procedure it to apply a low gas concentration of xLOW
and record the following:
ACTLOW REFCAL
ln
ACTLOW: the peak-to-peak output of the active detector in low concen-
REFLOW ACTCAL XX

b= tration gas.
x CAL x LOW
XX REFLOW: the peak-to-peak output of the reference detector in low
concentration gas.
XX TLOW: the temperature of the low concentration gas in K.
Then, for a gas of unknown concentration (x), where:
The second part of the calibration requires applying CO2 gas of a known
ACT is the peak-to-peak output of the active detector in unknown gas. concentration (xCAL) to the assembly. Usually, the xCAL concentration level is
chosen to be the maximum value of the concentration range (for example,
REF is the peak-to-peak output of the reference detector in unknown gas. 0.5% vol. for the industrial air quality range). Record the following:
T is the temperature of the unknown gas in K.
XX ACTCAL: the peak-to-peak output of active detector in the calibration gas
I ACT of concentration xCAL.
FA = 1 =1
REFCAL: the peak-to-peak output of the reference detector in the calibra-
I0
XX
REF ZERO
tion gas of concentration xCAL.
T ln (1 FA ) The following two simultaneous equations in two unknowns (I0 and SPAN)
x=
TLOW b
can then be written:

ACT I LOW c
T ln REF ZERO 1 = SPAN 1 eb(xLOW )
x= I0
TLOW b
I CAL
1 = SPAN 1 eb(xCAL c)
I0
The T/TLOW factor compensates for the change in concentration with
temperature due to the ideal gas law. Solving the two equations for ZERO and SPAN yields:

I0 = ZERO =
Modified Beer-Lambert Law
c c
Practical considerations in the NDIR implementation require modifications ACTLOW eb(xCAL ) 1 REFCAL + ACTCAL 1 eb(xLOW ) REFLOW

to the Beer-Lambert Law, as follows, to obtain accurate readings:
b(xCAL c) b(xLOW c)
e e REFCAL REFLOW
c
FA = SPAN (1 e bx )
SPAN =
The SPAN factor is introduced because not all the IR radiation that impinges ACTCAL REFLOW ACTLOW REFCAL
upon the active thermopile is absorbed by the gas, even at high concentra-
c c
tions. SPAN is less than 1 because of the optical filter bandwidth and the ACTLOW eb(xCAL ) 1 REFCAL + ACTCAL 1 eb(xLOW ) REFLOW

fine structure of the absorption spectra.

Analog Dialogue Volume 50 Number 4 13

Then, for a gas of unknown concentration (x), where: Changing C11 and C15 for various thermopiles also changes the noise
performance and the response time.
ACT is the peak-to-peak output of the active detector in unknown gas.
C9/C10
15 nF
REF is the peak-to-peak output of the reference detector in unknown gas.
T is the temperature of the unknown gas in K. R5/R8
R6/R10 47 k
bx c 220
FA = SPAN (1 e )
ADC1/
ADC2
ACT C11/C15 U3A/
FA = 1 8.2 nF U3B
REF ZERO AD8629
1
84 k
FA c
T ln 1 SPAN Thermopile
x= ADC3
TLOW b 200 mV

Figure 7. Thermopile driver equivalent circuit, G = 214.6.
This equation assumes that TLOW = TCAL.
The step function setting time of the 84 k/8.2 nF filter to 22bits
Effects of Ambient Temperature is approximately
The thermopile detector senses temperature by absorbing radiation, but
= 84 k 8.2 nF ln222 10.5 ms
it also responds to ambient temperature changes that can give rise to
spurious and misleading signals. For this reason, many thermopiles have
thermistors integrated into the package. The AD8629 noninverting amplifier is set to a gain of 214.6 and the 3 dB
cutoff frequency:
The radiation absorption is related to the number of target molecules in the
1
chamber, not the absolute percentage of target gas. Therefore the absorp- f3dB 225.75 Hz
tion is described by the ideal gas law at standard atmosphere pressure. 2 47 k 15 nF

It is necessary to record the temperature data in both the calibration state The settling time to 22 bits is approximately
and the measurement state:
= 47 k 15 nF ln222 10.75 ms
T
xT = x
TLOW The maximum NDIR chop frequency is 5 Hz, and the minimum half cycle
pulse width is therefore 100 ms. The settling time to 22bits is approxi-
where: mately 0.1 the minimum chop pulse width.
x is the concentration of gas without temperature compensation.
TLOW is the temperature in K at low and high gas concentration. The AD8629 has a 0.1 Hz to 10 Hz input voltage noise of 0.5Vp-p. Ignor-
T is the temperature in K at sampling. ing the sensor voltage noise and the AD8629 current noise, a 1 mV p-p
xT is the gas concentration at temperature T. signal output from the thermopile yields a signal-to-noise ratio (SNR) of:

In addition to the ideal gas law variation of concentration with temperature, 1 mV

SPAN and FA vary slightly with temperature and may require correction for
extremely high accuracy concentration measurements.
This article does not deal with SPAN and FA temperature correction;
however, details can be found in Application Note 1, Application Note 2,
Application Note 3, Application Note 4, and Application Note 5 from SGX
Sensortech, and the AAN-201, AAN-202, AAN-203, AAN-204, and AAN-205
application notes from Alphasense Limited.
SNR = 20 log 66 dB
0.5 V
One of the thermopiles is connected as the pseudo differential input to
the ADuCM360 ADC1/ADC3 pair, and the second isconnected to the ADC2/
ADC3 pair. The ADC3 input is connected to a common-mode voltage of
200 mV, driven by theADA4528-1 low noise amplifier. The ADA4528-1 input
0.1Hz to 10 Hz voltage noise is 99nV p-p. The 200mV common-mode volt-
age is required to keep the ADC input pins greater than 0.1V.

Thermopile Driver The gain of the AD8629 stage is 214.6, and the gain of the internal PGA
of ADuCM360 is automatically set by software from 1 to 128 to ensure
The HTS-E21-F3.91/F4.26 thermopile (Heimann Sensor, GmbH) has an
the input signal matches the full-scale span of the ADC input, 1.2 V.
84 k internal resistance in each channel. The equivalent circuit of the
The peak-to-peak signal from the thermopile can range from a few hun-
driver for one of the thermopile channels is shown in Figure 7. The internal
dred V to several mV. For instance, if the full-scale thermopile signal is
84 k thermopile resistance and the external 8.2 nF capacitor form an RC
1mVp-p, a PGA gain of 4 produces an 860mV p-p into the ADC.
low-pass noise filter with a 3dB cutoff frequency:

1 Thermopiles with different sensitivities may require a different gain in the

f3dB = 231 Hz AD8629 stage. Interfacing the CN-0338 Arduino shield board with other
2 84 k 8.2 nF
Arduino-compatible platforms may require higher gains if the platform
uses an ADC without an internal PGA.

14 Analog Dialogue Volume 50 Number 4

The easiest way to change the AD8629 gain is to change R6 and R10, which
does not affect the dominant pole frequency set by R5/R8 and C9/C10.
The thermopile output data processing algorithm can be selected in software.
The user can select between peak-to-peak and averaging algorithms
Further details regarding the acquisition of the signals, lamp pulse timing,
along with the processing algorithms for temperature compensation are
included in the CN-0338 source code found in the CN-0338 Design Sup-
port Package and in the CN-0338 User Guide.
NTC Thermistor Driver
The characteristics of the integrated NTC temperature sensor in the
thermopile are as follows:
RTH = 100 k
= 3940
The Thevenin equivalent circuit for the thermistor driver is shown in Figure 8.
The R3 and R4 divider resistors provide a 670.3mV voltage source in series
with the 103.6k. The driving voltage is 670.3mV 200mV = 470.3mV.
ADC3 ADC0
R3/R4
NTC 103.6 k
200 mV 670.3 mV
Figure 8. NTC thermistor driver equivalent circuit.
When RTH = 100 k at 25C, the voltage across the thermistor is 231mV,
and the PGA gain is therefore set at 4 when making the measurement.
The flexible input multiplexer and dual ADCs in the ADuCM360 allow
simultaneous sampling of both the thermopile signals and the temperature
sensor signal to compensate for drift.
IR Light Source Driver
The filament light source selected is the International Light Technologies
MR3-1089, with a polished aluminum reflector that requires a drive voltage
of 5.0 V at 150 mA for maximum infrared emission and the best system
performance. Heat from the lamp keeps the temperature of the optical
reflector higher than ambient, which is helpful in preventing condensation
in humid environments.
Filament lamps have a low resistance when cold (turned off), which can
result in a current surge at the instant of turn-on. A regulator with a soft
start function is useful in addressing this problem.
The ADP7105 low dropout voltage regulator has a programmable enable
pin that can be used with a general-purpose input/output pin of the
ADuCM360 to enable/disable the lamp voltage. A soft start capacitor,
C6, of 10 nF provides a soft start time of 12.2 ms, which is approximately
0.125 the minimum chop step time of 100ms.
The lamp on-current (~150 mA) is large, therefore careful circuit design
and layout is required to prevent the lamp switching pulses from coupling
into the small thermopile output voltages.
Take care to ensure the lamp return path does not flow through the sensitive
thermopile detector ground return path. The lamp current must not use the
same return path as the processorotherwise it may cause voltage offset
errors. It is strongly recommended that a separate voltage regulator be used
for the lamp drive and the signal conditioning portion of the system.
The ADP7105 lamp driver is supplied directly from the external power
supply connected to the EVAL-ADICUP360 board.
Analog Dialogue Volume 50 Number 4
Software Considerations
Synchronized Chopping and Sampling
To measure the gas concentration, the peak-to-peak signal value in both
the reference and active channel must be sampled. The ADuCM360 includes
two 24-bit, - ADCs, and the ADCs operate in continuous sampling mode.
Programmable gain amplifiers with gain options of 1, 2, 4, 8, 16, 32, 64, and
128 drive the ADCs.
The default chopping frequency is set to 0.25 Hz, and the default sampling
rate is set to 10 Hz. However, the chopping frequency can be set in the
software from 0.1 Hz to 5 Hz, and the ADC sampling rate from 3.5 Hz to
483 Hz. The software ensures that the sampling rate is at least 30 times
the chopping frequency.
For the default chopping frequency of 0.25 Hz, the thermopile data is taken
at a 10 Hz rate during the last 1.5 sec of the 2sec half cycle to ensure that
the signal has settled. The data during the first 500 ms is ignored (blanking
time). The blanking time can also be set in the software for both edges.
Note that the NTC thermistor data is taken during the blanking time.
Calibration Procedure: Ideal Beer-Lambert Equation
Because of differences in the characteristics of lamps and thermopiles,
the circuit must be calibrated initially and also after changing either the
thermopile or the lamp.
It is recommended that the entire assembly be placed in a closed chamber
where gas of a known CO2 concentration can be injected until all existing
gas in the chamber is flushed out. After stabilizing for a few minutes, the
measurements can then be made.
The calibration method and algorithms are shown in the following steps for
the ideal Beer-Lambert equation:
1. Input the following command: sbllcalibrate (standard Beer-Lambert
calibration).
2. Inject low concentration, xLOW, or zero gas (nitrogen), and stabilize
the chamber.
3. Input the CO2 concentration into the terminal.
4. The system measures ACTLOW, the peak-to-peak output of the active
detector in low concentration gas.
5. The system measures REFLOW, the peak-to-peak output of the reference
detector in low concentration gas.
6. The system measures temperature of low gas, TLOW.
7. Inject high concentration CO2, of concentration xCAL, into the chamber.
8. Input the CO2 concentration into the terminal.
9. The system measures ACTCAL, REFCAL, and the calibration
temperature, TCAL.
10. The system calculates ZERO and b:
xLOW
ACTLOW ACTLOW REFCAL xCAL xLOW
ZERO =
REFLOW REFLOW ACTCAL
ACTLOW REFCAL
ln
REFLOW ACTCAL
b =
x CAL x LOW
15
To measure an unknown concentration of CO2 gas using the ideal To measure an unknown concentration of CO2 gas using the modified
Beer-Lambert equation, do the following: Beer-Lambert equation, do the following:

1. Apply the unknown concentration of gas to the chamber and stabilize. 1. Apply the unknown concentration of gas to the chamber and stabilize.
2. Measure ACT, the peak-to-peak output of the active detector. 2. Measure ACT, the peak-to-peak output of the active detector.
3. Measure REF, the peak-to-peak output of the reference detector. 3. Measure REF, the peak-to-peak output of the reference detector.
4. Measure the temperature, T, in Kelvin. 4. Measure the temperature, T, in kelvin.
5. Use the ZERO value from the calibration. 5. Use the ZERO and SPAN values from calibration.
6. Use the b value from the calibration. 6. Use the values of b and c that were previously determined.
7. Calculate the fractional absorbance: 7. Calculate fractional absorbance:
ACT
FA = 1 ACT
REF ZERO FA = 1
REF ZERO
Calculate the concentration and apply the ideal gas law temperature
Calculate the concentration and apply the ideal gas law temperature
compensation:
compensation:
ACT 1
T ln REF ZERO
x= FA c
TLOW b T ln 1 SPAN
x=

TLOW b

This procedure assumes that TLOW = TCAL.
This procedure assumes that TLOW = TCAL.
Note that the CN-0338 software will automatically perform Steps 2
through 7.
NTC Thermistor Algorithm and Calculations
Calibration Procedure: Modified Beer-Lambert Equation The NTC thermistor equivalent circuit is shown in Figure 9.
If the constants b and c are known from measurements, use the following 3.3 V
procedure. ADC3 3.3 V ADC0
R7
5.1 k R3
200 mV
1. Input the following command: mbllcalibrate (modified Beer-Lambert NTC 510 k
calibration). R9
330 R4
2. Input the b and c constants. ADA4528-1
130 k

3. Inject low concentration CO2 gas, xLOW (nitrogen), and stabilize

the chamber. Figure 9. NTC thermistor circuit.
4. Input the CO2 concentration into the terminal.
The voltage across the thermistor is:
5. The system measures ACTLOW, the peak-to-peak output of the active
detector in low gas. (R4 R7 R3 R9) RNTC VCC
6. The system measures REFLOW, the peak-to-peak output of the reference VNTC =
(R7 + R9) [R4 RNTC + R3 (R4 + RNTC)]
detector in low gas.
7. The system measures the temperature, TLOW.
where:
8. Inject high concentration CO2, of concentration xCAL, into the chamber. VCC is 3.3 V.
9. Input the CO2 concentration into the terminal. RNTC is thermistor resistance.
10. The system measures ACTCAL, REFCAL, and the calibration
The NTC thermistor resistance can be expressed as:
temperature, TCAL.
11. The system calculates ZERO and SPAN: 1 1 1 RNTC
= + ln
T T0 RTH
ZERO =
c c
ACTLOW eb(xCAL ) 1 REFCAL + ACTCAL 1 eb(xLOW ) REFLOW where:

RTH is the thermistor resistance at temperature T0.
b(xCAL c) c is a parameter given in the NTC thermistor data sheet.
e eb(xLOW ) REFCAL REFLOW
RNTC is the the thermistor resistance at temperature T.
SPAN =
ACTCAL REFLOW ACTLOW REFCAL
c c
ACTLOW eb(xCAL ) 1 REFCAL + ACTCAL 1 eb(xLOW ) REFLOW

16 Analog Dialogue Volume 50 Number 4

Combining the two equations yields:

T=
T0
R3 R4 (R7 + R9) VNTC
+ T0 ln

(R4 R7 R3 R9) RTH VCC (R3 + R4) (R7 + R9) RTH VNTC

During each lamp chopping time interval, the ADC is switched to NTC A functional diagram of the test setup is shown in Figure 12 and a
sampling, as shown in Figure 10. photograph of the EVAL-CN0338-ARDZ Arduino shield board and the EVAL-
ADICUP360 Arduino-compatible platform board is shown in Figure 13.
NTC NTC NTC
Sample Sample Sample

7 V to 12 V EVAL-CN0338-ARDZ PC
Power
Thermopile Thermopile Thermopile
Sample Sample Sample
USB
EVAL-ADICUP360

Figure 12. Test setup functional block diagram.

Figure 10. Timing of NTC and thermopile sampling and
lamp chopping. Thermopile

User Interactive Interface Lamp

The EVAL-ADICUP360 platform board connects to a PC via the USB port.
The board appears as a virtual COM device. Any type of serial port terminal
can be used to interact with the EVAL-ADICUP360 board for development
and debugging. Further details regarding the operation of the software are
included in the CN-0338 Circuit Note. EVAL-CN0338-ARDZ
Shield Board

Figure 11 shows the fractional absorbance (FA) as a function of CO2 SPI Pmod
concentration for a typical EVAL-CN0338-ARDZ board. I2C Pmod

0.20
EVAL-ADICUP360
0.18 Arduino-Compatible
Development
Platform Board
0.16
Fractional Absorbance

0.14

0.12
User USB
0.10
Debug USB
0.08 Power
Figure 13. EVAL-CN0338-ARDZ board and EVAL-ADICUP360
0.06
board photos.
0.04

0.02 Summary
0 The analog electronics needed to implement the NDIR measurement
require precision low noise amplification and high resolution analog-
0

5000

10000

15000

20000

25000

30000

35000

40000

45000

50000

to-digital conversion. The circuit described in this article is a highly

CO2 Concentration (ppm)
integrated solution that utilizes the ADuCM360 precision analog
Figure 11. Fractional absorbance vs. CO2 concentration for microcontroller to perform the precision PGA function, the precision
the typical EVAL-CN0338-ARDZ board. - ADC conversion, and the digital control and processing.
A complete design support package for the EVAL-CN0338-ARDZ board The Arduino shield-compatibility allows for rapid prototyping of
including layouts, bill of materials, schematics, and source code can be NDIR designs with the ability to tailor the software to the specific
found at www.analog.com/CN0338-DesignSupport. application requirements.

Analog Dialogue Volume 50 Number 4 17

References
Application Note 1, A Background to Gas Sensing by Nondispersive CN-0338 Design Support Package:
Infrared. SGX Sensortech, 2007. www.analog.com/CN0338-DesignSupport. Analog Devices, Inc.

Application Note2, Signal Processing for Infrared Gas Sensors.
SGX Sensortech, 2007.
Application Note 3, Design of Microcontroller Software for Infrared Gas
Sensors. SGX Sensortech, 2007.
Application Note 4, Design of Electronics for Infrared Gas Sensors.
SGX Sensortech, 2009.
Application Note 5, Determining Coefficients for Linearisation and
Temperature Compensation. SGX Sensortech, 2009.
Application Note AAN-201, NDIR: Gas Concentration Calculation Overview.
Alphasense Limited, 2014.
HITRAN Catalog.
Micro-Hybrid, Construction and Function of Thermopiles.
MT-004 Tutorial, The Good, the Bad, and the Ugly Aspects of ADC Input
NoiseIs No Noise Good Noise? Analog Devices, Inc., 2009.
MT-031 Tutorial, Grounding Data Converters and Solving the Mystery of
AGND and DGND. Analog Devices, Inc., 2009.
MT-035, Op Amp Inputs, Outputs, Single-Supply, and Rail-to-Rail Issues.
Analog Devices, Inc., 2009.
MT-037 Tutorial, Op Amp Input Offset Voltage. Analog Devices, Inc., 2009.

Application Note AAN-202, NDIR: Electronic Interface and Signal Extraction MT-101 Tutorial, Decoupling Techniques. Analog Devices, Inc., 2009.
for Pyroelectric Sensor. Alphasense Limited, 2016.
Data Sheets and Evaluation Boards
Application Note AAN-203, NDIR: Determination of Linearisation and ADP7105 data sheet.
Temperature Correction Coefficients. Alphasense Limited, 2009.
ADuCM360 data sheet.
Application Note AAN-204, NDIR: Origin of Nonlinearity and SPAN.
Alphasense Limited, 2009. EVAL-CN0338-ARDZ Arduino Shield Board.
Application Note AAN-205, NDIR: Running the IRC-A1 at Reduced Lamp EVAL-ADICUP360 Arduino-Compatible Platform Board.
Voltages. Alphasense Limited, 2009.

CN-0338 Circuit Note, NDIR Thermopile-Based Gas Sensing Circuit.

Analog Devices, Inc., 2016.

Robert Lee
Robert Lee [robert.lee@analog.com] has been an applications engineer
at Analog Devices since January 2013. Robert received his B.S.E.E. from
University of Electronic Science and Technology of China (UESTC) in 2004
and M.S.E.E. from UESTC in 2009. He has more than 10 years of embedded
system design experience.

Walt Kester
Walt Kester [walt.kester@analog.com] is a corporate staff applications
engineer at Analog Devices. During his many years at ADI, he has designed,
developed, and given applications support for high speed ADCs, DACs, SHAs,
op amps, and analog multiplexers. An author of many papers and articles,
he prepared and edited 11 major applications books for ADIs global technical
seminar series; topics include op amps, data conversion, power management,
sensor signal conditioning, mixed-signal circuits, and practical analog design
techniques. His latest book, Data Conversion Handbook (Newnes), is a nearly
1000-page comprehensive guide to data conversion. Walt has a B.S.E.E. from
NC State University and an M.S.E.E. from Duke University.

18 Analog Dialogue Volume 50 Number 4

Rarely Asked QuestionsIssue 134
Because Mr. Ohm Said So
By Umesh Jayahoman
Share on
Question:
In my system the SPI interface for the ADC is returning 0xFF for every read.
What could be wrong?
Answer:
The new generation of GSPS (gigasample per second) ADCs (analog-to-
digital converters) offer industry-leading performance and reliability in
the systems implementation. However, if the SPI interface reads back
0xFF for every read, well, that is certainly a nonstarter. This could very
well mean something inside the ADC is not up to snuff. Let us find out
what it could be.
The latest generation of GSPS ADCs, like the AD9680 for example, is
designed on a deep submicron 65 nm CMOS process. In order to hit the
required ac performance specifications, the design had to accommodate
multiple voltage domains (1.25 V, 2.5 V, 3.3 V). Usually, any silicon device
with these multiple voltage domains will need some sort of power supply
sequencing. However, the designers at Analog Devices built in some super-
visory circuits to make the AD9680 easier for customers to implement
in their systems by eliminating the need for any power supply sequencing.
The AD9680 has an internal power-on reset (POR) nanny circuit that man-
ages all the power rails. Until this POR circuit is satisfied with the power
rail levels, the device will be in reset mode. In reset mode, if SPIVDD is at
1.8 V, 2.5 V, or 3.3 V, the ADC will send 0xFF through the SPI port for every
read. Looks like we are getting somewhere. This is where your best friend
is the old reliable digital multimeter (DMM).
Using the DMM, the first place to check would be the supply voltages at
the various pins of the AD9680. Chances are one of them is out of range
as far as the POR circuit is concerned. Now here is where things could get
Analog Dialogue Volume 50 Number 4
tricky. Take a look at Figure 1, which shows the block diagram schematic
of the AD9680-1250 being clocked at 1.25 GHz. Everything here looks
normal to someone taking a first look at the schematic. The decoupling
capacitors are not shown here, as neither are other supply domains. The
focus is on the 1.25 V domain as this is the smallest supply voltage.
1.25 V 1.12 V
~1.3 A
ADP1741
Ferrite Bead 802 mA 250 mA 220 mA
DCR = 100 m
AVDD1 + DVDD DVRDD
AVDD1_SR
AD9680
CLK
1.25 GHz
Figure 1. Powering the 1.25 V domains on the AD9680 using
the ADP1741 LDO.
The ADP1741 should have enough room to supply all the domains
connected to 1.25 V. However, the culprit here is not the LDO, nor the ADC,
but the unsuspecting ferrite bead. Usually, ferrite beads are used in power
networks to filter the power going to a certain device. One parameter of
the ferrite bead that is often overlooked is the DCR (dc resistance). So why
do we have to worry about the DCR? Because a certain gentleman by the
name of Georg Simon Ohm said so.
Ohms law states that the current through a conductor between two points
is directly proportional to the potential difference across the two points.
So, the ADP1741 LDO output might measure 1.25 V, which sounds OK.
However, if you measure the voltage at the ADC pins, or on the other side
of the ferrite bead, the DMM reads 1.12 V (assuming nominal currents).
This is the real reason why the ADC SPI was reading 0xFF. The nanny
obviously was not happy with the voltages inside the AD9680.
So what is the remedy? There are some options:
1. Choose to not use the ferrite bead. This may or may not make the
design more susceptible to noise.
2. Adjust the LDO output voltage up to account for the IR drop across
the ferrite bead. However, this could potentially expose the AD9680
to excessive voltages when an adequate amount of current isnt
being pulled.
19
3. Choose another ferrite bead that has the same impedance and current more noise immunity by providing some filtering between the AVDD,
carrying capacity, but lower DCR (less than 50 m). DVDD, and DRVDD domains.

4. Split the voltage outputs to the respective domains (AVDD1, AVDD1_SR,
DVDD, DRVDD) and use a ferrite bead with lower DCR to ensure proper
operating voltage.
Figure 2 shows Options 2 and 4, discussed above. Option 4 offers the
best compromise. However, this does add to the bill of material (BOM)
cost, which must be taken into consideration. Option 4 also provides
So the next time you plug in an ADC, clock it, and find that it doesnt
work and the SPI is returning 0xFF for every read cycle, you might have
Mr. Ohm to thank. In this case, the venerable DMM becomes your tool of
choice, not an oscilloscope or your friendly applications engineer. A ferrite
bead certainly can offer good noise immunity to your system. However, if
not chosen correctly, and if Ohms law is not heeded, this small component
can cause some serious issues in realizing an ADCs true performance in
the system.

1.275 V
1.25 V 1.12 V

~1.3 A
ADP1741
~1.3 A
ADP1741
Ferrite Bead
DCR = 30 m
Ferrite Bead
DCR = 100 m 802 mA 250 mA 220 mA
802 mA 250 mA 220 mA

1.25 V 1.26 V 1.27 V

AVDD1 + DVDD DVRDD AVDD1 + DVDD DVRDD

AVDD1_SR AVDD1_SR

AD9680 AD9680

CLK CLK

1.25 GHz 1.25 GHz

Figure 2: Different options of choosing and using a ferrite bead to power the AD9680.

Umesh Jayahoman
Umesh Jayamohan [umesh.jayamohan@analog.com] is an applications
engineer with Analog Devices in the High Speed Converter Group Also by this Author:
(Greensboro, NC). He has been a part of Analog Devices since 2010. Rarely Asked
Umesh received his B.S.E.E. from the University of Kerala, India, in 1998, Questions
and his M.S.E.E. from Arizona State University in 2002. Issue 129, May 2016
Who Ate My dBs?

20 Analog Dialogue Volume 50 Number 4

Whats Up with Digital Downconverters
Part 2
By Jonathan Harris

Share on

In the first part of this article, Whats Up with Digital Downconverters We will begin by looking at the DDC decimation filters when the complex
Part 1, we looked at the industry push for sampling higher frequencies in to real conversion block is enabled in the AD9680. This means the DDC will
higher frequency RF bands and how digital downconverters (DDCs) can be configured to accept a real input and have a real output. In the AD9680,
enable this type of radio architecture. Several technical aspects were dis- the complex to real conversion automatically shifts the input frequencies
cussed relating to the DDC that resides in the AD9680 family of products. up in frequency by an amount equal to fS/4. Figure 2 shows the low-pass
One such aspect was that higher input sampling bandwidths allow for response of the HB1 filter. This is the response of HB1 showing the real
radio architectures that can directly sample at higher RF frequencies and and complex domain response. In order to understand the real operation
convert the input signals directly to baseband. The DDC enables an RF of the filter it is important to first see the basic filter response in the real
sampling ADC to digitize such signals without the expense of a large amount and complex domains so that the low-pass response can be seen. The HB1
of data throughput. The tuning and decimation filtering that resides in the filter has a pass band of 38.5% of the real Nyquist zone. It also has a stop
DDC can be utilized to tune the input band and filter undesired frequencies. band that is 38.5% of the real Nyquist zone with the transition band making
In this installment we will take a closer look at the decimation filtering and up the remaining 23%. Likewise in the complex domain, the pass band and
apply it to the example that was discussed in Part 1. In addition we will stop band each make up 38.5% (77% total) of the complex Nyquist zone
take a look at Virtual Eval, which incorporates the ADIsimADC engine into with the transition band making up the remaining 23%. As Figure 2 illus-
a new and revamped software simulation tool. Virtual Eval will be used to trates, the filter is a mirror image between the real and complex domains.
demonstrate how closely the simulated result matches the measured data
from the example.

In Part 1, we looked at an example where we used the NCO and deci-

38.5% fS/2 38.5% fS/2
mation filtering in the DDC to see the effects of frequency folding and <0.001 dB <0.001 dB
translating in the DDC. Now we will take a closer look at the decimation
filtering and how ADC aliasing influences the effective response of the
decimation filtering. Once again we will look to the AD9680 as an example.
The decimation filter responses are normalized so that the response can
be seen and understood and can be applied to each speed grade. The
decimation filter responses simply scale with the sample rate. In the filter
response plots included here the specific insertion loss vs. frequency is
not given exactly but is figuratively shown to illustrate the approximate
response of the filter. These examples are intended to give a high level
understanding of decimation filter responses in order to understand 38.5% fS/2
>100 dB
approximately where the filter pass band and stop band reside.
100 dB
Recall that the AD9680 has four DDCs that consist of an NCO, up to four
cascaded half-band (HB) filters (which will also be referred to as decima-
tion filters), an optional 6 dB gain block, and an optional complex to real
conversion block as illustrated in Figure 1. As we discussed in Part 1, fS/2 fS/4 0 fS/4 fS/2

the signal first passes through the NCO, which shifts the input tones in Figure 2. HB1 filter responsereal and complex domain response.
frequency, then passes through the decimation, optionally through the
gain block, and optionally through the complex to real conversion. Now we can observe what happens when we place the DDC into real mode
by enabling the complex to real conversion block. Enabling the complex to
DDC 0 real conversion results in a shift of fS/4 in the frequency domain. This is illus-
Real/I Real/I trated in Figure 3, which shows the frequency shift and the resulting filter
DCM = Bypass or 2

DCM = Bypass or 2

DCM = Bypass or 2

GAIN = 0 or 6 dB

Complex to Real

Converter 0 response. Notice the solid lines and the dotted lines of the filter response.
Conversion
(Optional)

NCO
HB21 FIR
DCM = 2
HB4 FIR

HB3 FIR

HB2 FIR

+
Mixer
The solid line and shaded area indicates this is the new filter response
Real/Q (Optional) Real/Q after the fS/4 frequency shift (the resulting filter response cannot cross the
Converter 1 Nyquist boundary). The dotted lines are given for illustration to show the
filter response that would exist if not for running into the Nyquist boundary.
Figure 1. DDC signal processing blocks in the AD9680.

Analog Dialogue Volume 50 Number 4 21

 38.5% fS
77% fS/2 <0.001 dB
<0.001 dB

Complex Actual Filter Response

Portion Aliased Filter Response
Discarded

fS = Input Sample Clock

0 fS/4 fS/2 3fS/4 fS 5fS/4 3fS/4 7fS/4 2fS 9fS/4

Figure 4. HB1 effective filter response due to ADC aliasing.

100 dB
fS/4 0 fS/4 fS/2 3fS/2
Figure 3. HB1 filter responsereal DDC mode (complex to real
conversion enabled).
Notice that the HB1 filter bandwidth remains unchanged between
Figures 2 and 3. The difference between the two is the fS/4 frequency
shift and the resultant center frequency within the first Nyquist zone. Notice
however that in Figure 2 we have 38.5% of Nyquist for the real portion of
the signal and 38.5% of Nyquist for the complex portion of the signal. In
Figure 3 with the complex to real conversion block enabled there is 77%
of Nyquist for the real signal and the complex domain has been discarded.
The filter response remains unchanged apart from the fS/4 frequency shift.
Also, notice as a product of this conversion the decimation rate is now
equal to one. The effective sample rate is still fS but instead of the entire
Nyquist zone there is only 77% of available bandwidth in the Nyquist zone.
This means that with the HB1 filter and the complex to real conversion
block enabled the decimation rate equals one (see the AD9680 data
Now lets look at the case where we enable HB1 + HB2. This results in
a decimation ratio of two. Once again, the actual frequency response of
the HB1 + HB2 filters is given by the solid blue line. The center frequency
of the filter pass band is still fS/4. Enabling both HB1 + HB2 filters results
in an available bandwidth of 38.5% of the Nyquist zone. Once again,
notice the aliasing effects of the ADC and its impact on the combination
of HB1 + HB2 filters. A signal that appears at 7fS/8 will alias into the first
Nyquist zone at fS/8. Likewise a signal at 5fS/8 will alias into the first
Nyquist zone at 3fS/8. These examples with the complex to real conver-
sion block enabled can easily be extended from HB1 + HB2 to include
one or both of the HB3 and HB4 filters. Note that the HB1 filter is nonby-
passable when the DDC is enabled while HB2, HB3, and HB4 filters can
optionally be enabled.
38.5% fS/2
<0.001 dB
Actual Filter Response
Aliased Filter Response
100 dB
fS = Input Sample Clock

sheet for more information).

0 fS/8 fS/4 3fS/8 fS/2 5fS/8 3fS/4 7fS/8 fS 9fS/8

Next we will look at the filter responses of different decimation rates (that
is, enabling multiple half-band filters) and how aliasing of the ADC input
frequencies impacts the effective decimation filter responses. The actual
frequency response of HB1 is given by the solid blue line in Figure 4. The
dashed line represents the effective aliased response of HB1 due to the
aliasing effects of the ADC. Due to the fact that frequencies input into 2nd,
3rd, 4th, etc. Nyquist zones alias into the 1st Nyquist zone of the ADC,
the HB1 filter response is effectively aliased into these Nyquist zones.
For example, a signal residing at 3fS/4 will alias into the first Nyquist zone
at fS/4. It is important to understand that the HB1 filter response resides
only in the first Nyquist zone and that it is the aliasing of the ADC that
results in the effective response of the HB1 filter appearing to be aliased
into the other Nyquist zones.
Figure 5. HB1 + HB2 effective filter response due to ADC aliasing
(decimation rate = 2).
Now that the real mode operation with the decimation filters enabled has
been discussed, the complex mode of operation with the DDC can now be
examined. The AD9680 will continue to be used as an example. Similar
to the real mode operation of the DDC, the normalized decimation filter
responses will be presented. Once again, the example filter response plots
included here do not show the specific insertion loss vs. frequency, but
instead they figuratively show the approximate response of the filter. This
is done to give a high level understanding of how the filter responses are
affected by the ADC aliasing.

22 Analog Dialogue Volume 50 Number 4

With the DDC in complex mode it is configured to have a complex output
that consists of real and complex frequency domains commonly referred to
as I and Q. Recall from Figure 2 that the HB1 filter has a low-pass response
with a pass band of 38.5% of the real Nyquist zone. It also has a stop band
that is 38.5% of the real Nyquist zone with transition band making up the
remaining 23%. Likewise, in the complex domain, the pass band and stop
band each make up 38.5% (77% total) of the complex Nyquist zone with
the transition band making up the remaining 23%.
When operating the DDC in complex output mode with the HB1 filter
enabled the decimation ratio is equal to two and the output sample rate
is half of the input sample clock. Extending the plot from Figure 2 to show
the effects of the aliasing of the ADC we have what is shown in Figure 6.
The solid blue line represents the actual filter response while the dotted
blue line represents the effective aliased response of the filter due to
the aliasing effects of the ADC. An input signal at 7fS/8 will alias into the
first Nyquist zone at fS/8, placing it in the pass band of the HB1 filter.
The complex image of this same signal resides at 7fS/8 and will alias
in the complex domain to fS/8, placing it in the pass band of the HB1
filter in the complex domain.
38.5% fS/2
<0.001 dB
Actual Filter
Response
Aliased Filter
Response
Moving on, we will look at the case where HB1 + HB2 are enabled, which is
shown in Figure 7. This results in a decimation ratio of four for each I and Q
output. Once again, the actual frequency response of the HB1 + HB2 filters
is given by the solid blue line. Enabling both HB1 + HB2 filters results in an
available bandwidth of 38.5% of the decimated Nyquist zone in each of
the real and complex domains (38.5% of fS/4, where fS is the input sample
clock). Notice the aliasing effects of the ADC and its impact on the combi-
nation of HB1 + HB2 filters. A signal that appears at 15fS/16 will alias into
the first Nyquist zone at fS/16. This signal has a complex image at 15fS/16
in the complex domain and will alias into the first Nyquist zone in the com-
plex domain at fS/16. Once again these examples can be extended to the
cases where HB3 and HB4 are enabled. These are not shown in this article
but can be extrapolated easily based on the response of HB1 + HB2 shown
in Figure 7.
Some questions that come to mind when looking at all of these decimation
filter responses may be: Why do we decimate? and What advantage does
it offer? Different applications have different requirements that can benefit
from decimation of the ADC output data. One motivation is to gain signal-
to-noise ratio (SNR) over a narrow band of frequency that resides in an RF
frequency band. Another reason is less bandwidth to process, which results
in lower output lane rates across the JESD204B interface. This can allow
the use of a lower cost FPGA. By using all four decimation filters, the DDC
can realize processing gain and improve the SNR by up to 10 dB. In Table 1
we can see the available bandwidth, decimation ratio, output sample rate,
and the ideal SNR improvement offered by the different decimation filter
selections when operating the DDC in real and complex modes.

This discussion of the DDC operation has given a good insight into both
38.5% fS/2 the real and complex modes of operation of the decimation filters in the
>100 dB
AD9680. There are several advantages that are offered by utilizing the
100 dB
fS = Input Sample Clock
decimation filtering. The DDC can operate in real or complex mode and
allow the user to use different receiver topologies depending on the needs
fS 3fS/4 fS/2 fS/4 0 fS/4 fS/2 3fS/4 fS of the particular application. This can now be put together with what was
Figure 6. HB1 effective filter response due to ADC aliasing
discussed in Part 1 and help to look at a real example with the AD9680.
(decimation rate = 2)complex. This example will put measured data together with simulated data from
Virtual Eval so that the results can be compared.

Table 1. DDC Filter Characteristics for AD9680

Decimation Filter Selection Complex Output Real Output Alias Protected Ideal SNR
Bandwidth Improvement
Decimation Ratio Output Sample Rate Decimation Ratio Output Sample Rate
HB1 2 0.5 fS 1 fS 0.385 fS 1
HB1 + HB2 4 0.25 fS 2 0.5 fS 0.1925 fS 4
HB1 + HB2 + HB3 8 0.125 fS 4 0.25 fS 0.09625 fS 7
HB1 + HB2 + HB3 + HB4 16 0.0625 fS 8 0.125 fS 0.048125 fS 10

38.5% fS/4
<0.001 dB

Actual Filter Response

Aliased Filter Response

38.5% fS/4
>100 dB

100 dB
fS = Input Sample Clock

fS 7fS/8 3fS/4 5fS/8 fS/2 3fS/8 fS/4 fS/8 0 fS/8 fS/4 3fS/8 fS/2 5fS/8 3fS/4 7fS/8 fS

Figure 7. HB1 + HB2 effective filter response due to ADC aliasing (decimation rate = 4)complex.

Analog Dialogue Volume 50 Number 4 23

 Spectrum at ADC Output fs = 491.52 MSPS
Image 153.1 MHz

3rd Harmonic 2nd Harmonic

fs/2 7fs/16 3fs/8 5fs/16 fs/4 3fs/16 fs/8 fs/16 fs/16 fs/8 3fs/16 fs/4 5fs/16 3fs/8 7fs/16 fs/2
245.76 245.76

4.94 MHz Image

Spectrum After NCO Shift

3rd Harmonic 2nd Harmonic

fs/2 7fs/16 3fs/8 5fs/16 fs/4 3fs/16 fs/8 fs/16 fs/16 fs/8 3fs/16 fs/4 5fs/16 3fs/8 7fs/16 fs/2

4.94 MHz
Spectrum After Decimate by 2 HB1 Filter
3rdHarmonic and Image Reduced 2nd Harmonic

3rd Harmonic Image

fs/2 7fs/16 3fs/8 5fs/16 fs/4 3fs/16 fs/8 fs/16 fs/16 fs/8 3fs/16 fs/4 5fs/16 3fs/8 7fs/16 fs/2

4.94 MHz
Spectrum After Decimate by 4 HB2 Filter
3rd Harmonic Filtered
36.38 MHz
2nd Harmonic
59.28 MHz
Image

fs/2 7fs/16 3fs/8 5fs/16 fs/4 3fs/16 fs/8 fs/16 fs/16 fs/8 3fs/16 fs/4 5fs/16 3fs/8 7fs/16 fs/2

Figure 8. Signals as they pass through the DDC signal processing blockdecimation filtering shown.

In this example the same conditions as were used in Part 1 will be Spectrum After Decimate by 2:
used. The input sample rate is 491.52 MSPS and the input frequency is 1. The fundamental frequency stays at 4.94 MHz.
150.1 MHz. The NCO frequency is 155 MHz and the decimation rate is set
to four (due to the NCO resolution, the actual NCO frequency is 154.94 MHz). 2. The image of the fundamental translates down to 59.28 MHz and is
This results in an output sample rate of 122.88 MSPS. Since the DDC is attenuated by the HB1 decimation filter.
performing complex mixing the complex frequency domain is included in
the analysis. Note that the decimation filter responses have been added 3. The 2nd harmonic stays at 36.38 MHz.
and are shown in dark purple in Figure 8.
4. The 3rd harmonic is attenuated by the HB1 decimation filter.
Spectrum After the NCO Shift:
Spectrum After Decimate by 4:
1. The fundamental frequency shifts from +150.1 MHz down to 4.94 MHz.
1. The fundamental stays at 4.94 MHz.
2. The image of the fundamental shifts from 150.1 MHz and wraps
around to +186.48 MHz. 2. The image of the fundamental stays at 59.28 MHz and is attenuated
by the HB2 decimation filter.
3. The 2nd harmonic shifts from 191.32 MHz down to 36.38 MHz.
3. The 2nd harmonic stays at 36.38 MHz and is attenuated by the HB2
4. The 3 harmonic shifts from +41.22 MHz down to 113.72 MHz.
rd
decimation filter.

4. The 3rd harmonic is filtered and virtually eliminated by the HB2

decimation filter.

24 Analog Dialogue Volume 50 Number 4

The actual measurement on the AD9680-500 is shown in Figure 9. The
fundamental frequency is at 4.94 MHz. The image of the fundamental
resides at 59.28 MHz with an amplitude of 67.112 dBFS, which means
that the image has been attenuated by approximately 66 dB. The 2nd
harmonic resides at 36.38 MHz and has been attenuated by approximately
10 dB to 15 dB. The 3rd harmonic has been filtered sufficiently so that it
does not rise above the noise floor in the measurement.

4.94 MHz

59.28 MHz
Figure 11. AD9680 speed grade selection and block diagram in
Virtual Eval.
36.38 MHz

Next, the input conditions must be set in order to perform the FFT simu-
lation (see Figure 12). Recall the test conditions for the example include a
clock rate of 491.52 MHz and an input frequency of 150 MHz. The DDC is
enabled with the NCO frequency set to 155 MHz, the ADC input is set to
Real, the complex to real conversion (C2R) is Disabled, the DDC decimation
rate is set to Four, and the 6 dB gain in the DDC is Enabled. This means
the DDC is set up for a real input signal and a complex output signal with
a decimation ratio of four. The 6 dB gain in the DDC is enabled in order
Figure 9. FFT complex output of signal after DDC with NCO = 155 MHz to compensate for the 6 dB loss due to the mixing process in the DDC.
and decimate by 4.
Virtual Eval will show only noise or distortion results at a time, so two plots
Now Virtual Eval can be used to see how the simulated results compare are included where one shows the noise results (Figure 12) and the other
to the measured results. To begin, open the tool from the website and shows the distortion results (Figure 13).
select an ADC to simulate (see Figure 10). The Virtual Eval tool is on the
Analog Devices website at Virtual Eval. The AD9680 model that resides in
Virtual Eval incorporates a new feature being developed that allows the
user to simulate different speed grades of ADCs. This feature is key to the
example since the example utilizes the AD9680-500. Once Virtual Eval
loads, the first prompt is to select a product category and a product. Notice
that Virtual Eval not only covers high speed ADCs but also has product
categories for precision ADCs, high speed DACs, and integrated/special
purpose converters.

Figure 12. AD9680 FFT simulation in Virtual Evalnoise results.

Figure 10. Product category and product selection in Virtual Eval.

Select the AD9680 from the product selection. This will open up the main
page for the simulation of the AD9680. The Virtual Eval model for the
AD9680 also includes a block diagram that gives details on the internal
configuration of the ADC analog and digital features. This block diagram
is the same as the one given in the data sheet for the AD9680. From this
page select the desired speed grade from the drop-down menu on the
left side of the page. For the example here, select the 500 MHz speed
grade as shown in Figure 11.
Figure 13. AD9680 FFT simulation in Virtual Evaldistortion results.

Analog Dialogue Volume 50 Number 4 25

There are many performance parameters that are denoted in Virtual Eval.
The tool gives the harmonic locations as well as the location of the funda-
mental image, which can be very handy when frequency planning. This can
help make frequency planning a bit easier by allowing the user to see if the
fundamental image or any harmonic tones show up in the desired output
spectrum. The simulation in Virtual Eval gives an SNR value of 71.953 dBFS
and an SFDR of 69.165 dBc. Consider for a moment, however, that the
fundamental image would not typically be in the output spectrum and if we
remove that spur, then the SFDR is 89.978 dB (which is 88.978 dBc when
referred to the 1 dBFS input power).
Figure 14. AD9680 FFT measurement result.
Jonathan Harris [ jonathan.harris@analog.com] is a product applications
engineer inthe Space Products Group at Analog Devices in Greensboro, NC.
He has over 10 years of experience as an applications engineer support-
ing products in the RF industry. Jonathan received his M.S.E.E. from Auburn
University and his B.S.E.E. from UNC Charlotte. In his spare time he enjoys
motorcycle riding, college football, mobile audio, and spending time with
his family.
26
The Virtual Eval simulator does not include the fundamental image when
it calculates the SNR. Make sure to adjust the settings in VisualAnalog to
ignore the fundamental image in the measurement to achieve the correct
SNR. The idea is to frequency plan where the fundamental image is not
in the desired band. The measured result for the SNR is 71.602 dBFS,
which is quite close to the simulated result of 71.953 dBFS in Virtual Eval.
Likewise, the measured SFDR is 91.831 dBc, which is very close to the
simulated result of 88.978 dBc.
Virtual Eval does an incredible job at accurately predicting the behavior
of hardware. Device behavior can be predicted from the comfort of a nice
chair with a good hot cup of coffee or tea. Particularly in the case of an
ADC with DDCs such as the AD9680, Virtual Eval is able to simulate the
ADC performance including images and harmonics well enough that the
user can frequency plan and keep these undesired signals out of band
where possible. As carrier aggregation and direct RF sampling continue to
increase in popularity, having a tool in the tool box like Virtual Eval is quite
handy. The ability to accurately predict ADC performance and frequency
plan aids system designers to properly frequency plan a design in applica-
tions such as communication systems, as well as military/aerospace radar
systems and many other types of applications. I would encourage you to
take advantage of the digital signal processing features in the latest gen-
eration ADCs from Analog Devices. I would also recommend using Virtual
Eval to help plan out your next design and have an idea ahead of time of
the expected performance.
Jonathan Harris
Analog Dialogue Volume 50 Number 4
Fully Automatic Self-Calibrated Conductivity
Measurement System
By Robert Lee and Walt Kester
Share on
Introduction
The increasing importance of monitoring water quality has led to the devel-
opment of a number of related sensors and signal conditioning circuits.
Water quality is measured in terms of bacteria count, pH level, chemical
content, turbidity, and conductivity. All aqueous solutions conduct electricity
to some degree. Adding electrolytes such as salts, acids, or bases to pure
water increases the conductivity and decreases resistivity. This article
focuses on conductivity measurements.
Pure water does not contain significant amounts of electrolytes and
conducts only a small amount of electric current when a sample is sub-
jected to an applied voltageits conductivity is therefore low. On the other
hand, a large quantity of electrolytes in the sample causes more current to
be conductedits conductivity is higher.
It is more common to think in terms of resistance rather than conduc-
tance, but the two are reciprocals. The resistivity, , of a material or
liquid is defined as the resistance of a cube of the material with perfectly
conductive contacts on opposite faces. The resistance, R, for other
shapes, can be calculated by
R = L/A (1)
where:
Lis the distance between the contacts.
Ais the area of the contacts.
Resistivity is measured in units of cm. A 1 cm material has a resistance
of 1 when contacted on opposite faces of a 1 cm 1 cm 1 cm cube.
Conductance is simply the reciprocal of resistance, and conductivity is the
reciprocal of resistivity. The unit of measurement of conductance is siemens
(S), and the unit of measurement of conductivity is S/cm, mS/cm, or S/cm.
For the purposes of this article, Y is the general symbol for conductivity
measured in S/cm, mS/cm, or S/cm. However, in many cases, the
distance term is dropped for convenience, and the conductivity is simply
expressed as S, mS, or S.
Measuring Conductivity Using Conductivity Cells
A conductivity system measures conductivity by means of electronics
connected to a sensor, called a conductivity cell, immersed in a solution,
as shown in Figure 1.
Analog Dialogue Volume 50 Number 4
To I/V
Converter
V
EVAL-CN0359-EB1Z
A = Area of Electrode Surface (cm2)
L = Distance Between Electrodes (cm)
A I A V = Excitation Voltage
I = Cell Current
K = L/A = Cell Constant (cm1)
Y = Measured Conductance = I/V (S)
L YX = Water Conductivity = K Y (S/cm)
Figure 1. Interface between conductivity cell and electronics
(EVAL-CN0359-EB1Z).
The electronic circuitry impresses an alternating voltage on the sensor
and measures the size of the resulting current, which is related to the
conductivity. Because conductivity has a large temperature coefficient
(up to 4%/C), an integral temperature sensor is incorporated into the
circuitry to adjust the reading to a standard temperature, usually 25C
(77F). When measuring solutions, the temperature coefficient of the
conductivity of the water itself must be considered. To compensate accu-
rately for the temperature, a second temperature sensor and compensation
network must be used.
The contacting type sensor typically consists of two electrodes that are
insulated from one another. The electrodes, typically Type 316 stainless
steel, titanium palladium alloy, or graphite, are specifically sized and
spaced to provide a known cell constant. Theoretically, a cell constant of
1.0/cm describes two electrodes, each sized 1 cm2in area, and spaced
1 cm apart. Cell constants must be matched to the measurement system
for a given range of operation. For instance, if a sensor with a cell
constant of 1.0/cm is used in pure water with a conductivity of 1 S/cm,
the cell has a resistance of 1 M. Conversely, the same cell in seawater
has a resistance of 30 . Because the resistance ratio is so large, it is
difficult for ordinary instruments to accurately measure such extremes
with only one cell constant.
27
When measuring the 1 S/cm solution, the cell is configured with large
area electrodes spaced a small distance apart. For example, a cell with a
cell constant of 0.01/cm results in a measured cell resistance of approx-
imately 10 k rather than 1 M. It is easier to accurately measure 10 k
than 1 M; therefore, the measuring instrument can operate over the
same range of cell resistance for both ultrapure water and high conductivity
seawater by using cells with different cell constants.
The cell constant, K, is defined as the ratio of the distance between the
electrodes, L, to the area of the electrodes, A:
K = L/A (2)
The instrumentation then measures the cell conductance, Y:
Y = I/V (3)
The conductivity of the liquid, YX, is then calculated:
YX = K Y (4)
There are two types of conductivity cells: those with two electrodes and
those with four electrodes, as shown in Figure 2. The electrodes are often
referred to as poles.
2-Pole 4-Pole
Figure 2. 2-pole and 4-pole conductivity cells.
The 2-pole sensor is more suitable for low conductivity measurements,
such as purified water, and various biological and pharmaceutical liquids.
The 4-pole sensor is more suitable for high conductivity measurements,
such as waste water and seawater analysis.
The cell constants for 2-pole cells range from approximately 0.1/cm to
1/cm, and the cell constants for 4-pole cells range from 1/cm to 10/cm.
The 4-pole cell eliminates the errors introduced by polarization of the
electrodes and field effects that can interfere with the measurement.
28
The actual configuration of the electrodes can be that of parallel rings, coaxial
conductors, or others, rather than the simple parallel plates shown in Figure 2.
Regardless of the type of cell, it is important not to apply a dc voltage to
any electrode because ions in the liquid will accumulate on the electrode
surface, thereby causing polarization, measurement errors, and damage to
the electrode.
Take special care with sensors that have shields, as in the case of coaxial
sensors. The shield must be connected to the same potential as the metal
container holding the liquid. If the container is grounded, the shield must
be connected to the circuit board ground.
The final precaution is not to exceed the rated excitation voltage or
current for the cell. The following circuit allows programmable excitation
voltages from 100 mV to 10 V, and the R23 (1 k) series resistor limits
the maximum cell current to 10 mA.
Circuit Description
The circuit shown in Figure 3 is a completely self-contained, micropro-
cessor controlled, highly accurate conductivity measurement system that
is ideal for measuring the ionic content of liquids, water quality analysis,
industrial quality control, and chemical analysis.
A carefully selected combination of precision signal conditioning compo-
nents yields an accuracy of better than 0.3% over a conductivity range of
0.1 S to 10 S (10 M to 0.1 ) with no calibration requirements.
Automatic detection is provided for either 100 or 1000 platinum
(Pt) resistance temperature devices (RTDs), allowing the conductivity
measurement to be referenced to room temperature.
The system accommodates 2- or 4-wire conductivity cells, and 2-, 3-, or
4-wire RTDs for added accuracy and flexibility.
The circuit generates a precise ac excitation voltage with minimum dc offset
to avoid a damaging polarization voltage on the conductivity electrodes.
The amplitude and frequency of the ac excitation is user-programmable.
An innovative synchronous sampling technique converts the peak-to-peak
amplitude of the excitation voltage and current to a dc value for accuracy
and ease in processing using the dual, 24-bit, - ADC contained within
the precision analog microcontroller.
The intuitive user interface is an LCD display and an encoder push button.
The circuit can communicate with a PC using an RS-485 interface if
desired, and it operates on a single 4 V to 7 V supply.
The excitation square wave for the conductivity cell is generated by
switching theADG1419between the +VEXC and VEXC voltages using
the PWM output of theADuCM360microcontroller. It is important that the
square wave has a precise 50% duty cycle and a very low dc offset.
Even small dc offsets can damage the cell over a period of time.
Analog Dialogue Volume 50 Number 4
 +3.3 V
J2 J4 S1
AVDD ADM3483 J-Link Encoder
R13 AIN0 RS-485 PEC11R-S
J3 ADC0 PWM0
1 1.5 k
100 or AIN7/IEXC +15 V
ADC1 AIN1 PWM1
1000 J1
Pt RTD 2 AIN8 AIN2 15 V
ADC2 PWM2 +4 V to +7 V
AIN6 ADC3 AIN3 +3.3 V
ADuCM360 128 64
LCD Power
RX AIN5/IEXC P0.0 U2WRI +1.65 V Supplies
+3.3 V MCCOG128064A6S-SPTLY
AIN6 P2.0 U4WRI
3 AIN5/IEXC +VEXC
1 k P1.2 A0
AIN7/IEXC
+0.115 V P2.1 A1 VEXC
4
AIN9 AIN8
36 AIN9 DAC
AGND EP
R20
1.2 k
ADG1419
R23 +VEXC ADG1211 820 pF
R34
430 +15 V R19
J5 1 1 k VEXC G1 = 1, 10, 100, 1000 ADA4638-1 7.5 k +3.3 V
PWM0 +15 V AD8253 C50
2 U10 24
A0, A1, PWM1 4.7 F U12B ADC3
V1P-P U2WRI 15 V
U15 ADA4528-2 10 nF
1 k +1.65 V
5 430 R31
YX REF
1 nF 1.2 k
15 V ADG1211
ADA4000-1 VOUT1 =
+3.3 V R36 820 pF
3 +15 V G1 0.16 V1P-P
430 +15 V R29
4 ADA4638-1 7.5 k
U14 +1.65 V U22B C73
4.7 F U13 24
PWM2
Conductivity 15 V U12A ADC2
15 V
Cell 470 k 1 k +1.65 V ADA4528-2 10 nF

1 nF AD8542 1 nF

IP-P R38
1 nF 1.2 k
ADG1211
R41 820 pF
R47,1.0 k
G2 = 1, 10, 100, 1000 430 +15 V R37
+15 V ADA4638-1 7.5 k +3.3 V
+15 V AD8253 C84 U16 24
A0, A1, 4.7 F
PWM1 U20B ADC1
ADA4627-1 U19 U4WRI
V2P-P 15 V
U18 +1.65 V ADA4528-2 10 nF
430 1 k
15 V REF R52
ADG1211 1 nF 1.2 k
VOUT2 =
15 V R42 G1 0.16 V2P-P
430 +15 V R48
G2 VOUT2 820 pF
YX = 1 mS ADA4638-1 7.5 k
G1 VOUT1 +1.65 V U22A C93
4.7 F U21 24
PWM2 U20A ADC0
15 V
+1.65 V ADA4528-2 10 nF
1 k
AD8542 1 nF

Figure 3. High performance conductivity measurement system (simplified schematic: all connections and decoupling not shown).

The +VEXC and VEXC voltages are generated by theADA4077-2op amps a dropout voltage of less than 1.2 V. The U9A op amp has a closed-loop gain
(U9A and U9B), and their amplitudes are controlled by the DAC output of of 8.33 and converts the ADuCM360 internal DAC output (0 V to 1.2 V) to
the ADuCM360, as shown in Figure 4. the +VEXC voltage of 0 V to 10 V. The U9B op amp inverts the +VEXC and
generates the VEXC voltage. R22 is chosen such that R22 = R24||R27 to
R14
110 k achieve first-order bias current cancellation. The error due to the 15 V
offset voltage of U9A is approximately (2 15 V) 10 V = 3 ppm. The
1 nF
R15
primary error introduced by the inverting stage is therefore the error in the
15 k +15 V resistor matching between R24 and R27.
G = 8.33 +VEXC
R16
DAC 13 k
U9A The ADG1419 is a 2.1 , on-resistance SPDT analog switch with an
from + ADA4077-2 0 V to +10 V
ADuCM360 on-resistance flatness of 50 m over a 10 V range, making it ideal
0 V to +1.2 V
R27
for generating a symmetrical square wave from the VEXC voltages.
27 k The symmetry error introduced by the ADG1419 is typically 50 m
1 nF
1 k = 50 ppm. Resistor R23 limits the maximum current through the
R24 sensor to 10 V/1 k = 10 mA.
27 k
VEXC The voltage applied to the cell, V1, is measured with the AD8253
R22 U9B
13 k
0 V to 10 V
instrumentation amplifier (U15). The positive input to U15 is buffered by
+ ADA4077-2
15 V
the ADA4000-1 (U14). The ADA4000-1 is chosen because of its low bias
current of 5 pA to minimize the error in measuring low currents associ-
Figure 4. Excitation voltage sources.
ated with low conductivities. The negative input of the AD8253 does not
The ADA4077-2 has a typical offset voltage of 15 V (A grade), a 0.4 nA bias require buffering.
current, a 0.1 nA offset current, and an output current of up to 10 mA, with
The offset voltages of U14 and U15 are removed by the synchronous
sampling stage and do not affect the measurement accuracy.

Analog Dialogue Volume 50 Number 4 29

U15 and U18 are AD8253 10 MHz, 20 V/s, programmable gain (G = 1, 10,
100, 1000) instrumentation amplifiers with gain error of less than 0.04%.
The AD8253 has a slew rate of 20 V/s and a settling time of 1.8 s to
0.001% for G = 1000. Its common-mode rejection is typically 120 dB.
The U19 (ADA4627-1) stage is a precision current to voltage converter that
converts the current through the sensor to voltage. The ADA4627-1 has
an offset voltage of 120 V (typical, A grade), a bias current of 1 pA (typical),
a slew rate of 40 V/s, and a 550 ns settling time to 0.01%. The low bias
current and offset voltage make it ideal for this stage. The symmetry error
produced by the 120 V offset error is only 120 V/10 V = 12 ppm.
The U22A and U22B (AD8542) buffers supply the 1.65 V reference to the
U18 and U15 instrumentation amplifiers, respectively.
The following is a description of the remainder of the signal path in the
voltage channel (U17A, U17B, U10, U13, U12A, and U12B). The operation of
the current channel (U17C, U17D, U16, U21, U20A, and U20B) is identical.
The ADuCM360 generates the PWM0 square wave switching signal for the
ADG1419 switch as well as PWM1 and PWM2 synchronizing signals for
the synchronous sampling stages. The cell voltage and the three timing
waveforms are shown in Figure 5.
The offset voltage of the ADA4638-1 zero-drift amplifier is only 0.5 V
typical and contributes negligible error.
The final stages in the signal chain before the ADC are the ADA4528-2
inverting attenuators (U12A and U12B) that have a gain of 0.16 and a
common-mode output voltage of +1.65 V. The ADA4528-2 has an offset
voltage of 0.3 V typical and therefore contributes negligible error.
The attenuator stage reduces the 10 V maximum signal to 1.6 V with a
common-mode voltage of 1.65 V. This range is compatible with the input
range of the ADuCM360 ADC input, which is 0 V to 3.3 V (1.65 V 1.65 V)
for an AVDD supply of 3.3 V.
The attenuator stages also provide noise filtering and have a 3 dB
frequency of approximately 198 kHz.
The differential output of the voltage channel, VOUT1, is applied to the AIN2
and AIN3 inputs of the ADuCM360. The differential output of the current
channel, VOUT2, is applied to the AIN0 and AIN1 inputs of the ADuCM360.
The equations for the two outputs are given by
P-P (5)

P-P (6)
Cell Voltage +VEXC
0
The cell current is given by
VEXC
P-P P-P
(7)
PWM0

The V2P-P voltage is given by

Track V Track V
P-P = IP-P R47 (8)
PWM1
Hold V
tSETUP tHOLD

Track +V
Solving Equation 8 for IP-P and substituting into Equation 7 yields the
PWM2
Hold +V Hold +V following for YX:
tSETUP tHOLD V2P-P
YX = (9)
Figure 5. Cell voltage and track-and-hold timing signals. V1P-P R 47

The output of the AD8253 in amp (U15) drives two parallel track-and-hold
circuits composed of ADG1211 switches (U17A/U17B), series resistors Solving Equation 5 and Equation 6 for V1P-P and V2P-P and substituting into
(R34/R36), hold capacitors (C50/C73), and unity-gain buffers (U10/U13). Equation 9 yields the following:
G2 VOUT2
The ADG1211 is a low charge injection, quad SPST analog switch, operat- YX = (10)
G1 VOUT1 R 47
ing on a 15 V power supply with up to 10 V input signals. The maximum
charge injection due to switching is 4 pC, which produces a voltage error G2 VOUT2
of only 4 pC 4.7 F = 0.9 V. YX = 1 mS (11)
G1 VOUT1
The PWM1 signal causes the U10 track-and-hold buffer to track the negative Equation 11 shows that the conductivity measurement depends on G1, G2,
cycle of the sensor voltage and then hold it until the next track cycle. The output and R47, and the ratio of VOUT2 to VOUT1. Therefore, a precision reference
of the U10 track-and-hold buffer is therefore a dc level corresponding to is not required for the ADCs within the ADuCM360.
the negative amplitude of the sensor voltage square wave.
The AD8253 gain error (G1 and G2) is 0.04% maximum, and R47 is chosen
Similarly, the PWM2 signal causes the U13 track-and-hold buffer to track to be a 0.1% tolerance resistor.
the positive cycle of the sensor voltage and then hold it until the next track
cycle. The output of the U13 track-and-hold buffer is therefore a dc level From this point, the resistors in the VOUT1 and VOUT2 signal chain determine
corresponding to the positive amplitude of the sensor voltage square wave. the overall system accuracy.
The bias current of the track-and-hold buffers (ADA4638-1) is 45 pA The software sets the gain of each AD8253 as follows:
typical, and the leakage current of the ADG1211 switch is 20 pA typical.
Therefore, the worst-case leakage current on the 4.7 F hold capacitors XX If the ADC code is over 94% of full scale, the gain of the AD8253 is
is 65 pA. For a 100 Hz excitation frequency, the period is 10 ms. The drop reduced by a factor of 10 on the next sample.
voltage over one-half the period (5 ms) due to the 65 pA leakage current XX If the ADC code is less than 8.8% of full scale, the gain of the AD8253
is (65 pA 5 ms) 4.7 F = 0.07 V. is increased by a factor of 10 on the next sample.

30 Analog Dialogue Volume 50 Number 4

System Accuracy Measurements The following discussion shows simplified schematics of how the different
The following four resistors affect the accuracy in the VOUT1 voltage RTD configurations operate. All mode switching is accomplished in the
channel: R19, R20, R29, and R31. software, and there is no need to change the external jumper settings.

The following five resistors affect the accuracy in the VOUT2 current Figure 7 shows the configuration for 4-wire RTDs.
channel: R47, R37, R38, R48, and R52. ADuCM360
R13
1.5 k AIN7/
J3
Assuming that all nine resistors are 0.1% tolerance, and including the 0.04% RP 1 0.1% IEXC IEXC V7 V8
gain error of the AD8253, a worst-case error analysis yields approximately 100 or AIN8
to ADC
1000
0.6%. The analysis is included in the CN-0359 Design Support Package. Pt RTD RP 2 AIN6

In practice, the resistors are more likely to combine in an RSS manner, V6 V5

RX to ADC
and the RSS error due to the resistor tolerances in the positive or negative AIN5/
RP
signal chain is 5 0.1% = 0.22%. 3 IEXC

+3.3 V
Accuracy measurements were taken using precision resistors from 1 to
1 k
1 M (1 S to 1 S) to simulate the conductivity cell. Figure 6 shows the RP 4 +0.115 V AIN9
results, and the maximum error is less than 0.1%.
36
0.04 V6 V5
RX = 1.5 k
V7 V8

0.02 Figure 7. Configuration for 4-wire RTD connection.

0 The parasitic resistance in each of the leads to the remote RTD is shown
as RP. The excitation current (IEXC) passes through a precision 1.5 k
0.02 resistor and the RTD. The on-chip ADC measures the voltage across the
Error (%)

RTD (V6 V5) and uses the voltage across R13 (V7 V8) as a reference.
0.04
It is important that the R13 resistor and the IEXC excitation current value
0.06 be chosen such that the ADuCM360 maximum input voltage at AIN7 does
not exceed AVDD 1.1 V; otherwise, the IEXC current source does not
0.08 function properly.

0.10
1 10 0.1m 1m 10m 0.1 1
Conductivity (S)
Figure 6. System error (%) vs. conductivity of 1 S to 1 S.
RTD Measurement
Conductivity measuring system accuracy is only as good as its temperature
compensation. Because common solution temperature coefficients vary in
the order of 1%/C to 3%/C or more, measuring instruments with adjustable
temperature compensation must be used. Solution temperature coefficients
are somewhat nonlinear and usually vary with the actual conductivity as
well. Therefore, calibration at the actual measuring temperature yields the
best accuracy.
The ADuCM360 contains two matched, software configurable, excitation
current sources. They are individually configurable to provide a current
output of 10 A to 1 mA, and matching is better than 0.5%. The current
sources allow the ADuCM360 to easily perform 2-wire, 3-wire, or 4-wire
measurements for either Pt100 or Pt1000 RTDs. The software also
automatically detects if the RTD is Pt100 or Pt1000.
The RTD voltage is accurately measured using the two sense leads that
connect to AIN6 and AIN5. The input impedance is approximately 2 M
(unbuffered mode, PGA gain = 1), and the current flowing through the
sense lead resistance produces minimum error. The ADC then measures
the RTD voltage (V6 V5).
The RTD resistance is then calculated as:
V6 V5
RX = 1.5 k (12)
V7 V8
The measurement is ratiometric and does not depend on an accurate
external reference voltage, only the tolerance of the 1.5 k resistor. In
addition, the 4-wire configuration eliminates the error associated with
the lead resistances.
The ADuCM360 has a buffered or unbuffered input option. If the internal buffer
is activated, the input voltage must be greater than 100 mV. The 1 k/36
resistor divider provides a 115 mV bias voltage to the RTD that allows buff-
ered operation. In the unbuffered mode, Terminal 4 of J3 can be grounded
and connected to a grounded shield for noise reduction.

Analog Dialogue Volume 50 Number 4 31

The 3-wire connection is another popular RTD configuration that eliminates 4 V to 7 V BST
100 nF
22 H 3.3 V 3.3 V
lead resistance errors, as shown in Figure 8. VIN SW
EMI
Filter
EN
ADP2300
B120
10 k
100 nF 10 F 22 F 100 nF 7.5 k 1.65 V
R13 ADuCM360
FB
VP + 1.5 k AIN7/ GND 0.8 V 10 k
J3 2.4 k
RP 1 0.1% IEXC IEXC
V7 V8
to ADC 15 V
AIN8 15 V Unregulated EMI
100 or Filter
1000 2 AIN6 BAT54S
Pt RTD 22 F 100 nF
V8 V5 22 H
to ADC 10 F
BAT54S
RX 100 nF 47 F 1N4148 15 V
VP + EMI
AIN5/ IEXC VIN SW
RP 15 V Regulated
Filter
3 IEXC 100 nF EN
ADP1613 200 k
3.3 V
FREQ 1.235 V
FB
33 nF EMI Filters:
1 k SS COMP
18 k BNX025H01
RP 4 GND
0.115 V AIN9 3.3 nF 56 pF

36 47 k
V8 V5
RX = 1.5 k
V7 V8 Figure 10. Power supply circuits.
Figure 8. Configuration for 3-wire RTD connection.
Figure 11 shows the LCD backlight driver circuit.
The second matched IEXC current source (AIN5/IEXC) develops a voltage
3.3 V
across the lead resistance in series with Terminal 3 that cancels the
100 nF
voltage dropped across the lead resistance in series with Terminal 1. The 5.1 k
2.9 V
measured V8 V5 voltage is therefore free of lead resistance error.
3.3 V 36 k 3.3 V
Figure 9 shows the 2-wire RTD configuration where there is no compensa-
tion for lead resistance. K1 K2
3.3 V 6.8 U6B U6A 6.8 3.3 V

R13 ADuCM360
1.5 k AIN7/ 400 mV 400 mV
J3
RP 1 0.1% IEXC IEXC V7 V8
AD8592 AD8592
to ADC A1
100 or AIN8 A2
1000 60 mA LCD DISPLAY 60 mA
Pt RTD 2 AIN6
Figure 11. LCD backlight drivers.

RX
AIN5/ V8 V9
Each half of the AD8592 op amp acts as a 60 mA current source to supply
3 IEXC to ADC the LCD backlight currents. The AD8592 can source and sink up to 250 mA,
3.3 V and the 100 nF capacitor ensures a soft startup.
1 k
RP 4 0.115 V AIN9 Hardware, Software, and User Interface
36
The complete circuit including software is available as the CN-0359 Circuits
RX =
V8 V9
1.5 k 2RP
from the Lab Reference Design. The circuit board, EVAL-CN0359-EB1Z,
V7 V8 comes preloaded with the code required to make the conductivity
Figure 9. Configuration for 2-wire RTD connection. measurements. The actual code can be found in the CN-0359 Design
Support Package, in the CN0359-SourceCode.zip file.
The 2-wire configuration is the lowest cost circuit and is suitable for less
critical applications, short RTD connections, and higher resistance RTDs The user interface is intuitive and easy to use. All user inputs are from a
such as Pt1000. dual function push button/rotary encoder knob. The encoder knob can be
turned clockwise or counterclockwise (no mechanical stop), and can also
Power Supply Circuits be used as a push button.
To simplify system requirements, all the required voltages (15 V and +3.3 V) Figure 12 is a photo of the EVAL-CN0359-EB1Z board that shows the LCD
are generated from a single 4 V to 7 V supply, as shown in Figure 10. display and the position of the encoder knob.

The ADP2300 buck regulator generates the 3.3 V supply for the board. The
design is based on the downloadable ADP230x Buck Regulator Design Tool.

The ADP1613 boost regulator generates a regulated +15 V supply and an

unregulated 15 V supply. The 15 V supply is generated with a charge
pump. The design is based on the ADP161x Boost Regulator Design Tool.

Details regarding the selection and design of power supplies are available
at www.analog.com/ADIsimPower.

Use proper layout and grounding techniques to prevent the switching reg-
ulator noise from coupling into the analog circuits. See the Linear Circuit
Design Handbook, the Data Conversion Handbook, the MT-031 Tutorial,
and the MT-101 Tutorial for further details.
Figure 12. Photo of an EVAL-CN0359-EB1Z board showing the home
screen in measurement mode.

32 Analog Dialogue Volume 50 Number 4

After connecting, the conductivity cell and the RTD the board is powered
up. The LCD screen appears as shown in Figure 12.
The encoder knob is used to input the excitation voltage, excitation
frequency, temperature coefficient of the conductivity cell, the cell constant,
setup time, hold time, RS-485 baud rate and address, LCD contrast, and so
forth. Figure 13 shows some of the LCD display screens.
Summary
The circuit described in this article is based on the Analog Devices
CN-0359 reference design. Complete documentation including circuit note,
detailed schematic, bill of material, layout, Gerber files, and source code is
available at http://www.analog.com/CN0359-DesignSupport.
References
A Designers Guide to Instrumentation Amplifiers, 3rd Edition.
Analog Devices, Inc.

ADIsimPower Design Tool. Analog Devices, Inc.

CN-0359 Circuit Note, Fully Automatic High Performance Conductivity

Measurement System. Analog Devices, Inc.
Setting Screen Setting Excitation Voltage
CN-0359 Design Support Package. Analog Devices, Inc.
Figure 13. LCD display screens.
Linear Circuit Design Handbook. Analog Devices, Inc./Elsevier.
The EVAL-CN0359-EB1Z is designed to be powered with the
EVAL-CFTL-6V-PWRZ 6 V power supply. The EVAL-CN0359-EB1Z MT-031 Tutorial. Grounding Data Converters and Solving the Mystery of
requires only the power supply and the external conductivity cell AGND and DGND. Analog Devices, Inc.
and RTD for operation.
MT-101 Tutorial. Decoupling Techniques. Analog Devices, Inc.
The EVAL-CN0359-EB1Z also has an RS-485 connector, J2, that allows
Op Amp Applications Handbook. Analog Devices, Inc./Elsevier.
an external PC to interface with the board. Connector J4 is a JTAG/SWD
interface for programming and debugging the ADuCM360. Section 7: Temperature Sensors in Sensor Signal Conditioning.
Analog Devices, Inc.
Figure 14 is a typical PC connection diagram showing an RS-485 to
USB adapter. The Data Conversion Handbook. Analog Devices, Inc./Elsevier.

6V
PC
Data Sheets
Supply
AD8253 data sheet. ADA4638-1 data sheet.
AD8542 data sheet. ADG1211 data sheet.
J1
Conductivity J5
RS-485 to AD8592 data sheet. ADG1419 data sheet.
J2 USB
Cell
Adapter
ADA4000-1 data sheet. ADM3075 data sheet.
EVAL-CN0359-EB1Z
ADA4077-2 data sheet. ADP2300 data sheet.
RTD J3 J4 JTAG
ADA4528-2 data sheet. ADP1613 data sheet.

Figure 14. Test setup functional diagram. ADA4627-1 data sheet. ADuCM360 data sheet.

Robert Lee
Robert Lee [robert.lee@analog.com] has been an applications engineer
at Analog Devices since January 2013. Robert received his B.S.E.E. from Also by this Author:
University of Electronic Science and Technology of China (UESTC) in 2004 Complete Gas Sensor
and M.S.E.E. from UESTC in 2009. He has more than 10 years of embedded Circuit Using Nondis-
system design experience. persive Infrared (NDIR)
Volume 50, Number 4

Walt Kester
Walt Kester [walt.kester@analog.com] is a corporate staff applications
engineer at Analog Devices. During his many years at ADI, he has designed, Also by this Author:
developed, and given applications support for high speed ADCs, DACs, SHAs, Complete Gas Sensor
op amps, and analog multiplexers. An author of many papers and articles, he Circuit Using Nondis-
prepared and edited 11 major applications books for ADIs global technical persive Infrared (NDIR)
seminar series; topics include op amps, data conversion, power management, Volume 50, Number 4
sensor signal conditioning, mixed-signal circuits, and practical analog design
techniques. His latest book, The Data Conversion Handbook (Newnes), is a
nearly 1000-page comprehensive guide to data conversion. Walt has a B.S.E.E.
from NC State University and an M.S.E.E. from Duke University.

Analog Dialogue Volume 50 Number 4 33

Rarely Asked QuestionsIssue 135
Amplifier RF : Think Before You Choose!
By Tina Collins

Share on

7
6
5 G = 11
4 G = 21
3 G = 31
2

Normalized Closed-Loop Gain (dB)

1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Question: 16
Im selecting an op amp for my precision signal path. Isnt faster 0.1 1 10 100
Frequency (MHz)
always better?
Figure 1. Lab results for different gains with R F = 10 k. VS = 5 V,
R LOAD = 1 k for gains 11 V/V, 21 V/V, and 31 V/V.
Answer:
When selecting the feedback resistor (RF) for single-ended voltage feedback 42
and a fully differential amplifier, consideration needs to be given to the 39
36 G=2
system requirements. There are trade-offs in the selection of RF, which
33 G = 31
include power dissipation, bandwidth, and stability. If speed is critical, as 30
discussed in RAQ Issue 122, The Truth About Voltage Feedback Resistors, 27
Normalized Closed-Loop Gain (dB)

the recommended data sheet RF value is advised. If power dissipation 24

is critical, and the system requires a higher gain, a larger RF can be the 21
right choice. 18
15
12
The choices for RF increase as gain increases. The destabilizing effect
9
between the internal capacitance of the amplifier and the feedback resistor
6
is reduced with larger gains. As gain increases, the amplifier is less 3
sensitive to gain peaking. 0
3
The example of Figure 1 shows the lab results of the normalized frequency 6
response for the ADA4807-1, low noise, rail-to-rail input and output, 9
voltage feedback amplifier in a noninverting configuration with an RF of 12
15
10 k for gains of 11 V/V, 21 V/V, and 31 V/V.
18
21
The degree of peaking in the small signal frequency response indicates 0.1 1 10 100
instability. Increasing the gain from 11 V/V to 31 V/V results in less than Frequency (MHz)
1 dB of peaking. This would imply that the amplifier has sufficient phase Figure 2. Simulation results using the ADA4807 SPICE model.
margin with an RF of 10 k and is stable at high gains. R F = 10 k, VS = 5 V, R LOAD = 1 k for gain = 2, and 31 V/V.

34 Analog Dialogue Volume 50 Number 4

Validating a circuit in the lab is not a mandatory step for verifying potential There are system trade-offs in the selection of RF. To achieve full
instabilities. Figure 2 shows the simulation results using the SPICE model performance from a system, the appropriate RF choice will depend on the
with gain of 2 V/V and 31 V/V. The instability with using a large gain resistor system requirements with respect to stability, bandwidth, and power.
such as 10 k in a gain of 2 V/V is shown in comparison with the same RF
in a gain of 31 V/V. Figure 3 shows results for gains 11 V/V, 21 V/V, and
31 V/V in the time domain.

0.25 5

Input
0.20 G = 31 V/V 4
G = 21 V/V
0.15 G = 11 V/V 3

0.10 2

Output Voltage (V)

0.05 1
Input Voltage (V)

0 0

0.05 1

0.10 2

0.15 3

0.20 4

0.25 5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Time (s)

Figure 3. Pulse response simulation results using the ADA4807 SPICE model. VS = 5 V,
R F = 10 k; G = 11 V/V, 21 V/V, and 31 V/V and R LOAD = 1 k.

Tina Collins [Tina.Collins@analog.com] is an applications engineer in the Linear Products and Technology Group
in Wilmington, MA. Her main interests are analog and mixed-signal design for high speed amplifiers. Tina joined
Analog Devices in 2001. Prior to becoming an applications engineer in 2013, she focused on developing and testing
high speed amplifiers. Tina received a B.S.E.E. from the University of Florida in 2001 and an M.S.E.E. from
Northeastern University in 2010.

Analog Dialogue Volume 50 Number 4 35

PLC DCS Analog Input Module Design Breaks
Barriers in Channel-to-Channel Isolation and
High Density
By Van Yang, Songtao Mu, and Derrick Hartmann

Share on

Introduction
In high end factory automation applications such as gas and oil plants
and power plants, the requirements of low EMI, small size, high reliability,
and low cost are especially challenging for channel-to-channel isolated
designs. For this reason, the standard module implementation has a chan-
nel density that is typically limited to only four or eight channels, with only
hundreds of volts of channel-to-channel isolation.
This article will briefly discuss isolation in the process control analog input
module and the traditional approaches to achieving this. It then outlines
an alternative high density, easy to design, channel-to-channel isolation
analog input module architecture. Test results are included that show that
the 16-channel, 2.5 kV rms channel-to-channel isolation demo module
easily passes the EN55022, Class B isolation standard.
Isolation in the Process Control Analog Input Module
Galvanic isolation is the principle of physically and electrically separat-
ing two circuits, so that there is no direct conduction path but data and
power can still be exchanged. This is typically achieved using transform-
ers, optocouplers, or capacitors. Isolation is used to protect circuitry and
human beings, break ground loops, and improve common-mode voltage
and noise rejection performance.
Typically process control inputs are either group isolated or channel-to-
channel isolated (see Figure 1). For group isolation, a number of input
channels are grouped together to share a single isolation barrier, including
power isolation and signal isolation. This saves cost over channel-to-channel
isolation, but it limits the common-mode voltage difference between
channels in the group, meaning they should all be placed in the same zone.
Channel-to-channel isolation, as in the right of Figure 1, is always favorable
for its improved robustness. That said, it comes at a much higher cost per-
channel, so this trade-off must be carefully assessed by plant builders.
Group Isolated Channel-to-Channel Isolated
AIN Ch. 1 AIN1
A Ch. 2
. IN GND1 GND
. Group X
.
AIN Ch. M GNDx
GND AIN2
GND2 GND
With a channel-to-channel isolation design, every channel needs dedicated
power isolation and signal isolation. The isolation is one of the key limita-
tions for input module channel density, EMI, cost, and reliability. In modern
designs, a digital isolator is used per channel for data isolation. A typical
digital isolator, such as theADuM141E, would have four isolated data
channels in a 16-lead SOIC (6.2 mm 10mm) package. Power isolation
is still required per channel, though, so lets discuss three traditional
approaches to power isolation: multitaps transformer, push-pull design,
and isolated dc-to-dc modules.
Figure 2 shows a flyback isolation dc-to-dc architecture with a multitap
transformer. A flyback converter drives the transformer to generate multiple
outputs on the taps. Its a mature power architecture but has six major
disadvantages for process control applications, which are:
1. It needs a customized transformer with multitaps and a shield
to control EMI. This is hard to achieve in a small form factor with
sufficient reliability.
2. Only one channel could be used for a feedback control loop, meaning
that the other channels are more loosely regulated. This needs to be
carefully evaluated to ensure reliable operation.
3. Channel density is limited by specific transformer placement. For the
power coming from each tap output, the transformer is placed as the
center of the analog input module with each input channel laid out in
fanout sectors around the transformer, limiting the analog input module
card channels to four or eight.
4. Interference from one channel can be coupled into other channels
through the coupling capacitors between the taps of the transformer.
5. The isolation voltage level. Multitap transformers can only achieve
hundreds of volts of channel-to-channel isolation unless special
insulation materials or designs are incorporated, which significantly
increases the transformer cost.
6. The high cost of achieving UL/CSA certification for the customized
transformer.

AIN Ch. 1
A Ch. 2
. IN AINM
. Group Y
.
AIN Ch. M GNDy GND GNDm GND

Figure 1. Group isolation and channel-to-channel isolation.

36 Analog Dialogue Volume 50 Number 4

 VISO1
while increasing isolation voltage to thousands of volts. That said, the cost
is relatively high and typically these can only pass the EN55022 Class A.
These modules may also have conducted electromagnetic interference
issues as most of the modules PWM frequency are below 1 MHz to mini-
GND1
mize the electromagnetic radiation interference. Also, the majority of the
VISO2
process control analog input modules consume less than 10 mA current,
VIN far less than most of the isolated power modules in the market.
SW All three traditional approaches discussed struggle to meet the required
GND
isolation performance and cost. These approaches also still require sepa-
GND2
FB VISOn
rate data isolators per channel, adding additional space and cost. What if
GND the power isolation could be included as part of the data isolator? It can,
and it is.

ADIiCouplertechology andisoPowertechnology are widely used in

GNDn
GND GNDn
Figure 2. Multitap transformer power isolation design.
Another approach is to use a separate transformer per channel and use
a push-pull approach to isolating each channel. In this approach, no
feedback is used. Instead, a well-regulated supply (for example, 7 V) is
used to drive each of the transformers, which is then further regulated on
the secondary side using an LDO. This approach is feasible as the current
draw on the secondary side is relatively low, which makes adequate
regulation possible.
the industrial and automotive market and these two technologies can be
integrated into a single package. Taking theADuM5411as an example,
per the block diagram shown in Figure 4, this device includes complete
power isolation and four channels of data isolation in a 7.8 mm 8.2 mm,
24-lead TSSOP package. It offers up to 150 mW output, enough for analog
input signal conditioning and digitizing and passes the 2500 V rms UL1577
isolation standard. Whats more, the CMTI (common-mode transient
immunity) is greater than 75 kV/s, making it ideal for harsh industrial
environments, such as power plants, where high transient voltages and
currents exist.
VDD1 1 24 VDD2
GND1 2 23 GNDISO

I/O1A 3 22 I/O2A
Some of the drawbacks of this approach are the requirement for prereg-
I/O1B 4 21 I/O2B
ulation as well as additional components per channel. The transformer 4-Channel iCoupler Core
ADuM5410/ADuM5411/ADuM5412
selected must meet the isolation rating required. The preregulation, as well I/O1C 5 20 I/O2C

as a transformer, switches, and an LDO per channel take up board space I/O1D 6 19 I/O2D
and add cost. There is also a significant evaluation effort required to ensure VE1 7 18 VE2
that the regulation is sufficient under all conditions.
NIC 8 17 NIC
Switch Control
GND1 9 16 GNDISO
24 V 20% 7V 3.3 V PDIS 10 PCS 15 VSEL
Pre-
regulation LDO
VDDP 11 14 VISO

12 OSC RECT REG 13 GNDISO

GND1

Data Figure 4. ADuM5411 block diagram.

Isolation
Channel 1 Due to the high integration of both data and power isolation, the analog
.
.
input module design is greatly simplified and higher channel densities are
. possible. It enables the possibility of providing 16 or more channels in the
3.3 V same space as eight channels using older isolation methods.
LDO
A 16-channel, channel-to-channel isolation temperature input module
was designed and tested using this isolation approach (see Figure 5).
The ADuM5411 devices in the module provide isolated power and data to
Data each of the 16 temperature input channels. The thermocouple and/or RTD
Isolation
measurements are performed by highly integrated temperature front-end
Channel N
ICs (AD7124, orAD7792) providing additional space saving over more
Figure 3. Push-pull isolation design. discrete designs. TheADP2441converts the 24 V backplane supply to 3.3 V
to power the MCU, touchscreen, and the ADuM5411. Each input channel
Using surface-mount isolated dc-to-dc modules certified by UL/CSA make requires an area of only 63.5 mm 17.9 mm.
the isolated power design much easier and can improve channel density

Analog Dialogue Volume 50 Number 4 37

 24 V
AD7124 AD7124 AD7124 AD7124 AD7124 AD7124 AD7124 AD7124

3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V

ADP2441
ADuM5411 ADuM5411 ADuM5411 ADuM5411 ADuM5411 ADuM5411 ADuM5411 ADuM5411
5V

SPIData

ADuM5411 ADuM5411 ADuM5411 ADuM5411 ADuM5411 ADuM5411 ADuM5411 ADuM5411

ADuCM3029

3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V

AD7124 AD7124 AD7124 AD7124 AD7124 AD7124 AD7124 AD7124

Touch Screen

Figure 5. 16-channel temperature channel-to-channel isolation input module block diagram.

Layout Design for ADuM5411

The ADuM5411 uses a switching frequency of 125 MHz. Due to the high
number of channels, special care was taken to ensure the board would pass
the electromagnetic radiation interference test per EN55022 to Class B.
To minimize the radiated emission, the principles used were to minimize
the power draw and minimize the current loop return path. The power was
minimized by using low power integrated temperature front-end ICs. This
means less power will be drawn across the isolation barrier, meaning there
will also be less energy radiated. TheAD7124only draws 0.9 mA when fully
active. To minimize the current return loop, both ferrite beads as well as a
small amount of stitching capacitance were used.
Ferrite beads are a useful method to control the radiating signal at its source
by presenting a much higher impedance than a PCB trace. Referring to
Figure 6, ferrite beads were placed in series with the ADuM5411s pins.
The frequency response of the ferrite beads is a very important consider-
ation. The ferrite bead used is BLM15HD182SN1, which provides greater than
2 kbetween 100 MHz and 1 GHz frequency range. The ferrite beads
should be placed as close to the ADuM5411s pad as possible. E9 on the
VISO path and E10 on the GNDISO path are the most critical ferrite beads.

P9

U3
E1 24 1 E5
VDD2 VDD1 3V3
E2 23 2 E6
3V3V9 GNDISO GND1
DIN9 E17 22 3 SPI2DIN
C4 1 F VOA VIA
SCLK9 E18 21 4 E25 SPI2SCLK C41 1 F C49 10 F
VOB VIB
C136 0.01 F CS_9 E19 20 5 E132 CS9
VOC VIC C219 0.010 F
DOUT_9 E20 19 6 E133 SPI2DOUT9
VID VOD
C50 1 F 18 7 E134
VE2 VE1
17 8 C209 1 F
C169 0.01 F NIC NIC C235 10 F
E9 16 9
GNDISO GND1 C220 0.010 F
15 10
C33 10 F VSEL PDIS
R202 R228 14 11 E30
VISO VDDP
16.9 k 10.2 k 13 12 E31
GNDISO GND1
E10

AGND9 ADuM5411BA9Z C47 AGND

DOUT_9 C37 10 PF
1000 PF SPI2SCLK C51 10 PF
SCLK9 C38 10 PF SPI2DIN C52 10 PF
DIN9 C39 10 PF CS9
C53 10 PF
CS_9
C40 10 PF SPI2DOUT9
C54 10 PF
AGND
AGND9

Figure 6. ADuM5411 schematic.

38 Analog Dialogue Volume 50 Number 4

Capacitance can also be used to provide a low impedance return path, thus Top

reducing emissions. One method to do this is to use a surface-mounted 20 mils

safety rated capacitor crossing the barrier, guaranteed to meet standards
GND1
for creepage, clearance, and withstand voltage. These capacitors are avail- 5 mils
able from suppliers like Murata or Vishay. This method is only effective up SIG
5 mils
to around 200 MHz, though, due to the inductance introduced by mounting PWR
the capacitor. For this reason, a more effective technique is to build a 5 mils
stitching capacitance internal to the PCB under the ADuM5411. This could GND2

be a floating stitching capacitor or an overlapping stitching capacitor, as 20 mils

shown in Figure 7.
Bottom
Figure 8. Six-layer PCB stack assignment.
w1 w2
As per Figure 9, the overlap stitching capacitors planes are built in the
I
GND1, SIG, PWR, and GND2. The planes on GND1 and PWR are connected
to the ADuM5411s secondary side and the planes in the SIG and GND2 are
connected to ADuM5411s primary side. This means three parallel stitching
capacitors are formed between GND1 and SIG, SIG and PWR, PWR and
d
GND2. The width of the overlap area is 4.5 mm, and the length is 17 mm,
meaning the total stitching capacitance is 72 pF.
w
I

d
Figure 7. Floating stitching capacitor and overlapping stitching
capacitor.

For the floating stitching capacitor, two serial capacitors are built in, C1
and C2. The total capacitance is calculated by Equation 1.

C1 C2 lw1 lw2
C= , C1 = , C2 =
C1 + C2 d d

where:
is the permittivity of the PCB insulation material, 4.5 for FR4 material.

For the overlapping stitching capacitor, the capacitance is calculated by

Equation 2.

lw
C1 = ,
d

where:
is the permittivity of the PCB insulation material, 4 1011 F/m for FR4
material.

With the same material, area, and distance, the total capacitance value of
floating stitching is half that of the overlapping stitching, but the thickness
of the insulation material is doubled. Reinforced insulation, per IEC60950
2.10.6.4, requires 0.4 mm (15.74 mils) minimum insulation material thick-
ness in the interior layers, but basic insulation has no such requirement.
As the ADuM5411 only provides 2.5 kV rms basic isolation, an overlapping
stitching capacitor was chosen to maximize the capacitance. The thickness
of the interior layers has also been controlled to 5 mils for the same reason.

The 16-channel, channel-to-channel temperature input module PCB uses

a 6-layer board. To maintain mechanical and EMI performance, the top and
bottom layers were controlled to 20 mils and interior layers to 5 mils, as
per Figure 8.
Figure 9. Six-layer PCB layout of the ADuM5411 area.

Analog Dialogue Volume 50 Number 4 39

Test Results Against the EN55022 Specification 70
Limit
Two sets of EMI tests were performed at 10 m, as per the EN55022 spec- Margin
ification. For the first test, a board with stitching capacitance was used, as
Class A
shown in Figure 10. Figure 11 shows the resultsit passed the EN55022 5
Class B standard with about 11.59 dB margin. For the second test, a board Class B 2 3 46 7
with no stitching capacitance was used, and, instead, external safety 1

dB V/m
capacitors, KEMET C1812C102KHRACTU 3 kV, 150 pF, were mounted on 20

the board. Figure 12 shows the resultsit passed the EN55022 Class B
standard with 0.82 dB margin.

30
30 127 224 321 418 515 612 709 806 1000
Frequency in MHz

Figure 12. The no stitching capacitance, but with safety capacitors

PCB, EN55022 Class B test result.

The results proved that stitching capacitors under the IC is a more effective
decoupling method than the safety capacitors.

Conclusion
Channel-to-channel isolation is often viewed as a design challenge in high
Figure 10. Stitching capacitors built into the PCB without safety capacitors. end process control systems. ADIsisoPower technology andiCoupler tech-
70
nology enables significant increases in channel density over traditional digital
Limit and power isolation approaches. They also greatly simplify the design task
Margin and can improve channel robustness and reliability. With stitching capacitor
built into the PCB, or safety capacitor mounted aside the PCB, EMI radiation
Class A
can be easily controlled to pass EN55022 Class B or Class A. Its a break-
Class B though in technology.
6
dB V/m

4 5
3
20
2 References
ADuM5411 data sheet. Analog Devices, Inc.

AN-0971,Recommendations for Control of Radiated Emissions with

isoPowerDevices. Analog Devices, Inc.

30 AN-1349,PCB Implementation Guidelines to Minimize Radiated

30 127 224 321 418 515 612 709 806 1000
Frequency in MHz Emissions on the ADM2582E/ADM2587E RS-485/RS-422 Transceivers.
Figure 11. Stitching capacitors built into PCB EN55022 Class B test result. Analog Devices, Inc.

Van Yang
Van Yang [van.yang@analog.com] is a field application engineer at Analog Devices in Shanghai,
China. He joined ADI in 2015 to support regional medical and industrial customers in China.
Prior to joining ADI, Van worked at Texas Instruments as an FAE for four years. Van earned
his masters degree in communication and information systems from Huazhong University of
Science and Technology in Wuhan, in 2011. In his spare time he is a super fan of basketball and
enjoys hiking.

Songtao Mu
Songtao Mu [songtao.mu@analog.com] is a system applications engineer in Analog Devices
Industrial Automation Group. He is based in Shanghai, China. Prior to joining Analog Devices,
Songtao worked at Schneider Electric Co., Ltd., as a hardware design engineer for over eight
years. Songtao holds a bachelors degree in industrial automation from the Harbin institute of
Technology University, China.

Derrick Hartmann
Derrick Hartmann [derrick.hartmann@analog.com] is a system applications engineer in
the Industrial Automation Group at Analog Devices. He is based in Wilmington, MA. Prior to Also by this Author:
his current role, Derrick was a product applications engineer supporting Analog Devices
industrial DAC portfolio. Derrick holds a degree in electronic engineering from the University PLC Evaluation Board
of Limerick, Ireland. Simplifies Design of
Industrial Process
Control Systems

40 Analog Dialogue Volume 50 Number 4

Next-Generation SAR ADC Addresses Pain
Points of Precision Data Acquisition Signal
Chain Design
By Maithil Pachchigar and Alan Walsh
Share on
Introduction
Many applications require a precision data acquisition signal chain in order
to digitize analog data so that it can be collected and processed accurately.
Precision system designers are continually pressed to find innovative ways
to improve performance and reduce power dissipation while accommodat-
ing increased circuit density in a small PCB footprint. This article discusses
the common pain points encountered in designing a precision data acquisi-
tion signal chain and how to address them using the next generation of
16-/18-bit, 2 MSPS, precision successive approximation register (SAR)
ADCs. Designed using ADIs advanced technology, theAD4000/AD4003
(16-/18-bit) ADC incorporates ease of use features that offer a multitude
of system-level benefits that help to lower the signal chain power, reduce
signal chain complexity, and enable higher channel density while pushing
the performance level higher. This article will highlight data acquisition
subsystem performance and design challenges and explain how this ADC
family creates application level impact in multiple end markets.
Common Signal Chain Design Pain Points
Figure 1 shows a typical signal chain used in building precision data acqui-
sition systems. Applications that require precision data acquisition systems
such as automated test equipment, machine automation, industrial, and
medical instrumentation have common trends that are typically considered
technically conflicting. For example, system designers are forced to make
performance trade-offs to keep a tight system power budget or small area
on the board to achieve high channel density. System designers of these
precision data acquisition signal chains face common challenges in terms of
driving the SAR ADC inputs, protecting ADC inputs from overvoltage events,
reducing the system power with single supplies, and achieving higher
system throughput with low power microcontrollers and/or digital isolators.
Signal Digital
Conditioning Ref
Ref
Isolator
Buf
Stage (Optional)
FPGA/
Sensors
JFET/ Driver RC
ADC Micro-
In-Amp Stage Filter
controller
Figure 1. Typical precision data acquisition signal chain.
Driving high resolution precision SAR ADCs has been traditionally a tricky
issue because of the switched capacitor inputs. System designers need to
pay close attention to the ADC driver data sheet and look at the noise, dis-
tortion, input/output voltage headroom/footroom, bandwidth, and settling
time specifications. Typically, high speed ADC drivers are required that are
wide bandwidth, low noise, and high power in order to settle the switched
capacitor kickback of the SAR ADC inputs within the available acquisition
time. This significantly reduces the options available for amplifiers to
drive the ADC and results in significant performance/power/area trade-
Analog Dialogue Volume 50 Number 4
offs. Furthermore, selecting an appropriate RC filter to place between the
driver and the ADC inputs imposes further constraints on amplifier choice
and performance. The RC filter between ADC driver output and SAR ADC
input is required to limit wideband noise and reduce the effects of charge
kickback. Typically, the system designer needs to spend significant time
to evaluate the signal chain to ensure that the selected ADC driver and RC
filter can drive the ADC to achieve a desired performance.
In power sensitive applications like battery-powered instrumentation, it
is often desirable to run the system from a single low voltage supply. This
minimizes the power dissipation of the circuitry but introduces issues with
headroom and footroom for the amplifier front end. This means it may not be
possible to use the full ADC input range because the driving amplifier cannot
drive all the way to ground or all the way to the upper end of the ADC input
range, reducing the performance of the overall system. This can be remedied
by increasing the supply voltage at the cost of higher power dissipation or
accepting the lower dynamic range performance from the system.
Most ADC analog inputs, IN+ and IN, have no overvoltage protection
circuitry apart from ESD protection diodes. In applications where the
amplifier rails are greater than VREFand less than ground, it is possible
for the output to go outside the input voltage range of the device. During an
overvoltage event, the ESD protection diode between either analog input (IN+
or IN) pin to REF forward biases and shorts the input pin to REF, potentially
overloading the reference, causing damage to the device, or disturbing a
reference that is shared among multiple ADCs. This results in having to add
protection circuitry like Schottky diodes to the ADC input to prevent overvolt-
age conditions from harming the ADC. Unfortunately, Schottky diodes could
add distortion and other errors due to leakage currents.
Precision applications have different needs in terms of the processors that
interface to the ADC. Some applications need to be electrically isolated for
safety reasons and use digital isolators between the ADC and processor to
achieve this. This choice of processor or need for isolation puts constraints
on the efficiency of the digital interface used to connect with the ADC.
Typically, lower end processors/FPGAs or lower power microcontrollers
have relatively low serial clock rates. This can result in lower than desired
throughput from the ADC because of a long ADC conversion time delay
before the conversion result can be clocked out. Digital isolators can
also limit the maximum serial clock rate that can be achieved across the
isolation barrier due to propagation delays in the isolator limiting the ADC
throughput. In these scenarios an ADC that can achieve a higher through-
put rate without a significant increase in serial clock rate is desirable.
AD4000/AD4003 Precision SAR ADC Family Solves
Common Design Challenges
The AD4000/AD4003 family is a fast, low power, single-supply, 16-/18-bit
precision ADC based on a SAR architecture.
41
The AD4000/AD4003 precision ADC family uniquely combines high High Input Impedance Mode
performance with ease of use features that reduce system complexity, To achieve the optimum data sheet performance from high resolution
simplify signal chain BOM, and significantly decrease time to market (see precision SAR ADCs, system designers are often forced to use a dedi-
Figure 2). This family enables designers to solve the system-level technical cated high power, high speed amplifier to drive the traditional switched
challenges for their high precision data acquisition system without making
capacitor SAR ADC inputs for their precision applications. This is one of the
significant trade-offs. For example, a combination of a long acquisition
common pain points encountered in designing a precision data acquisition
phase, high input impedance (Z) mode, and span compression mode of
signal chain. The benefits of high-Z mode are low input current for slow
the AD4000/AD4003 ADC family reduces the design challenges associated
(<10kHz) or dc type signals and improved distortion (THD) performance
with the ADC driver stage and increases the flexibility in ADC driver
over an input frequency range up to 100kHz.
selection. This enables overall lower system power, higher density, and
reduced customer design cycle time. Most of the ease of use features can
The AD4000/AD4003 ADC incorporates a high-Z mode that reduces the
be enabled/disabled through writing to the configuration register via an SPI
nonlinear charge kickback when the capacitor DAC switches back to the
interface. Note that AD4000/AD4003 ADC family is pin-compatible with the
input at the start of acquisition. With high-Z mode enabled, the capacitor
10-lead AD798x/AD769x ADC family.
DAC is charged at the end of conversion to hold the previously sampled
Easy to Use voltage. This process reduces any nonlinear charge effects from the con-
Reduces Design Time
version process affecting the voltage that is acquired at the ADC input prior
to the next sample.

Low Power Figure 3 shows the input current of the AD4000/AD4003 ADC with high-Z
16 mw @ 2 MSPS Small Footprint mode enabled/disabled. The low input current makes the ADC a lot easier
80 W @ 10 kSPS 3 mm 3 mm
to drive than traditional SAR ADCs available in the market even with high-Z
mode disabled. If you compare the input current in Figure 3 with high-Z
mode disabled against that of the previous generationAD7982ADC, the
AD4003 has reduced the input current by 4 at 1MSPS. The input current
reduces further to submicroampere range when high-Z mode is enabled.
High-Z mode should be disabled for input frequencies above 100kHz or
when multiplexing the input.

With the reduced input current of the AD4000/AD4003 ADC, it is capable of

being driven with a much higher source impedance than traditional SARs.
This means the resistor in the RC filter can have 10 larger value than
traditional SAR designs.
15.0

12.0

9.0

Overvoltage High Precision 6.0

Robust 18-Bit
Input Current (A)

INL 3.6 ppm Max 3.0

0.0

3.0
High Throughput
2 MSPS 6.0
25C High-Z Enabled
Figure 2. AD4000/AD4003 ADC key benefits. 9.0
25C High-Z Disabled
12.0
AD4000/AD4003 ADC Ease of Use Features
15.0
5 4 3 2 1 0 1 2 3 4 5
Long Acquisition Phase
Input Differential Voltage (V)
The AD4000/AD4003 ADC features a very fast conversion time of 290 ns
and the ADC returns back to the acquisition phase 100 ns before the end Figure 3. AD4003 ADC input current vs. input differential voltage
with high-Z enabled/disabled.
of the ongoing conversion process. SAR ADC cycle time is comprised of
conversion and acquisition phases. During the conversion phase, the ADC As shown in Figure 4, the AD4000/AD4003 ADC allows a choice of lower
capacitor DAC is disconnected from the ADC inputs to perform the SAR power/bandwidth precision amplifiers with a lower RC filter cutoff to drive
conversion. The inputs are reconnected during the acquisition phase, and the ADC, removing the need for dedicated high speed ADC drivers, saving
the ADC driver must settle the inputs to the correct voltage before the next system power, size, and cost in precision, low bandwidth applications
conversion phase begins. A longer acquisition phase reduces the settling (signal bandwidths <10 kHz). Ultimately, the AD4000/AD4003 allows the
requirement on the driving amplifier and allows a lower RC filter frequency amplifier and RC filter in front of the ADC to be chosen based on the signal
cutoff, which means a higher noise and/or lower power/bandwidth ampli- bandwidth of interest and not based on the settling requirements of the
fier can be tolerated. A larger value of R can be used in the RC filter with switched capacitor SAR ADC inputs.
a corresponding smaller value of C, reducing amplifier stability concerns
without impacting distortion performance significantly. A larger value of R Signal Digital
Ref
helps to protect the ADC inputs from overvoltage conditions. It also results Conditioning Ref
Buf
Isolator
in reduced dynamic power dissipation in the amplifier. Stage (Optional)

FPGA/
JFET/ Driver RC
Sensors ADC Micro-
In-Amp Stage Filter
controller

Figure 4. Traditional precision signal chain.

42 Analog Dialogue Volume 50 Number 4

Figure 5 and Figure 6 show the AD4003 ADCs SNR and THD performance 80

using theADA4077(IQUIESCENT= 400 A/amplifier),ADA4084(IQUIESCENT= 84

600 A/amplifier), and ADA4610(IQUIESCENT= 1.5mA/amplifier) precision
88
amplifiers when driving the AD4003 ADC at full throughput of 2MSPS for
both the high-Z enabled/disabled cases with various RC filter values. These 92
amplifiers achieve 96dB to 99dB typical SNR and better than 110dB 96

THD (dB)
typical THD with high-Z enabled for a 2.27MHz RC bandwidth and 1kHz
100
input signal. THD is approximately 10dB better with high-Z mode enabled
even for large R values greater than 200. SNR holds up close to 104

99dB even with a very low RC filter cutoff. 108 ADA40771, 2 MSPS, High-Z Disabled
ADA40771, 2 MSPS, High-Z Enabled
112 ADA46101, 2 MSPS, High-Z Disabled
With high-Z enabled, the ADC will consume around 2 mW/MSPS extra ADA46101, 2 MSPS, High-Z Enabled
power, but this would be still significantly lower than using dedicated ADC 116 ADA40842, 2 MSPS, High-Z Disabled
drivers like theADA4807-1and results in PCB area and bill of material ADA40842, 2 MSPS, High-Z Enabled
120
savings. For most systems, the front end usually limits the overall ac/dc 470 pF 470 pF 180 pf 180 pf 180 pf
performance achievable by the signal chain. Its evident from the selected 1.3 k 680 680 390 200
260.482 kHz 497.981 kHz 1.3 MHz 2.27 MHz 4.42 MHz
precision amplifiers data sheet in Figure 5 and Figure 6 that its own noise Capacitor (pF), Resistor (), and RC Filter Bandwidths (Hz)
and distortion performance dominates the SNR and THD specification at
a certain input frequency. However, the AD4003 ADC with high-Z mode
Figure 6. THD vs. RC bandwidths using ADA4077, ADA4084, and
allows a greatly expanded choice of driver amplifier including precision
ADA4610 precision amplifiers.
amplifiers used in signal conditioning stages along with more flexibility
in the RC filter choice. For example, when the AD4003 ADCs high-Z
is enabled and using theADA4084-2driver amplifier with a wideband Figure 7(a) shows that system designers can use the 2.5 lower pow-
input filter of 4.42 MHz, the SNR performance is about 95 dB. With more er ADC driver ADA4077 (vs. the ADA4807), and the AD4003 ADC still
aggressive filtering of the ADC drivers noise using a 498 kHz filter, SNR achieves SINAD of about 97dB (3dB better than the AD7982 ADC) when
improves by 3 dB, to 98 dB. The AD7982 ADCs SNR performance at lower high-Z mode is disabled. Even with a wider RC bandwidth of 2.9 MHz, the
RC cutoff is degraded because the ADC input does not settle the kickback ADA4077 amplifier cannot drive the AD7982 ADC directly and achieve op-
within its short acquisition time. timum performance. The driver cannot settle the ADC kickback within the
available acquisition time with aggressive filtering at a lower RC bandwidth
100
98
cutoff and hence the ADC SINAD performance is degraded. The AD4003
96
ADCs switched capacitor kickback with either high-Z mode disabled or
94 enabled is much reduced and the acquisition time is 2.5 longer at 1 MSPS
92 and hence its SINAD performance is still significantly better than that of
90 AD7982 ADC.
88
With high-Z mode enabled, the AD4003 ADCs SINAD performance is better
SNR (dB)

86
84 using both ADC drivers at lower RC filter cutoff, which helps remove more
82 wideband noise coming from the upstream signal chain components when
80 ADA4077-1, 2 MSPS, High-Z Disabled the signal bandwidth of interest is low. Without high-Z mode enabled there
78 ADA4077-1, 2 MSPS, High-Z Enabled is a trade-off between RC filter cutoff and SINAD performance.
76 ADA4610-1, 2 MSPS, High-Z Disabled
ADA4610-1, 2 MSPS, High-Z Enabled
74
ADA4084-2, 2 MSPS, High-Z Disabled Span Compression
72 ADA4084-2, 2 MSPS, High-Z Enabled
70 The AD4000/AD4003 ADC includes a span compression mode, which is
470 pF 470 pF 180 pf 180 pf 180 pf useful for systems that only have a single positive supply to power the
1.3 k 680 680 390 200
260 kHz 498 kHz 1.3 MHz 2.27 MHz 4.42 MHz SAR ADC drivers. It eliminates the ADC drivers need for a negative supply
Capacitor (pF), Resistor (), and RC Filter Bandwidths (Hz) while preserving the full resolution of the ADC, saving power and reducing
Figure 5. SNR vs. RC bandwidths using ADA4077, ADA4084, and power supply design complexity. As shown in Figure 8, the ADC performs
ADA4610 precision amplifiers. a digital scaling function that maps zero-scale code from 0 V to 0.1 V
2.5 Lower Power
100 100
98 98
96 96
94 94
92 92
90 90
88 88
86 86
84 84
82 82
80 80
SINAD (dB)

SINAD (dB)

78 78
76 76 Higher Performance
74 74 Maintained at Lower
72 72 RC Bandwidth
70 70
68 68
66 66
64 64
62 62
60 AD7982/ADA4077: 1 MSPS 60 AD7982/ADA4077: 1 MSPS
58 AD4003/ADA4077: 1 MSPS 58 AD4003/ADA4077: 1 MSPS
56 AD7982/ADA4077: 1 MSPS 56
54 54 AD7982/ADA4077: 1 MSPS
52 AD4003/ADA4077: 1 MSPS 52 AD4003/ADA4077: 1 MSPS
50 50
470 pF 470 pF 180 pf 180 pf 180 pf 470 pF 470 pF 180 pf 180 pf 180 pf
1.3 k 680 680 390 200 1.3k 680 680 390 200
260.482 kHz 497.981 kHz 1.3 MHz 2.27 MHz 4.42 MHz 260.482 kHz 497.981 kHz 1.3 MHz 2.27 MHz 4.42 MHz
Capacitor (pF), Resistor (), and RC Filter Bandwidths (Hz) Capacitor (pF), Resistor (), and RC Filter Bandwidths (Hz)
(a) High-Z Mode Disabled (b) High-Z Mode Enabled

Figure 7. AD4003 ADC and AD7982 ADC amplifier driver comparison using ADA4077 and ADA4807: SINAD vs. RC bandwidths for high-Z mode
disabled and enabled (F S= 1 MSPS, f IN= 1 kHz).

Analog Dialogue Volume 50 Number 4 43

VREFand full-scale code from VREFto 0.9 VREF. The AD4000/AD4003 ADCs
SNR takes a hit of about ~1.9 dB (20log(4/5)) for the reduced input range.
As an example, for a subsystem operating from a single 5 V supply and
a typical reference voltage of 4.096 V, the full-scale input range is now
~0.41 V to 3.69 V, which provides adequate headroom for powering the
driving amplifier.
3.69 V
of use features and a 6-bit status word can be appended to the conver-
sion result that allows diagnosis along with register read back. The serial
interface is completely specified down to 1.8 V logic levels and can achieve
the full 2MSPS throughput under these conditions. A minimum SCK rate
of 75 MHz is required to run the AD4003 ADC at 2MSPS with turbo mode
enabled.

Digital Output
AD4000/AD4003 ADC Performance
5V
Analog
+FSR Operating from a 1.8 V supply, the AD4000/AD4003 ADC consumes
Input typically 14mW/16mW at 2MSPS and offers superior linearity of
0.41 V
All
ADC
2N Codes 1.0 LSB (3.8 ppm) max and guaranteed 18 bits no missing codes.
Figure 11 shows the AD4003 ADCs typical INL vs. code performance. The
FSR
AD4003 ADC achieves better SINAD performance than the AD7982 ADC
Figure 8. AD4000/AD4003 ADC span compression operation.
over a wide range of input frequencies up to Nyquist (Figure 12), enabling
system designers to develop wider bandwidth, higher precision instrumen-
Overvoltage Clamp tation equipment. The AD4000/AD4003 ADC is available in a small 10-lead
In applications where the amplifier rails are greater than VREFand less than footprint (3 mm 3 mm, LFCSP and 3 mm 5 mm, MSOP options), and is
ground it is possible for the output to violate the input voltage range of the pin-compatible with the AD798x/AD769x ADC family.
part. When positive input is over-ranged, current flows through D1 into
1.0
REF (see Figure 9), disturbing the reference. Even worse it could pull the
reference above the absolute maximum reference value and hence could 0.8 +125C
+25C
damage the part. 0.6 40C

0.4
When the analog input exceeds the reference voltage by ~400 mV, the
AD4000/AD4003 ADCs internal clamp circuit will turn on and the current 0.2

INL (LSB)
will flow through the clamp into ground, preventing the input from rising 0
further and potentially causing damage to the device.
0.2
REF
0.4

0.6
D1
0 V to 15 V REXT IN+/IN RIN CIN
0.8

1.0
0 32768 65536 98304 131072 163840 196608 229376 262144
CEXT CPIN CODE
VIN D2 Clamp
Figure 11. AD4003 ADC INL vs. code.
101
GND
AD4003
98
Figure 9. AD4003 ADC equivalent analog input circuit.
95
As shown in Figure 9, the AD4000/AD4003 ADCs internal overvoltage
clamp circuit with a larger external resistor (REXT=200 ) eliminates the
SINAD (dB)

92
need for external protection diodes (and hence the need for additional
board space). The clamp turns on before D1 and can sink up to 50 mA of 89
current. The clamp prevents damage to the device by clamping the input
voltage to a safe operating range and avoids disturbance of the reference, 86

which is particularly important for systems that share the reference among
multiple ADCs. 83 AD4003
AD7982
80
Efficient Digital Interface 1 10 100 1k

The AD4000/AD4003 ADC has a flexible digital serial interface that offers
seven different modes with register programmability. Its turbo mode allows
the user to start clocking out the previous conversion results while the ADC
is still converting, as shown in Figure 10. A combination of short conversion
time and turbo mode allows a lower SPI clock rate and simplifies the isola-
tion solution, resulting in reduced latency requirements on digital isolators
and broadening a choice of processors including lower end processors/FP-
GAs or low power microcontrollers with relatively low serial clock rates. For
example, the AD4003 ADC can use a 2.5 slower SPI clock rate (25MHz
vs. 66MHz) than the AD7982 ADC when running at 1 MSPS. The user can
write/read back the register bits to enable the AD4000/AD4003 ADCs ease
Frequency (kHz)
Figure 12. AD4003 ADC vs. AD7982 ADC SINAD vs. input frequency.
The AD4000/AD4003 ADC powers down automatically at the end of each
conversion phase; therefore, its power scales linearly with the throughput
as shown in Figure 13. This feature makes the device ideal for low sam-
pling rates (even down to a few Hertz) and battery-powered portable and
wearable systems. Even in low duty cycle applications, the first conversion
result is always valid.

44 Analog Dialogue Volume 50 Number 4

 SDI = 1

tCYC

CNV

TACQ

Acquisition Conversion Acquisition

tCONV L tSCK

tSCK
tQUIET2
tQUIET1
SCK 1 2 3 16 17 18

tHSDO tSCKH

tEN tSDO tDIS

SDO D17 D16 D15 D1 D0

Figure 10. AD4003 ADCs turbo mode operation.

Automated Test

16 Total Power (mW)

VDD Power (mW)
14 VIO Power (mW)
REF Power (mW)
Electrical Test
Power Dissipation (mW)

12 Machine Automation and Measurement

10

0
0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
Throughput (kSPS)

Figure 13. AD4003 ADC power dissipation vs. throughput.

System Applications
A combination of ease of use features and high performance, small
footprint, and low power makes the AD4000/AD4003 ADC family a great
solution for many precision control and measurement system applications
Optical Avionics
as shown in Figure 14. The AD4000/AD4003 ADC reduces measurement Communications Measurement
uncertainty, increases repeatability, allows high channel density, and in- and Control
creases the throughput efficiency of automated test equipment, automated
machine control equipment, and medical imaging equipment. This ADC is a
good fit for systems that demand higher frequency performance to capture Medical Imaging CT
fast transients and time of flight information, such as power analyzer and and Digital X-Ray

mass spectrometer applications. Figure 14. AD4000/AD4003 ADC end system applications.

(continued on Page 47)

Analog Dialogue Volume 50 Number 4 45

Rarely Asked QuestionsIssue 136
Precision Current Outputs Are Easy to Make
By James Bryant
Share on
Question:
How do I design a circuit with an accurate current output into a nonlinear
load resistance?
Answer:
Its easy to make current output devices. A number of simple circuits can
deliver unipolar constant current into a varying or nonlinear load. Bipolar
circuit options are more limited, although still quite simple.
I recently needed power for some LED lamps. Several engineer friends
thought that I would have trouble making the variable current supply that is
needed to allow them to be dimmed. In fact, I quickly modified some black
brick laptop power supplies (bought for pennies at a car boot sale) to do
the job.1
If the input to the amplifier is also a stiff current source (that is, a current
whose value does not vary with loading), a current mirror using two
matched bipolar junction transistors (BJTs), on a single chip to ensure
temperature matching, is often all that is needed. The current is applied to
both bases and one collector, the two emitters are grounded and an equal
current flows in the other collectorslightly more complex arrangements
may improve performance but the basic circuit is often adequate.
46
It is far easier to obtain matched NPN BJTs than matched PNPs, although
the latter are available. A current mirror of a current from positive supply
to a grounded source with the mirrored current to a grounded load may be
made with matched PNP transistorsbut there are also a couple of fast
current mirrors with a dynamic range of 106 (1,000,000:1), the ADL5315,
andADL5317.2
For a voltage input you simply need an op amp, a transistor (FET or BJT),
and a resistor. The input is applied to the op amp noninverting input, the op
amp drives the transistor gate/base, the resistor is connected to ground,
and to the op amp inverting input and the source/emitter, and the output
current flows in the drain/collector.
These circuits are normally grounded and their load is connected to a dc
supply. Whether NPN/N-channel or PNP/P-channel devices are necessary
depends on the supply polarity. If the current must drive a grounded load
the circuit may be connected to the supply railbut the signal input will
require level shifting.1
If a bipolar current output is required, a standard voltage amplifier
(probably an op amp) is used to drive the load through a small current
sense resistor. Negative feedback to the amplifier is taken from a current
sensing amplifier connected across this resistor. The supply voltage must
be large enough to drive the maximum expected current into the maximum
load under worst-case load bias conditions.
If a circuit requires a fixed current load despite varying voltage, a very
simple (but not very stable with temperature) two terminal constant
current device may be made from a depletion-mode JFET with a resistor
connected between its source and its gatethe gate and the drain are
the two terminals (with an N-channel JFET the drain is positive, with a
P-channel one its negative). The current is set by adjusting the resistor.
The short article mentioned below describes the circuits mentioned above
in more detail, and with diagrams, but the basic principles of accurate
current output amplifiers are simple.1
When I started to write this article I was going to describe how a precision
two terminal floating current source could be built with an op amp, a
precision voltage reference, three resistors, and a capacitor, but since
Analog Devices and Linear Technology have announced that they are
Analog Dialogue Volume 50 Number 4
merging, Ill recommend an integrated solution. Linear Technology has References
two such devices, ready-made, in their catalogI have used them in my 1
James Bryant. Current-Output Circuit Techniques Add Versatility to Your
personal projects for some years but have not, of course, mentioned them Analog Toolbox. Analog Dialogue, Apr 2014. Analog Devices, Inc.
in my articles for Analog Devices. I am very pleased that now I am able to
do so. 2
AD5315 data sheet/AD5317 data sheet. Analog Devices, Inc.
They are actually three terminal devicesan external resistor between 3
LT3092 data sheet. Linear Technology.
the negative supply and a reference pin and another between the negative
output and the negative supply define the current. The LT30923 works from 4
LT3083 data sheet. Linear Technology.
500 A to 200 mA, and the LT30834 from 500 A to 3 A.

James Bryant
James Bryant [ james@jbryant.eu] was a European applications manager
at Analog Devices from 1982 to his retirement in 2009 and still writes and Also by this Author:
consults for the company. He holds a degree in physics and philosophy Who Killed the
from the University of Leeds and is also C.Eng., EurEng., MIET, and an FBIS. In Component?
addition to his passion for engineering, James is a radio ham and holds the Volume 50, Number 4
call sign G4CLF.

(continued from Page 45)

Conclusion
The AD4000/AD4003 ADC family enables designers to solve the system-level
technical challenges for their high precision data acquisition system
without making significant trade-offs, reducing the total system design
time. The AD4000/AD4003 ADCs high performance increases measure-
ment accuracy and its small footprint coupled with low system-level
thermal dissipation enables higher density.

Maithil Pachchigar
Maithil Pachchigar [maithil.pachchigar@analog.com] is an applications
Also by this Author:
engineer in the Instrumentation, Aerospace and Defense business unit at
Analog Devices in Wilmington, MA. Since joining ADI in 2010, he has been Integrated Multi-
focused on the precision ADC product portfolio and customers in the plexed Input ADC
Solution Alleviates
instrumentation, industrial, healthcare, and energy segments. Having worked Power Dissipation and
in the semi-conductor industry since 2005, he has published numerous Increased Channel
technical papers. Maithil received his B.E. in electronics engineering degree Density Challenges
from S.V. National Institute of Technology, India, in 2003, M.S.E.E. degree from Volume 50, Number 1
San Jose State University in 2006, and M.B.A. degree from Silicon Valley
University in 2010.

Alan Walsh

Alan Walsh [alan.walsh@analog.com] is an applications engineer at Analog

Also by this Author:
Devices. He joined ADI in 1999 and works in the Precision Converters
Applications Group in Wilmington, Massachusetts. He graduated with a B.Eng. Front-End Amplifier and
RC Filter Design for a
in electronic engineering from University College Dublin.
Precision SAR Analog-
to-Digital Converter
Volume 46, Number 4

Analog Dialogue Volume 50 Number 4 47

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