Lecture-I

An Overview of Microprocessor
The first question comes in a mind "What is a
microprocessor?. Let us start with a more familiar term computer. A
digital computer is an electronic machine capable of quickly
performing a wide variety of tasks. They can be used to compile,
correlate, sort, merge and store data as well as perform calculations.
A digital computer is different from a general purpose calculator
in that it is capable of operating according to the instructions that are
stored within the computer whereas a calculator must be given
instructions on a step by step basis. By the definition a programmable
calculator is a computer.
Historically, digital computers have been categorized according
to the size using the words large, medium, minicomputer and
microcomputer. In the early years of development, the emphasis was
on large and more powerful computers. Large and medium sized
computers were designed to store complex scientific and engineering
problems. These computers were accessible and affordable only to
large corporations, big universities and government agencies. In the
1960s computers were accessible & affordable only to large
corporations, big universities & government agencies, In late 1960s,
minicomputers were available for use in a office, small collage,
medium size business organization, small factory etc. As the
technology has advanced from SSI to VLSI & SLSI (very large scale
integration & super large scale integration) the face of the computer
has changed. It has now become possible to build the control
processing unit (CPU) with its related timing functions on a single
chip known as microprocessor. A microprocessor combined with
memory and input/output devices forms a microcomputer. As for as
the computing power is concerned the 32- bit microcomputers are as
powerful as traditional mainframe computers.
The microcomputer is making an impact on every activity of
mankind. It is being used in almost all control applications. For
example analytical and scientific instruments, data communication,
character recognition, musical instruments, household items, defence
equipments, medical equipments etc.
Computers communicate and operate in binary numbers 0 and
1 also known as bits. It is the abbreviation for the term binary digit.
The bit size of a microprocessor refers to the number of bit which can
be processed simultaneously by the arithmetic circuit of the
microprocessor. A number of bits taken as a group are this manner is
called word. For example, the first commercial microprocessor the
Intel 4004 which was introduced in 1971 is a 4-bit machine and is
said to process a 4-bit word. A 4-bit word is commonly known as
nibble and an 8-bit word is commonly known as byte. Intel 8085 is an
8-bit microprocessor. It should be noted that a processor can perform
calculations involving more than its bit size but takes more time to
complete the operation. The short word length requires few circuitry
and interconnection in the CPU.

Microcomputers:
In a very general a microcomputer is best regard as a system
incorporating a CPU and assisted hardware whose purpose is to
manipulate data in same fashion. This is exactly what any digital
circuit designed using SSIs and MSIs will also do therefore,
microcomputer should be regard as a general purpose logic device.
In contrast to standard SSIs and MSIs where the manufacturer
decides what the device will do, with microcomputer it is the user who
decides what the device should do by asking it to execute a proper
set of instructions. A microcomputer, from this point of view is merely
an assembly of devices whose sole task is to ensure that the
instruction desire are indeed carried out properly and to allow the
microprocessor to communicate with the real world, i.e. the user
environment. The power of the microcomputer lies in the fact that if
the application change, the same system can still used by
appropriately modifying the instruction to be executed and if
necessary some changes in the hardware. In contrast, a digit circuit
designed using SSIs and MSIs for same application will need to be
completely redesigned if the application changes significantly.
The objective of a microcomputer is to manipulate data in a
certain fashion specified by the system designer. A typical
microcomputer achieves their objective by getting its CPO (p) to
execute a number of instructions in the proper sequence. This
sequence of instruction comprises the program that is executed by
the micro computer.
A microcomputer which does nothing other than manipulate
data present within itself, Will not be of much use to anybody. In order
to do something meaningful, data being manipulated should depend
on same fashion on input provided to the microprocessor would be
completely senseless unless the results of these manipulations
affects things outside the c itself. A c should on its input, the which
in same way, depends on its input, the way input and output are
related is decided by the program that gets executed.
Therefore, a c is an assembly of devices including a CPU,
which manipulate data depending on one or more inputs and
according to a program, in order to generate one or more output.

There are several standards for logic 1 and logic 0.

A) TTL logic 0V-0.8 V logic 0
2.4 V-5.2V logic 1

B) 20 mA current loop Zero current logic 0

20 mA current logic 1

C) RS-232 C +3V to +15V logic 0

-5V to +15V logic 1
For microprocessor and most of its peripherals, TTL logic levels
are used. 20 mA current loops are used for TTY and RS-232 C is
used for serial data communication.

Microcontrollers
A P does not have enough memory for program and data
storage, neither does it has any input and output devices. Thus when
a P is used to design a system, several other chips are also used to
make up a complete system. For many applications, these extra
chips imply additional cost and increased size of the product. For
example, when used inside a toy, a designer would like to minimize
the size and cost of the electronic equipment inside the toy.
Therefore, in such applications a microcontroller is used more often
than a microprocessor.
A microcontroller is a chip consisting of a microprocessor,
memory and an input/output device. There are 4 bit as well as 32 bit
microcontrollers.

Evolution of the Microprocessors

The history of the P development is very interesting. The first
P was introduced in 1971 by Intel Corporation. This was the Intel
4004, a processor on a single chip. It had the capability of performing
simple arithmetic and logical operations. E.g. Addition, subtraction,
comparison, logical AND and OR. It also had a control unit which
could perform various control functions like fetching an instruction
from the memory, decoding it and generating control pulses to
execute it. It was a 4 bit P operating on 4 bits of data at a time. The
processor was the central component in the chip set, which was
called the MCS-4. The other components in the set were a 4001
ROM, 4002 ROM and a 4003 shift register.
Shortly after the 4004 appeared in the commercial market
place, there is other general purpose P were introduced. These
devices were the Rockwell International 4 bit PPS-4, the Intel 8 bit
8008 and the National Semiconductor 16 bit IMP-16. Other
companies had also contributed in the development of P.
The first 8 bit P, which would perform arithmetic and logic
operations on 8 bit words, was introduced in 1973, by Intel. This was
8008 that was followed by an improved version- the 8080 from the
same company. The Ps introduced between 1971and 1972 were
the first generator systems. They were designed using the PMOS
technology. This technology provided low cost, slow speed and low
output currents and was compatible with TTL.
After 1973, the second generation Ps such as Motorola 6800
and 6809, Intel 8085 and Zilog Z80 evolved. These Ps were
fabricated using NMOS technology. The NMOS process offered
faster speed and higher density than PMOS and was TTL compatible.
The distinction between the 1st & 2nd generation devices was primarily
the use of new a semiconductor technology to fabricate the chips.
This new technology resulted in a significant increase in instruction
execution speed & higher chip densities.
After 1978, the 3rd generation microprocessors were introduced.
Typical Ps are Intel 8086/80186/80286 and Motorola 68000/68010.
These Ps were designed using HMOS technology.
HMOS provides the following advantages over NMOS.
1) Speed power produced (SSP) of HMOS is 4 times better than
that of NMOS. That is for NMOS, SSP is 4 picojoules (PJ) and
for HMOS, SSP is 1 picojoules (PJ).
Speed power product = speed * power
= nanoseconds * mill watt
= picojoules
2) Circuit densities provided by HMOS are approximately twice
those of NMOS. That is for NMOS. It is 4128 m2/gate and for
HMOS it is 1052.5 m2/gate, where 1 m = 10-6 meter.
 Later, Intel initialized the HMOS technology to fabricate the
8085A. Thus, Intel offers a high speed version of the 8085A called
8085AH.
The third generation introduced in 1978 is typically separated
by the Intel 8086 iAPX 8086 iAPX 80186, iAPX 80286 Zilog 78000,
and the Motorola 68000 which are 16- bit s with minicomputer like
performances. One of the most popular 16 bit P has been
introduced by Intel, which is 8088. The 8088 has the same
introduction set as the 8088. However, it has only an 8 bit data bus.
The 8088 is the P used in the IBM PC and its clones.A precursor to
these microprocessors was the 16-bit Texas instruments 9900
microprocessor introduced in 1976. The latest microprocessor has
the word length of 32-bit. Example of 32-bit microprocessors are Intel
iAPX 80386, iAPX 432, Motorola MC68020, National semiconductor
NS 32032. The characteristic for few microprocessors introduced by
Intel are given in the Table. This shows that power of
microprocessors has increased tremendously with advancement in
integrated circuit technology & microprocessor systems architecture.
Very large & cute integration, VLSI allow extremely complex system
consisting of as many as a million of transistors on a single chip to be
realized.
In 1980, the fourth generation Ps were evolved. Intel
introduced the first commercial 32 bit microprocessor, Intel 432. This
P was discontinued by Intel due to some problem. Since 1985, more
32bit Ps have been introduced. These include the Motorola MC
68020/68030/68040 and Intel 80386/80486. These processors are
fabricated using the low power version of HMOS technology called
HCMOS, and they include an on-chip RAM called the cache memory
to speed up program execution.
Table evaluation of major characteristics.
4004 8008 8085A 8086 80386
Data 71 71 77 78 85

Lass 4-bit 8 8 16 32

Technology PMOS PMOS NMOS HMOS CHMOS

Record size 4/8 8/8 8/8 16/16 32/32

data/ must
Address 4K 16K 64K 1M 4G
capacity
Clock 740/2 800/2 6250/2 8000/2 16000/2
kHz/phase
Add time 10.8 s 20 s 1.3 s 0.375 s 0.125 s

Internal reg. 1/16 1/6 1/6 1/8 1/8

al/gp
Tale size 3*12 7*14 RWM RWM RWM

Records/ bits 150- -9.5v +5V +5V +5V

10,5*
Voltages 16pin 18pin 40pin 40pin 132pin

Package size 45 48 74 133 135

introduction
Transition 2300 2000 6200 29000 275000

Chip size 117*159 125*170 164*222 225*230 390*390

(mil)
Manufactures Intel Intel Intel Intel Intel

The performance offered by a32 bit P is more comparable to that of

super computers such as VAX 11. Recently, Intel and Motorola
introduced a 32 bit RISC (Reduced Instruction Set Computer) P
(Intel 80960 and Motorola 88100) with a simplified instruction set. The
trend in Ps is not toward introduction of 64 bit Ps. Extensive
research is being carried out for implementation of more on chip
functions and for improvement of the speed of the memory and I/O
devices; i.e. microcontrollers.

Lecture-3
MEMORY:
It is a storage device. It stores program data and the results.
There are two kind of memories; semiconductor memories &
magnetic memories. Semiconductor memories are faster, smaller,
and lighter and consume less power. Semiconductor memories are
used as the main memory of a computer. Magnetic memories are
slow but they are cheaper than semiconductor memories. Magnetic
memories are used as the secondary memories of a computer for
bulk storage of data and informations. With the development in
technology, semiconductor memories are used everywhere.
Let us see how semiconductor memories are developed.

Development of Memory:
The smallest unit of information a digital system can store in a
binary digit which has a logic value of 0 or 1. A bit of data is stored in
electronics devices called a flip flop or a 1-bit register. A flip flop is
a general memory and has two stable states in which it can remain
indefinitely as long as the operating power is not interrupted. The
output can be changed only if the input signals allow for it. A very
simple type of flip flop is D- type flip- flop as shown in fig.

D Q
PR

CLK

CLR
 It has a single data input D and two input, Q and . Output Q
represents the state of flip- flop; represent the complement of the
flip- flops state. The logic value at a flip- flops D input when a clock
signal, CLK occurs is stored in the flip- flop. If the store value is equal
to 1 (Q = 1) the flip flop is set. If the stored value is equal to 0 (Q =
0) the flip flop is clear.
The logical operation of a D type flip flop is expressed by the
characteristic equation Qn+1 = Dn. This equation indicates that the
output of a D- type flip flop after the accordance of a clock pulse,
Qn+1 is equal to the logic value of the D input before the accordance
of the clock pulse Dn. But D type flip-flop differ with regard to the
praise time at which the clock pulse causes the input data to be
accepted, the output to change in accordance with the input, and the
output to be held or latched.
Two clock pulse or strokes are shown in fig positive clock pulse.
This signal is logic 0 in its quiescent state, makes a transition to logic
1 remains at logic 1 momentarily, and then returns to logic 0. The
leading edge of the pulse is a 0 to 1 or positive transition and the
trailing edge is a 1 to 0 or negative transition. The clock pulse shown
is a negative clock pulse, its quiescent value is logic 1 and it makes a
momentary negative transition to logic 0 followed by a positive
transition back to logic 1. A positive transition is also referred to as a
using edge, and a negative transition is also referred as the following
edge.
 Leadingedge
Trailingedge

1 Trailingedge
1

0 0

Leadingedge
(a)
(b)

An edge triggered D type flip-flop latches the logic value at

the D input during the clock pulses transition from one logic value to
the other. The sensitivity of the flip-flop to the transition (edge) of the
clock is indicated on the flip-flop logic symbol by a dynamic indicator,
a triangle <, at the clock input. Positive edge triggered flip flops
latch on the positive transition of the clock.

D Q

CLK
>CLK
(+veedge)
D

D Q Q

>CLK ( veedge)

Negative edge triggered Flip-flop/ latch on the negative transition of

the clock. If the clock pulse of fig (a) is applied to the +ve edge pulse
triggered flip-flop, the data is latched at the trailing edge of the pulse.
If the clock pulse of (b) is applied to a +ve edge triggered flip-flop, the
data is latched at the trailing edge of the pulse. Note that in the edge
triggered flip-flop, the input is accepted, and the output changes and
is latched during a single clock transition.
 A level triggered flip-flop usually referred to simply as a latch
has a clock input that is sensitive to the level of the clock signal. The
output of a positive level triggered D flip-flop follows the D input when
the clock signal is high. When the edge makes a transition from 1 to
0, the data present at the D input is latched. The output of a negative
level triggered D flip-flop follows the input. When the clock is logic 0
and latches the input on a 0 to 1 transition. Thus for a level triggered
flip-flop, the output follows the input, when the clock is at the trigger
level. During this condition the flip-flop is referred to as being the
input data is latched on the transition from the trigger level to the
quiescent level.

7475

D Q CLK

>CLK D

D Q
>CLK Q
(+ve)

Q
( ve)

The D flip-flop shown two additional inputs common to most ICs

preset & clear. Both the input is active low signals. Preset & clear are
asynchronous input; they affect the state of the flip-flop independent
of the clocks level or transition. Thus preset & clear have over side
influence on clock & synchronous input. Logic 0 at the clear input
clears it for proper operation preset & clear are not absorbed
simultaneously.
Examples of latches:
Typical examples of transparent latches are 74LS373 & the
Intel 8282 shown in fig. Both are functionally similar; however, they
are not pin compatible. These octal latches are suitable to latch 8-bit
data.

Function table:

Output Enable Input Output Output STB Input O/P

control G enable DI
L H H H L H H H
L H L L L H L L
L L X Q L L X D type
latch
H X X Hi
edge H X X L

 These devices include eight D latches with tri-state buffers.

They require two input signals, enable (G) & the output control for
the 74LS373 which are synchronous to the stroke ( STB ) & the
output control ( ) for the 82072. The enable is an active high signal
connected to the clock signal input of the flip-flop. When this signal
goes low data are latched from the data bus. When the output control
is low (active) the data latched is accessible to the display devices.
m- Bit register:
Memory is storage device and it is used to store both
instructions and data. The smallest unit of information a digital system
can store is a binary digit which has a logic value of 0 and 1. A bit
of data is stored in a flip flop. It is general memory cell and has two
states in which it can remain indefinitely as long as power is not
interrupted. The output can be changed only if the output signals
allow for it. D flip flop is the simplest flip flop to store one bit of
information. To store several bits of data simultaneously, the clock
inputs of several D flip-flops are connected in parallel to form an m bit
register (m may be 4, 6 or 8). Such registers store m bits of data D0 to
Dm-1 under the control of the clock and provide m bits of data output
Q0 to Qm-1.
To store m-bits of data simultaneously, the clock input of
several D- flip-flops are connected in parallel to form an m- bit
register (m may be 4, 6 or 8). Such register store m bit of data D0 to
Dm-1 under control of the clock and provide m data outputs O0 to Om-1.
The act of storing data in a register is a writer operation. Determining
the value of the content of a register is a read operation.
 The m- bit of data stored in a register make up a word. A word
is simply a number of contiguous bits operated upon or considered by
the hardware as a group. The no of bit in the word m is a word length.
The m input to the register are provided by an m- bit input data bus
and the m- output by an m- bit output data bus. A bus is a number of
signal line grouped together because of similarity of function, which
connect two or more systems or subsystem. Eight bit register are
often called octal registers (examples).

Several equal length registers can be incorporated in a single

IC and share a common set of inputs, a common set of inputs and a
single clock such as circuit is referred to as a memory. Each register
occupies a distinct location, which has a unique numerical address.
Thus, memory can be thought of as a collection of addressable
registers. Logic is necessary to decode address inputs to ensure that
only a single register outputs its contents when data is being read
from the memory, and only a single register has data stored in it
when the data is being written into the memory.

Lecture-5
Development of Memory Chip:
Let us consider a memory of 16 words, each of 8 bits is to be
stored. 16 words can be stored in 16 memory locations, each having
a unique 4 bit memory address (0000 to 1111) and each location
being capable of containing 8 bits of data.
To set up this memory system using ICs, 16 bit flip-flop
registers are required. To identify the correct address a 4 line-16 line
decoder can be used to decode the 4 bit location address to select
the appropriate data register (1 to 16) for input/output. Figure shows
the circuit used to implement the memory system.
 The 74LS374s are octal D flip flops with three state of outputs.
To store data in them, 8 bits of data are put on the D0 to D7 data
inputs via the data bus. Then the low to high edge on the clock input
will cause the data a D0 to D7 to be latched into each flip-flop. the
stored value in the D flip-flopis observed at the outputs Q0 to Q7 by
making the output enable pin low
To select the appropriate memory location, a 4 bit address is
input to 74154 (4 Line to 16 Line decoder), which outputs a low pulse
on one of the output lines when the is pulsed low. The timing
of setting up the address bus, data bus and pulsing the line
is critical. The following figure shows standard timing diagram bus
driven devices. Rather than showing all four address lines and all
data lines, they are grouped and X is used to show where any or all
of the lines are allowed to change digital levels.
 The address and the data lines must be set up some time (ts)
before the low to high edge of . In other words the address
and the data lines must be valid some period of time (ts) before the
low to high edge of in order for the74374 to interpret them
correctly.
When the line is pulsed, the decoder outputs a low
pulse on one of its 16 outputs which clocks the appropriate memory
location to receive data from the data bus. After the propagation
delay, (tp) the data output at Q0 to Q7 will be the new data just
entered into the D flip-flop. Then the tp will include the propagation
delay of decoder and of the D flip-flop.
In the figure all the three state outputs are continuously enabled
so that their Q outputs always active. To reduce the number of lines
the 8 outputs Q0 to Q7 of all 16 memory locations back to the data
bus. The enables of the 16 memory locations have to be
individually selected at the appropriate time to avoid a conflict on the
data bus, called bus contention. Bus contention occurs when two or
more devices are trying to send their digital levels to the shared data
bus at the same time. To individually select each group of Q outputs,
the grounds on the enables would be removed and instead be
connected to the output of another 74154 1 of 16 decoder.
 Commercially available memory chips combine all the decoding
and the storage elements in a single package.

MEMORY:
If a memory stores N- words of information each word being of
m bits, we say it is a Nxm memory. e.g. 8x4 memory means there are
8 words 4 each word containing 4- bit of information (called nibble). 8
words are stored at 8-memory locations and these memory locations
are clearly identified by addresses. Addresses are formulated by bit
combinations available in wires known as address lines. To identify 8
memory locations we require 3 address lines designed A2A1A0. The
memory locations identify and the corresponding content stored is
shown in table.
A2 A1 A0 Decimal Memory Contents of the
Equivalent Location memory location
0 0 0 0 0 M(0)
0 0 1 1 1 M(1)
 0 1 0 2 2 M(2)
0 1 1 3 2 M(3)
1 0 0 4 3 M(4)
1 0 1 5 5 M(5)
1 1 0 6 6 M(6)
1 1 1 7 7 M(7)

M(0) is the content of memory location 0. It has 4 bits here. M(1) is

the content of memory location 1 and so on. It can also be shown
us.

AB--- address bus.

The three address lines A2 A1 A0 together is known as address

bus. It is a unidirectional bus. The microprocessor always sends the
addresses.
In general, a Nxm memory shall have K address lines
designated Ak-1 Ak-2 Ak-3 A2A1A0, such that K is the smallest
integer satisfying the inequality 2k N. e.g. 200x8 memory shall have
200 memory locations 8 bit of information. To identify 200 memory
locations we require a minimum of K= 8 lines designated A7 A6 A5 A4
A3 A2 A1 A0. However K = 8 address lines can identify a total of 256
memory location starting from (0000 0000)2 to (1111 1111)2 or 00H to
FFH. but we are using only 200 memory locations and rest locations
are redundant. The 200 memory location shall be identified starting
from (0000 0000)2 to (1110 0111)2 or 00H to E7H. The other
combinations 1110 1000 B to 1111 1111 B or E8 H to FF h are not
used in this memory & are redundant addresses.
Since it is too tiring & boring to use binary numbers for identifying the
addresses we normally make use of hexadecimal number notation.
E.g. 200 memory location are identified starting from (00)H to (C7)H
,(C0)H to(FF)H are redundant memory locations. Using 10 address
lines designated A9A8A7..A2A1A0, we can directly address 210 =
1024 memory locations. This is conventionally known as 1K memory
locations.
The capacity of a memory is specified terms of the maximum
number of words the memory can store. In general, if the memory
has an R bit address and each word is of length m, then the memory
has a capacity of 2R*m bits, organized as 2K words each of m bits. If
R=10, then the memory can store 1024 words or 1K words. In most
of the 8 bit p the ps has 16 address lines. Therefore it can address
directly
216 memory locations = 20 x 210 memory locations
= 64 K memory locations
= 65536.
Thus, 8-bit microprocessor provides a maximum of 216 or 64 K
memory addresses ranging from 0000 to FFFFH.
Lecture-6
Characteristics of Memory:
An important characteristic of a memory is whether it is volatile
or non volatile. The contents of volatile memory are lost if the power
is turned off. On the other hand, a non volatile memory retains its
contents after the power is switched off. The best known non volatile
memory is magnetic core.
In the broad sense, a Cs memory system can be logically
divided into three groups:
1) Processor memory
2) Primary or main memory
3) Secondary memory
Processor memory refers to a set of P registers. These
registers hold temporary results when a computation is progress.
There is no speed disparity between these registers and the P
because they are fabricated on the same chip using the same
technology.
Primary memory is the external memory to store both program
and data. The P can access their memories directly. In earlier days,
the primary memory was designed using magnetic cores. In modern
Ps, MOS technology is employed in the primary memory design.
Usually, the size of primary memory is much larger than the
processor memory and its operating speed is slower than that the
processor registers by a factor of 25 or 30.
Secondary memory refers to the storage medium compositing
slow devices such as hard disks and floppies. These devices are
used to hold large data and huge program that are not needed by the
processor frequently. Sometimes, secondary memories are also
referred to as auxiliary or back up storage.
In order to design an efficient memory system, the following
characteristics of memory must be known.
The most important factor of a memory system is its cost,
expressed in dollars per bit. A good design implies a very low cost
per bit.
There are two parameters that will indicate the speed with
which information can be transferred in and out of a memory.
1) Access time, tA
2) Cycle time, tC
The access time tA is defined as the average time taken to read
a unit of information from the memory. Sometimes the access time is
also referred to as read access time. Similarly, one can define write
access time. Usually, the write access time will be equal to read
access time. The cycle time tC of a memory unit is defined as the
average time lapse between two successive read operations.
The reciprocal of access time is called the access rate (rA=1/tA),
which is expressed in bits per second. Similarly, the reciprocal of
cycle time is referred to as date transfer rate or bandwidth also
expressed in bits per second.
The third important characteristic of memory unit is its access
mode. The access mode refers to the manner in which information
can be accessed from the memory. There are two major access
modes. They are the random access mode and sequential access
modes. In random access mode, any memory location access time is
independent of the location from which the date is read. In sequential
access mode, the memory is accessed strictly in a sequential
manner. In this mode, the access time depends on the location in
which data is stored. They are also referred as serial access
memories. A bipolar memory and magnetic tape are typical example
for random & serial access memories.
Random access memories than its sequential access memory
2nd order to active a compromise. Some memories combine both
access modes and called semi-random memories. A typical example
is magnetic access whit one read/write head for each track. This
arrangement permits any track to be accessed. At random however.
Access within a track must be made in a serial fashion.

Classification of Memory:
In general, semiconductor memories can be clarified in two
main groups random access memories (RAM) and sequential access
memories (SAM).
RAM can be classified in three main groups as shown below.

ROMS:
The type of memory means the content of an address location
can only be read and cannot be written into. The contents of the
memory location are not destroyed whether the power is ON or OFF.
Such a memory is known as non volatile memory. ROMs are used to
store data on permanent basis. They are random access memories
and this makes them very useful for the storage of computer
operating systems, software language computers, look-up tables and
programs for dedicated microprocessor applications. ROMs can only
be read are not written into.

MASK ROMs:
Mask ROMs are programmed by a masking operation
performed on the chip during the manufacturing process. The
contents of a ROM are decided by the manufacture. These contents
are permanently stored in a ROM at the time of manufacturing. The
contents of MROMs cannot be changed by the user. Most desktop
computers use MROMs to contain there operating system and for
execution fixed procedures, such as decoding the keyboard and the
generation of characters for the CRT.

PROMs:
If user needs relatively few ROMs, there is a variation, which
cost more per devices but allows the user to in rest the information.
To avoid the high one-time cost of producing custom mask ROMs, IC
manufacturing provides user programmable ROMs. This device is
called programmable Read only memory. Using special equipments,
called PROM programmers, user can program a PROM- once.
Subsequently one can read the information out of PROM as often as
one wish, but one can never write into it again. Therefore once the
PROM is programmed with correct information it can be used as a
ROM only in microcomputer. If one needs to change or correct the
information stored in the PROM, one must pull it out, throw it away
and replace is with a fresh unused PROM, writing the new on
corrected information into this in used devices. The PROM will hold
its contents indefinitely.

These PROMs are provided with fusible links which are burned
during the programming. Once the data are permanently stored in the
PROMs, it can be read again and again by just accessing the correct
memory location.

EPROMs:
If a mistake is done in programming ROM and PROMs, the
correction cannot be made. The solution of this problem is erasable
PROM (EPROM). An EPROM is an erasable PROM. The contents
are erased by ultra violet light. Therefore, they are also called
UVEPROM. The user can not erase the content of a single memory
location, the entire contents are erased.
EPROMs can be reprogrammed using EPROM programmer.
Once programmed, it can be used as ROM in microcomputer. Later,
if one needs to correct the information stored, it is taken out from the
system, erase the program written, write new program into it and use
it.
The EPROM is erased by exposing an open window in the IC to
an ultraviolet light source for a specified length of time, typical erase
time vary between two and 30 minutes, the EPROM programmed and
providing proper addresses.
An EPROM also holds the information indefinitely once it has
been programmed. One can read the contents of an EPROM as often
as one like.

RMMs:
They are read mostly memories, since they have much slower
write time then read time, there memories are usually suited for
operation where mostly reading rather than, sorting will be performed.

E2PROMs:
E2PROM are electrically erasable PROM. They need not to be
removed from a microcomputer board for erasing. Erasing &
programming E2PROM is much easier as the ultraviolet sources are
not required. The stored information can be erased by applying a high
voltage of about 21V, a singly byte or the entire chip can be erased
in10 mille sec. This is faster than UV erasing and it can be done
easily while the chip is still in circuit, It is also known as EAPROM
(electrically alterable PROM). One can write into at any time without
erasing prior contents. The problems with EAROM are that
electronically they are relatively difficult to use also, they slowly lose
their information.
One application of the E2PROM is in the tuner of a morden TV
set. The E2PROM remember (i) the channel, you were watching
when your tuned off the set (2) the volume setting of the audio
amplifier.
RWMS:
In this type of memory one can either read the contents of an
addressed location in a MEMORY READ operation or one can write a
m bit of data in the addressed memory location in a MEMORY
WRITE operation. It is a volatile memory. It is normally known as
RANDOM ACCESS MEMORY (RAM). The content of RWM shall be
destroyed when the power is OFF. During of MEMORY REALD
operation the content of the addressed location is not destroyed. It is
only read onto the external data bus. During a MEMORY WRITE
operation, however, the original content of the addressed location is
destroyed and the new content takes it placed which is just now
written.
Read/write memories are used for temporary storage of data
and program instruction in a up based septum there are also RAMs,
RWMs are generally called RAMs, RAMMs a specific terms it tells
that the data can be read on written to any memory location,
RAM is classified as either static on dynamic, static RAMs
(SRAMs) flip flops as basic storage elements; whereas the dynamic
RAMs (DRAMs) use internal capacitor as basic storage elements,
additional refresh circuitry is needed to maintain the charge on the
internal capacitor of a dynamic RAM; they have more packing
density, there it has more storage capacity per unit area team a
static RAM, the cast per bit of dynamic RAMs is also much less than
that of the static RAMs.
Non-volatile RAM:
A Non-volatile RAM combines a static RAM and E2PROM into
the same chip. Such a device operates as a normal RAM. If power
supply fails the entire content of RAM are stored in E2PROM by a
single signal . A signal can transfer data from
E2PROM back into the RAM. E.g. x2201 is a non-volatile RAM of 1K
bit. The transfer time is 4msec.
Lecture-7
The symbolic diagram of a static RAM and ROM are shown below:

= Chip selection to control input.

= output enables signals.
Both the control signals are active low (in general) but they may
be active high, when the chip is selected then only addressed
memory location data is available on data lines provided is active.

= Chip selection to control input.

= output enables signal
= write enable signal
These are representative signal. These signals may be LOW or HIGH
for other ROMs. For READ operation, first address is placed and then
make = LOW, the output is available. Under WRITE operation
may be HIGH or LOW but is active LOW. Under READ operation
is ACTIVE LOW but must be HIGH.
All these memories are random access memories. In RAM any
memory location can be accessed in a random fashion without regard
to another location. The access time is same for each memory
locations.
INTEL 2716 EPROM:
This is an Ultra Violet Erasable Programmable ROM {UVEPROM}.
The pin connection & logic symbolism is shown in fig. (a) and (b)
respectively. It is a 2Kx8 ROM. It has 2048 memory. It has 11
address lines. While programming Vpp must be held at 25 volts. It this
chip is used in a microcomputer after programming this voltage must
be held at +5V.

Figure (a)
The pin details are given below:
GND = +5V and Ground
- address lines
data lines
Programming voltage
= output enables (to enable the output data buffer)
/PROG= dual function pin. While programming HIGH pulse is
applied at this pin and during read operation the chip is selected
enabled by making pin low.

When it is completely erased then each bit must be 1. If we want to

store 0 we write 0 there. Before programming each address stores
FFH but to store any data at the addressed location a 50ms pulse is
given to the PROG.

For programming 2716 is connected as shown in figure and following

operations are done in sequence:
1. Apply 25V dc to pin no 21(Vpp).
2. Keep the (output enable bar) high (+5v).
3. Establish the address at the address bus.
4. Established the desired data to be stored at the addressed
location on then data bus.
5. A positive TTL pulse of 50msec duration is applied to the pin
no. 18 ( /PROM).

The waveforms during programming are shown in figure below:

The above procedure is repeated for all location to programme all the
2K memory location. One can programme 2716 partly as required. All
the above actions are carried out in separate unit known as EPROM
programmer. It requires only 100sec to programme all the memory
locations.
Once the programme is written down in memory chip, it cannot be
erased. If we want to change it we put it in UV eraser and erase it and
then programme it again.

Once the chip is programmed, it can be used to read data again

as again. When the two inputs and are in their normal state
(HIGH) the output is tri-stated. Now one can only perform a
MEMORY READ operation from this device. The following is the
procedure for a MEMORY READ operation.
1. Establish the addresses of the memory location to be read on
the address bus.
2. Make the signal ACTIVE LOW.
3. Apply a control signal to terminal i.e. make the
ACTIVE LOW.
 is normally HIGH by the microprocessor and to read date low
is generated. This is known as MEMORY READ operation. The
waveforms during read operation are shown in figure below:

The wave forms of the chip show that the data out puts became valid
after a delay for setting up the addresses on enable the chip on
inability the output whichever is completed last.

INTEL 6116 RAM:

It is 2Kx8 memory. It is a static RWM (2Kx8). This is pin by pin
compatible with 2716 ROM. The pin connection is shown in fig.(a)
and the logic symbolism is shown in fig.(b).
Fig (a)

Fig (b)
The truth table for control signals are as follows:
Operation REMARKS
The data available on the data bus shall
0 0 X WRITE be written on the addressed location. The
original contents are lost. The new labes
it place
The content of the addressed location is
0 1 0 READ READ on to the output data line 0-00. The
content other addressed location is not
destroyed.
No
0 1 1 operation Output is Tri state.
*tri stated
No
1 * * operation Output is Tri state.
tri stated

The two chips 2716 and 6116 are pin by pin compatible and can be
used in place of other. The pin by pin compatibility of 6116 with 2716
has a advantage. In the initial stage of a programme development we
fix up 6116 in the 24 pin socket provided on the microcomputer and
develop the programme. After a lot of effort we are ready with a
permanent programme. Once the programme is completely tested
and satisfactory then using a PROM programmer the programme can
be transferred to 2716 ROM for permanent storage. Thereafter, 2716
can be put directly to the same socket occupied by 6116. A simple
jumper should be provided for pin no 21. This is shown in figure
below.
Lecture-8
Dynamic RAM chip:
A dynamic RAM comprises storage cells that may be thought of
eclectically as capacitors there are many thousands of these
capacitors, or storage cells on a dynamic RAM chip, each all is
capable of storing one bit of information.
The capacitor that makes this storage cell is not ideal. That is,
change placed on this capacitor will leak off given enough time. In a
DRAM, the change on the capacitor represents the stored data.
Therefore, the data stored in the cell can be lost. A more accurate
model of the storage cell is a capacitor in parallel with a resistor.

To keep the stored information in a cap cell, DRAM is refreshed

again & again. In a dynamic RAM, the storage wills are organized in a
matrix form. Fig shows, the organization of 16cells in a matrix of
4rows & 4 columns. Each cell in a matrix has a unique position
specified by the intersection of a row& a column.
 Using Row & Column, any cell can be uniquely identified.
External signal lines are used to indicate which storage cell in the
internal matrix is to be accessed. These lines are called row address
lines & column address lines.

Due to the way in which DRAMS are fabricated, the storage

capacitor is not capable of providing large Q/P current to an external
load. Therefore a circuit called sense amplifier is placed at the output
of the storage cap to increase the Q/P current drive capability of the
cell.
 Solid state switch S, is fabricated in the DRA chip to isolate the
storage cell from all circuit external to that cell S1 is closed when
the row address & etc. address corresponding to the storage cell are
selected upon clearing s1, the change stored on the capacitor flame
through s1 & RL. Current flawing through RL causes a voltage drop
arose RL, the voltage developed across RL is increased by the sense
amplifier to a lever suitable for during an external load (which is
usually TTL),
 When S1 is closed, current flews thought r1 and change on the
capture is lost, this type of read is called destructive read operation
the data should not disappear in read operation. A latch is used to
refresh the stored data as shown in fig;

4116 dynamic RAM chip:

4116 is a161kv dynamic RAM, the chip has 16,384 storage
cells in its matrix from and as commonly referred to as a 16kk X 1 bit
DRAM, there are 16k unique memory location, storage cell A block
diagram of the chip is shown below;
Storage cell matrix block:
There are 16,384 storage cell in the 4116 organized in a cell
contains a storage cap & an.ssw which isolates the cap from the rest
of the incant in DRAM.

Address latch block:

Seven address lives A1-AO are input to this block, after proper
time, an address is latched in the address latch block, the output of
this block is input to both the how decode & the col multiplexer block.
Row address Recorder block:
The block have seven input line &128 output lines, seven
output line represent one now of the storage matrix cell.
Sense address Decoder block:
The output of the col of cells in the storage matrix are tied
together on a single line celled a bit line; there are 128 bit line in the
matrix and 128 sense amplifier.

Data latch block:

After data is read from a now of cells, it is mitten into the
latches in this block.
Column Multiplexer block:
Only are of 128 line input to this block is switched through to
the DOUT output lines the seven address signals input to the DRAM,
chip determine which one is selected.
Time block:
The sequence of events that take place within the DRAM is
determined by this block also provides control signal to most of the
other block the DRAM.
Pin out of 4116:
A6-A0: The up accesses are memory cell by outputting the row&
column address on these seven lines.

: When the up has output the col address on the A5-A0 lines, the
line is assented internally.

: When is asserted, the read add on AR-AO line is latched

internally.

DIN: Data is stored in the cap cell by making this line o or 1. After
the row & ecol address are latched internally, the up writer to the cell
by places data on this line.

DOUT: Data is read from the RAM chip their line, after the row & col,
address are latched internally, the selected cell entreats are output to
the line.

Lecture 2
Microcomputer Organization:
The basic components of a microcomputer are:
1) CPU
2) Program memory
3) Data memory
4) Output ports
5) Input ports
6) Clock generator.
These components are shown in figure below:

Central Processing Unit:

The CPU consists of ALU (Arithmetic and Logic Unit), Register unit
and control unit. The CPU retrieves stored instructions and data word
from memory; it also deposits processed data in memory.
a) ALU (Arithmetic and Logic Unit)
This section performs computing functions on data. These
functions are arithmetic operations such as additions subtraction and
logical operation such as AND, OR rotate etc. Result are stored either
in registers or in memory or sent to output devices.
b) Register Unit:
It contains various register. The registers are used primarily to
store data temporarily during the execution of a program. Some of the
registers are accessible to the uses through instructions.
c) Control Unit:
It provides necessary timing & control signals necessary to all
the operations in the microcomputer. It controls the flow of data
between the p and peripherals (input, output & memory). The
control unit gets a clock which determines the speed of the p.
The CPU has three basic functions
1) It fetches an instructions word stored in memory.
2) It determines what the instruction is telling it to do.(decodes the
instruction)
3) It executes the instruction. Executing the instruction may
include same of the following major tasks.
1. Transfer of data from reg. to reg. in the CPU itself.
2. Transfer of data between a CPU reg. & specified memory
location.
3. Performing arithmetic and logical operations on data from a
specific memory location or a designated CPU register.
 4. Directing the CPU to change a sequence of fetching
instruction, if processing the data created a specific
condition.
5. Performing housekeeping function within the CPU itself in
order to establish desired condition at certain registers.
4) It looks for control signal such as interrupts and provides
appropriate responses.
5) It provides states, control, and timing signals that the memory
and input/output section can use.

Program Memory:
The basic task of a microcomputer system into ensure that its
CPU executes the desired instruction sequence is the program
properly. The instruction sequence is stared in the program memory
on initialization- usually a power up and manual reset the processor
starts by executing the instruction in a predetermined location in
program memory. The first instruction of the program should
therefore be in this location in typical p basic system, the program to
be executed is fixed one which does not change. Therefore p
program are store on ROM, or PROM, EPROM, EEPROM.
In the trainer kit, ROM contains only the monitor program. The
user program is not stored in ROM because it needs not to be stored
permanently.

Data Memory:
A microcomputer manipulates data according to the algorithm
given by the instruction in the program in the program memory.
These instruction may require intermediate results to be stored, the
functional block in c have same internal reg. which can also be used
if available for such storage external data memory is needed if the
storage requirements is more.
Apart from intermediate storage, the data memory may also be
used to provide data needed by the program, to store some of the
results of the program. Data memory is used for all storage purposes
other than storage of program. Therefore, they must have head write
capability RWM or RAM.
It stores both the instructions to be executed (i.e. program) and
the data involved. It usually contains ROM (Read memory). The ROM
can only read and cannot be written into and is non volatile that is, it
retains its contents when the power is turned off. A ROM is typically
used to store instructions and data that do not change. For example,
it stores the monitor program if a microcomputer.
One can either read from or write into a RWM. The RWM is
volatile, that is it does not retain its contents when the power is turned
off. It is used to store user programmes & data which are temporary
might change during the course of executing a program. Both ROM &
RWM are RAM (Random access memory). RWM is respectively.
During a memory read operation, the content of the addressed
location is not destroyed. During a unit operation, the original content
of the addressed location is destroyed.
Both ROM & RWM are arranged into words, each of which has
a unique address. The address of a word is memory location and it is
placed in parentheses. Therefore, X is an address and (X) is the
content of that address X.
 The address decodes taken an address and from the control
unit and select the proper memory location and obtaining its content
takes a certain amount of time, this times is the access time of the
memory. The access time affects the speed of the computer, pins,
and the computer must obtain the instruction and data from the
memory. Computer memory as usually RAM so that all memory
location have the same access time. The computer must wait shiner
of units memory, typical memory access time range from several
uses. Memory sections often subdivided into units called pages. The
entire memory section may involve million of cords, when a page
contains between 256 & 4k warts. The computer may access a
memory location by first decreasing a particular page and then
accessing a location on that page. The advantage of paging is that
the computer can reach several locations on the same page with just
the address in the page. The process is like describing street address
by first specifying aspect and them listing the have numbers. The
control section transfers data to or from memory as follows.
1. The control section reads an address to the memory.
2. The control section sends a read and write signal to the
memory to indicate, the direction of the transform.
3. The control section waits until transfer has been completed .this
delay precedes the actual datas transfer in the input case and
follows it in the output case.

Input/Output Ports:
The input & output ports provide the microcomputer the
capability to communicate with the outside world. The input ports
allow data to pass from the outside world to the c data which will be
used in the data manipulation being done by the microcomputer to
send data to output devices
The user can enter instruction (i.e. program) and data in
memory through input devices such as keyboard, or simple switches,
CRT, disk devices, tape or card readers. Computers are also used to
measure and control physical quantities like temperature, pressure,
speed etc. For these purposes, transducers are used to convent
physical quantise into proportional electrical signals A/D computers
are used to convert electrical signals into digital signals which are
sent to the compute.
The computer sends the results of the computation to the
output devices e.g. LED, CRT, D/A converters, printers etc.. These
I/O devices allow the computer to communicate with the outside
world I/O devices are called peripherals.

Clock Generator:
Operations inside the p as well as in other parts of the c,
are usually synchronous by nature. The clock generator generates
the appropriate clock periods during which instruction executions are
carried out by the microprocessor. This condition ensures that events
in different path of the systems can proceed in a systematic fashion.
Some of the microprocessors have an internal clock generator
circuit to generate a clock signal. These microprocessors require an
external crystal or RC network to be connected at the appropriate
pins for deciding the operating frequency (e.g. 8085). Some
microprocessors require an external clock generator (e.g.
8086).These microprocessors also provides an output clock signal
which can be used by other devices in the microcomputer system for
their can timing and synchronizing.
Lecture-9
Intel 8085 Microprocessor
It is a 40-pin DIP(Dual in package) chip, base on NMOS technology,
on a single chip of silicon. It requires a single +5v supply between
Vcc at pin no 40 and GND at pin no 20. It can address directly 216
memory locations or 6536 memory locations or 64k memory locations
using 16 address line (A15-A0).
Pin no 28 to 21 gives as the higher order 8 bits of the address (A15-
A8).these 8- address lines are uni-directional tri-state address lines
these address lines becomes tri-state under three conditions namely.
(a) During DMA (direct memory access )operation
(b) When a HALT instruction is executed
(c) When is being RESET.
A15-A8 at pin no 19 to pin no 12 pin no 19 to pin no 12, marked A7-
A0 is used for dual purpose. The during it operation shall move
from one state to the other. There are ten (10) different states for the

(1) RESET STATE (TRESET) can be in TRESET state for an

integral multiple clock cycle.
(2) WAIT STATE (TWAIT) can be in this state for an integral no
of clock cycle. The duration being determined by an external
control signal input marked READY.
(3) HOLD STATE (T HOLD) depends upon the external control
signal input HOLD.
(4) HALT STATE (THALT) enter there state when an ILT
instruction is executed by it remains in this state till such time
when an external signal dictated by the use asked the to
perform further duties.
(5) The other states, the can be IN are marked T1,T2,T3,T4,T5 &
T6 states each of them states are of one clock period duration
each of there states clearly identifies the predetermined timing
 slots T1,T2,T3,T4,T5 & T6 perform specific very well defined
activities during these states.

Pin Configuration of Intel 8085A Microprocessor:

Pin no 19 to pin no 12 shall be utilize by the to sent lower order
bits of the 816 bit of information during T1 timing slots and therefore,
the same 8-points shall be utilized as bi-directional data bus (BDB)
for data transfer operation in the subsequent timing slots T2 & T3
Hence these pins are designated AD7 to AD6
These 8- lines are also tri-state line they will be tri-stated during T4,
T5 & T6 states. They will also be tri-stated during DMA operation and
when a HALT instruction is executed. These lines will also be tri-
stated for a very-short duration of time (few neon sec) between T1 &
T2 states.
ADDRESS LATCH ENABLE (ALE) AT PIN NO 30
it is a single pulse issued every T1 state of the as shown on
fig-2.since the lower order 8-bits of the address information A7 to A0 is
available at pin no 19 to 12, when ALE pulse exists at pin no 30. We
can use these information to latch the lower order bits of the address
externally using (say) an 8212 register latch once save on an external
latch the lower order address A7 to A0 shall be available at the output
of the register latch for the subsequent states T2, T3, T4, T5 & T6,
while pin no 19 to 12 can then be utilized by the for bi-directional
operation.
The manner of utilization of pins 19 to 12 is known as time
multiplexed mode of operation.
De multiplexing the Address bus AD1 AD0:
The 8085 A uses a multiplexed address-data bus. This is due to
limited number of pins on the 8085A-IC. Low-order 8-bits of the
memory address (or I/O address) appear on the AD bus during the
first clock cycle. (T1 state of an m/c cycle) It then becomes the data
bus during the second and third clock cycles (T2 and T3 states). ALE,
address latch enable signal occurring during the T1 state of a m/c
cycle is used to latch the address into the on-chip latch of certain
peripherals such as 8155/8156/8355/8755A. These chips ALE input
pin is connected to the ALE output pin of the 8085 A, thus allowing a
direct interface with the 8085 A. Thus IC chips internally de multiplex
the AD bus using the ALE signal. Since a majority of peripheral
devices do not have the internal multiplexing facility, there is external
hardware necessity for it.
Fig. shows a schematic that uses a latch and the ALE signal to
de multiplex the bus. The bus AD1-AD0 is connected as the input to
the latch 74LS373. The ALE signal is connected to the enable (G) pin
of the latch, and the output control (OC) signal of the latch is
grounded. When ALE goes high during the T1 state of a m/c cycle, the
latch is transparent in the output of the latch changes according to the
input. The CPU is putting lower-order bits of address during this time.
When the ALE goes LOW, the address bits get latched on the output
and remain so until the next ALE signal.

Read & Write Control signals at pin no 32 & pin no 31 &

The BDB at pin no 19 to 12 are used for bi-directional data transfer

operation T2 & T3 states when the BDB is inputting the information
from the external world into the , we say that is in READ MODE
and operation is READ operation. When the is outputting 8-bit of
information to the external world through BDB we have a WRITE
operation is in OUTPUT MODE or WRITE MODE. To tell the
external world that is in WRITE MODE. Issues a control signal
output at pin no 31 it is normally HIGH & becomes active & LOW.
It goes LOW during T2 state and goes HIGH again during T3 state of
the. This is shown is fig.3
When the BDB is in the input mode for READ operation, the
control signal. Output goes Low during T2 state and goes HIGH
during T3 state. Note that the normal state of is HIGH. Also note
that for obvious reasons & are not made active LOW
simultaneously. Note further whenever, the BDB is made to be in the
INPUT MODE by the , it issues the control signal output by
making it active LOW as described and it is for the user to beep the
appropriate 8-bit data either from the memory or from a peripheral
device at this appropriate time similarly during a WRITE operation
first send the desired address in the address lines during T1 states.
Thereafter, if places the desired 8-bit data on the BDB which is na in
the output mode and then issues the control signal output as
described. It is for the user to take appropriate action externally by it
interfacing circuitry so that the data so placed goes to the appropriate
device.
IO/ at pin no 34
O/ is an output tri-state control signal. It is active both way
whenever the address issued by the on the address lines refers to
the memory then the makes IO/ LOW throughout T1,T2,T3,T4,T5
& T6 states to indicate the external world that the address so sent
belongs to the memory and data on the BDB refers to the memory.
Whenever the address in the address lines. Refers to an I/O device
the makes IO/ control signal output HIGH to tell the external
world that the address in the address lines refer to I/O device and the
data in the BDB refers to an I/O device.
Note that IO/ signal is LOW or HIGH as the case may be
throughout six timing slots T1,T2,T3,T4,T5 & T6 states. It is for the user
to make use of the facilities give to develop proper interfacing
circuitry.
Lecture-10
READY at PIN NO 35
this is a control signal input. There are many peripheral devices
which are slow in operation can be to the speed eg. The occurs
time of a memory interfaced with a may be much larger than the
clock period of the Thus is a need for telling the that the device
so addressed by the is not ready for data transfer operation. The
device, selected should have the ability to generate a control signal
output READY which shall be LOW of the device is not ready for data
transfer operation and goes HIGH when the device is READY for
data transfer operation.
This idea is summarized in fig-4 considering memory as the external
device.

The sent the address during T1 state of the to address the

memory and then issues appropriate RD or WR signal during T2
 state either to read the memory or write into the memory Having
issued the appropriate or signal during T2 states the
monitors. READY control signal input if the READY control signal
input LOW the knows that the device addressed is not ready
for data transfer operation and therefore goes to WAIT state
(TW). Once in WAIT state, the does not do any other work
except monitoring control signal as long as READY signal is
LOW, remains in WAIT state when the READY signal goes
HIGH realized that the device addressed is ready for data
transfer operation and comes out of the WAIT state and goes into
T3 state. The partial state dig describing the above process is
shown in fig.5.

The appropriate control signal output or shall remain LOW

throughout the TW state and goes HIGH when the comes out of
the WAIT state and goes to T3 state the corresponding timing signals
are shown below. In fig-6.
 at pin no.36

It is an input control signal normally HIGH and active LOW. It is used

to RESET the to its initial state. The initial state of the shall be
described later. During power ON the must be RESET. The
necessary circutary for resetting the is shown in fig-7. Initially the
capacitor is discharged therefore to start with when the power is first
ON, control signal is LOW. Therefore the will be RESET
to its initial state. Depending upon the time constant RC the voltage
across the capacitor experientially increases to 5 volts. When the
voltage across the capacitor reaches to 2.4 volts, control
signal goes to logical 1. Comes out of the RESET state and
straight away goes to T1 state. The time duration to reach around 2.4
volts from the instant of switching the supply is around 4 to 5 CLK
cycles. If this duration is not maintain the resetting action of the is
not guaranteed and therefore, RC combination should be selected
accordingly.
The diode D in fig-7 is to provide for the discharge path for the
capacitor charge voltage. Whenever the power supply is finally put
OFF the push bottom switch provided in fig-7 can be used to RESET
the to its initial state as and when necessary during the functioning
of the The partial state diagram when Control signal is
active is shown-in fig -8
RESET OUT at PIN NO 3 It is normally LOW, when
control signal is HIGH. Reset out goes active HIGH as long as
is active LOW. This RESET OUT control signal is provided
for the user to use it RESET all the peripheral devices to their initial
states.
It is normally low signal output. It indicates 8085 A is being
RESET. When RESET IN control signal is low, RESET OUT goes
HIGH. It remains HIGH as long as RESET IN is active and LOW. This
output is used to reset other devices used in the microprocessor
system. The signal is synchronized with the system CLK and it
remains high for an integral no. of clock periods. After the RESET IN
goes HIGH, RESET OUT goes LOW, the microprocessor enters in
the T1 state and normal operation begins.

X1,X2, terminal at pin no.1& 2 and CLK (OUT) at pin no.37 :

Intel 8085A provi9des on chip crystal oscillator circuit which is
shown in fig-9.
A crystal has to be connected across X1& X2 to provide a crystal fq of
fc MH3. Because of the internal T-F/F the operating fq , clock is fc/2
(half the crystal fq). The , clock is also buffered and sent out through
pin no 37 to the outside world as clock (OUT) signal clock (OUT)
signal is used for synchronizing the operation. The data sheet of 8085
puts a lower limit, to the operating fq at 500 kH3. The max operating
fq limit fq for 8085 A-2 is 5MH3. Therefore, while using 8085A , a
crystal having a +q from 1MH3 up to 6.25 MH3 can be used; 10MH3
crystal has to be used for 8085A-2 . The 20pf capacitor on fig-9 is
necessary between X2 and ground if the crystal fq is less than 4 MH3
to provide for proper oscillation. It is not necessary for higher gq. The
data sheet also mentions 15pf. Sheet capacitors across X1&X2
internally.
A crystal is to be used across X1&X2 to get stable fq of oscillation if
stable fq of oscillation is not necessary in our application, then a L-C
network or a R-C network can be used as shown in fig 9(b) & 9 (c).
 The frequency of oscillation of fig 9(b) is given by
f=

The data sheet recommends as external capacitance of around. If a

large variation of fg can be tolerated in our application then fig-9(c)
can be used. Fig-9(c) is for 3MH3 oscillation. No other fq is
recommended using the connection if we have an external clock
whose fq is same and can be varied from 1MH3 to 6.25 MH3, then the
external clock can be connected as shown in fig-9(d).
If we have an external clock whose frequency is same and can
be varied from 1MHz to 6.25 MHz, the external clock may be
connected to x1 and x2 is left open. If the driving frequency is 8 MHz
to 12 MHz, stability of the clock generator will be improved by driving
x1 and x2 with a push pull force. To prevent self oscillations of the
8085, x2 should not be coupled back to x1 through the driving circuit.
In last two cases, pull up resistors are required to assure that the high
level voltage of the input is at least 4v and maximum low level voltage
of 0.8V.
Lecture-11
INTERRUPT CONTROL SIGNALS TRAP at pin no 6, RST 7.5 at
pin no 7,at pin no 6.5 at pin no 8, RST 5.5 at pin no 9, and INTR at
pin no 10 are interrupt control signal input provided for interrupting
the while it is executing the main programme. These interrupt
control signal input can be broadly divided in to two categories.
(a) Non maskable interrupts
(b) Maskable interrupts
Non maskable control signal input are those control signal input
which can interrupt the programming execution once the power is
ON. The maskable interrupts are those control signal inputs which
can be individually disabled or enabled as and when necessary, once
the power is on. The TRAP signal control input of INTEL 8085 is NMI
(non-maskable interrupts) signal.
The way these interrupt control signal input interrupt the can be
pictorially represented as shown in fig.10.

TRAP at pin no.6:

TRAP is a non maskable RESTART vectored interrupt. When
the power is ON, it is enabled and enable interrupt command is
required TRAP has the highest priority of any interrupt. It is both
raising edge and lends sensitive interrupt i.e. it becomes active at the
Lo-Hi edge but must stay high until it is sampled and recognized.
Whenever this interrupt is recognized, it forces the 8085 A to perform
a CALL (0024) H instruction, means when the current execution is
over, the PC is loaded with 0024 H so that the CPU starts executing
the program from 0024 H.

INTR at pin no.10:

This is the lowest priority interrupt request in the 8085 A
processor and is used as a general purpose interrupt. An input of
INTR=1 implies some external device has put up an interrupt and
wants the CPU to execute an appropriate service routine. The 8085 A
monitors the status of the INTR line by sampling it in the last but one
clock cycle of each instruction and during HOLD & HALT states. If the
interrupt structure of the 8085 A is enabled when INTR is sampled
high, the program counter (PC) will not be incremented and an
INTA=0 will be issued by the in response to INTR. It is now the
responsibility of the interrupting device to issue a RESTART or CALL
instruction so that the 8085 A can jump to the proper interrupt service
routine.
 The INTR is enabled by executing a EI instruction and is
disabled by executing a DI instruction. Disabled means INTR will not
be acknowledged. It is also disabled by RESET and immediately after
an interrupt is acknowledged.

INTA at pin no.11:

(Interrupt acknowledge) This is an active low control signal
output. When the acknowledges the interrupt than instead of RD
signal it issues INTA signal to tell the external world that it is in
interrupt acknowledge m/c cycle. Basically, it replaces RD control
signal output during INTA m/c cycle. INTA is normally high and
becomes active low during T2 timing slot of the and goes high
again during T3 state of the just like RD signal. During this period
RD signal is HIGH. It can be used to activate an 8259 A interrupt chip
or some other interrupt port.

RST 5.5, 6.5 & 7.5:

These are 8085 As maskable restored interrupts. They operate
exactly like INTR except for the following:
1. The RESTART instruction is automatically inserted by internal
logic. It does not have to be provided from outside. These
instructions are:
RST 5.5 CALL 0020 H
RST 6.5 CALL 0034 H
RST 7.5 CALL 0030 H
The address for any RST can be calculated multiplying the RST
number with 8 and converting it into hex.
 E.g. For RST 5.5 the address is 5.5x8 = 44D = 002C H
2. RST 7.5 is an edge (LO-Hi) sensitive interrupt unlike RST 6.5,
RST 5.5 and INTR which are lend (High) triggered.
3. These three interrupts can be individually masked or unmasked
using SIM instructions.
4. They have higher priority than INTR, among them RST 7.5 has
the highest priority and RST 5.5 has the lowest priority.
Like the INTR, whenever any of these interrupts is recognized it
disables all the interrupts. These interrupts can be enabled/disabled
using EI/DI instruction.
M7.5 (Mask 7.5) is a FLIP-FLOP, R7.5 (RESET 7.5) is a flip-
flop. It is normally RESET when the power is on. Only LOW to HIGH
transition of RST 7.5 will SET the FLIP-FLOP and stores in R7.5.
When M7.5 is RESET only then this signal can interrupt the . R7.5
provides a seat (MASK is said open when it is RESET). A common
chain (MASK ENABLE FLIP-FLOP) is provided for all the MASKS.
This MASK ENABLE must be SET for individually enabling or
disabling the MASK doors.
The pictorial representation shown in fig-10 is self-explanatory.
The following FLIP-FLOPs are internally provided in the interrupt
system of the .
1). INTE FLIP-FLOP
When this FLIP-FLOP is RESET, the entire interrupt system is
disabled except for TRAP & no other interrupt control signal can
interrupt the . When the INTE FLIP-FLOP is SET, the interrupt
system is enabled and the other interrupt control signal can be
selectively enabled or disabled.
When the power is ON for the first time goes LOW
and it RESET, the INTE FLIP-FLOP so that the entire interrupt
system is disabled as described above. Then the INTE FLIP-FLOP
can be SET or RESET using instructions.

2) INTA FLIP-FLOP (Interrupt acknowledge

This is used only for internal operation by the .when first the
power is ON this FLIP-FLOP will be RESET by the control
signal. Thereafter, whenever a valid interrupt is recognized by the
it always RESETs the INTE FLIP-FLOP and then SET, the INTA
FLIP-FLOP. Before further action thus, further interrupts shall not be
recognized, unless, user through instructions in the programme
desires further recognition of the interrupt. This statement shall be
elaborated further in the interrupt chapter.

MASK FLIP-FLOP (M5.5, M6.5, M7.5)

These Mask FLIP-FLOPs are used individually to MASK the
interrupts RST5.5, RST 6.5, RST7.5 (RST stands for RESTART).
When these FLIP-FLOPs are individually SET, then the
corresponding interrupt is masked and the interrupt control signal in
question can not interrupt the (see fig-10). These Mask FLIP-
FLOPs can be individually and selectively CLEAR to 0 through SIM
instruction (SET INTERRUPT MASK) provided a particular FLIP-
FLOP known as MASK ENABLE FLIP-FLOP is also SET (set fig-10)
MASK ENABLE FLIP-FLOP can be SET simultaneously using SIM
instruction.

R7.5 FLIP-FLOP
The RST 7.5 control signal input is a LOW to HIGH transition
active interrupt control signal input. The LOW to HIGH transition of
the signal is registered in R7.5 FLIP-FLOP. Whenever M7.5 FLIP-
FLOP is CLEAR, the output of R7.5 is sensed and recognized as an
interrupt by the R7.5 FLIP-FLOP can be CLEAR through the
same SIM instruction. It is for the user to make use of these facilities.

With the above explanation, we can write the logic expression for the
logic variable, VALID INT.
VALID INT = 0 when none of the interrupt control signal input are
interrupting the microprocessor and VALID INT = 1 when any of the
interrupt control signal is active. Thus
VALID INT= TRAP+ INTE [INTR+R7.5 + RST 6.5 + RST
5.5 ]

(Interrupt acknowledge bar) signal at pin no.11

This is an active LOW control signal output replaces control signal
at pin no 32 during INTA machine cycle. when INTR control signal
input at pin no 10interrupt the tells the outside world that it is in
INTA machine by issuing IO/ =1 and also S1=1, S0=1throughout the
machine cycle output is normally HIGH and becomes LOW
during T2 timing slot of the and goes high again during T3 state of
the just like signal (note that =1 during this cycle).

SID & SOD at PIN NO 5 & 4

SID stands for SERIAL INPUT DATA and SOD stands for
SERIAL OUTPUT DATA. These two pins are specially provided in
8085 for communicating with serial devices, like CRT, TTY,
PRINTERS etc. as and when needed uses SID, SOD lines for
transfer of data bit by bit along the same lines more about these lines
when we talked about the use of RIM & SIM instructions.

Status Signals S1 (33) and S0 (29):

These two outputs along with IO/M signal output identify the
type of the machine cycle being executed by the 8085 A. These
signals are issued (or become valid) at the beginning of the machine
cycle and remain stable throughout the machine cycle. The falling
edge of ALE may be used to catch the state of these lines. The seven
types of machine cycles are:
1. Opcode Fetch Machine Cycle (OFMC)
2. Memory Read Machine Cycle (MRMC)
3. Memory Write Machine Cycle (MWRMC)
4. I/O Read Machine Cycle (IORMC)
5. I/O Write Machine Cycle (IOWRMC)
6. Interrupt Acknowledge Machine Cycle (INTAMC)
7. Bus Idle Machine Cycle. (BIMC)
The tells the external world the type of m/c cycle it is IN by issuing
the status signals IO/ , and throughout the machine

cycle. The truth table is shown below:

Machine Status signal Control Signal
Cycle
IO/M S1 S0 RD WR INTA
OFMC 0 1 1 0 1 1
MRMC 0 1 0 0 1 1
MWRMC 0 0 1 1 0 1
IORMC 1 1 0 0 1 1
IOWRMC 1 0 1 1 0 1
INTAMC 1 1 1 1 1 0
BIMC
HALT X 0 0

These control signal are normally HIGH and becomes active LOW
during T2 state and goes back to HIGH during T3 state. In between T2
& T3 states any no of WAIT states Tw can be inserted.

HOLD at pin no 39 and HLDA at pin no 38:

HOLD is a control signal input and HLDA is a control signal output
these two (hold acknowledge) signals are used for hand shaped
control during DMA operation (Direct memory access). The use of
these control signals are depicted in the function diagram of fig-12
The device asking for DMA makes the HOLD signal HIGH the
which continually monitor the HOLD signal input during even m/c
cycle recognizes that an external device is requesting for a DMA,
complete the current m/c cycle in, thereafter, tri -states the address
bus & the BDB (Bi-directional data bus), enters in to a HOLD states.
THOLD also while entering the HOLD state it issues the HLDA control
signal at pin no 38 HIGH. The external device asking for DMA
monitors the HLDA control signal and knows that the has gone
into the HOLD state when HLDA is HIGH thereafter, the address bus
and the data bus which are tri state with respect to the are in the
exclusive control of external signal asking DMA. The DMA operation
between the external device and memory continues
The while in HOLD state continues to monitor the HOLD control
signal input as long as it is HIGH it remains in HOLD state. The
external device performing the DMA operation, after completing its
operation makes HOLD signal LOW to tell the that the DMA is
over which is continuously monitoring HOLD signal in HOLD state
recognizes the above fact & comes out of HOLD state and continues
the operation from there it has gone into HOLD state.
Lecture-3
The Bussed Architecture for P
Now, the operation same, how the p connected to all memory
elements and I/O path one perfectly is that all the chips are
connected separately, to CPU in the case large no of address lines,
signal lines input and output lines are required from the CPU. The
size of the CPU increases much of all the blocks are to be
simultaneously controlled. The capability of expanding the system by
adding more components will be surely limited of CPU is fabricated
on action such that it provides interface to N devices adding on more
devices will be impossible. The system becomes too complete,
therefore bussed architecture is used to connect component to the
p.
Consider a situation where these are N devices connected to
one signal line. Devices P can use their line to transfer data to
devices N provided.
1. Device i knows when to output such that device v is a position
to receive the data, this can be easily successful device v has
same mean of signally devices i to output data.
2. Other than device i no other device outputs data on that signal
line during this time. Device i should be the only device ouput
data during the signal time. At this time other than device v no
other device should input the data on the signal lines.

If the above conditions can be entered the same signal line

can be shared by N devices to transfer data between any two of the
devices. The signal lines that are shared by a number of devices are
referred to as the bus.
Normal gates are not selected for driving the bus in a bussed
architecture. There is because such a gate will always be outputting
and it will not be possible to rectify condition (2). Therefore tri state
buffer are used for driving a bus the system bus includes data bus,
address bus and control bus.

Buses:
Bus is a group of parallel lines that connect two or more
devices. It carriers information in bits (When the microprocessor
needs to access a circuit memory location or I/O devices) in another
part of the c; it does so by setting up signals on the address bus to
identify the appropriate circuit. Data may be transferred by means of
data bus, in required direction between the circuit and the processor.
Signals on the control bus server a number of purpose such as
control the transfer of data direction.

The Microcomputer Bus:

The microcomputer contains three buses which carry all the
address, data and control information involved in program execution.
These buses convert the p to other devices so that information
transfer between the p & any of the elements can take place.
Address Bus:
In this bus, information flow takes place only in one direction,
from the microprocessor to the memory or I/O elements. Therefore,
this is called unidirectional bus. This bus is typically 16 bit long (A0 to
A15) and CPU can generate 65,536 different addresses and bus. A
memory location or an I/O element can be represented by each one
of these addresses.
When the microprocessor wants to transfer information
between itself and a certain memory location on I/O devices, it
generates the 16-bit address from an internal register and its 16
address pins, which then appear on the address bus. These address
bits are decoded to determine the desired memory location on I/O
devices. The decoding process normally requires hardware
(decodes).

Data Bus:
A set of data lines (8) referred to as the data bus is shared by
number of devices to transfer data between p and peripherals.
Case must be taken that at a time only. One device should output
data on the data bus, the other devices data on the data bus, the
other devices which can output data meet be in high 7 condition. The
data can flow in both directions that is to or from the p. Therefore,
this is a bidirectional bus. (BDB) In some microprocessors, the data
pins are also used to send other information such as address bits in
addition to data. This means that the data pins are time shared or
multiplexed. The Intel SDK-85 microcomputer, is a example where
the lower 8 bits of the address are multiplexed on the data bus,

Control Bus:
This bus consists of a number of signals that are used to
synchronize the operation of the individual microcomputer elements
The p uses these signals for every operation it performs (like
reading or writing a memory location on device). These signals are
also used to identify memory or I/O devices etc. e.g., RD, WR, IO/M ..
The microprocessor sends some of these control signals to the other
elements to indicate the type of operation being performed. The
bussed architecture of microprocessor is shown.

A microprocessor performs the function of the central processing

unit. The microprocessor in combination with memory, I/O & a clock
is essentially a microcomputer.
Computer Language:
Each machine has its own set of instructions based on the
design of its microprocessor. To communicate with the computer one
must give instruction in binary language or machine language the
form in which it is stored in memory that is as patterns of 1s & 0s.
Since it is difficult for most users to write programs in machine
language, computers manufactured have developed English like
words to represent the binary instructions of a microprocessor. e.g.
ADD, SUB or JMP etc. Users can write programs, called assembly
language, programs using these words called memories. However,
since the p can only executes the bit pattern of machine language
instructions, the assembly language program must be converted to
machine codes. This conversion can be carried out by hand, but this
procedure is also time consumes and error prone. Special programs
are available for each type of p that converts their assembly
language programs to the equivalent machine code. These programs
are called assembles and are num either on a microcomputer,
minicomputer.
Because an assembly language is specific to a gives machine
programs written in assembly language are not transferable from one
m/c to another. To circumvent this limitation, such general purpose
language as BASIC, FORTRAN, PASCAL, PL/M, C, have been
desired a program written in these languages are called high level
language. To convert these program written in HLL are converted in
to machine language by another program called compiler or
interpreter.
 High level language do have same limitations in p
applications. The machine codes produced by compiler may be less
efficient than that of the optimum equivalent ALP, increased memory
requirement may not be important in view of cheap memory chips but
increased executions time may be unacceptable in time critical
applications. It is then desirable to write time critical parts of the
program of the ALP. Further many peripheral devices dependent
operation may have to be programmed in ALP as such operation is
often not supported by high level language.

Applications of Microprocessors:
The application of microprocessors is increasing day by day.
There are memories applications few are:
1) Analytical scientific instruments
2) Smart terminals
3) Stacker crane controls
4) Conveyor controls
5) Word processor
6) Point of scale systems
7) Standalone electronics cash system
8) Electronic games
9) Vending and dispensing machines
10) Market scales
11) Traffic light controls
12) Home heating and lighting controls
13) Security & fire alarm system
14) Home appliances
15) Computer aided instruction
16) On line control of lab instrumentation
17) Desktop computers
18) Check processor
19) Payroll system
20) Inventory control
21) Automatic type setting
22) Compact business machines
23) Medical instrumentation
24) Automobile diagnostics
25) Data communication processing
26) Optical character recognition
27) I/O terminal for computers.

Lecture-12
INTERNAL ARCHITECTURE OF INTEL 8085: The Functional Block
Diagram Of 8085 Is Shown In Fig 16.

It consists of five essential blocks.

(1) ARITHMEDIC LOGIC SECTION

(2) REGISTER SECTION
(3) THE INTERRUPT CONTROL SECTION
(4) SERIAL I/O SECTION
(5) THE TIMING AND CONTROL UNIT
The description of each unit follows.

There is an internal bi directional bus of 8 bits. All the internal registers

which transfer data to the internal bus are tri state registers.

(1) ARITHMETIC LOGIC SECTION: This section consists of

(a) Accumulation(A)
(b) Temporarily Register (TR)
(c) A flag register (FR)
(d) An arithmetic logic unit (ALU)

(1) ACCUMULATION (A): It is a 8 bit tri state register accessible

to the user. Its tri state output is connected to the internal bus in
addition, it has a two state 8 bit output. The content of the
accumulator is always available at this two state output as the
accumulator can be manipulated through instruction. Its content
can be incremented its content can be decremented. Its content can
be transferred to memory location. The content of a memory
location can be transfers to the accumulator. All these can be done
through instructions. The result of an arithmetic operation carried
out by ALU shall also be stored back in the accumulator the result
of the operation, hence the name accumulator.
(2) TEMPORARILY REGISTER (TR): This is an 8 bit register not
accessible to the user. It is used by the p for internal operations.
The second operand as and when necessary shall be loaded into
this register by the p before the desired operation takes place in
the ALU. The register has 8 bits two state output. This shall be the
second operand to the ALU.
(3) ARITHMETIC LOGIC UNIT (ALU): ALU is a combination
logic block which performs the desired operation on the two
operands. One from the A and the other from the TR as the dictate
of the control signals. Generated by the timing & control unit. In
8085 p binary addition operation, binary subtraction operations
are the only arithmetic section possible. The result of only
arithmetic section possible. The results of the operation shall the
stored back in a accumulator when the instruction to be executed is
 subtraction operation, then the content of the TR shall subtracted
from the content of the accumulator and result shall be stored back
in the accumulator.
(4) FLAG REGISTER: Flag register is a bit register accessible to
the user through instruction each bit in the flag register has a
specific functions only of the bit are used as shown in fig 17.
D7
D0
S Z AC P CY

The three crossed bits are redundant bits and not used. They can be either 0
or 1. It is immaterial but normally forced to be zero. These five bits are
affected as a result of execution of an instruction. All instruction execution
do not affected the flags e.g. data transferring operation do not affect these
flags the arithmetic operation effect all these flags the meaning & the effect
of the fleegs are as follow;

CY CARRY FLAG BIT: this particular bit is SET if there is a carry from the
MSB position during an addition operation or if there is a borrow during the
subtraction operation, otherwise this flag is RESET.

P-PARITY FLAG BIT: The E flag is SET if the result of an operation

contains even nos of 1s otherwise it is RESET.

AC- AOXILIARY CARRY FLAG BIT: This bit is SET if there is a carry
from A3 bit to A4 bit of the accumulator during the process of executing
operation connected with an accumulator otherwise it is RESET. The AE
flag is useful for arithmetic & is used in a particular instruction known as
DAA (Decimal adjust accumulates).

Z-ZERO FLAG: Zero flag bit is SET if the result of an operation is zero,
otherwise it is RESET.

S-SIGN FLAG: This flag is SET if the MSB of the result is a 1 otherwise it
is RESET. As an example, let us consider the execution of the instruction
ADDB. ADD is the mnemonic for addition B is the second operand. The
first operand is known to exist as the content of the accumulator. The
meaning of the instruction is add the content of the B register to the content
of A register and store the result back in the accumulator, symbolically, we
write the macro RTL complemented.

(A) (A) + (B).

Let us suppose the contents of the A& B register are,

(A) = 9BH & (B) = A5H.before the execution of the instruction. It

mean content of (A) & (B) are,
A 1001 1011
B 1010 0101

A B 1 0100 0000 A
cy 1111 1111 AC

As a result of addition there is a carry from A3 will be A4 position in the

example and therefore, AC will be SET. Also there is a carry from the MSB
cut & therefore CY flag will also be SET soon after the execution of ADD B
instruction the accumulator certain (A) = (0100 0000)2 40 H and is not zero.
Therefore the Z flag is RESET to zero. Also the result certain only one 1
an add number. Therefore the parity pit will also be RESET to 0, therefore,
the sign flag shall be RESET to 0. Thus the flag register contains soon after
the execution instruction are 0001 0001 B = 11H.

As a second example, consider another instruction DCR C. DCR is the

mnemonic for decrement. C is the operand. This information means
decrement the content of the C register by 1 and store it back in the C
register, the MACRO RTL implemented is

C C 1 C C

Let us suppose C contains (C) =D2H before the execution of the instruction
after the instruction, C shall contains D1H and therefore in not zero.
Therefore the flag register will be affected as follows.
 S Z X AC X P X CY
FR = 1 0 0 0 010 0

On the other hand, if a contains 01H just before the execution if the
instruction, C shall contain 00H. Since the result of the operation is 0 the
zero flag shall now be SET to 1. Other flag will be affected in the normal
way.

These flag bits are utilized in many instructions for branding operations
during the execution of a programme normally one of these bits are tested
for TRUE or FALSE condition depending upon the condition the
programme branches. This is shown in fig 18.

REGISTER SECTION:

There are 6-8 bit register designed B, C, D, E, H, & L. all are accessible to
the user. In an instruction these six 8bit register along with the accumulator
A shall be identified by a 8 bit code designated either SSS or DDD.
Whenever SSS is used, it corresponds to service register. Whenever, DDD is
used, it corresponds to destination register. The code used as follows,

SSS or DDD
000 ----- B
001 ----- C
010 ----- D
011 ----- E
100 ----- H
101 ----- L
111 ----- A
Note in the above code 110 is not used. Whenever 110 is used for SSS or
DDD, it means a specific register pair (H,L), together to from 16 bit register
known as memory address register (MAR) or M- pointer.

As an example consider the instruction MOV V1, V2

This is an ALP statement, MOV is the mnemonic for move, and V1, v2 are
the operand register, in the statement, V2 is the source register and V1 is the
destination register. The meaning of the instruction is MOVE the contents of
v2 register into V1 register5. Symbolically this basic operation can be
described by a basic RTL statement (V1) ---- (V2).
This is a single byte instruction. The single byte being the operation code.
The arrangement of the op code single byte is shown in fig 19.

V1 code V2 code
0 1 D D D S S S
Fig 19 (a) gives the example of MOV A, H code for this statement is,

0 1 1 1 1 1 0 0
For move fig 19 (a).

The opcode is read is together 0111 1100 B = 7CH. when the instruction7CH
is executed content of H register shall be transferred to A register. Note
that content of H register is not destroyed. However, the original content of
A register is lost. Let us take another example for the use of code 110.

Consider the instruction MOV D, M

This is an ALP statement, M is the source of the operand and D is the

destination register. MOV is the mnemonic for move. The meaning of the
instruction is move the content of this memory location whose address is
available in (H, L) pair into the D register. This is a single byte instruction.
The operation code is 01010110 B = 56 B
 Figure 20

Whenever the instruction 56H is executed content of the memory location

whose address is available in (H,L) pair shall be loaded into the D register.
The content of the memory location is not destroyed. However, the content
of the memory location Y1 Y0 H whose address is X3 X2 X1 X0 H available
in (H,L) pair goes into the D register. The original content of D is lost. This
is illustrated in fig 20. The six general purpose register B, C, E, H, L can
also be combined together as register pairs are possible. (B,C) pair with
lower order 8 bits & B higher order 8 bits; (P,E) pair , E lower order 8 bits,
D higher order 8 bits, (H,L) pair with L- lower order 8 bits & H higher
order 8 bits. There is another register name stock pointer, (S,F) which is 16
bits register itself. Whenever an instruction refers to the register pair (B,C),
(D,E), (H,L), or (S,P) a 2 bit code RP is used to identify the register pairs (R
stands for the register pairs. (R stands for one bit & P stands for other bit)

RP
00 ----- (B, C)
01 ----- (D, E)
10 ----- (H, L)
11 ----- SP --------- (SPH, SPL)
Lecture-13
PROGRAM COUNTER:

This is a 16 bit register accessible to the user. It always contain the

address of the next instruction to be executed in a program
sequence. Thus the program counter keeps the track of the program
execution up to which it is complete.

Whenever necessary, the address information available in PC shall

be sent out through the address lines & BDB during T1 timing slot.
The higher order 8 bits PCH shall be sent out through A15 A8
address lines & the lower order 8 bits program counter shall be sent
out through AD7 AD0.lines during T1 states since the BDB contains
the lower order 8 bit address information during T1 state an ALE
pulse is also used by p.

The above statement can be symbolically stated through macro RTL

shown in the figure 22.

T1 :(AD7 ASD0 ) , A15 A8 PCH , ALE

T2 :RD 0, (PC) (PC) 1

Whenever the address information sent from the program counter to

the external world during T. state, then the PC shall be incremented
by 1 down the subsequence T2 state so that program counter points
to the next sequential byte. This also shown in fig.

Note: If the address information for PC has not been sent out during
T state to the external world, them the PC will not be incremented
using T2 state.

Whenever the address information is sent out from the program

counter to the address bus (external world) then the PC is
incremented by automatically during the subsequent T2 state so that
the PC points to the next sequential byte. If the data required
provides instruction is of two bytes or three bytes long or it may be
the next instruction to be fetched and executed. If instructions are
sequentially arranged in memory, this will guarantee that they will
also be executed sequentially. Sometimes, program execution
requires that non-sequential instructions executed e.g. JUMP or
CALL type instructions. This requires the program counter to be
loaded with an entirely new value. An 8-bit with a 16-bit program
counter requires two data moves to completely modify the contents of
the PC. If the address information from PC has not been sent out
during T1 state, the external worlds then PC will not be incremented
during T2 state.

When the is RESET, the CPU initializes the PC to 0000 H.

Therefore, the first instruction in the program should be at 0000 H in
the memory address space of the CPU.

STACK POINTER REGISTER:

The stack is a storage structure. It consists of number of

sequential and RAM locations in which a saves the internal
register contents during subroutine calls and interrupts so that they
will not be changed or destroyed by a subroutine.

8085 can address directly 64K memory locations. This is

known as directly addressable memory space starting from the
address 0000 H to FFFF H. this entire memory area is usually divided
by the user into program area, data area and stack area. It is for the
user to see that program area and data area do not overlap with that
of stack memory area. The size of the stack memory area depends
upon the application.
 E.g. the user for a particular process control operation may
decide to reserve memory space starting from 2600 to 2700 as the
stack memory space. This is shown in fig.

The stack pointer is a 16-bit register accessible to the user. It is

required to address a memory location in the stack. It contains the
address of the top of stack into which last data is written. Writing data
into a stack is called a PUSH operation and reading data from a stack
is called a POP operation. In the fig. shown 2700 H is known as the
bottom of the stack. There is an instruction in the instruction set to
initialize the stack pointer register to the bottom of the stack. This
instruction is LXI SP, BADR.

LXI is the numeric for Load immediate, BADR is a symbolic

name given to the 16-bit address which is to be loaded into the stack
pointer. The meaning of the instruction is to load the 16-bit of data
immediately available in the instruction itself into the stack point. In
this example, BADR equals 2700 H. when this instruction is executed
the situation is shown in fig. the stack pointer now points to the
bottom of the stack.

Now, let us suppose that while calling a subroutine it becomes

necessary to save the contents of (BC) reg pair and (DE) reg. pair as
they are used in the subroutine. The process of saving the content of
a reg. is known as push operation. The push operation is performed
at the beginning of a subroutine to save reg. contents and the
instruction for pushing the contents of the internal register is PUSH.
E.g. PUSH B. The meaning of the instruction is to push the contents
of BC reg. pain on to the stack so that it can be saved there till it is
restored. PUSH B operation affects the stack and stack pointer as
follows. Since the stack pointer always adds the address of the last
byte of data pushed onto the stack, therefore when PUSH B
instruction is executed, the stack pointer is decremented by 1 and the
contents of the B register are copied onto the stack at that address.
The stack pointer is decremented again, and the contents of the C
register are copied to that addr. Just after the execution of PUSH B,
the situation is shown in fig.
 Similarly, to store the contents of (D, E) pair PUSH D
instruction is used. The meaning of this instruction is push the
contents of the (D,E) pair onto the stack to save them there as shown
in fig. just after the execution.

Since the contents of (B, C) & (D, E) reg. pairs are stored at the
top of the stack, these registers are now available for further
computation in the subroutine. At a later stage of execution of the
program after utilizing B, C, D, E registers, there may be a need to
restore the original contents to the respective registers. E.g. at the
end of the subroutine, the data is restored to the proper register.

The restoration of the contents is a READ operation from the

stack and is known as POP operation. A POP register instruction
copies the stored data from the stack buck into the indicated register
pair. Just before the execution of POP instruction, let us say the
situation is as shown.
 Note that regs B, C & D, E have same different contents
because these registers are used in the subroutine.

To restore the contents of B, C reg pair POP B instruction is

used. Whenever their instruction is executed, the contents of the top
of the stack are read into the register (B, C) pair. To restore the
contents of the top of the stack is read into the (D, E) reg pair. The
question in which sequence these instructions are to be executed so
that the contents are restored properly. The obvious sequence in
POP D first & the POP B in the data must be popped off in the
reverse order from which it was pushed. This type of stack is called
last in first out (LIFO) memory.

Just after the execution of POP D & POP B instructions the

situation is as shown in fig.

When POP D is executed the data from the top of the stack is copied
to reg. E, data pointer is incremented by 1, then the next byte of the
saved data is copied from the stack to the reg. D, and SP is further
incremented by 1.

This is similar to previous one but now some data has been
stored in the stack area but these are irrelevant anyway. They will be
destroyed during the next PUSH operation on the stack.
From the above discussion, following points emerge:
1. The stack pointer always points to the top of the stack up to
which it is full with relevant data.
2. Storing or saving the data on stack is known as PUSH
operation.
3. The restoring or reading data from the stack onto certain
internal registers are known as POP instructions.
4. The stack operates on Last in first out basis.
5. The stack pointer can be initialized to the bottom of the stack
but bottom of the stack cannot be utilized to store any useful
data.
6. It is for the user to see that the program area does not overlap
with stack area.
Lecture-14
W-Z:
When a 3-byte instruction containing 2 byte address is to be
executed by the , the first byte is the (op-code) which is fetched
and then decoded by the decoder. Then two memories read m/c
cycles are executed to read the two byte address one in each m/c
cycle and placed in W-Z register. During instruction execution, (in
next m/c cycle), the addr in W-Z register pair is transferred to the
address latch to address memory or I/O for data transfer.
Interrupt Control Section:
Sometimes it is necessary to interrupt the execution of the main
program to answer a request from an I/O device. For instance, an I/O
device may send an interrupt signal to interrupt control unit to indicate
that data is ready for input. The temporarily stops what it is doing,
inputs the data and then returns to what it was doing.
Serial I/O Control:
Sometimes, I/O devices work with serial data rather than
parallel. In this case, the serial data stream from an input device must
be converted to 8-bit parallel data before the computer can use it.
Likewise the 8-bit data out of a computer must be converted to serial
form before a serial output device can use it.
The SID input is where serial data enters the 8085. The SOD
output is where the serial data leaves the 8085. Two instructions
known as SIM & RIM allow the user to perform the serial parallel
conversion needed for serial I/O device.
Timing and control section:
 The timing and control section supervise the complete
operation of the . The on chip clock oscillator which produces the
internal clock is a part of this section. The timing and control section
also has a state generator to generate 10 different states namely
state generator is a multi
mode counter. The next state of the state generator from the present
state is decided by the many control signals like READ, HALI, INTR,
HOLD etc in each states then section of generator many control
signals for executing the instruction fetched.
The operation of the is cyclic in natural. During the normal
operation from the ward Go, sequentially and executes one
instruction after another until a HALT instruction is executed. The
fetching and execution of a single instruction constitutes an
instruction cycle. The instruction cycle consists of one or more read
or write operation to memory or an I/O device each memory I/O
reference requires a mechanic cycle. In other words every time a byte
of data is more from CPU to I/O or memory or from memory I/O to
cpu , a machine cycle is required.
There are seven different kinds of m/c cycles in the 8085 A:
1. OPCODE FETCH
2. MEMORY READ
3. MEMORY WRITE
4. I/O READ
5. I/O WRITE
6. INTEROPT ACKNOLEDGE
7. BUS IDLE
 Three status signals IO/ generated at the beginning of
each m/c cycle (and generated during state of
the M/C cycle) identify each type of the m/c cycle the station signals
remain valid for the duration of the cycle. The instruction fetch portion
of an instruction cycle requires a machine cycle for each byte of the
instruction to be fetched since instruction consist of 1 to 8 bytes (1,2
or 3), the instruction fetch Is one to three machine cycles in duration.
The first m/c cycle in an instruction cycle is always an OPCODE
fetch m/c cycle which is always single by long and the 8 bits obtained
during an OPCODE FETCH are always interpreted as an OPCODE
of an instruction. Note that to fetch an instruction is to transfer an
entire instruction from memory to the necessitates an OPCODE
FETCH m/c cycle. However, one or two memory read m/c cycles are
also needed to complete the fetch for 2&3 byte instruction
respectively.
The number of m/c cycles required to execute the instruction
depends on the particular instruction. Some instruction require no
addition m/c cycles after the instruction fetch is complete, other
requires additional m/c cycles to write or read data to or from memory
or I/O devices from one to five. Around 50% of the instruction
requires only one m/c cycle for fetching and executing the instruction,
no instruction requires more than five m/c cycles M/C cycles like the
memory read or memory write may occur more than once a single
instruction cycle.

MC-1 MC- MC-3 MC- MC-5

 2 4
INSTRUCTION cycle
The shaded area may be required for executing the
instruction. The timing and control unit of automatically generates
the proper m/c cycles required for an instruction cycle from
information provided by the op-code.
Each m/c cycle contains a number of 320ns clock periods
when cryptal used is 6.25MHz. One clock period, i.e. the period
between two negative going transitions of that clock is called T state.
The various T-states are . Most of the m/c cycles
have 3 T states each ( only OPCODE FETCH MC has
either 4 or 6 states depending on the instruction. The first 3rd states of
the mc are identical to a MRMC, the additional T states in OFMC are
the T states required by the 8085 A to decode the op code and
decide what actions are needed in succeeding MCS.
The combined MCS along with T-states are shown in fig.
MC-1 MC-2 MC-3 MC-4 MC5

MC-i (i=2,3,4,5)
Thus one complete transition from state through the state
diagram and back to constitutes a complete m/c cycle the partial
state transition diagram is shown below assuming READY=1 is no
wait.
 The shaded portion above that these state may be neede in
same instructions. Instruction cycles for various 8085A instruction
required to execute an instruction will depend on the READY & HOLD
signal inputs.
For example consider the 3 byte instruction STA ADDR, STA stands
for store accumulator direct the meaning of the instruction is transfer
the content of the accumulator to an external memory location whose
address is specified in the instruction is ADDR since. The location
can be anywhere in the 64k memory space that the 8085A can
directly address, 16k are required for the address thus the STA
instruction contain 8bytes; a 1 byte op-code and 2-byte address. The
instruction is stored in the memory as follows.

OP CODE BYTE 1

LOWER ADDR 2

HIGHER ADDR 3
Three m/c cycles are required o fetch this
instruction. In MC-1 is op code fetch M/C ,the opcode is transferred
from memory to the instruction register during states and then
during state it is interpreted , at this point the cpu knows that it
must do more m/c cycles two RMC to fetch the complete instruction
in MC-2 the lower addresses transferred from the memory to the
temporary register Z. in MC-3 the third byte i.e. the higher address is
transferred from the memory to the temporary register W. when the
entire instruction is in the it is executed. Execution means a data
transfer from the to memory. The contents of the accumulators
are transferred to the memory location, whose address was
previously transferred to the by the proceeding two memory read
m/c cycles the address of the memory location to be written is
generated as follows the high order address byte is temp reg. W is
transferred to the address latch and the low order address byte in Z
reg. is transferred to address/data latch. The content of the A is then
placed on the data bus. This data transfer is affected by a MWRMC
thus 3 byte STA instruction has four m/c cycles in its instruction
cycles.
Mnemonic Instruction byte
STA op code OP CODE
FETCH
LO addr MRMC
Hi addr MRMC
MWRMC
 This STA has a total of 13 states. If the 8085A is operating at
325.5ns time, the STA instruction cycle is executed in 4.23 . This
time period is the instruction execution time, although it actually
includes both the instruction fetch and the execution time.
Lecture-15
MACHINE CYCLES

OPCODE FETCH machine cycle:

Fig. shows the 8085 instruction fetch timing diagram. The
instruction fetch cycle requires either four or six clock periods (T
states). The other m/c cycles that follow OFMC will need three clock
cycles.
The purpose of an OF is to read the contents of a memory
location containing the opcode addressed by the program counter
and to place it in the instruction register.
In the beginning of state , the 8085A puts a low on the
IO/ line of the system bus indicating a memory operation the 8085
sets on the system bus, indicating the memory
fetch operation this status information remains constant for the
duration of the m/c cycle. During state, the 16 bit address
of the memory location containing the op code is obtained
from the program counter pc and placed in the address and address
data latches the higher order 8 bits of the address appears on the
address bus remains constants until the end of the state
during state the data on the address bus is unspecified. The low
order 8 bits of the address is placed on the address/data bus,
at the beginning of this data however remains valid
only until the beginning of state at which time the addr/data bus is
floated (3 states) because this is time multiplexed bus and used on
the data bus during state. Therefore addr latch enable
(ALE) signal issued by the during is used to latch this lower
order addr in same external hardware 8212 on its falling edge the 16
bit addr select a particular memory location.
During state , at the beginning. The single goes low
indicating readf operation and the opcode to be fetched is placed on
the data bus, , by the addressed memory location. The
contents of (pc) is incremented be 1 during this state as during
state the pc has sent the addr to addr bus . the access memory
should be fast enough to output its data before goes high slower
memories can gain more time by pulling the READY signal of 8085
LOW this will introduce an integral no. of sate between
as long as READY is low on the ring edge of the
control signal in , the opcode obtaining from memory is
transferred to the micro process instruction register.
During data , the 8085 decodes the instruction and
determines whether to enter state or to enter state of the
next m/c cycle from the operation code the determines what other
m/c cycles if any must be execute to complete the instruction cycle
state when entered, are used for internal operations
necessitated by the instruction.
 The micro RTL flow for 4 data OFMC is shown below.
OFMC: status IO/ =0,

(PCL) , (PCH), ALE=

: (PC)+1, M(AB)
: , (IR)
: decodes the opcode and decides whether
states are required or next m/c cycle is executed. During T4 T6
states,
Fig below shows the timing diagram for a 6-state OFMC

Note: whenever the addr information is sent from the program

counter to the external world during state, then the pc is
incremented by 1 during the subsequent state so that pc points to
the next subsequent byte. However if the addr information from pc
has not been sent out during the state to the external until then pc
will not be incremented during state.

Memory READ m/c cycle:

It requires 3 states to the purpose of the memory
READ operation is to read the contents of a memory location
addressed by a and place the data in a register by a register pair,
the source of address issued during is not always the program
counter but may be any one of the several other register pairs in
the depending on the particular instruction of which the m/c cycle
is a part.
The 8085 uses m/c cycle MC1 to fetch and decode the instruction.
It then performs the memory read operation in MC2. E.g. in LXIH,
Addr.
The IO/ signal made low to indicate the external world that a
memory reference is required. Then made
indicating that memory READ operation is to be performed. During
the 8085 places the contents of high byte of the memory address
register, such as that contents of the (PCH) or (H) register on
lines and the contents of the low byte of the memory
address register such as contents of the (PCL) or (L) reg. On
lines . The 8085 sets ALE to HIGH, indicating the
beginning of MC-2 AS soon as ALE goes to low, the 8085 latches the
low byte of the address lines, since the same lines as going to be
used as data lines.
During state, the signal goes LOW indicating a READ
operation. If the addr sent and during state is from pc, then pc is
incremented by 1 otherwise not the external logic gets the data from
the memory location addressed by the memory address register such
as (H,L) pair and places the data on to data bus .
During state, signal goes high, this low to high signal
transfer the data from the data bus to internal register such as the
accumulator.
MRMC: status signals IO/ =0,
(PCL) , (PCH), ALE=
: (PC)+1, M(AB)
: , , (internal reg.)
Or
(PCL) , (PCH), ALE=
: M(AB)
: , , (internal reg.)
MEMORY WRITE MC:
It also requires only states the purpose of memory
write is to store the contents of any of the 8085 reg. such as the
accumulator into a memory location addressed by a register pair such
as HL.
The 8085 made IO/ =0 in the beginning of state to
indicate memory reference operation then it puts ,
indicates a memory write operation.
During state 8085 places the memory address register
high byte such as the contents of the H register on lines
and also places the MAR low byte such as the contents of the L-
register on lines . the 8085sets ALE to HIGH, indicating
the beginning of MWRMC. As soon as ALE goes to low, the 8085
latches the low byte of the address lines since the same lines are
going to be used as data lines. During state, goes low
indicating memory write operation It also places the contents of the
internal register say accumulator on data lines .
During state, goes high this low to high transition is
used to transfer the data from the data lines to the memory location
address by MAR such as HL reg. pair.
MWRMC: IO/ =0,
(L), (H), ALE=
: ( internal register)
: , M(AB)
I/O READ and I/O WRITE M/C cycle:
These are identical to MRMC & MWRMC respectively except
that appropriate status signals are issued at the beginning of
state. IO/ signal goes high at the beginning to indicate I/O device
reference is needed in case of I/O mapped input/output device in
these m/c cycles higher & lower address bytes are identical and
equal to the 8 bit address of the I/O port while in case of MRMC or
MWRMC, the address bus output is the true 16bits address.
Lecture-15
STATE TRANSITION DIAGRAM
HALT state: (THALT):
Whenever the HALT instruction is executed enters in to
the HALT state the op code for HALT is 76H. Assume that an op
code fetch m/c cycle is initiated and the op code transferred to the
instruction register during state is 76H is the op code of HLT
instruction during state , the control unit decodes the instruction
op code and sets a HALT f/f inside the 8085A upon exiting state ,
the enters state of the next m/c cycle, As indicated in the fig
the HALT f/f is checked in state of the next m/c cycle if it is fount
set instead of entering state, the enters in to the HALT state
otherwise in state thus five states are required to reach the
HALT state. In the HALT state, the address and address/data buses
along with IO/ are placed in their high independence
states (floated).
There are only three ways to exit from a HALT state.
First; a low an input of the 8085 resets the entire system
and loads the program counter with all 0s when signal is
active, comes out of HALT state and enters into RESET state
and remains their as long as is active. After reset, 8085A
immediately start program execution from 00004.
The second way to get out of the HALT state is to make the
HOLD signal input high. The processor then enters the HOLD input
goes to again, the CPU returns to the HALT state.
 The third method of coming out of a HALT state is when and
interrupt signal is active. This method works only if information were
enabled with an enable interrupt (E) instruction in the program before
HALT instruction is executed. Whenever interrupt comes leaves
the HALT state and start executing the ISR.

WAIT State TWAIT:

According to faming specification for the 80854A, during a read
operation (OFMC/MRMC/RMC). The device providing dater to the
must have valid data on the dater bus within [(5/2) T-225] ns after the
provides a valid address at its address pins. For T=320ns, the
memory or input device must have an access time of 575ns or less.
Sometimes is used with memories or I/O devices which
have longer access time. In case of memories, the lower the cost,
generally the longer the access time. To accommodate long access
time, the longer the access time. To accommodate long access time,
the 8085A has a state called the WALT state, Twait as shown in
figure.

When the generates an address in T state, external control

logic monitoring then address can request that the microprocessor
integral number of clock periods. The external control logic does this
by making the READY input to the logic O during state . MP
in , state, after making signal LOW, monitors READY signal
input, If this input is find low, then microprocessor enters state Twain
instead of , when the READY signal becomes logic 1 the

comes out of Twout state and enters into state and cycle
continues wait states continues to be inserted as long as READY is
low.
The effect of entering a wait states is to hold all external signals
from the in the same state they were on at the end of state . Is
the content of address bus, data bus, and control bus are all hold
constant. This stretches the duration of address pulse, so
devices with access time greaten than 575ns can be read. If N wait
states are introduced into the cycle, the required access time is
[( T-225] ns.
Fig shows a single WAIT state or transition in OFMC. Sampling
of the READY line in state and the transition into the WAIT state

allow the to synchronize to memories or devices with long

access time. This of course, is associated with increased instruction
cycle time and additional logic to control the READY input.
External logic controlling the READY line can be designed so
that name, a fixed number or a variable number of WAIT states
transitions occur during to that these wait states occurs only for
specific types of cycles eg OFMC. eg. A men stable can be
triggered by 8085A or pulse, to make READY low each
time the slower device is address the men stable can be enabled by
the same signal that is sent to select the addressed device. This
prevents a WAIT state to be introduced during each read or write
operation.
HOLD State THOLD:
The enter in this state, if same external device wants direct
memory access so that a stirs of data can be transferred at a fast
rate. The device requesting for DMA makes the HOLD signal input
high.
There are two possibilities-(i) the may be in the HALT state
and then the HOLD signal input becomes high. In this situation, the
first sits the HLDA F/F. (HOLD acknowledge F/F) & then enters
the HOLD state (ii) the is executing same m/c cycle. While
execution cheek the HOLD signal and unique points during an
m/c cycle.
Note: HOLD-signal is to processor is co synchronous is nature.
The synchronize this request and at props time in a m/c cycle
provides the HLDA signal by setting HLDA F/F- for the requesting
device. The HOLD state is entered after an m/c cycle is completed.
The HOLD signal is checked during state after (READY
input has been checked) and also during state (provided if the
concerned m/c cycle requires & state, also). If the HOLD signal
is found high HLDA F/. Is set and the processor enter the HOLD state
after the current m/c cycle.
Upon entering the HOLD state, the HLDA output signal from the
is set high during this state, the address & the data buses at the
or & IO/ control lines are float (tri-stated). Buy floating its
address, data control buses, the effectively disconnects itself from
the system from this point in, is up to the requesting device to provide
addresses data & control signals to memory & I/O port to implement
the data transfer is the requesting device their enables its tri-state
buffers when DMA process is over it floats its address data, and
control buses and then bring the HOLD signal input low.
The exit the HOLD state and then continues its processor
operation from the point at which it was suspended by the HOLD
request. If reset, the HLDF F/F first of the HALT F/F is found to be It,
if enters the HALT state else enters state.
 Fig. State transaction diagram of 8085 A

Fig shows the 8085A state transition diagram this is compact way of
showing when during an instruction cycle the 8085A will enter a halt
state, insert a wait state, res to HOLD input or respond to an interrupt
input.

If is acceded, the 8085A state, in a rest state with

the address bus floating when is net is not asserted or the
previous m/c cycle is finished, the CPU enters of a new m/c cycle.
If the previous instruction was a HLT state. The CPU goes. Directly to
a halt state the three ways to exit the halt state are by a rest, a valid
into and a HOLD request. Note that the hold exit is only temporary as
soon as HOLD is not asserted, the CPU returns to the halt state.

If a halt state was not entered, then the CPU proceeds to of

the m/c cycle here it checks the READY input. If the READY line is
not asserted (Low, the CPU inserts wait state, until READ goes high.

The hold input is checked at several point .if a hold request in

present on it, the hold acknowledge F/F is set. However the CPU until
not enter the hold after until the end of bus use for the m/c cycle.

Note that the does not check whether a valid intercept request
is present until the end of the unidirectional cycle .this is necessarily
so that the address if the next instruction can be pushed into the
stack.

To summarize, a halt is entered during the T1, a wait state is

entered after T2, a hold state is entered after a m/c cycle is
completed, and an interrupt is responded to after an instruction cycles
completed.
Lecture-17
MICROPROCESSOR INSTRUCTIONN SET:
A microprocessor system there memory microprocessor and
the input and output devices- can be thought if in terms of the register
it contains random access semiconductor memory is a collection of
register .A microprocessor itself consist of general purpose and
dedicated registers input and output devices contain register that
hold their data.
The function of a microprocessor system is implemented by a
sequence of data transfer between register in the memory, the Mp
and I/O devices and data transformation that accrue primarily in
register within the microprocessor. Each register that can be
manipulated under program control is addressable in same manner
allowing it to be singled out for use in a data transfer or
transformation.
The kinds of individual transfer & transformation possible are
specified by the microprocessor instruction sets .each instruction in
the set causes one or more data transfer and or transformation. A
sequence of instruction consists a program. The content section
decode, the program instruction in turn, and using timing signal
derived from the system code, content what register transfer or
transformation table places and when. Each is designed to
execute particular function set .instruction set one fixed by design
cannot be changed Intel 8080 .which came in to market in 1973 has
72 bases instruction and 244 variation 8085 which came in to the
market in Jan 1977 is a commercial with lintel 8086 has 74 basic
instruction and 246 variation it includes all the 72 instruction of 8080.
The two other instructions in 8085 are RIM & SIM.
8085 is faster than 8080 the program written for 8080 can be
run without any modification in 8085 but the user has to be careful
where the DELAY ROUTINES are involved because of difference in
speed of operation.
INSTRUCTION FORMAT:
All instruction of 8085are 1 to 3 bytes in length .the bit pattern
of the first cycle is the op code. The bit pattern is decoded in the
instruction register and p[provides information used by the timing and
content section to generate sequence of elementary operation micro
operation that implemented the instruction.
D7 D6 D5 D4 D3 D2 D1 D0

Figure shows a single byte instruction is the opcode of the

instruction. The 8-bit of the op-code available at the memory location
N is divided into three potion first group D7, D6 recent group D5D4D3
and third group D2D1D0, D2D1D0 when necessary contains the same
code SSS. D2D1D0 group contain the combination of register DDD. If
a register pair is involved the bits. RP is placed in D5D4. Whenever
D5D4 represents the register pair D3 normal tells whether it is loading
operation or storing operation .the first group D7, D6 gives the idea of
the mnemonic of the operation code.
Whenever 8-byte instruction is used the first byte at memory N
is the op-code of the instruction followed by either an 8-bit data or an
8-bit address at memory location N+1.
 Whenever a 8-byte instruction is in solved .the first byte at
memory location N is the opcode followed by either a-16 bit address
or a 16-bit data. The second memory location U (N+1).contain the
lower order addresses or data and (n+2) contain the higher order
address or data.
ADDRESSING MODES:
Most of the instruction executes requires two operands e.g.
transfer of data between two register of a microprocessor system.
How the Mp knows the position of these operands. The method of
identifying the operands position by the instruction format is known as
the addressing mode. Whenever two operands are involved in an
instruction the first operand is assumed to be in a register Mp itself. It
is for the user to put that operand may be located in one of the
following.
i. In any general purpose register in the .
ii. In a particular memory location.
iii. It can be immediately available in an instruction format.
iv. I/O device.

In 8085 the following addressing modes are used.

Register addressing:
When the operands for any instruction are available in the
internal general purpose register. Only the register need be specified
as the address of the operands. Such instruction are said to be use
the register addressing mode. These instruction are one byte
instruction within that byte i.e. OP code, the register are specified.
E.g., MCV r1, r2, ADD r, XCHG, DAD rp etc.
 MOVr1, r2 this is an ALP statement and memory of the
instruction is more the content of reg (2) to register r1 .the opcode for
the instruction is 01DDD SSS .DDD specifies. The code for the
operation register (r1) and specifies the code for transfer the first two
bits 01 specify the MOV operates MOV B, A the opcode 01 000
111=47H.
ADD r:
This is an ALP statement ADD is the mnemonic for addition
and meaning of the instruction is add the content of the register to the
content of the accumulator and store the result back in accumulator
.the one of the operand is assumed to be in accumulator. By implied
addressing mode the second operand is available in any general
purpose register specified in the instruction .the op code is 10 000
SSS.
E.g. ADD H. The opcode is 10 000 100=84, the macro ITL is
implemented.
(A) (A) +(r)

Direct addressing mode:

In the addressing mode, the instruction contains the address of
the operand contains the address of the operand (external register)
involved in the transfer. The 8085A provides.16-bit memory
addresses requiring that the address contained in the instruction 1b
16-bit long as a second their byte of the instruction thus it is invariably
eg.3-byte instruction.
E.g. LDA addr. This is an ALP statement ADDR in operand field is a
symbolic name given to 16-bit address .the systematic name given to
16-bit address symbolic name can be chosen by the user either
reference to context LDA is the mnemonic for LOAD accumulator
direct. The instruction format for this is as shown.
Opcode N
<B2> N+1
<B3> N+2

Where the memory location N contains the opcode namely 00

110 010=(3A)4 followed by a lower order 8-bits of address <B2>and
higher order 8-bit of address <B3> at memory location NH&N+2
respectively. The meaning of instruction is load the accumulator from
the memory location whose address is available directly, in the
instruction itself. The macro RTL implemented is,
(A) M(B3,B2)
This is symbolic representation. Only one operand is involved
in the instruction e execution.

Register indirect addressing:

The instruction specifies a register pair which contains the
address of the memory. Where the data is located or into which the
data in to be placed these, the address of the operand is given
indirectly through a register pair. In other words, the operand is in
memory location or external register share address is available in an
internal general purpose register pair.
The H8L register pair is used as a pointer in memory 8885 A,
register indirect instruction .the reg H holds the high and reg L holds
the large bytes of the effective address e.g. MOV r, M transfer single
bytes from an external reg. M to any of the several integral varying
register. External reg M means the external reg pointed by HL the
macro RTL implemented is,
(r) M (H, L)
Before reg indirect instruction are used in a program, a
previous instruction most load register pair HL with the appropriate
address.
The register pair BC & DE is also used as pointer register in
two 8085A instructor i.e. LDAX & STAX rp .the internal register
involved for data transfer is always accumulator.
The meaning of LDAX rp is load the accumulator from the
memory location. Whose address is available in rp (reg pair either BC
or DE). The macro RTL implemented is, the opcode for LDAX B is 00
001 010 = (0A).

Immediate Addressing Mode:

In the type of addressing mode, the operand is available
directly in the instruction itself. If the operand data involved is of 8-bits
then the instruction is of two bytes. The first byte is the opcode
followed by 8-bit data. If 16-bit data is involved in the instruction then
the first byte is opcode at memory location N followed by the lower
data at memory location NH and higher order data at memory
location N+2.
e.g. MVI r, data there is two byte instruction .the instruction format is
00 DDD 110 N
<B2> N+1
The meaning of the instruction is more the 8-bit data immediately
available in the instruction as the 2nd byte to the destination reg r.
DDD identifies the internal register the macro RTL implanted
i.e., (r) <B2>

e.g. LXI rp data,

00 RR0 001 N
<B2> N+1
<B3> N+2

(RpL) <B2 >

(RpH) <B3>

Implied addressing mode:

There are certain instructions that operate on one operand in the
ACC and therefore need not specify any address. Many instructions
in the logics group like RLC, RRC, RAR, RAL, CMA fall in to the
category. All these are one byte instruction .these instruction that
specify the address the operand is implied addressing for the other
operand.
 Lecture-18
INSTRUCTION SET

Classification of instruction set:

The 74 instructions available in the 8085A can be divided into
five groups depending on their function.
1. Data transfer group: Instruction that more data between registers,
between register and memory location and I/O transfer.
2. Arithmetic group: Instructions that add subtract increment or
decrement data in the register.
3. Logic group: Instruction that carry out logic operation, such an AND,
OR, EX-OR compare between and data in the accumulator & a
register compliment and rotate data in the accumulator.
4. Branch group: Instruction that change .the execution sequence of a
program, such as conditional and unconditional jump instruction and
subroutine call and return instruction.
5. Stack machine control group: Instruction for maintaining the stack
and internal control flags.

DATA TRANSFER GROUP:

It consists of 15 basic operation and 86 variations. The basic
operation involved is DATA transfer between two register of a
microprocessor system. One of the register is always located in the
itself the other may be located in one of the following
1) An I/o device
2) Memory
3) The microprocessor
Registers located in the microprocessor are referred to as
internal registers. (A, A, C, D, E, H, L, SP, PC) and those in ROM
,RWM, or I/O are referred to as external registers therefore, this
group includes transfer of data from reg to mg, Reg to memory,
memory to reg. Reg (a) to output devices, or from input device to reg
(A).
 The register from which data in transfers is the source register
and the register to which data is transferred in the destination
register. A transfer involves copying the contents of the source reg
into the destination register; the contents of the source register and
not attend. Each data transfer instruction identifies the source register
and the destination register. Identification of one or both of these
register may be implied by the instruction in memories or may be
explicit. Internal registers are frequently implied; whereas the external
registers are usually identified by an explicit address that is part of the
instruction.

The operation code format pr shown on fig.

MOV r1, r2: This is an ALP statement, MOV is the mnemonic for
move. r2 is the source register. r1 is the destination register in the offer
and fields the meaning of the instruction is move the contents of the
register r2 into r1. The content of r2 is not destroyed .content of r1os
destroyed and new value form r2 takes it place. The macro RTL
implemented is
(r1) (r2)

This is a single byte instruction at memory location N. The code of will

be
 It has 49 variations (7x7) seven for SSS and seven for DDD. It
is register addressing mode. How the execution of this instruction
takes place. During the T1 state of the first M/C up to (OFMC), the
contents of the program contents are placed on the address bus (A15
...A8) and address data bus (AD1- AD0). Since address may be low or
high, it is customary to use the double sided waveforms, the high byte
of the program counter (PCM) goes to the address bus and the low
byte (PCM) to the address data bus.
The ALE signal initially goes high then midway through the T1
state, ALE goes low 2 ties this falling edge that latches the address in
to the external latch. Also IO / N go low near the beginning of the T1
state there enables the peripheral chips for a memory operation
rather than an I/O operation.
During the T2 state, the program counter is incremented. The
address disappears from the address data bus at the beginning of
the T2 state. This is
Necessary because as instruction fetch is in needed. The dashed line
an AD1-AD0. Wave from means that the data on the bus is invalid.
Towards the end of the T2 state, the OP code appears on the address
data bus the precise time when OP code appears depends on the
memory access time; the length of the buses and other factors.
At the beginning of the T2 state goes low and stays low
until the middle of the T1 state during the T3 state, the OP code on the
AD bus is copied into the instruction reg. During the T4 state, the
instruction is decided. The pl now knows that the instruction is MOV
r1, r2 21 is represented as MOV r1, r2=1 and is executed.
In fact the execution does not take place instantaneously, when
the instruction is decoded, the contents of register 2 are copied states
T1,T2 the contents of the temporary register are copied into register 1
this completes the
Execution of the MOV instruction since (in these two states) during
MC-2 up on only the internal bus is used. Add r bus and add data bus
are not used, therefore there buses can be used for some other
purpose.
One way to save processing time is by starting the next
instruction up to during the second M/C of the move instruction. This
is called fetch executed overlap. During T1 of this m/c, the contents of
the program counter are out pattern to Addr bus & AD bus during T2,
state the next OP code is transferred to AD bus form memory and
simultaneously MOV r1, r2 instruction is implied. Hence, during the
MC-2 of the move instruction cycle, MC1 of the next cycle is
operative.

Thus the instruction cycle for MOV r1,r2 takes only L1 clock
states (& not six) after the executions PC point to next address.

MC- 1.

OFMC T1 : AD,- AD (PCL) , A15 A5= (PCH), ALE =

IO/ =0 T2 : = 0, (PC) (PC ) + 1, AD1- AD0 M(AB)
S1 = 1 T3 : = 1, , (IR) (AD2- AD0)
S0 = 1 T4 : MOV r1, r2= 1, ----------- approximately or (Z) ( r2)

Mc 2
FEO T1 : AD7- AD0 (PCL) , A15 A5= (PCH), ALE
(r1) (z) T2 :: = 0, (PC) (PC ) + 1, AD1- AD0 M(AB)
This Operation Require Only Single M/C Cycle of OFMC & needs
only four state.
MC -1 OFMC
T1 T2 T3 T4
INSTRUCTION CYCLE
Now after execution of this instruction pointer goes to T1 state & PC
points to next address.

MOV r, M: This is an ALP statement, the meaning of this instruction

is the content of the memory location whose address is available into
(H,L) pair should be moved into the internal general purpose register
r. The macro RTL implemented.
r M(H, L)
M is the source, v is the destination. It is a single byte instruction at
memory location N. The operation code is,
01 DDD 110 N
It has seven variations. DDD cannot be 110 because memory to
memory transfer is not allowed.

The micro RTL follows:

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH) , ALE
OFMC
T2: RD 0, (PC) (PC) 1, AD7 AD0 M (AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:MOV r, M 1
S0 1

C2
OFMC T1:AD7 AD0 (L), A15 A8 (H) , ALE
IO / M 0 T2: RD 0, AD7 AD0 M (AB)
S1 1 T3:RD 1, , (R) (AD7 AD0 )
S0 0

This Operation requires only two m/c cycle OFMC & MRMC and total
7 states. It requires 3.5 sec using 2 MHz clock

INSTRUCTION CYCLE

OFMC MRMC
T1 T2 T3 T4 T1 T2 T3

Fig.7
The addressing mode is register indirect addressing mode fig 7
illustrates the operation cycle.

MOV M, r This is an ALP statement. The meaning of the instruction

is then content of the internal general purpose register r should be
move into the memory location whose address is available is
M (H, L) (r)

It is a single byte instruction. The operation code is

01 110 SSS N
It has seven variations SSS cannot be 110.

The micro RTL flow is

MC 1 T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC)(PC) 1, AD7 AD0 M(AB)
IO / M 0
S1 1 T3:RD1,,(IR)(AD7 AD0)
S0 1 T4:MOV MV 1

MC 2
MWRMC T1:AD 7 AD0 (L), A15 A8 (H),ALE
IO / M 0 T2: WR 0, AD7 AD 0 M (v)
S1 0 T3:WR 1, , M(AB) (AD 7 AD0 )
S0 1

The Operation requires only Two m/c cycles- OFMC & MWRMC and
total no of 7 states. It requires 3.5 p using 2 MHZ internal clocks. It
is register indirect addressing mode.

INSTRUCTION CYCLE

OFMC MWRMC
T1 T2 T3 T4 T1 T2 T3
MVI r, DATA:

This is an ALP statement DATA is the symbolic name given to

8 bit data which is immediately available as second byte of the
instruction. Therefore, the source of data is the 2nd byte instruction
itself. Therefore, it is immediately addressing mode MVF is the
mnemonic for move immediate v is the destination register. It is a 2
byte instruction at the memory location N & N+1. The opcode is,

00 DDD 110 N
<B2> N+1

The meaning of the instruction is 8 bit data immediately available as a

2nd byte of the instruction should be loaded into the destination
register. Whose code is DDD. It has 7 variations

(v) B2
The micro RTL flow is
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC)(PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,,(IR)(AD7 AD0)
S1 1
T4:MVI V1
S0 1

MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC)(PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,,(v)(AD7 AD0)
S0 0
It require only two m/c cycles OFMC & MRMC and 7 states. It
requires 3.5 using 2 MHz internal clock.

.
Figure. 9
 Lecture-19
Instruction Set

MVI M, DATA:
This is an ALP statement DATA is symbolic name given to the
nd
2 byte of the instruction MVI is the mnemonic for move immediate. M
in the operand field stands for memory pointer. The meaning of the
instruction is 8 bit data available as a 2nd byte of the instruction should
be moved to the memory location whose address is available in m
pointer namely (H, L) register pair. The macro RTL implement should
be.
M (H, L) B2

The instruction format

00 110 110 N
<B2> N+1

There is no variation in this instruction. It is a 2 byte instruction. First

byte is opcode & 2nd byte is 8 bit data. Figure 10.
The operation is illustrated in fig 10. The micro RTL flow is
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC)(PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,,(IR)(AD7 AD0)
S1 1
T4:MVIM 1
S0 1

MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M (AB)
S1 1 T3:RD1,,(Z) (AD7 AD0 )
S0 0

MC 3
MWRMC T1:AD 7 AD0 (L), A15 A8 (H),ALE
IO / M 0 T2: WR 0, AD7 AD 0 (Z)
S1 0 T3:WR 1, , M(AB) (AD7 AD 0 )
S0 1

It requires three m/c cycle OFMC, MRMC, MWRMC and total 10

states. It needs 5 sec time to execute this instruction using 2 MHz
internal clock. Its immediate addressing mode.

LXI rp, DDATA:

This is an ALP statement DDATA stands for double data a
symbolic name given to 16 bit data available immediately as the 2nd &
3rd byte of the instruction. Rp stands for LOAD IMMEDIATE register
pair. The alphabet X in the mnemonic till that register pair is involved.
The meaning of the instruction is the 16 bit data immediate available
as the 2nd & 3rd byte of the instruction be loaded into register pair. The
macro RTL implemented is,

(rpL) B2
(rpH) B3
The instruction format is

00 RPO 001 N
<B2> N+1
<B3>
N+2

Notes: Only in the instruction D3 is zero for loading otherwise D3 is 1

for loading. 4 variations exists in the this instruction. The bit code RP
in the opcode at memory location N identifies the register pair.

RP = 00 LXI B, DDATA
RP = 01 LXI D, DDATA
RP = 10 LXI H, DDATA
RP = 11 LXI SP, DDATA
The micro RTL flow is
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:LXIrp 1
S0 1

MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0, (PC) (PC) 1 AD7 AD0 M(AB)
S1 1 T3:RD1,, (rp) (AD7 AD0 )
S0 0

MC 3
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0, (PC) (PC) 1 AD7 AD0 M(AB)
S1 1 T3:RD1,, (rpH) (AD7 AD0 )
S0 0
 It requires three m/c cycle OFMC & two MRMC. And total no of 10
states. It needs 5sec using 2 MHz internal clock. It is immediate
addressing mode.

LDA ADDR:

This is an ALP statement. ADDR is the symbolic name given to

the 16 bit address directly available in the instruction. LDA is the
mnemonic for LOAD ACCUMULATOR DIRECT. The meaning of the
instruction is the content of the memory location whose address is
directly available in the instruction be loaded into the accumulator this
is a 3 byte instruction format is

00 111 010 N
<B2> N+1
<B3>
N+2

The macro RTL implemented is

(A) M(B3 , B2 )

This is directed addressing mode

The micro RTL flow is:

 MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR)(AD7 AD0)
S1 1
T4:LDA 1
S0 1

MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
S1 1 T3:RD1,, (Z) (AD7 AD0 )
S0 0

MC 3
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
S1 1 T3:RD1,, (W)(AD7 AD0)
S0 0

MC 4
MRMC T1:AD7 AD0 (Z), A15 A8 (W),ALE
IO / M 0 T2: RD 0, AD7 AD0 M(AB)
S1 1 T3:RD 1, , (A) M(AD7 AD0 )
S0 0

STA ADDR:

This is an ALP statement STA is the mnemonic for the STORE

ACCUMULATOR DIRECT. The meaning of the instruction is the
content of the accumulator should be moved to the memory location
whose address is directly available in the instruction itself as a 2nd &
3rd byte of instruction. This is a 3 byte instruction. The instruction
format is

00 110 010
<B2>
 <B3> N

N+1

N+2

The macro RTL should be

M(B2 , B3 ) (A)

This has no variations this is. This is direct addressing mode. The
micro RTL flow is:
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR)(AD7 AD0)
S1 1
T4:STA 1
S0 1

MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
S1 1 T3:RD1,, (Z)(AD7 AD0)
S0 0

MC 3
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
S1 1 T3:RD1,, (W)(AD7 AD0)
S0 0

MC 4
MWRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:WR0, AD7 AD0 (A)
S1 0 T3:WR1,, M(AB) (AD7 AD0 )
S0 1
 It requires 4 machine cycle OFMC & 2 MRMC & one MWRMC and
13 states. It need 6.5sec using 2 MHz internal clock.

(9) LHLD ADDR: This is an ALP statement LHLD is the mnemonic

for LOAD (H, L) REGISTER PAIR DIRECT. The meaning the
instruction is the content of the memory location whose address is
directly available as 2nd & 3rd byte of the instruction register L and
the content of the memory location at next higher address to the
register H. this a 3 byte instruction. The instruction format is

00 101 010 N
<B2> N+1
<B3>
N+2

The macro RTL implemented is

(L) M(B3 ,B2 )

(H) M((B3 ,B2 ) 1)

The micro RTL flow is

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, M(AB) (AD7 AD0 )
S1 1
T4:LHLD 1
S0 1

MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,, (Z) (AD7 AD0 )
S0 0
 MC 3
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,, (W) (AD7 AD0 )
S0 0

MC 4
MRMC T1:AD 7 AD 0 (Z), A15 A8 (W), ALE
IO / M 0 T2: RD 0, AD 7 AD 0 M(AB)
S1 1 T3:RD 1, , (L) (AD 7 AD 0 )
S0 0

MC 5
MRMC T1:AD7 AD0 (Z 1), A15 A8 (W),ALE
IO / M 0 T2: RD 0, AD7 AD0 M(AB)
S1 1 T3:RD 1, , (H) (AD7 AD0 )
S0 0

This instruction requires 5m/c cycles OFMC & 4 MRMC and total 16
states. It needs 8s using 2 MHz clock. This instruction has no
variations. It is direct addressing mode.

(10) SHLD ADDR: This is an ALP statement SHLD is the

mnemonic for STORE (H, L) REGISTER PAIR DIRECT. The
meaning for the instruction is the content of (L) register should be
 moved into the memory location whose address is available as 2nd
& 3rd byte of the instruction itself and the content of (H) register
should be moved into the memory location whose address is next
higher address. The instruction format is

00 100 010 N
<B2> N+1
<B3>
N+2

The macro RTL implemented should be,

M(B3 ,B2 ) (L)

M((B3 ,B2 ) 1 (H)

The micro RTL flow is,

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:SHLD 1
S0 1

MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,, (Z) (AD7 AD0 )
S0 0

MC 3
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,, (W) (AD7 AD0 )
S0 0
 MC 4
MWRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:WR 0, AD7 AD0 (A)
S1 0 T3:WR 1,, M(AB) (AD7 AD0 )
S0 1

MC 5
MWRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:WR0, AD7 AD0 (A)
S1 0 T3:WR1,, M(AB)(AD7 AD0 )
S0 1

This instruction requires 5 m/c cycles OFMC, 2MRMC & 2 MWRMC

and total 16 states, it needs 8sec using 2 mhz. this instruction has
no variations. It is direct addressing mode
Lecture-20
(11) LDAX rp: This is an ALP statement LDAX is the mnemonic for
LOAD THE ACCUMULATOR INDIRECTLY. The alphabet x in the
mnemonic is for tells that a register pair is involved in the instruction.
Rp is known as operant field. The meaning of the instruction is load
the accumulator from the memory location whose address is
available in register pair only one operand in involved in this
instruction & the operand is available in the memory location. Whose
address is a register pair the macro RTL implements shall be
(A) H(rpH,rpL)

This is a single byte instruction. The instruction format is

00 RP1 010 N

There are two variations in this instruction RP =00 for (B, C) pair and
RP= 0 form DE pair note that RP=10 and 11 are not allowed in this
instruction. The micro RTL is

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:LDAXrp 1
S0 1

MC 2
MRMC T1:AD7 AD0 (rpL), A15 A8 (rpH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,, (A) (AD7 AD0 )
S0 0

This instruction requires 2 m/c cycles OFMC & MRMC and 7 states. It
needs 3.5 sec using 2MHz clock. The addressing mode is register
indirect addressing mode.
(12) STAX rp: This is an mnemonic for STAX accumulator indirectly
using register indirect addressing mode. The meaning of the
instruction is the content of the accumulator should be moved to the
memory location whose address is available in register pair. The
macro RTL implemented shall be

M(rpH,rpL) (A) . This is a single byte instruction. The instruction

format is

00 RP0 010 N

Here also only two variations RP=00 and 01 are allowed. The micro
RTL flow is
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:STAX rp 1
S0 1

MC 2
MWRMC T1:AD7 AD0 (rpL), A15 A8 (rpH),ALE
IO / M 0 T2: WR 0, AD7 AD0 (A)
S1 0 T3:WR 1, , M(AB) (AD7 AD0 )
S0 1

It requires only 2 m/c cycles OFMC & MWRMC and 7 states. It needs
3.5sec using 2MHz clock.

IN PORT & OUT PORT:

Data is transferred from the microprocessor to an output device
in to the transfer and from an input device to the microprocessor in an
input transfer. Output devices certain one or more register each of
which is addressable and strobe by the MP to the latched data on the
data bus at the appropriate time during an output transfer. Input
devices contain a register the MP and an addressable three-state
buffer that is enabled by a strobe from the Mp at the appropriate time
to place data on data bus.
The 8085 A CPU outputs a signal IO/ which is 1 when an I/0
port is being accessed and O when memory is being accessed. This
can be used to distinguish between I/O & memory READ & WRITE
operations 2f IO/ =1 is used to select any I/O port than it is known
as I/O mapped I/O structure or isolated I/O, 2f IO/ =0 is used to
select any I/o port then system will not distinguish between I/O &
memory. An I/O port will then be treated as just another memory.
Location:
This is referred to as memory mapped I/O. In this case, same of
the GK addressable locations are used to identify the I/O port & not
memory.
IN PORT:
This is an ALP statement port is the symbolic name given to Q-
kit address of the input device available as a 2nd byte of the
instruction. In this the mnemonic for INPUT. The meaning of the
instruction is an 8 kit data from the output device. Whose address is
available as a 2nd byte of the instructions is loaded into the
accumulator, the macro RTL implemented is,
(A) I/O (port)
(A) I/O (<B2>)
The necessary interfering circuitry between MP & the input
device is shows below for inputting an 8-bit data from an input device
whose port address is B2 the Instructions format is,
This is a 2 byte instruction. The instruction format is

11 011 011 N
<B2> N+1
 The data generated by an i9nput device is stored temporarily in
some register which can be used by the MP when necessary 2n
order to place the contents of the input register and the MP system
bus, the outputs the connected to the data bus through a three, state
input instructions places an Q- bit devices address at the address
bus, where it is duplicated an higher & lower order bus An external
decoder decodes the device address, the IO/ , & the pulse in
order to generate an input device select pulse state buffer, the
addressed input parts three state buffer, thus placing the input ports
data an the data bus.
The IN port is a2- byte instructions, the first byte is the OP code
and the second byte is the 8-bit input device address. The address
may be any varying from 00 to FF. Thus , a total of 256 input devices
can be connected directly, through updated I/O structure, where the
source register to identified by an explicit 8-bit address, the
corresponding I/O structure is shown by the map.
The micro RTL flow for executing this instruction is as follows:
MC- 1 OFMC T1 : AD,- AD (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC ) + 1, AD1- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : IN = 1

Mc 2 MRMC
IO/ =0 T1 : AD1- AD0 (PCL), D5 A8 (PCH),ALE =
S1 = 1 T2 : = 0, (PC) (PC ) + 1, AD1- AD0 M(AB)
S0 = 1 T3 : = 1, (W) (AD7- AD0) (Z) (AD7- AD0)

Mc3 IORMC T1 : AD7- AD0 (Z), D5 A8 (W), ALE =

IO/ 2 T2 : = 0, (AD,-AD) A0(Y,Y0 Y, Y0)
S1 = 1 T3 : = 1, (A) (AD7- AD0)
S0 = 1

Thus at the end of 2nd m/c cycle W register together shall

certain
(Y,Y0 Y, Y0), where Y, Y0 it is the 2nd byte data happen to be the
address.
Whenever an input device is interface as shown in fig 12, and the
data is inputted using IN PORT instruction. It is known as I/O mapped
I/O structure or isolated I/O structure. The input device address can
be any 8 bits dependently upon the user varying from 00H to FFH .
thus a total of 256 input devices can be connected directly through
isolated I/O structure. The corresponding I/O space is shown by map
in fig 13.

00H

FFH

IO / M 1
S1 1`
S0 0
RD 0

(14) OUT PORT : This is an ALP statement fig 14 given the

interfacing circuitry for outputting an 8 bit data into an output device
whose address is the symbolic name PORT in the output instruction
OUTPORT.
OUTPORT is a 2 byte instruction. PORT is the symbolic name given
to the address of the output device available as the 2nd byte of
instruction. The instruction format is

110 100 11 N
<B2> N+1

The meaning is the content of the accumulator is outputted to the

output device whose address is the 2nd byte of the instruction. The
macro RTL implemented should be
I / O(PORT) (A)
or
I / O(B2 ) (A)

It is directed addressing mode and has no variations. The micro RTL

flow is
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR)(AD7 AD0)
S1 1
T4:OUTPORT 1
S0 1

MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,, (Z)(AD7 AD0)&(W) (AD7 AD0)
S0 0

Thus address is duplicated.

MC 3
IOWRMC3 T1:AD7 AD0 (rpL), A15 A8 (rpH),ALE
IO / M 1 T2:WR0, AD7 AD0 (A)
S1 0 T3:WR1,, M(AB)(AD7 AD0)
S0 1

Thus it requires 3m/c cycles OFMC, MRMC & IOWRMC and total 10
states. It needs 5sec using 2 MHz internal clock. If the output device
is interfaced for communications using this instruction then the
structure is known as isolated I/O structure I/O structure or I/O map
I/O structure. We can address directly 256 output devices addressed
from 00H to FFH. Shown in fig19a.

00H

FFH
 IO / M 0
WB 0
fig 14 a output I/O space
(AB) (B0 ,B1 )H
(Y1Y0 Y1Y0 )H

(15) XCHG: This is an ALP statement. This is a single byte

instruction. The meaning is the contents of (H, L) register pair is
exchanged with the contents of (D,E) pair. The macro RTL
implemented is
(H) (D)
(L) (E)
or
(H, L) (D, E)

The single byte operation CODE IS

11 10 10 N
11
The micro RTL flow is
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:XCHG 1, (H,L) (D,E)
S0 1
Lecture-21
2) ARITHMETIC GROUP: This group perform the arithmetic operation on
the operands normally the operands are necessary for any arithmetic
operation one of the operand is always seen in the accumulator the other
operand can be seen in one of the three positions.(a) an internal general
purpose register (r) .

(b) In a memory location pointed by M pointer (H, L) pair.

(c) Immediately in the instruction itself as a 2nd byte.

All of the flags are effected as per standard rule. The format of the operation
code is shown in fig 15.

There are 20 basic instructions in this group.

(1)ADD v: The macro RTL implemented is

(A) (A) (v)

This is a single byte instruction. The meaning is add the content of register
(v) to the content of accumulator and store it back to the accumulator. The
operation code is 10 000 SSS. It has 7 variations. The micro RTL flow is
given below:
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:(A) (A) (v)
S0 1

It requires single m/c cycle OFMC requiring 4 states. It is register addressing

mode.

(2) ADD M: The macro RTL implemented is

(A) (A) M(H,L)

This is a single byte instruction. The meaning is add the content of memory
location whose address is in (H, L) pair to the content of accumulator and
store it back to the accumulator. The operation code is 10 000 110 or 86H. It
has no variations. It is register indirect addressing mode. The micro indirect
addressing mode. The micro RTL flow is given below,

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR)(AD7 AD0 )
S1 1
T4:ADD M 1
S0 1

MC 2
MRMC
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1
T3:RD1,, (TEMP)(AD7 AD0),(A)(A) (TEMP)FEO
S0 0
FEO
IT requires two m/c cycle OFMC, MRMC, and 7 state.

(3) ADI DATA: It is a two byte instruction. The second operand is seen in
the instruction itself. The operation code is

11 000 110 N
<B2> N+1

The macro RTL implemented is

(A) (A) B2

The meaning of the instruction is add the content available as the second
byte of the instruction to the content of accumulation and store the result
back to the accumulator. It has no variations and it is immediate addressing
mode. The micro RTL flow is,

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:ADIDATA M 1
S0 1

MC 2 T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE

MRMC T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0 T3:RD1,, (TEMP) (AD7 AD0 ), (A) (A) (TEMP)
S1 1 FEO
S0 0

(4) ADC v: The meaning of the instruction is add the content of register (v)
to the content of accumulator with carry. The macro RTL implemented is
(A) (A) (v) (cy)
It is a single byte instruction. The opcode is 10 001 SSS. It has 7 variations.
It is register addressing mode. The micro RTL flow is

MC 1 T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE

OFMC T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0 T3:RD1,, (IR) (AD7 AD0 )
S1 1 T4:(A) (A) (v) (cy)
S0 1 FEO

It requires one m/c cycle OFMC and 4 states.

(5) ADC M: The meaning of the instruction is add the contents of memory
location whose address is in (H, L) pair to the contents of accumulator with
carry, the macro RTL implemented is
(A) (A) M(H,L) (cy)

It is a single byte instruction. The opcode is 10 001 110. It has no variation.

It is register indirect addressing mode. The micro RTL flow is-

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:ADC M M 1
S0 1

MC 2 T1:AD7 AD0 (L), A15 A8 (H),ALE

OFMC T2: RD 0, AD7 AD0 M(AB)
IO / M 0 T3:RD 1, , (TEMP) (AD7 AD0 )
S1 1 (A) (A) (TEMP) (cy)
S0 0 FEO

It requires two m/c cycles and 7 states

(6) ACI DATA: The meaning of the instruction is add the content available
the second byte of instruction itself to the content to accumulator with carry
and store the result back to the accumulator. It is a two byte instruction. The
opcode is

11 001 110 N
<B2> N+1

The macro RTL implemented is

(A) (A) (B2 ) (cy)

It has no variations. It is immediate addressing mode. The micro RTL flow

is

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:ACIDATA 1
S0 1

MC 2 T1:AD7 AD0 (L), A15 A8 (H),ALE

MRMC T2: RD0,(PC) (PC) 1,AD7 AD0 M(AB)
IO / M 0 T3:RD1,, (TEMP) (AD7 AD0 )
S1 1 (A) (A) (TEMP) (cy)
S0 0 FEO

It require two m/c cycles OFMC & MRMC and 7 states.

(7) SUB v: The meaning of the instruction is subtract the content of register
from the content of accumulator and stored the result back into accumulator.
The macro RTL implemented is
(A) (A) (v)

It is a single byte instruction. The operation code is 10 010 SSS. It has 7

variations. It is register addressing mode.

The micro RTL flow is

MC 1 T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0 T3:RD1,, (IR) (AD7 AD0 )
S1 1 T4:SUBv 1(A) (A) (V)
S0 1 FEO

It requires one m/c cycles OFMC and 4 cycles.

(8) SUB M: The meaning of the instruction is subtract the content of the
memory location. Whose address is in (H, L) pair from the content of
accumulator and store the result back in the accumulator. The macro RTL
flow is
(A) (A) M(H,L)

It is a single byte instruction. The operation code is 10 010 110. It has no

variation. It is register indirect address mode. The micro RTL flow is.

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:SUB M 1
S0 1

MC 2
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
MRMC
T2:RD0, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (TEMP)(AD7 AD0) (A) (A) (TEMP)
S1 1
FEO
S0 1

It requires two m/c cycle OFMC and MRMC and 7 states.

(9) SUI DATA: The meaning of the instruction is subtraction the content
available as a second byte of instruction from the content of accumulator and
store the result back in the accumulator. It is a two byte instruction. The
operation code is

11 010 110 N
<B2> N+1

The macro RTL implemented is

(A) (A) B2

It has no variation. It is immediate addressing mode. The micro RTL

implemented is

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:SUI DATA 1
S0 1

MC 2
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
MRMC
T2:RD0, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (TEMP) (AD7 AD0 ) (A) (A) (TEMP)
S1 1
FEO
S0 0

It require two m/c cycles OFMC, MRMC and 7 states

(10) SBB v: The meaning of the instruction is subtract the content of register
from the content of accumulator with borrow and store the result back in the
accumulator. The macro RTL implemented is
(A) (A) (v) (cy)

It is a single byte instruction the operation code is 10011 SSS. It has 7

variation. It is register addressing mode. The micro RTL flow is
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:SBBv 1
S0 1

It require one m/c cycle OFMC and 4 states

(11) SBB M: The meaning of the instruction is subtract the content of

memory location whose address is in (H,L) pair with from the content of
accumulator with barrows and store the result back in the accumulator. The
macro RTL implemented is
(A) (A) M(H,L) (cy)

It is a single byte instruction. The operation code is 10 011 110. It has no

variation. It is a register indirect address mode. The micro RTL flow is

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:SBB M 1
S0 1

MC 2
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
MRMC
T2:RD0, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (TEMPR)(AD7 AD0)(A) (A) (TEMP)
S1 1
FEO
S0 0

It require two m/c cycles OFMC and MRMC and 7 states.

(12) SBI DATA: The meaning of the instruction is subtract the content
available as a second byte of the instruction from from content of
accumulator with barrow and store the result back in accumulator. It is a two
byte instruction. The operation code is
 11 011 110 N
<B2> N+1

It has no variations. It is immediate addressing mode. The micro RTL flow

is

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:SBI DATA 1
S0 1

MC 2
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
MRMC
T2:RD0, (PC) (PC) 1,AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (TEMPR)(AD7 AD0)(A) (A) (TEMP) (cy)
S1 1
FEO
S0 0

It requires two m/c 7 states.

Note: In all these above instruction all the flow are affected as per rule.
Lecture-22
(13) INR v: The meaning of the instruction is incremented the content of
register v by 1 and store it back to the register r. the macro RTL
implemented is
(v) (v) 1

The operation code is 00 DDD 100. It is a single byte instruction. It is

register addressing mode. It has 7 variations in this all the flags are affected
except carry flag. The micro RTL flow is

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:INRv 1 (TEMP) v, (v) (TEMPp)a
S0 1

It require one M/C OFMC and 4 state

(14) INR M: The meaning of the instruction is increment the content of

memory location by 1 whose address available in (H, L) pair and store the
result back in the same location. The macro RTL implemented is
M(H, L) M(H,L) 1

It is a single byte instruction. The operation code is 00 110 100. It has no

variations. It is register indirect addressing mode. The micro RTL flow is

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:INR M 1
S0 1
MC 2
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
MRMC
T2:RD0,AD7 AD0 M(AB)
IO / M 0
S1 1 T3:RD1,, (TEMP)(AD7 AD0), (ALU) (TEMP) 1
S0 0

MC 3
MWRMC3 T1:AD 7 AD 0 (L), A15 A 8 (H), ALE
IO / M 0 T2: WR 0, AD 7 AD 0 (A)
S1 0 T3:WR 1, , M(AB) (AD 7 AD 0 )
S0 1

It requires 3 m/c cycles OFMC, MRMC, MWRMC, and 10 states.

(15) DCR v: the meaning of the instruction is decremented of register v by

one and content result back in the register. The macro RTL implemented is
(v) (v) 1

It is a single byte instruction. The operation code is 00 DDD 101. It has 7

variation. It is a register direct addressing mode. The micro RTL flow is

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:DCR v 1,(v) (v) 1
S0 1

It require one cycle OFMC and 4 states.

(16) DCR M: The meaning of the instruction is decremented the content of

memory location whose address is stored in (H, L) pair by the same location.
The macro RTL implemented is
M(H,L) M(H,L)
It is a single byte instruction. The operation code is 00 110 101. It has no
variation. It is a register indirect addressing mode. The micro RTL flow is

MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:DCR M 1
S0 1

MC 2
MRMC T1:AD7 AD0 (L), A15 A8 (H),ALE
IO / M 0 T2:RD0,AD7 AD0 M(AB)
S1 1 T3:RD1,, (TEMP) (AD7 AD0 ), (ALU) (TEMP) 1
S0 0

MC 3
MWRMC T1:AD 7 AD 0 (L), A 15 A 8 (H) , ALE
IO / M 0 T 2: WR 0, AD 7 AD 0 (A )
S1 0 T3:WR 1, , M (AB) (AD 7 AD 0 )
S0 1

It require three m/c cycles and 10 states. In above 4 instructions and 10

states. In above 4 instructions all flag are affected except CY.

(17) INX rp: The meaning of the instruction is incremented the register pair
(rp) implemented is
(rp) (rp) 1

It is a single byte instruction. The operation code is 00 RP 0011. It has 4

variations. It is register addressing mode. The micro RTL flow is
 T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
MC1
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
OFMC
T3:RD 1, , (IR) (AD7 AD0 )
IO/M 0 T4:INX RP 1, (rpH) (rpL) 1
S1 1 T5: T6 : IF(rpL 00H),(rpH) (rpH) 1
S0 0 ELSE NOTHING

It require one m/c cycle OFMC and 6 states.

(18) DCX rp: The meaning of the instruction is decrement the register pair
(rp) together by1. The macro RTL implemented is
(rp) (rp) 1

T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE

MC1
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
OFMC
T3:RD 1, , (IR) (AD7 AD0 )
IO/M 0 T4:INX RP 1, (rpL) (rpL) 1
S1 1 T5: T6 : IF(rpL) FFH),(rpH) (rpH) 1
S0 0 ELSE NOTHING

It requires one m/c cycle OFMC and 6 states. In above two instructions no
flag is affected.

(19) DAD rp: The meaning is double precision addition is add the content of
(H,L) pair to the content of register pair (rp) and store the result back is in
the (H,L) pair. The macro RTL implemented in
(H,L) (H,L) (rpH, rpL)

Only the CY flag is effected as per rule. It is a single byte instruction. The
operation code is 00 RP 1001. It has memory is needed, if the opcode is read
from the memory therefore it goes into bus m/c cycle because to requires 10
states even single byte instruction. The micro RTL flow
MC 1
T1:AD7 AD0 (Z 1), A15 A8 (W),ALE
OFMC
T2: RD 0, (PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:DAD rp 1
S0 0

MC 2
T 1: ( W ) ( A ) , ( Z ) ( P R )
BIMC
T 2 : ( A ) ( rp L ), (T E M P ) ( rp L )
IO / M 0
T 3 :( L ) ( L ) ( rp L )
S1 0
( c y f la g i s S E T o r R E S E T )
S0 1

MC 3
BIMC
T1: ( A ) ( rp H ), (T Y R ) ( rp H )
IO / M 0
T 2 : ( H ) ( H ) 1, ( r p H ) C Y
S1 0
T 3 : ( A ) ( W ) ( P R ) (S , Z A C , P )
S0 1
RD 1

This requires 3 m/c cycles OFMC and two BIMC.

DAD H: This statement means (H,L) (H,L) (H,L)

The meaning of this multiplying the 10 byte content of (H,L) by 2. It

actually shift all the 16 bits content of (H, L) to left by one bit position.

(20) DAA: Meaning is decimal adjust accumulator. It is specifically used for

BCD addition operation. It adjusts the content of accumulator to two bit
BCD. It performs the following operation on 8 bit data in the accumulator.
When DAD is executed:

(1) if the lower order 4 bits A3 A2 A1 A0 is an illegal BCD code or if AC is

SET then 06H is added to accumulator.

(2) thereafter if the higher order 4 bits A7 A6 A5 A4 is an illegal BCD code or

if CY is SET then 60 H is added to accumulator else no action. It is a single
byte instruction. The operation code is 00100111 or 27h. it has no variations.
The micro RTL flow is

T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE

MC 1
T2: RD 0, (PC) (PC) 1, (AD7 AD0 ) M(AB)
OFMC
T3:RD 1, , (IR) (AD7 AD0 )
IO / M 0
S1 1 T4:DAD M 1

S0 1 FEO
AdjustA & flags
Lecture-23
LOGICAL GROUP:

Fig 17

Fig 17 gives the operation code format for logical group. It consists of
19 basic instructions. There are three basic logic operation AND XOR
& OR logical operation takes place bit by. The operand is assumed to
be in the accumulator. The second operand is seen either in the
internal general purpose register, in the memory location pointed to
the M- pointer or as the second byte logical operation is stored back
in the accumulator.

(21) ANA v: The macro RTL implemented is

(Ai ) (Ai )n(vi ) i 0 to7

Or
(A) (A) n (v)

This is a single byte instruction. The meaning of the instruction is

AND bit by bit the content of register (v) to the content of accumulator
and store the result back in the accumulator. The operation code is

10 100 N
SSS
It has 7 variations. The micro RTL flow is
given below. The cy flag is cleared and AC is set.
 T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC T2: RD 0, (PC) (PC)H,AD7 AD0 M(AB)
IO / M 0 T3:RD 1, , (IR) (AD7 AD0 )
S1 0 T4 : (A) (A) (r)
S0 1 FEO

It requires single M/C cycle OFMC of 4 states. It is register

addressing mode.

ANA M:

The macro RTL implemented is,

(A) (A) M(H,L)

This is a single byte instruction the meaning of the instruction is AND

bit byte the content of the memory location whose address is stored
in (H, L) pair to the content of the accumulator and store the reset
back in the accumulator. The operation code is,

10 100 110
N

It has no variation. The Micro RIL flow as given below:

T1:AD7 AD0 (PCL), A15 A8 (PCH) , ALE

OFMC
T2: RD 0, (PC) (PC) 1, (AD7 AD0 ) M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 0
T4 : ANAM 1
S0 1
MRMC T1:AD7 AD0 (PCL), A15 A8 (H),ALE
IO / M 0 T2:RD0, (PC),(AD7 AD0 )M(H,L)
S1 1 T3:RD1,, (Temp)(AD7 AD0),(A) (A) (Temp)
S0 0

It requires 2 machine cycle OFMC & MRMC 7 states. It is regular

indirec5t addressing mode.

ANI DATA The macro RTL implemented

(A) (A) B2

It is two byte instruction the meaning of the instruction is AND bit by

bit the content available as a second byte of instruction to the content
of the accumulator and store the result back in the accumulator the
operation code is

11 011 110
<B2>

It has no variation the micro RTL flows given below

OFMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE

IO / M 0 T2: RD 0, (PC) (PC) 1, (AD7 AD0 ) M(AB)
S1 1 T3:RD 1, , (IR) (AD7 AD0 )
S0 0 T4:ANI DATA 1

MRMC
T1:AD7 AD0 (PCL), A15 A8 (H),ALE
IO / M 0
T2: RD 0, (PC) ,(AD7 AD0 ) M(H,L)
S1 1
T3:RD 1, , (Temp) (AD7 AD0 ),(A) (A) (Temp)
S0 0

It requires two machine cycle OFMC&MRMC and 7 states. It is

immediate addressing mode.
Note: In these AND operation except for CY and AC flags other flags
are effect as per standard rules, CY flag is always clear to0 and AC
flag set to1.

XRA r Exclusive or register the macro RTL implemented is,

(A) (A) + (r)

It is a single byte instruction the meaning of the instruction is

exclusively
Ed bit by bit the contents of register r is with the contents of
accumulator and
Store the result back into accumulator the operation code is

10 1 0 1 S S S N

It has seven variations and the addressing mode is register

addressing mode. Only one Machine cycle is required i.e. OFMC of 4
states.
XRA M Exclusive OR memory), the macro RTL implemented is
(A) (A) + M (H, L)
It is a single byte instruction the meaning of the instruction is
exclusively ORed bit by bit the contents of memory location printed by
(H,L) register pair with the contents of accumulator and Store the
result back into accumulator the operation code is,

1 0 1 0 1 110 N

If has no variation the addressing mode is register indirect

addressing mode two machine cycles are required OFMC-4, OFMC-
3,is total 7 states.

XRI data (Exclusive OR immediate ), the macro RTL implemented is

(A) (A) + < B2>
 If is a two byte instruction the meaning of the instruction is the
contend of the second byte of the construction is exclusive ORed with
the contents of accumulator bit by bit and the result is stored back
into accumulator the operation code is,
11101110

If has no variation the addressing mode is immediate

addressing mode two M/C cycles are required OFMC-4, MRMC-3 is
total 7 states.

Note 1: In all exclusive OR ALP is all the flags are affected as per
standard rule expect AC & CY flags are cleared.
2. There is no explicit instruction to clear the accumulator to
zero however it is implicit is the statement XRAA. This means (A)
(A) + (A) ,the result will be 0000 0000 is the accumulator along with
dealing AC & CY flags.
7) ORA r (OR Register), this is an ALP statement. The macro RTL
implemented is,
(A) (A) U (r)
If is a single byte instruction the contend of the register r is
inclusive ORed with the contents of accumulator bit by bit and the
result is stored back into accumulator the operation code is,

10 110 S S S N

If has seven variation the addressing mode is register

addressing mode if
requires are M/C cycles OFMC of 4 states, All the flags are affected
except AC CY flags are cleared.
8). ORA M (OR Register), this is an ALP statements .the macro
RTL implemented is
(A) (A) U M (H, L)
 If is a single byte instruction the content of the memory location
whose address is available in the H, L register pair is inclusive ORed
with the contents of accumulator and the result is placed in the
accumulator. The operation code is,

10 1 1 0 110 N

If it has no variation the addressing mode is register indirect

addressing mode if requires two M/C cycles OFMC- 4 and MRMC- 3
& total 7 states. All the flags are affected except AC CY flags are
cleared.
9). ORI data (OR immediate), this is an ALP statements .the
macro RTL implemented is,
(A) (A) U < B2 >
If in a two byte instruction, the content of the second byte of the
instruction is inclusive ORed with bit by bit with the contents of
accumulator. The operation code is,

11 110 1 1 0
< B2 >

If has no variation the addressing mode is immediate

addressing mode. If
requires two Machine cycles OFMC- 4 and MRMC- 3 & total 7 states.
All the flags are affected except AC CY flags are cleared.
Note: ANI data, XRI data & ORI data are used for manipulating any
bit of the
Accumulated without affecting the other bits. For example,

(i) Set Bit 5 of ACC without affecting the other bits.

 OR operation `
ORI 20 set bit 5 of (A) without affecting the other bits. This is known
as Masking.
(ii) Force bit 3 & bit 2 to 0,0 without affecting the other bits.

ANI operations ANI F3

4
(iii) Complement bit 7 , bit-5 & bit -3 without affecting the other bits.

EX-OR operation XRI AS

4
(iv) Test a particular bit (say bit.6) to find whether it is zero or 1

And MOV B,A

ANI 40

2f A6= 0, content of the code will be zero

A6 = 1, content of the code will be non zero.
13. CMP r: (compare register with ACC) this is also an ALP
statement. The content is also an ALP statement the content of
register r is subtracted from the accumulator (A) (r) operation is
performed but the result of the subtraction operation is not content of
Acc & register (r) is not destroyed but as result of this operation the
flags are affected as per standard rule as follows.
If (A) > (V) CY = 0, z = 0
(A) = (V) CY = 0, z = 1
(A) < (V) CY = 1, z = 0
If is a single byte instruction. The operation code is,
10 111 S S S

If has seven variations. The addressing mode is requiring

addressing mode. One M/C cycle is required OFMC 4 of 4 states.
CMP M: (compare memory with ACC); the content of the memory
location whose address is contained in the HL register pair is
subtracted from the accumulator. The accumulator remains
unchanged. The condition flags are
set as a result of the subtraction.
2f (A) >M (H,L) CY = 0, z = 0
(A) = M (H,L) CY = 0, z = 1
(A) < M (H,L) CY = 1, z = 0
2f is a single byte instruction. The operation code is,

10 1 1 0 110 N

It has no variations. The addressing mode is requiring indirect

addressing mode. It requires two machines cycle of OFMC & NMRC
of seven states.

12) CPI data: (compare immediate) this is an ALP statement. The

content of the second byte of the instruction is subtracted from the
 accumulator, the result of the subtraction flags are set as a result of
the subtraction. The Z flag is set if
(A) = < B2)>,the CY flag is set if (A) = < B2)>
2f is a two byte instruction the operation code is

11 110 1 1 0
< B2 >
2f has no variations. The addressing mode is immediate
addressing. It requires too M/C cycle OFMC and MRMC of seven
states.
Lecture-24
13) RLC: This is an ALP statement. The macro RTL implemented is,

(A0+ 1) (A1) 0 = 0 to 6
(A0) (A7)
(CY) (A7)

The meaning of the instruction is not the left the content of the
accumulator by one bit the lower order bit & the CY flag are both set to the
value shifted out the high order bit position. Only the CY flag is affected.
The operation code is,

10 1 0 1 S S S N 074

If has no variations. The addressing mode is implied addressing mode

the macro RTL flow is,

OFMC T1 : AD7 AD0 (PCL) , A15 A8 (PCH) , ALE =

IO/ = 0 T2 : = 0, (PC) (PC ) H, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : RLC = 1 , (ALV) (A)

Mc 2 T1 : FEO (rotate left )

T2 : (A) (ALV) ;
Therefore, one M/C cycle OFMC of 4 states is required. This instruction
is used to check any
14) RRC: This is an ALP statement the macro RTL implemented is
 (Ai) (Ai+ 1) i = 0 to 6
(A7) (A0), (CY) (A0)

The content of the accumulator is rotate right by one bit position as shown
In fig

A2 A0
CY
The high order bit & the Cy flag can both set to the value of shifted out
of the low order bit position only the Cy flag is affected the operation is

10 1 0 1 11 1 N is O Fm

If has no variations. Only OFMC of 4 states is required. The

addressing mode is register and implied addressing mode.
15) RAL: (Rotate left through carry), this is an ALP statement the macro
RTL implemented is,

(Ai + 1 ) (Ai) i = 0 to 6
(CY) (A7),
(A0) (CY)
The content of the accumulator is rotate left one position through the
CY flag. The low order bit is set equal to the CY flag. The CY flag is set to
the value shifted out of the A7 bit as shown in fig

CY A7 A0
Only the CY flag is affected the operation code is

10 1 0 1 11 1 N = 17H
 If has no variations, the addressing mode is implied addressing mode.
Only one M/C cycle OFMC of 4 states is required.

16) RAR: (Rotate accumulator right through carry), this is an ALP statement
the macro RTL implemented is,

(Ai) (Ai + 1) i = 0 to 6
(CY) (A0),
(A7) (CY)

The content of the accumulator is rotate right one bit position through
the CY flag. The high order bit is set equal to the CY flag and The CY flag
is set to the value shift10 out of the A0 only the flag is affected.

CY A7 A0
The operation code is,

000 1 11 11 = (IF)H

This is a single byte instruction. The M/C cycles required is only one
OFMC- 4 the addressing mode is implied addressing mode.

17) CMA: (complement accumulator), this is an ALP statement; the macro

RTL implemented is,
(A) ( )

The content of the accumulator is complemented bit by bit and the

result is stored back into the acc no flags are affected, the operation code is,

000 1 11 11 N= 2FH
 It is a single byte instruction & no variation. The addressing mode is
implied addressing mode requires one M/C- 4.

18) CMC: (complement carry), this is an ALP statement, and the macro RTL
implemented is,
(CY) ( )

The CY flag is complement and it is stored back into the same CY

flag position. The operation code is,

00 11 11 11 = (3F)H

It is a single byte instruction & no variation. 2f this no other flags are

affected, it requires the M/C cycle OFMC-4.
T4: CMC = 1, (ALU) (CY)
FEO : FEO, ALU ( )
(CY) (ALU)

Therefore only 4 states are required.

19) STC: (set carry), the macro RTL is,
(EY) 1

The carry flag is set to 1 and no others flags are affected, the operation
code is,

00 11 01 11 N= 3T4

It has no variation. 2f requires one M/C cycle of - 4 states only. i.e.

OFMC- 4.
Branch group:
This group of instructions are used to alter the normal required flaw
and for the program to proceed from a different point. Conditions flags are
not affected by any instruction in this group only PC is affected; sometimes
stretch also comes into picture. Branch instruction can be of two types
conditional & unconditional. Unconditional branch instruction simply cause
the program to branch to the indicated instruction whenever it is encountered
is PC is located with a new address conditional branch instructions examine
the stares of one of the four processor flags (Z, CY, P, S) to determine if the
specified tested is TRUE, it causes is not used for specifying condition the 8
conditions that are tested are given below.
Conditions flag tested identification code CCC
NZ not zero Z=0 000
Z zero Z=1 001
NC not carry CY = 0 010
C carry CY = 1 011
PO parity odd P=0 100
PE parity even p=1 101
P plus S=0 110
M minus S=1 111
2f Z = 0 is not true, then NZ is true
Z = 0 is true, and then NZ is not true.
The identification code CCC when involved in an instruction shall be
seen on the bit D5D4D3 of the operation code
There are 8 basic operations in this group the operation code format is
shown,

JMP DDR:
This is an ALP statement DDR is the symbolic name given to the
16- bit address data available as the second & the third byte of the
instruction. JMP is the mnemonic for jump the meaning of the instruction is
load the PC with the 16- bit data available in the instruction itself so that he
next instruction is fetched cycle. This is a 3 byte instruction the instruction
formed being.

The macro
RTL implemented is
(PCH) < B3 >
(PCL) < B2 >
Conditions before & after the execution of JM addr instruction are
shown below.
 The macro RTL flow is as shown below.
MC - 1
OFMC T1 : AD1 AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : instruction is decoded JMP = 1

MC - 2
MRMC T1 : AD1 AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (Z) (AD7- AD0)
S0 = 1

MC - 3
MRMC T1 : AD1 AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ =0 T2 : = 0, (PC) (Z ), (AD7- AD0) M(AB)
S1 = 1 T3 : = 1, (PCH) (AD7- AD0)
S0 = 1 W FEO =WZ+1 Wz pc wt

Thus, it requires three machine cycle OFMC, MRMC & MRMC and
total 10 states using a 2 MH3 internal clock it requires 5 sec. No variation
in this instruction. The addressing the mode in their case is immediate
addressing mode because the 16 bit address data is immediately in the
instruction itself to be loaded into the PC.

2. J cend ADDR: There are 8 variations for this instructions depending upon
the conditions to be tested. They are JNZ, JZ, JNC, JC, JPO, JPF, JP, and
JM. This is also an ALP statement. This is a 3 byte instruction the operation
code format is,

11 000 011 N
< B2 > N+1
N+2
< B3 >
The meaning of the instruction is illustrated in the flow chart

Where (PC) = (X3X2X1X0 )4 just at the start of instruction exit.

X3X2X1X0 11ccc010 N Y3Y2

N+1
Y1Y0

Y3Y2 N+2
X3X2X1X0
PC

Fig shows the condition existing just before the stand of instruction
cycle J cend ADDR the IC, b address in the PC just often the end of the
instruction cycle depends upon the condition to be tested PC will be loaded
 with B3B2 if the given condition is TRUE, otherwise (PC) will go to (PC)
where (PC) shall be the address X3X2X1X0 which points to the operation
code 11 CCC 010. The micro RTL flow given below.
MC - 1
OFMC T1 : AD1 AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : J cond = 1

MC - 2
MRMC T1 : AD1 AD0 (PCL) , A15 A8 (PCH) , ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (Z) (AD7- AD0)
S0 = 1 if condition = true, go to MC-3 else (PC) (PC) + 1

MC - 3
MRMC T1 : AD1 AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 0 T2 : = 0, (PCL) (Z ), (AD7- AD0)
M(AB)
S1 = 1 T3 : = 1, (PCH) (AD7- AD0)
S0 = 1 W FEO =WZ+1 Wz pc wt

Therefore if the condition is true it takes 10 states to get instruction

executed 2f the condition is not true then it takes 7 states for the instruction
to be executed. The addressing mo0de is immediate addressing mode Z and
no flags affected.
Lecture-25
2. CALL ADDR: This is an ALP statement ADDR the symbolic name
given to the 16-bit address available as the 2nd and 3rd byte of the instruction
that is a 3byte instruction the operation code format is,

11 000 011 N = CD 4
< B2 > N+1
N+2
< B3 >

If a program it looks as shown in fig.

CD
X3X2X1X0 N
Y1Y0
N+1
Y3Y2 N+2
X3X2X1X0+3 Nextinstruction N+3

The op-code cycle CD being at memory location, the next address

being (X3X2X1X0)4 then N +3 = (X3X2X1X0)4 is known as the return address
this instruction is used for unconditional subroutine CALL. The starting
address of the subroutine is Y3Y2Y1Y0 available immediately in the
instruction itself. The stack is made use of to store the return address before
jumping to the subroutine. The meaning of the instruction is save the return
address on the PC with the address immediately available RTL implemented
is,
M [ (sp)-1 ] (PCH)
M [ (sp)-2 ] (PCL)
(sp) (sp)-2
(pc) (B3 , B2)
Where (PCH,PCL) is the RETURN address the high order 8bits of the
return address are moved to the memory location whose address is are less
 than the content of sp. The low order 8 bits of the return address are moved
to the memory location whose address is two less than the content of SP the
content of the register SP is decremented by 2 so that it always point to the
top of the stick. Content is transferred to the instruction whose address is
specified in byte 2 & 3 of the current mode because the 16- bit address is
immediately available in the instruction. Their also includes register indirect
address has to be saved in the memory location whose address is available in
the register SP. Condition before execution is,

X3X2X1X0 CD N X3X2X1X0 Y3Y2Y1Y

N+1 Z3Z2Z1Z0
Y1Y0 Full
N+2
X3X2X1X0
Y3Y2 N +3 Full

PC Z3Z2Z1Z0
Full
SP
The main RTL flow is
MC - 1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : CALL = 1

: (sp) (sp) - 1
MC - 2
MRMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (Z) (AD7- AD0)
S0 = 1
MC - 3
MRMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+ 1, (AD7- AD0)
M(AB)
S1 = 1 T3 : = 1, (W) (AD7- AD0)
S0 = 1

MC - 4
RMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (AD7- AD0) (PCH),(SP) (SP)-1
S1 = 1 T3 : = 1, M(AB) (AD7- AD0) , (SP) (SP)-1
S0 = 1

MC - 5
NRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH), ALE =
IO/ =0 T2 : = 0, (AD7- AD0) (PCL),
S1 = 1 T3 : = 1, M(AB) (AD7- AD0) ,
S0 = 1
T1 : A15- A8 (W) , AD1 AD0 (Z) , ALE =
FEO T2 : = 0, 1 (PC) (WZ) +1,

Thus it requires 5 machine cycles and total18 states the largest

instruction cycle is 8085.using 4MH3 crystal, is 2 MH3 internal lock it
require 9 sec to execute this instruction there is no variation in this
instruction.

4) C cend ADDR (condition call):

This is an ALP statement, this is also 3-byte instruction, 2nd and 3rd byte
give the address of the subroutine when this instruction is executed, the
jumps to the subroutine if the condition tested is TRUE. 2f the condition is
not true then goes to execute the next instruction the instruction format
is,

11 CCC 10 0 N
N+1
< B2 > N+2
< B3 > N + 3 return address

This has 8 variations for CCC, 000 to 111 the corresponding

instructions are CNZ, CZ, CNC, CC, CPO, CPE, CP, CM the macro RTL
implemented is shown in Fig.

If has immediate addressing mode register indirect addressing mode.

If the specified condition is true, the execution specified in the CALL

 Instruction are performed otherwise control continues sequentially. The
micro RTL flow is,
MC - 1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : C cend = 1

: (sp) of condition is (sp) - 1

MC - 2
MRMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (Z) (AD7- AD0)
S0 = 1
MC - 3
MRMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+ 1, (AD7- AD0)
M(AB)
S1 = 1 T3 : = 1, (W) (AD7- AD0)
S0 = 1

MC - 4
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (SP) (SP)-1 (AD7- AD0) (PCH),
S1 = 1 T3 : = 1, M(SP) (AD7- AD0) ,
S0 = 1

MC - 5
MWCMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (AD7- AD0) (PCL),
S1 = 1 T3 : = 1, M(AB) (AD7- AD0) ,
S0 = 1
T1 : A15- A8 (W) , AD1 AD0 (Z) ,ALE
FEO T2 : (PC) (WZ) +1,

Thus if condition is true it requires 18 states and otherwise 9 states are

required.

5) RET (Return):
This is an ALP statement, stands for RETURN. The meaning OS
return to the main program from the subroutine unconditionally, obviously
the instruction should be a part of the subroutine program. This is a single
byte instruction the operation code format is,

11 CCC 10 0 N = C9H

The macro RTL implemented is,

(PCL) M(SP)
(PCH) M[(sp) + 1]
(sp) (sp)+2
When this instruction is executed the 16 bit, address data available at
the top of the stack shall be loaded into the (PC) and stack print is
readjusted a that it again print to the top of the stack the content of the
memory location whose address is specified in register SP is moved to the
low order 8 bits of the memory location whose address is one more than the
content of register SP register is moved to the high order 8 bits of pc, the
content of the register SP is incremented by 2. 2f is for the used to set to it
that the proper RETURN ADDR is available correctly on the top of the stack
before asking the p to execute the RET instruction

The micro RTL flow is,

MC - 1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) , ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : RET = 1

MC - 2
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) , ALE =
IO/ = 0 T2 : = 0, (SP) (SP)+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (PCL) (AD7- AD0)
S0 = 1

MC - 3
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (PCH) ,ALE =
IO/ =0 T2 : = 0, (SP) (SP )+ 1, (AD7- AD0) M(AB)
S1 = 1 T3 : = 1, (CH) (AD7- AD0)
S0 = 1
Thus it requires 3m/c cycles and 10states, for 2MH3 internal clock the
time required is 5 sec, the address mode is register indirect.

Rn: This is a conditional return statement, if is also a part of the subroutine.

Whenever this instruction is executed p checks up the condition
(condition flags).
If the condition is true then the p returns to the main program by
loading the PC with the return address stored at the top of the stack of the
conditional is not true then the next instruction is the subroutine will be
executed. The macro RTL Implemented is shown as a flow chart.
 This is a single byte instruction the OP code is

There are 8 variations in this statement depending upon CCC. They

are RNZ, RZ, RNC, RC, RPD, RPE, RP and RM. The addressing mode is
register indirect because the return address is available in the memory
location pointed by SP the micro RTL flow is given.

MC - 1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : R cond = 1

: 2f (ccc) = true teen go for MC2 8 MC 3 else, go for

MC1
Of the next instruction.
MC - 2
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ = 0 T2 : = 0, (SP) (SP)+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (PCL) (AD7- AD0)
S0 = 1

MC - 3
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (SP) (SP )+ 1, (AD7- AD0) M(AB)
S1 = 1 T3 : = 1, (PCH) (AD7- AD0)
S0 = 1

Thus if the conditions is true it needs 12 states otherwise 6 states.

Lecture-26
6. RST n:
This is a single byte unconditional subroutine call instruction. The
address of the subroutine is fixed depending upon the decimal no. n in the
instruction the decimal no. n can change from 0 to 7. The comparing binary
no(NNN)2 is available as D5 D4D3 bit of the operation code.
NNN n RST-n
00 0 0 RST-0
001 1
11 1 7 RST-7
The single byte operation code is

The subroutine starting address is calibrated as follows;

Multiple the decimal no, by 8 convert it to the corresponding 2 digit
hexadecimal no. Y1,Y2.
(8 n)D (Y1Y0)4
Append (00)4 for the two MSB Hex digit, (Y3Y2)4 so that a 16-bit
address
Y3Y2Y1Y0 4 0 0 Y1Y0 4 is obtained e.g. the subroutine starting address
for
RST 5 is (8 D = <10 D = 2 8 4 00 284

The macro RTL implemented is,

M [ (sp)-1 ] (PCH)
M [ (sp)-2 ] (PCL)
(sp) (sp)-2
(pc) (8 )
 Where (PCH, PCL) is the return address.[this has 8 variations
depending upon the NNN changing from 000 to 111. The addressing mode
is register indirect, no flags affected.]

The high order 8 bits of the next instruction address are moved to the
memory location whose address is one less than the content of register SP.
The low order 8 bit of the next instruction address are moved to the memory
location whose the address is two less than the content of register SP. The
content of register sp is decremented by 2 control is transferred to the
instruction whose address is eight times the content of NNN.

The micro RTL flow is,

MC - 1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : RST n = 1

: (sp) (sp)-1 (address is calculated)

MC - 2
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (SP) (SP)+1, AD7- AD0 (PCH)
S1 = 1 T3 : = 1, M(A6) (AD7- AD0),(PCH) (00)
S0 = 1

MC - 3
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, AD7- AD0 (PCL)
S1 = 1 T3 : = 1, M(AB) (AD7- AD0),(PCL)(8 N)4

Thus 12 states are required for the execution of this instruction. One
important point while writing a subroutine program starting from the fixed
location as calculated.
Consider for example RST 5 & D 576.the corresponding starting
address of the subroutine are 0028 for RSTS, & 00304 for RST 6.recollect
that there is RST 5-5 interrupt control signal input at pin no 9 of the p this
also corresponding to an interrupt service routine starting from 00204. These
addresses are shown in fig.

The fig shows that there are only four bytes, possible for each
subroutine link and it is difficult to write subroutine here therefore, first byte
will be C3 (jump Instruction) and 2nd & 3rd bytes will be the address of same
memory locations which is the starting address of subroutine, this is known
as subroutine link address 4th byte is no operation.
8) PCHL: this is a single byte instruction the operation code is,
N=E94
11101001
There is no variation in this instruction. The macro RTL implemented is,
(PCL) (L) (PC) (H,L)
(PCH) (H)
The content of register (H) is merged to the (PCH) and content of
register (L)is merged to (PCL).the meaning of the instructions is jump to (H)
(L) location. Register indirect jump instruction. This is the only instruction
available in 8085 which allows the use to obtain a jump address from a
register. This instruction uses register addressing mode other jump
instruction use immediate reg indirect addressing mode.
This instruction is very useful in implanting select structure of the
software program. The means RTL flow is,
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : PCHL = 1

: (pcl) (l) (pc+1) (H)

Thus 6 states are required no flags affected.

This group of instructions manipulates the stack. Unless otherwise

specified, condition flags are not affected by any instruction in there
group.2f is the user responsibility to define stack area and to initialize the SP
with the bottom address before these instructions are used.
1. The meaning of the instruction is push (save) the contents of register pair
rp on top of the stack. The macro RTL is,
M [ (sp)-1 ] (rph)
M [ (sp)-2 ] (rpl)
(sp) (sp)-2
The content of the higher order register of register pair rp is moved to
the memory location whose address is one less than the content of register
SP. The content of the low-order register of register pair is moved to the
memory location whose address is two less than the content of register SP.
the content of the register is decremented by 2 the operation code is,
11RP1001N
This is a single byte instruction has 3 variations.
RP = 00 ---- (B, C)
= 01 ---- (D, E)
 10 ---- (H, L)
SP is not allowed, the addressing mode is register indirect. The macro RTL
flow is,
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) , ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : PUSH r/d = 1

: (sp) (sp) -1
MC - 2
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH), ALE =
IO/ =0 T2 : = 0, (SP) (SP)-1, AD7- AD0 (rph)
S1 = 1 T3 : = 1, M(AB) (AD7- AD0)
S0 = 1

MC - 3
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) , ALE =
IO/ =0 T2 : = 0, AD7- AD0 (rpl)
S1 = 1 T3 : = 1, M(AB) (AD7- AD0)
Thus it required 12 states.
2. PUSH PSW (push processor status word):
The meaning of the instruction is save (push) the processor status
word on the top of the stack. The accumulator & flag register together form
a 16- bit word known as the processor status word (psw), ACC will occupy
the higher order 8 bits and flag register will occupy the lower order 8-bits in
PSW.
The operation code is
11110101N = (F5)H
The macro RTL implemented is
M (sp)-1 (A)
M (sp)-2 (PR)
 (sp) (sp)-2
The content of the register A is moved to the memory location whose
address is one less than the register SP. The contents of flag register are
moved to the memory location whose address is two less than the content of
register SP. The content of the register SP is decremented by 2.2f requires 3-
M/C cycles and 12 states, the macro RTL flow is same as push rp the
addressing mode is register indirect.

3. The meaning of the instruction is pop (load) the content form the top of
the stack into register pair rp. The operation code is,

The macro RTL implemented is

(rpl) M(SP)
11RP0001
(rph) M(SP+1)
(sp) (sp)+2

The content of the memory location points by the content of register

SP is moved to the low order register of register pair rp. He content of the
memory location whose address is one more than the content of register SP
is moved to high order register of register pair. The content of register SP is
not included in this. It has 3 variations none of the flags affected the micro
RTL flow is,

MC-1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : POP rp = 1

MC - 2
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (SP) (SP)+1, AD7- AD0 M(AB)
 S1 = 1 T3 : = 1, (rpl) M(AB)
S0 = 1

MC - 3
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (SP) (SP)+1, AD7- AD0 M(AB)
S1 = 1 T3 : = 1, (rpH) M(AB)
S0 = 1
It requires 3 m/c cycles and 10 states. The addressing mode is register
indirect addressing mode.
4) POP PSW: The meaning of the instruction is load the processor vector
word register from the top of the stack. The operation code format is,
1111 =F1H
0001
It has no variation. The macro RTL implemented is,
(FR) M (SP)
(A) M (SP+1)
(SP) (SP) +2
The content of the memory location pointed by SP is moved to the
flag register (i.e. to restore various condition flags). The content of the
memory location whose address is one move than the content of SP is
moved to register A. the content of SP is incremented by 2.
The micro RTL flow is same as Popup. It also requires 3 m/c cycles
and 10 states the addressing mode is register indirect. Flags affected are Z,
S, AC, P, and CY.
5) The meaning of the instruction is exchange the top of the stack with the
content of (H, L ) register pair. The macro RTL implemented is,
M (SP) (L)
M (SP+1) (H)
The content of register L is exchanged with the content of the memory
location whose address is specified by the content of SP. The content of
register H is exchanged with content the memory location whose address is
one more than the content of SP.
 The operation code format is
11 100 011 =E3H

It has no variations. It is a single byte instruction. The addressing

mode is register indirect addressing mode none flags affected. The micro
RTL flow is,

MC-1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : XTHL = 1

MC - 2
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH), ALE =
IO/ =0 T2 : = 0, (SP) (SP)+1, AD7- AD0 M(AB)
S1 = 1 T3 : = 1, (Z) (AD7-AD0)
S0 = 1

MC - 3
MWRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH), ALE =
IO/ =0 T2 : = 0, AD7- AD0 (L), (SP) (SP)+1
S1 = 1 T3 : = 1, M(AB) (AD7-AD0),(L) (Z)

MC - 4
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH), ALE =
IO/ =0 T2 : = 0, AD7- AD0 M(AB)
S1 = 1 T3 : = 1, (Z) (AD7-AD0)
S0 = 0 or W
MC - 5
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH), ALE =
IO/ =0 T2 : = 0, (SP) (SP)-1, AD7- AD0 (H)
S1 = 0 T3 : = 1, M(AB) (AD7-AD0),(H) (Z),(SP)
(SP)-1
S0 = 1
Thus it requires 16 states and 5 m/c cycles flags affection.

6. SPHL: The meaning of the instruction is the contents of register H & L

are moved to register SP the macro RTL implements is,

(SPH) (L)
(SPH) (H)
The operation code format is
11 111 001 =E9H

It has no variations the addressing mode is register addressing mode

flags affected nnone.tha micro RTL flow is,

MC-1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : SPHL = 1
T5 : (SPL) (L) (SPH) (H)
T5 : x
2f requires one m/c cycle and 6 states.
Lecture-27
M/C control instructions:
EI (Enable interrupts):
The interrupt system is enabled following the execution of the next
instruction when this instruction is executed, then INTE F/F is set so that all
the interrupts are enabled and 8083 A will recognize external interrupt
request except those that are masked.
The operation code format is
1111 1 0 11 =FBH

If is a single byte instruction no variation flags affected.

None the micro RTL flow is

MC-1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) , ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : EI = 1

MC-2 T1 : {FEO into F/F = 1

Thus, it requires one m/c cycle & 4 states.

Note: Interrupts are not recognized during The EI instruction placing an EI

instruction on the bus response to during an INA cycle is prohibited.
DI (disable interrupts):
The interrupt system is disabled immediately following the execution
of the DI instruction. The macro ETL implemented is,
INTE F/F 0
It is a single byte instruction. The operant code is
11110011 F3H
 It has no variation No flag affected. The micro RTL flow is
MC-1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : DI = 1

MC-2 T1 : {FEO into F/F = 0

Thus it requires 4 states of OFMC.
Note: interrupts are not recognized during the DI instruction. Placing a DI
instruction on the bus in response to during an INA cycle is
prohibited.
3) NOP: (no operation). No operation is performed. The registers and flags
are unaffected the p idles for 4 states. The operation code is
0000 0000 00H
It is a single byte instruction. It has no variation. The
micro RTL flow is
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : NOP = 1
Thus one m/c of 4 states is required. This instruction has three main uses;
1) It is frequency used in delay loops to introduce a delay of 4 states.
2) It is also used to interface slower peripheral devices with 8085 A.
3) It is also used to remove or introduce any instruction in the program
HLT (Halt): when this instruction is executed the processor is stopped. The
registered & flags are unaffected.
When this instruction fetched & decoded during T4 state of instruction
cycle, then an in the immediate next T1 state this HALT F/F is checked to
see whether it is set if it is formed SET, p goes to HALT state. The micro
RTL implemented is
 HALT F/F 1
The operation code is 0111 0110 =516H
It is a single byte instruction & it has no variation.
The micro RTL flows
OFMC
T1: AD3 AD0 (PCL), A15 - A8 (ACH), ALF =
T2: =0, (PC) (PC) +1, (AD7 - AD0) M (AB)
T3: =1, , (IR) (AD3 AD0)
T4: if HALT F/F = 1, go to halt state.
Thus it requires 5 states flag affected none.
RIM & SIM:
The 8085A has three inputs, RST 5.5 RST 6.5, RST 7.5. Which are
referred to as vectored interrupts. A proper input on these 8085A inputs will
cause the program being executed by the CPU to branch to some known
locations.
I.e. 00 2C H for RST5.5
00 34 H for RST6.5
00 3C H for RST7.5
These locations should have the first instruction of the corresponding
service routine i.e. the jump instruction. The RST 5.5 & RST 6.5 input are
level sensitive here as RST 7.5 is edge sensitive the RST5.5 & RST 6.5
input will have to be held high till the 8085A acknowledge the interrupt. A
low to high transition of RST7.5 sets an internal flip flop so this input can
then be lowered without losing the interrupt request.
The 8085 also has an INTR interrupt & one non mask able vectored
interrupt called TRAR. A high at the TRAR input after a low to high edge
causes the program to branch to 0024H.
The 8085A also provides on chip facility for serial I/O via the SID& SOD
lines. The SID line can be used to input serial data to the 8085A. While the
SOD line outputs serial data from the 8085A. Inputting & outputting these
bits are also achieved using the RIM & SIM instruction
SIM (Set interrupt mask):
 This is a single byte instruction. It operates on the contents of A
before SIM is executed the operate is
0011 0000 = 30 H
The SIM instruction uses the contents of the
accumulation to perform the following functions:
(i) Program the interrupts mask for the RST 5.5, RST 6.5, & 7.5
hardware interrupts. The interrupts can be masked or unmasked by
controlling A0, A1, & A2 bits of occur before using SIM. If these bits are the
interrupt is unmasked. These bits will affect the interrupts only if MSE
(mask set enable) bit (A3) is also 1. If A3 is 0

When the SIM instruction is executed, the interrupt mask register not
changed.
(ii) RST 7.5 is edge sinister (LO). A pulse at the RST 7.5 always sets an
internal RST 7.45 F/F, even if the jump to the service routine is inhibited by
masking If interrupts are disabled at the time the RST 7.5 pulse occurs, this
input will still be recognized later since the RST 7.5 F/F has can be cleared
(or Reset) by keeping bit A4=1 when SIM is executed, this may be required
if we do not want to service an earlier RST 7.5 interrupted.
The RST 7.5 F/F is also cleared by a signal input or when the
CPU acknowledges a RST 7.5 interrupt. All three mask bit (A2, A1, A0) are
also set by its all vectored interrupt (except) are masked and therefore
disabled are masked and therefore disabled.
(iii) Load the SOD (serial output data) latch.
The SOD output of the 8085A shown the status of a 1-bit output port,
execution of the SIM instruction sets the output port content to that of A7
provided the serial output enable A6 is also
1. If SOE = A6=0, the contents of the output port is unaffected SOD is reset by
the input.
Using SOE & MSE properly one can use the SIM instruction is different
ways the format of Ace for SIM instruction is
 Ace content before SIM

This instruction requires are m/c cycle of four states no flags affected.
E.g. (1) send a1 to the SOD output line. The following sequence of
instruction shall do the word.
MVI A, CO (1100 0000)

SIM:
(2) The following sequence of instruction shell unmask RST 6.5 interrupt
control signal input & mask all other after power on.
MVI A, OD (0000 1101)
SIM, EI:
RIM: (Read interrupt mask): Whenever their instruction is executed the
status of the mask F/F INTE F/F the SID input & if any interrupts are
pending is read into accumulation as follows.
 The RIM instruction loads data into accumulation relating to
interrupts & the serial input. After RIM is executed the content of A are as
follows:
1) Current interrupt enables status for the RST 5.5, 6.5, 7.5 hardware interrupts
in A0 A1 & A2 bits (1= if mask disabled, 0 if they are enabled).
2) Current interrupt enable flag status in bit A3. (=1 interrupts enabled) except
immediately following a TRAP interrupt.
Following a TRAP interrupt (enables/ ) prior to the TRAP
interrupt.
This is useful to retrieve current interrupt since TRAP. This is important
since TRAP is a non mask able interrupt which can happen at any time.
3) Hardware interrupts pending. (Received but not serviced). On the RST 7.5,
6.5,& 5.5 line. A 1 at A6, A5, A4, respectively indicate that RST 7.5, 6.5 &
5.5 interrupts are pending.
4) Transfer the bit present at 8085s SID input to A7.
Apart from the CPU get the SID input, the RIM instruction is primarily used
to monitor interrupt status e.g.
a) Monitor whether or not an interrupt is pending without actually servicing it.
b) Check using IE properly if CPU is currently, servicing an interrupt.
c) By properly using RIM & SIM one can design any other prior structure. The
operation code is (20)4. 2f is a single byte instruction If requires 4 states.
MC 1 OFMC 4
MC 2 T1 = FEO
T2 = INTERRUPT MASK (A)

Lecture-28
UNSPECIFIED OP CODES OF THE 8085A
Examine the instruction set of 8085a, one finds that out of the 256
possible opcode with 2 bits, Intel announces only 246, there are no
announced instruction corresponding to the 10 missing opcode. User
have since reported that these missing opcode. The flags specified
by Intel are S, Z, AC, P, CY located in the flag register as

S Z X AC X P X CY

Users have reported that there are two more flag bits having same
useful meaning.

S Z X5 AC X P V CY

V = overflow bit. This bit is set to 1 of overflow occurs in 2s

complement addition / subtraction/ DCX/INX for8 and 16- arithmetic
operation.
X5 their bit has been named for its position in the condition code byte
2t does not resemble any normal flag bat this bit is affected as per the
following expression.
X5 = S1.S2 + SI.R + SL.R
Where, S1= sign of operand 1
S2= sign of operand 2
R= sign of result.
For subtraction & compression replace S1 by where operand 2 the
subtraction ie result, operand 1- operand 2. The only use for the bit
termed are as an unsigned overflow indication resulting from a data
change of FFFF to 0000 on executing the instruction INX and as an
unsigned underflow indicator from a data change of 0000 to FFFF an
executing DCX.
The ten new instructions, include seven opcode that involve
the processing of register pairs, the involve jump operation with X5
flag bit are that perform a conditional flag bit V.
The various instructions are
1) DSUB: (double subtraction): the macro RTL implements is
(H, L) (H, L) (B, C)
This is a single byte instruction. The opcode is (OB)H. the
meaning of the instruction is the content of reg. pain BC are
subtracted foam the content of reg. pain (HL) and result placed back
in reg pain (H,L). all seven condition flag are affected.
It requires 3 m/c cycles and 10 states like DAD instruction. The
addressing mode is register addressing mode.
2) ARHL: (arithmetic right shift HL reg ) the macro RTL
implemented is
H7 (H7), Hn-1 Hn,

L7 H0, Ln-1 Ln, CY L0

This is a single byte construction the opcode is (10)H. the meaning of

the instruction is the contents of register pair (HL) are shifted right by
one bit. The upper most bit is duplicated and the lower bit is shifted
into the carry bit. The result is placed back into the (H, L) reg. pair
only ax flag is affected It requires 2 m/c cycles and 7 statues the
addressing mode is register address mode.
 3) RDEL: (Rotate D.E reg. pair left through carry) the macro
RTL implements
CY D7, Dn+1 DE ,
D0 E7 , En+1 En , E0 CY.
This is a single byte instruction. The operation code is 184. The
meaning of the instruction is the content of repair DE is rotated left by
one b through the carry flag. The low order but is set equal to the CY
flag and the CY flag is set to the value shifted out of the V flag bits
are affected. The result is placed book into the DE register pair. It
requires 3m/c cycle and 10 states. The addressing mode is register
addressing mode.
4) LDHI: (Lead D, E reg pair with (H, L) flow immediate data). The
macro RTL implements is (D,E) (H,L)+<B2>
This is a 2 byte instruction the operation code format is

28 N
<B2> N+1

The meaning of the instruction in the contain of register pair (H, L) are
added to the immediate byte. The result is placed in register pair (D,
E) no condition flags are affected.
It requires three m/c cycles and 10 states. The addressing
mode is immediate & register addressing mode the second byte is
called offset.
5) LDSI: (Load (D, E) reg pain with SP flow immediately byte). The
macro RTL implements is
(D.E) (BP) + <B2>
This is a byte instruction the opcode format is
3S N

<B2> N+1

The meaning of the instruction is the content of register pair SP are

added to the immediate byte & the results is placed in register pair
(D,E). No condition flag are affected.
It requires 3m/c cycle and 10 states. The addressing mode is
immediate register addressing mode.

6) RSTV (Restart in overflow). The macro RTL implements is

shown below
I iS
M((SP)1)(PCH)
V=1?
(PC)(PC)
M((SP)2)(PCL)

(SP)(SP)2

(PC)0040H

This is a single byte instruction. The opcode is (CS)H. the

meaning is the overflow flag V is set, the actions specified above are
performed, otherwise control continues sequentially.
It requires 1 or 3 m/c cycles and 6 or 12 states. The
addressing mode is register indirect addressing mode none flags are
affected.
7) SHLX: (Store H,L indirect through D,E) the macro RTL
implemented is
M ((D,E)) (L)
M ((DE)+1) (H)
This is a single byte instruction. The opcode is (D9)H. the
meaning is the content of register L are moved to the memory
location whose addressing register DE. The contents of register are
moved to the succeeding memory location.
It requires 3m/c cycles and 10 states. The addressing mode is
reg indirect addressing mode is reg indirect addressing mode. None
flags are affected.
8) JNX5: (Jump on not X5)
The macro RTL implemented is shown below:

False is True
X5 = 0

(PC)(PC)f3 (PC1)<B>

(PCH)<B3>

Where (PC) is the address for opcode.

This is an S byte instruction. The operation code format is
N
DD
N+1
<B2>
N=2
<B3>

This instruction tests the X5 bit, if the X5 bit is 0, the control is

transferred to the instruction whose address is specified in byte 2 &
byte 3 of the current instruction, otherwise control continues
sequentially. It requires 2 or 3 machine cycle of 7 to 10 states. The
addressing mode is immediate mode. None flag are affected.
9) JX5: (Jump on X5): the macro RTL implemented is shown
below.

IS
False X5=1 True

(PC)(PC)+3 (PCL)<B1>

(PCH)<B3>

This is an 8 byte instruction. The operation code formats.

N
FD
N+1
<B2>
N=2
<B3>

This instruction test X5 bit if X5 bit is set, the control is

transferred to the instruction whose address is specified in byte 3&2
of the current instruction otherwise the control continues sequentially.
It requires 2or 3 m/c cycles and 7 or 10 states. The addressing mode
is immediate none flags are affected.
10) LLX: (Load H,L indirect through DE)
The macro RTL implemented is (DE)
(L) M (D, E)
(H) M ((D, E) +1)
 This is a single byte instruction. The operation code is EDH.
The meaning is the content of the memory location whose address is
in (DE) reg. pair are moved to register L, & the content of the
succeeding memory location are moved to register H. it requires 3m/c
cycles and 10 states. The addressing mode is register indirect none
flags are affected.
 Lecture-29
FUNDAMENTALS OF PROGRAMMING:
It is very difficult for the user to write his program directly in
machine code. 2t is more common to write the program in Assembly
language and the translate the AL program into machine language
either by hand coding or using an assembly program. (Program from
notes)
Assembly language program are usually written in a standard
form so that they can be translated to machine language by an
assembly to machine language by an assembler program (may be
self on cross assembler). In general, the assembly language
statements have four sectors in general known as fields.

Label Mnemonic Operand Comment

1) Label field: The first field is the label field. A label is a symbol used to
represent an address that is not specified known on it is a name to be
field is usually ended with a colon.
2) Mnemonic field: This field contains the mnemonic for the instruction
to be performed sometimes mnemonics are referred to as operation
codes or opcode. It may consist of pseudo mnemonics.
3) Operand field: Operand field consists of operand and operands either
constants or variables with reference to the instruction in the
mnemonic field it may be any register, data, or address on which the
instruction is to be performed. Repenting upon the absent, may
contain one operand or two operands separated by a comma. A
 comma is required between register initials or between register initial
and a data byte.
4) Comment field: A very important part of an any ALP in the comment
field. For most assemblers the comment field is started with a
semicolon. Comments do not become part of the machine program.
They are written for the reference of the user. If you write a program
without comment and set it aside for 6 months it may be very default
for you to understand the program again when you back to it. It may
even that someone else must have written it. Comments should be
written to explain in detail what each instruction or group of instruction
is doing. Comments should not just describe the mnemonic, but also
the function of the instruction in the particular routine. For best result,
write comments as if you trying to explain the program to someone
who initially knows nothing about the programs purpose. In addition
to the comments of a program or subroutine should start with a series
of comments describing what the program is supposed to do. The
staring comments should also include a list of parameter, registers
and memory location used.

The best method to introduce software program is to taken example

first and solve.
Example1: Write software program to obtain the sum of N natural
numbers only 8-bit register are to be used.
SUM =
First note down the constrains in this problem since we have to use
only 8-bit register SUM cannot exceed 255D working back we can
find out the constrain on N . We know SUM of N natural number is

given by

For SUM 255, N 22

The second stage is to list down the algorithm to be used to solve the
problem. Draw the flow chart of the algorithm for this problem it is
shown in fig(1).

Fig.1 Flow Chart of Algorithm

Fig -2 gives better picture terms of FORTRAN flow chart.

Fig.2 Flow Chart using FORTRAN

Having obtained the flow chart of this problem we shall identify the
register or the memory location to define all the variables in the flow
chart in descending this we shall follow one general rule namely. Use
internal register or register pairs only for as possible. If they are not
available then on think of a memory location as.
For the problem under consideration following may be defined as the
variable.
SUM A
 COUNTER C
I B
Having decoded the variables in the register we draw the macro RTL
flow. While drawing this flow chart we take the help of FRTRAN flow
chart drawn easily and also the instruction set. Every block in the
macro RTL flow chart must be in the macro RTL flow chart must be
implemented. Using one instruction at this stage. For the given
problem this is shown in fig (3).

Fig(3)
Having written the macro RTL flow chart we can directly write ALP.
The preliminary ALP for fig -3 is shown in fig -4
NSUM: XRA A ; CLEAR ACCUMULATOR
MVI C, N ; INITIALIZE THE COUNTER WITH LAST NN
MOV B, A ; INITIALIZE N.N IN B TO ZEI
NEXT: INR B ; GENERATE NEXT N.N
ADD B ; OBTAIN RUNNING SOMINA
DCR C ; HAS ALL N.N ADDED?
JNZ NEXT ; NO, GO BACK TO GENERATE NEXT N.N
HLT ; YES

In the above program, an ALP statement is

NEXT: INR B; GENERATE NEXT N.N
In this statement NEXT is in the LEBEL field INR is the mnemonic. B
is the operand and reset is the remark. It is also dear from the fig 4
that label field& remark field are obtained.
All the programs written down in AL should start from a specific
address which is not known before hand. Therefore, the symbol
name is given to the starting address of ALP in the program written
NSUM is given the name to the program.
The program is said to be completely written if all the instruction
mnemonics including labels are listed along with proper comments.
Next the program is assembled, i.e. the source code (instruction
mnemonics) is translated to object code (machine code) a form in
which the program can be loaded into the program memory. It is done
by hand or using an assembler.
 Hand assembly a program consists of assigning memory
address and machine codes for each of the labels, opcode and
operands. For hand assembly, two blank columns are allocated to the
lift the label field, after assembly, the first column i.e. the address
column contain the address of the first byte of each object instruction
column contain the hexadecimal representation of the 1,2, or 3 bytes
of code that comprise the instructions. Manual assembly is carried
out two steps, each require a complete scan or pass through the
program. The first pass or scan determines the memory location into
which the first byte of each instruction is assembled and creates a
table for the values of the all symbolic names in the program. A
starting address is assigned to the first byte of the first instruction and
is recorded in the address column. This is the initial value for a count
that is increment by the number of byte in each instruction. This count
corresponds to the location in memory which the first byte of each
instruction is to be placed. A counter used as the location counter
keeps the count. The counter location of the first byte of each
instruction is recorded in the address column. The label (for each
instruction that has one) is recorded is a symbol table together with
the address of the first byte of the instruction. All the completion of
the first pass through the ALP, all the symbolic label and operand
appear in the symbol table along with their assigned values. Thus, at
the end of the first pass, the address columns & symbol tables are
complete.
The second pass of the assembly process fills in the object
code column. During their pass, each instruction is examined and the
instruction mnemonic is replaced by its machine code written in
hexadecimal notation. If the address or constant constituting the
additional byte is written symbolically, the symbol table is consults to
determine the hexadecimal code for the symbolic operand. At the end
of the second pass, the assembly process is complete. The
microprocessors memory and executed.
Insertion or deletion of instruction requires program
reassembly. To avid reassembly, NOP instruction may be noted after
every few instruction. Few NOPs should left between the main
program and subroutines, so that the main program can be expanded
without having to change the addresses curtained in the subroutine
cells.
If we are not using an assembler to obtain MLP from ALP then
fig (4) is sufficient to MLP directly using hand coding procedure.
However, then the starting address should be known to us. Obviously
this should be in the RWM area. Let us suppose that the starting
address for the problem -2000H. Then the hand coding for fig-4 is
done as shown in fig-5.
LEBEL ADDR CONTENTS MNEMONICS REMARKS
&OPERAND
NSUM 2000 AF XRA A CLEAR ACC
2001 OE ___ MVI C,N INITIALIZE THE
COUNTER WITH LNN
2003 47 MOV B,A INITIALIZE N.N IN B TO
ZERO
NEXT 2004 04 INR B GENERATE NEXT N.N
2005 80 ADD B OBTAIN RUNNING SUM
2006 OD DCR C HAS ALL N.N ADDED?
2007 C2 04 20 JNZ NEXT NO,GO BACK TO GEN
N.N
200A 72 HLT YES,STOP
Lecture-30
Assemblers
To assemble a program automatically the assembler needs
information in the form of assembler direct that controls the assembly.
E.g. the assembler must be told at what address to start assembling
the program. These assembler directives are command placed in the
program by the designer that provides information to the assembler.
They do not become part of the final program as the microprocessor
nor did they translate into executed code. Therefore, they are also
known as pseudo instruction on false instructions.
Each assembler has its own unique pseudo instruction written
in assembly language format.
ORG:
The origin (ORG) instruction tells the assembler the address of
the memory location for the next instruction or data byte should be
assembled ORG entered at the beginning of a program. When
different parts of a program (e.g. subroutines) are to be placed in
different areas of memory, an ORG pseudo instruction is used before
each part of the program to specify the starting location for assembly
of that part of the program. The origin instruction has the following
form.
ORG expression
Where expression evaluation to a 16 bit address is ORG is
followed by an address if no origin pseudo instruction appears before
the first instruction in the program, assembly will begin, by default, at
memory location 0000H.
E.g. ORG 0100H tells the assembler start assembling the
immediately following program at 0100 in memory.
END:
When an assembler scans the program to be assembled it must
know, where the program ends it cannot defined on a halt instruction
for their because some program dont contain a halt as the last
instruction and other dont contain a halt at all, an application program
used, e.g., in process monitoring on control might run continuously
and therefore not contain a halt instruction. Thus, an end assembly,
END directive must be the last instruction. The directive has a form.
END
The END statement explicitly indicates the end of the program
to the assembler. If no END statement is given, then the assembler
just keeps on running through all the memory.
The ORG and END assembler direction in effected from the program
to be assembled.
ORG 0000H
[Assembly language instruction]
END
When there is more than one ORG assembler directive, then the
assembly of group of instruction start at the location specified by the
origin assemble directive that proceeds. e.g.
ORG 0000H
This block of instruction is assembled starting at location 0000H

ORG 0100 H
At location 0100h [AL instruction]
 END

EQU:
Symbolic names, which appear in assembly language programs as
labels, instructions mnemonics and operands are translated to binary
values by the assembles. As discussed in hand- assembly the labels
are assemblers location counter when entertained on the first pass of
the assembly. Instruction mnemonics have predefined values that the
assembler obtains from a table that is part of the assembler.
A symbolic operand can be a register name, an address or a data
constant. Register names have predefined values, all addresses
correspond to labels in
The program and their values are defined. Data constants, on the
other hand, are defined by the designer using an equate instruction
EQU defines symbolic used in the program. Equate assembler
directives usually appear as a group at the beginning of a program
and have the form.
Name EQU expression.
NAME stands for the symbolic name, the assemble evaluates the
expression and equates the symbolic name to it by placing the name
in its symbol table along with the value of the expression. Therefore,
whenever the name appears in the program, it is replaced by the
value the expression in the equate pseudo instruvtion.eg
COUNT EQU 0100 H
Note the symbolic name is not followed by a adan and is not a label
even though it appears in the label field. The symbolic name in are
equate statement cannot be used in another nor can it be used as the
label of another instruction. That is, the name in an equate directive
cannot be redefined. If its value is changed, the equate assemble
directive must be changed and the program reassembled.
4) SET: SET is simi8lar to EQU assemble directive this directive also
assigns a value to the name associated it. However, the same
symbol can be redefined by another SET statement late in the
program. Thus, mere that one SET instructio0ns can have the same
name the SET assembles directive has the form.
Name set expression.
5). DS: Another pheudo instructions, the define storage, reserves or
allocates read/write memory locations for storage of temporary data.
The first of the locations allocated can be referred to by an optional
symbolic label. The define storage instruction has the form
Opt label: DS expression.
A number of bytes of memory equal to the value of the expression
are reserved. However, no assumptions can be made above the
initial values of the data in these reserves locations.re the assembler
does not initialize the contents of these locations in anyway.
(e.g. BUFFER: DS 96 tells the assembler to reserve 96 memory
locations for storage when it assembles the program the address of
the first location is BU*FFER. (Buffer to BUFFER +96-1) such a
buffer is usually written and read sequentially using reg indirect
addressing. 2f has a symbolic name is used with the DS pseudo
instructions, it has the value of the address of the first reserved
location.eg to establish two byte storage registers in C/N memory
with the names TEMP 1 & TEMP 2,the instruction is written.
 TEMP 1: DS 1
TEMP 2: DS 2
During the first pass, the assembler assigns the values of its location
counter to TEMP 1& TEMP 2,respectively and thus as address is
associated with each Label. Instructions in the program can read a
write these locations using memory reference instructions such as
STA TEMP 1or LDA TEMP 2.
A memory buffer is a collection of consecutive memory locations
also used to store data temporarily.
6). DB: When a table of foxed data values is required, memory must
also be allocated. However, unlike the DS, each memory l0ocations
must have a defined value that is assembled into it. The pseudo
instructions for this is define, DB.
Opt name: DB list
List refers either to one or more arithmetic or logic expressions that
evaluate to 8 bit data quantities or to strings of character enclosed in
quotes that the assembler replaces with their equivalent ASCII
representations. Assembled bytes of data are stored in successive
memory location until the list is exhausted.eg DB 07A H stores 7A H
in meaning location right after the preceding instruction. E.g. DB
JOMA stores 4A,4F,48 & 4E in the four successive memory
locations to represent the string of ASC II characters.
7) DW: Define war instruction is similar to define byte pseudo0
instruction.
Opt name: DW list
The only difference between the DB & DW is that expression in this
define ward list is evaluated to 16-bit quantity and stored as 2-bytes.2f
is stored with the low order bytesi9n the lower memory locations and
the high order byte in the next higher one .this is consistent with the
convention for storing 16- bit quantities in 8085 A systems.
Macros:
Sometimes it is required that same set of instructions are to be
repeated again & again. One way to simplify the problem is the care
of subroutine. The other way is the use of macros. The assemblers
which have the capability to process macro instructions are called
macro assemblers. The assemblers are designed such that the
programmer need to write set of instruction once and then refer it
many times as desired.
A macro instruction is a single instruction that the macro assemble
replaces with a group of instruction whenever it applies in an
assembly language program. The macro instruction and the
instruction that replace it are defined by the system design only once
in the program. Macros are useful when a small group of instruction
must be repeated several times in a program, with only minor or no
changes in each repetition.
The use of macro in ALP entails three groups:
1) The macro definition
2) The macro reference
3) The macro expansion.
The macro definition defines the group of instruction equivalent
reference is the use of the macro instruction as an instruction in the
program. A macro expansion is the replacement of the instruction
defined be its equivalent.
The first two steps are caused out by the system designer and the
third by the macro assembler.
The macro definition has the following format:
LABEL CODE (Mnemonic) OPERAND
Name MACRO List
[Macro body]
ENDM
Name stands for the name of the macro that appears in the label
field of the macro definition. A list of dummy parameters may be
specified as List, and, if so, these parameters also appear in the
macro body. The macro body is the sequence of assembly language
instructions the replace the macro reference into program when
assembled. The macro definition produces no object code
(hexadecimal number); it simply indicates to the assembler what
instructions are represented by the macro name.

Example:
Consider the use of a macro involving a large amount of indirect
addressing. An indirect addressing input capability is provided by the
two instructions:
LHLDaddr
MOV r, M
This sequence can be written as a macro named LDIND; with a
macro definition of
LDIND MACRO REG, ADDR
LHLD ADDR
MOV REG, M
 ENDM

To have the macro body appear at any given point in the program
requires a macro reference. This format is identical to that of an
assembly language instruction.
Label code (Mnemonic) operand optional label name parameters list
Name is the label by which the macro is referenced or called.
The following macro instructions load reg c indirectly through the
address PRT
LDIND C, PTR

When a program containing macro is input to a macro assembler the

assembler carries out a test substitution, the macro expansion,
substituting for each macro reference the macro body specified in the
macro definition. And for each dummy parameter list in the macro
body, the appropriate parameter from the parameter list of the macro
reference macro assembler encounter the macro instruction
LDIND C, PTR
It replaces it with the instructions
LHLD PTR
MOV C, M
The following macro rotation the contents of the accumulator to the
left through carry, N times. This is done with a loop that is terminated
when a register is counted down to zero. The numbers of rotation, N.
and the register to be used as the counter are the parameters in the
macro definition:
RALN MACRO N, REG
 MVI REG, N
LOOP: RAL
DCR REG
JNZ LOOP
ENDM
It this macro appears in a program, which reference, it twice, a
problem results. When the macro is expanded, the label LOOP will
appear twice in the program, resulting in a multiply define symbol
error when the program is assembled. This problem is avoided by
use of the LOCAL directive; which is placed in the macro definition.
The LOCAL directive has the form.
LABEL CODE OPERAND

--- LOCAL label names

The specified label names are defined to have meaning only within
the current macro expansion. Each time the macro is referenced and
expanded; the assembler assigns each local symbol a unique symbol
in the form ??nnnn. The assembler assigns ??0001 to the first
symbol, ??0002 to the second symbol and so on. The most recent
symbol name generated always indicates the total number of symbols
created for all macro expansions. These symbols are never
duplicated by the assembler.
Lecture-31
Example: Write the software program for the same problem is
example if the largest natural number exceeds 22.
In this case the sum shall exceed 8 bite therefore 16 bit operation
are involved therefore let as take the sum to be in (H,L) pair (!6 bits)
if the sum is in (H.L) pain, the constraint on the sum is sum 65,535.
This shall give the largest value for N 361, this the largest number
also needs 16-bit register for 16 bit arithmetic operation
(Largest N.N) CONTER (B.C)
I (D.E) current A.N
Therefore the macro RTL flow chalet till be as sham in fig, 8
Fig7 give the ALP for this problem
THIS PROGRAMME / SUM OF N NATURAL NUMBERS
FOR N G.T 22
ORG 08004
LNN EQU 360 D
NSUM: LXIH, 0000 H ; INITIALIZE . SUM
LXI B, LNN ; INITILIZE CONTER
LXI D, 0000H ; INITILIZE C.N.N
NEXT: INX D ; GENERATE NEXT NN
DAD D ; OBTAIN TRUNNING SUM IN (H.L)
DCX B ; DECREMENT COUNTER
MOV A, B ; IS CONTER ZERO
ORA C ;
JNZ NEXT ; NO, GOTO GENERATE NEXT N N
HLT ; YES, SUMIN (H.L)
Fig-- 7
Example 3: write a program me to introduce 1m sec delay in the
main programmed 4 MHZ crystal is used in .
The philosophy of software data is to ask the up to do some irrelevant
job for the requested delay duration the inelegant job is to load an
eternal register with a pre calculated no. n, ask the up to decrement it
repeatedly fill the counter becomes zero, and came out of the loop,
when the canter becomes zero it this process the up must have spent
the required time delay duration, the two points to be noted in this
connection are
i) No N to be loaded is to be recalculated
ii) The register used for entail loading the number should not
contain any useful data of main programmed, the necessary
macro RTL flow chart for introducing the necessary m sec is
Shaun in fig-10

The corresponding ALP is shown in fig -4

MVI D, N 7
LP: DCR D 4 N
JNZ LP 10(N4)+7,
Fig --11
The fig 11 also shows the no. of states elapsed in executing each
instruction the total no, of state elapsed is 7+4n+10 (n-7)+7= 14n+4
if t see is the duration of a state then time dicey interfused
, THIS MUST BE EQUAL TO I MSEC, FOR 4MH3
CLOCK, THE TIME PERIED T=0.5u sec
On substitution we get,
(14N+4) 0.5 =1
 7X N = 1X _2X
1X

143D = 8FH.
So in FIG-11 the no N to be loaded in to the D register is off to
introduce m sec delay in the main pregame
Example 4: Modify examples -3 to introduce k m ser delay

In this problem use have to introduce a variable time delay from 1 m

sec up to k m sec the register pain (B.C) can be used for loading, the
constant k , k shall be for I m sec delay and k shall be 60000D for I
min delay the corresponding macro RTL flow chest in given in flg-14
While drawing the macro RTL flow chart of fig-14 it is assumed that
register pain (B.C), the register D and the accumulator it is available
to the user at this stage, the corresponding ALP for fig- 14 is shown in
fig -15
Lx I B, K 10
LP2 MVI D, N 7
LP1 DCR D 4N
DNZ LP1 10(N1) +7
DCX B 6
MOV A, B 4
ORA C 4
JNC LP2 10/7
FIG-15
The constant N can be calculated again to introduce 1msec delay,
the constant to calculate shall not differ from 8fm calculated in
example -3 because only few extra un mutation are involved in this
example, however we shall calculate the value of N
K = 1, because outer loop will not be treasured at all ,
Td = (10+7+4N+ 10(N-1)+7+6+4+4+7)T
= (14N+35)T
Assuming T=0.5 u sec, i.e., 2MHz external clock
1x (14N+35) 0.5x
14N +35 = 2x
N 140d = 8ch
8CH can be taken as I msec constant for introducing 1mesc delay
wing ALP of this constant shall not change even if some more
instructor are added to fig -15.
Consider now that of we have to implement k m sec delay, k unviable
at different point in the main programmed is when in fig- 16

One way to solve the problem of fig-16 is to repeat the flow chart of
fig-15 every time loading the (B.C) pain in the appropriate constant
k, this is empery and occupies reminder amount of memory space
unnecessarily , we can therefore write a subroutine program for k m
esc time delay starting from the symbolic address KDLEY, while
writing the subtracting it shall be assumed that values k is available in
the (B . c) register pain, this means that the value of k must be loaded
in to the (B.C) pain in the main programmed before calling the
subtraction this is known As the input to subtraction, or parameter
passing from the main programmed, the second point has to be
noted while written the subroutine , contents of all the register made.
Use of in the subtraction programmed should not be destroyed they
should be saved on the top of stack introduce the necessary delay
through software delay restore the contents of registers by pop
operations, and then RETURN to the main programmed the
subtraction is incorporation the above details is shown in fig-17.
KDLEY: PUSH B
PUSH D
PUSH PSW
MVI D, 8CH
DCR D
JNZ LPI
DCX B
MOV A, B
ORA C
JNZ LP2
POP RET
fig-17
Lecture-32
Problem 1:
An output port with an 8-bit register latch driver is interfaced
using isolated I/O PORT address 30H. This register latch driver o/p
driver o LED (0-0ff, 1-on) write a software programmed in MLP to
simulate a 8-bit ring counter as the PORT 30h. Ring counter
Must go from one state to the nest in 10 sec k m sec delay
subroutine programmed is available to you from the starting
address, 0430h, write your programmed from 0800h,
Note: For 1 T.T.T load when at is high current dram is 40 u amp
called sourcing currant when logical 0 wits then Io1 = -10ma (sinking
current) most of the J.C chip can take 10 T.T.L load,

In the ring counter only one F/F is set at a time

 LXI B. 10000D
MVI A, 80 H
NEXT: OUT 30 H
CALL KDLEY
RRC
JMP NEXT
Problem 2:
Simulate a BCD counter for up counting, the creating should be
MOP-@% BCD up counting this should go from one state to other in
10-sec,
Sample:
Write a SUBROUTINE programmed to multiply two unsigned number,
the multiply is inputted as a 16-bit number through (D,E) pain, the
multiplier is inputted to the subtractive through the accuse emulator
in the (HC) pain register on RETURN, in the process of multiplication
no register should be destroyed except (H,L) pain the a longtime
used for unsigned multiplication can be best on explained by taking a
simple example consider 4 bit multiplication.
(7x10)D = 70D
Multiplication = 0111 B= 0000 0111
Multiplication = 1010 B=
Partial Sum= 0000 0000
ADD MULITIPLICAND 0000 0000
0000 0111
0000 0111
SHIFT LEFT 0000 0111
 NO ADDITION 0000 1110
SHIFT LEFT 0001 1110

ADD MULITIPLICAND 0000 0111

SHIFT LEFT 0100 0110
NO ADDTION 0100 0110
NO SHIFITING 0100 0110 =
70D
From this simple up see dearly the algorithm chook the multiplier bit
starting from MSB, if Multiplier bit is 1, add the multiplicand to correct
partial production and them shift the partial production by one bit to
the left if the current multiplier bit is zero, do not add the multiplicand
only shift left the partial production by one bit repeat this number of
times for n bit multiplier few more refinements nil be done when we
draw the flow chart is shown in fig -18,

Fig -19 given the ALP for subroutine programmed

 UNS MUL: LIX H, OOOOH
ANA A
RZ
POSHB
MVI B, 08 H
NEXT: DAD H
RLC
JNC TEST
DAD D
TEST: DCR B
JNZ NEXT
POP B
RET
The fig-20 give is the summary of the subtraction is the proper
format, proper formatting of subroutine is necessary because once
the subroutine is satisfaction fig tested, it can be used as library for a
further use, if can be used by anybody having access to this library
provided the relevant information are given as per fig-20,
SUBROUTINE NAME: UNSMUL
INPUT:
In this we should give the parameter passed from the main
programmed to the subtraction Programmed in this case multiplicand
in (O, E) pair & multiplier is ACC.

OUTPUT: PRODOCT IN (H, L)

CALLS: NOTHING
DESTROYS: (H, L) PAIR
DESCRIPTION: THIS SUBRCOTION MULTIPLTES A 16-BIT
MULTIPLICAND BY AN 8 - BIT MULTIPLTE TO GIVE 16- BIT
PRODCT.
Example: write a subroutine to obtain
SUM =
It is assumed that 80M can be accounted in 16-bit, the coefficients ,
DTN are the +ve integers and stored is a look up table from the
starting address COEFF.
The variable X is an unsigned 8-bit integer inputted from PORT
whose symbolic address is PRTX through isolated I/O. the subroutine
is entered in this all the coefficients entered is the look up take as
explained and the starting address COEFF, namely h
available in memory location CLP to (qp+1) and the no is available in
B register,
On return from the subroutine the SUM should be available is (H, L)
pain. If is the only register destroyed by the subroutine we can make
use of the subroutine cretin earlier for aligned, multiplication of two
numbers,
SUBROUTINE: USMUL
INPUT : MULTIPLIER=(A)
MULTIPLICAND= (D,E)
OUTPUT : (H,L)= PRODUCT
CALLS : NOTHING
DESTROY : (H, L) pain
Description of the subroutine to be written is given following format,
SUBROUTINE: SUM (POLSM)
INPUT : (I) Coefficients are arranged in the starting
address COERF is parsed through two memory location CLP
and (CLPH),
OUTPUT: SUM= a x is (H, L) pain

CALLS : USMUL
DESTRCYS : (H, L)
Algorithm: SUM
POLSM: POSH PSW ; SAVE PROCESSOR STATOS
WORD
 POSH D ; SAVE (D, E) PAIR
POSH B ; SAVE (B, C) PAIR
LXI D, 0000H; INITIALIZE RONNING SUM
IN PRTX ; INPUT X VALUE PROMPRTX IN
10ACC
NEXT: LHLD CLP ; LOAD (H, L) WITH CLP
MOV.C, M ; BRING CORRENT COEFF INTOC
INX H ; (H, L) POINTS TO NEXT COEFF.
SHLD CLP ; SAVE THE NEXT COFEE ADDR IN
CLP
MOV L, C ; BRING CURRENT COEFF IN (L)
MVI H, 004 ; EXTEND THE COEFF TO
RONNING
SUM, RUNNING SUM IS NOW IN
(H,L)
XCHG ; CURRENT MULTIPLICAND IS NOW
IN
PROPER POSITION
CALL USMUL; CURRENT PRODUCT IS IN (H,L)
PAIR
XCHG ; UPDATE THE RUNNING SUM IN
(DF)
DCR B ; ALL PONE
JNA NEXT ; NO
LHLD CLP ; (H, L) PAIR NOW POINTS TO ao
MOV L, M ; BRING ao TO (L)
MVI H, OOH ; EXTEND IT TO 16-BITS
 DAD D ; (H, L) NOW CONTAINS TOTAL
SUM
POP B
POP D
POP PSW
RET
EXAMPLE; It is desired to divide a 16 bit number in locations 2000
and 2001 (HIGH BXTE IN 2001) by an 8-bit number is location 2002
using the division algorithm
a) Flowchart the problem
b) Convert the flowchart to an 8085 MLP
2000 DATA
2001 DATA
2002 DATA
2003 DATA
2004 MVI D, 00 ; INITIALIZE D= 00
2006 LIX H, 2000 ;( H,L) points to 20004
2009 MOV A, M, LOWER BYSE OF DIVIDEND IN
(A)
200A LXI 4, 2002 ; (4, U POINT TO
2002H
200D ANA A To CLEAR THE or
(Dividend L-
200F SBB M
Davison-L)
200F LXI M, 2000H same the serum of
subtract in 2000h
2012 MOV M, A
2013 LXI H, 2001H, (Dividend h-Divisor CY)
2016 MOV A, M save it is 200 TH
2019 LIX H, 2000H
201A SBBM
201 B LIX H, 2001H
201E MOV M,A
201F JP 2026
2022 LIX H, 2000 (A) (Dividend L)
2025 MOVA, M (M) (Divison L)
2026 LXI H, 2002 A (A)-1(M)
2029 ADD M
202A MOV D, A (E) A
202B HLT
202C INRD
202D JMP 2006 - increment D.

00001010 0100 0000

0011 0011 0011 0010
00 0000
0001 0001
0010/10 0010

00001000/0000000101
0101 0001 0000
0011 000000011 0010
0010/0000 00100
0000
Lecture-33
INPUT/OUTPUT Techniques

In all process content applications, p would like to

communicate with different I/O devices for data transfers is transfer of
data between circuitry external to the p itself. This transfer of data is
in addition to transfers between the microprocessor and memory and
is referred to as input/output or I/O.
In addition to the memory and keyboard interfaced to the p
many input & output peripheral devices may have to be interfaced
with the system to obtain a micro-computer depending upon a
particular control applications same of the input devices interfaced are
push bottom switches, toggle switches, a TTY, CRT, analog to digital
converters etc. some of the output devices interfaced are LED s,
seven segment displays, TTY, CPT, printers, digital to analog
converters etc.
 In the case of CPU initiated I/O transfer, it is the p which
through a software initiates the action of data transfer. In the case of
device initiated it is the external device which is interested in
communication with CPU initiates the data transfer operation. The
CPU initiated I/O transfer is also known as program controlled I/O,
because the transfer of data is completely under the control of the
microprocessor program. An I/O operation takes place only when an
I/O transfer instruction is encountered in the execution of the
program.
This I/O transfer may be unconditional or conditional I/O
transfer. In the case of CPU initiated unconditional I/O transfer
CPU initiates the data transfer and assumes that the external device
is always ready to input a data into the p at the time of data transfer
initiated by the p and therefore microprocessor affects the transfer
of data through corresponding instructions.(toggle switches).In the
case of an output data transfer the p assumes that the output
device is already to accept data and sends the necessary data
through the corresponding instructions.
In the case of CPU initiated polled I/O transfer, again it is the
CPU that initiates the data transfer operation but it does not assume
that the peripheral device is ready for data transfer.2f checks the
readiness of the device before the data transfer occurs. This involves
testing one or more status flags or bits associated with the I/O device
before the data transfer .this is known as hand shake control signals
.the flow chart for CPU initiated polled I/O transfer is shown in fig.
 CPU initiated polled I/O transfer can be preferred if and only if
the p has no other useful work to do in the process control under
consideration and can wait away the ti9me till the device is ready
for data communication. On the other hand, if the wait away time is
large like 1 sec or 1min and the process control application under
consideration demands some useful work to be done by the p. In
such cases, CPU initiated polled I/O transfer shall be dispensed with
and device initiated I/O transfer should be preferred.
Device initiated I/O transfer is one which the device initiates
the transfer of data. There are two main of data transfer;
 In the case of device initiated interrupt I/O transfer (also
known as interrupt program controlled I/O), an external device
indicates directly to the p its readiness to transfer data by making
the corresponding interrupt control signal active. Most p interrupted
input can be disabled u8nder program controlled I/O. when a
microprocessor program is interrupted, p recognizes the fact that the
external device has requested for the data transfer & control is
transferred to an interrupt service subroutine. This subroutine
performs the data transfer and then return the control to the program
at the point it was interrupted, and processing continues thus, with an
interrupt program controlled I/o operation, the data transfer is
requested by an external device and then implemented by an
interrupt service subroutine.
D.M.A stands for direct memory access.2f is also referred to as
hardware controlled I/O, 2f is the only type of I/O transfer in which the
p is not involved in the transfer of data between the memory and the
external device .In this case there is direct data transfer between an
I/O device and memory, data Is not transferred from an I/O device to
one of the p registers and then to memory a vice-versa. In DMA, p
goes to the HOLD state. the address bus data and the data
communication control signal like , .IO/ are all tri-stated and
the external device which initiates the D.M.A through making HOLD
control signal active, takes the command of the address bus BDB and
BCB and The control signal for data transfer applications between the
memory & device DMA is used primarily to transfer a number of
words or black of data at high speed.
Lecture-34
Interfacing IO Devices
As discussed earlier, input port and output port are basically
external registers. The IO/ the 8085 A determines
whether the address generated during a data transfer refers to
memory (IO/ (IO/
Address space is truth divided by control strobes into an input
address space ( and an output address space ( . Fig
shows how the address space of 8085 A is partitioned by this control
signal. When I/O ports are assigned separate address space distinct
from the address space of the external register that comprise main
memory (other than memory space), they are referred to as isolated
or standard I/O.

Along with or
Or
Only the IN and OUT instructions provide data transfer for
isolated I/O IN and OUT each require three m/c cycles for execution
the first is of course, an OPCODE FETCH. The second is MEMORY
READ during which the 8-bit port address is transferred from memory
to the p and placed in both the W & Z temporary registers and the
third is either an I/O READ on I/O WRITE machine cycle during which
the actual data transfer from or to the I/O device occurs.
During the I/O READ and I/O WRITE m/c cycles, the 8-bit port
address, in W & Z is outputted from the 8085 A on address data bus
lines AD7-AD0 and on address lines AD15-AD8.the read and
write control strobes from the 8085 A specify the exact time at
which an input ports tri-state buffer is enabled to drive the data bus
or the exact time at which an output port the data placed on the data
bus by the p respectively.
For input ports, external decoding logic combines IO/ ,
and the port address and generates a unique input device select
pulse for each input port. The pulse occurs only during the I/O READ
m/c cycle of an in interaction that address the specific port. The input
device select pulse enables the input ports tri-state buffer.2f through
design or program error. The tri-state buffers of two or more ports or
a port and a memory device are simultaneously enabled both drive
the data bus and cause bus contention.
 For output operation, external decoding logic combines ,

IO/ and the port address and generates a unique output device
select pulse occurs only during the I/O WRITE m/c cycle of an OUT
instruction that addresses the port and decks the output ports
register. Typically each output device select pulse checks a single
output port; however it is possible that more than one port are
selected simultaneously.
The design of device selection logic varies, depending on how
many I/O devices are required in a system. 2f only a single input port
and a single output port are required address decoding is
unnecessary. The I/ control signal is simply combined with to

generate an output write strobe I/ .these strobes directly control

the input buffer and the output latch, respectively the port address
byte of the I/O instruction is, in such cases are dont care but cannot
be omitted from the instruction or its object code IN & OUT are 2-byte
instructions, and both bytes must appear in the program wherever the
instruction is used 2f may be 00 to FF does not matter.

When more than one input or output port is required in a

system, the port address is decoded to generate device select pulses
for each input and output port. The simplest form of decoding is the
linear selection methods. This requires the smallest amount of logic
but can only be used for eight or fewer input and eight or fewer output
ports. Here, one address bit is associated exclusively with each I/O
port and is logically combined with IO/ and or strobe,
delayed only by the propagation time of the device selection logics.
E.g. in fig A4 = 1 address bit select port 16.2f the strobe is

inverted and NANDed with A4 and IO/ an active low device select
pulse is generated. This pulse is connected to the active
low enable of a tri-state buffer and determines when the buffer drive
the bus.2f the IC tri-state buffer has multiple inputs, the internal logic
of the tri-state buffer itself may be sufficient, and no external gates
are required.

A disadvantage of linear selection is the possibility that a

programming error will damage the hardware.2f the port address is
not decoded properly, two or more input ports can drive the data bus
simultaneously. Suppose for, example, a particular design using
linear selection contains an input port 4 and an output port 8 selected
by address bit A2 and A3 respectively.2f a programming error results
in the use of an IN 12 instruction instead of an IN 8, execution causes
input ports 4 & 8 to be selected simultaneously and damaging the tri-
state buffers. When linear selection is used extra care must be taken
to ensure that two ports are not selected simultaneously.
 Since there are only eight unique address bit in the port
address, only eight input and eight output ports can be selected with
linear selection method. To select from a large number of I/O devices
requires decoding port addresses with exhaustive decoding the
maximum of device select pulses that can be generated is 512:256
associated with IN instructions, 256 with OUT instructions.

To generate more than one device select pulse, decodes are

used to decode the address bits.2f an applications requires four or
less a input and four or less sec output device select pulses, a 74/139
dual 1- of 4 decoder can be used. The active low enable of one of the
decodes is connected to the I/ strobe and the select inputs to
address bits A0 and A1 ,providing four input device select pulses All
four output remain high until the IO/ strobe occurs. The active low
strobe enables the decoder and an active low device select pulses
occurs at the output selected by A0 and A1 .the unselected output
remain high the active low enable of the other 1 of 4 decoder is
connected to strobe and select inputs to address bit A1 and
A0,thus providing four output device select pulses.
Because only the least signified two address bits are connected to
the decoder ;the most significant six port address bits in the second
byte of the instructions are dont cause the effect of these dont
causes is the generation of same device relied pulses by a number of
IN and OUT instruction with different address called FOLD BACK
ADRR
Decoders with both active low and active high enable inputs
provider even greater flexibility. The 74138(8205),is a 1-out of 8
binary decodes with two active low and one active high enable inputs.
When the required input combination is not applied to the enables, all
output of the decoder are high, regardless of the select or address
input value. When 8205, the or strobe is connected to one of
the active low enables, the second input may be grouped and the
signal is connected to the active high enable this arrangement
requires no additional logic to generate an or I/ because
generation is accomplished by the internal enable gating of the 8205.
Lecture-12
Interfacing I/O Devices
Example: 1
Interface 8-toggle switches is with the using isolated I/O address
AOH, the requires connection is shown in fig-5,

Switch open logical 1-4

Switch closed logical 0-2
Whenever. . intends an 8-bits to be inputted from this input device,
it jest implements the instruction IN AOH, this type of inputting data
from the input device is known as CPO imitated unconditional I/O
transfer ,
Example 2:
This decoding circuit of example contest of logic garter because have
used a single port address AOH, to identify this input device there is
no reason way we have allocate only one PORT address to on input
device if many port address are vacant, we can simplify the decoding
circuitry greatly by allocator m sce than one port address to the Sam
device provided the user lemons that these addresses are a lactated
to the Sam device and shall not be used anywhere to refer to any
other input device.
Let us suppers in this example we have allocated shall the 16 port
address AOH to AFH to the same input device the escort address A!
H to AP h allocated to the same device are k name as FOLD BACK
ADDRESS once AOH to AP this allocated to this device, there
address should never be allocated to any other device this is uses
responsibility.
By using address like this we have made the laver order 4-bit
redundant there are decoding circuitry shall be as shown in fig-6,
 P inputs an 8-bit data whenever squired through CPU initiated un
additional I/O structure using IN PCRT structure & any one of the
port addresses allocated to this input device.

Example 3:
In example 1 & 2 we have used SSI chips for obtaining the
PORT select signal, we can also use MSI chips to simplify the
decoding circuitry fig-9 gives the decoding circuitry for inputting 8-bit
data from 8-toggle switches involutes I/O, PORT address allocated
body AC to AF it with ACH as primary address and AF H as foil back
address, we have used 8205 (3 fine to 8-bit line decoder.
The advantage of fig-7 can be realized when we have more than one
port to select because a maxm of 8 chip select signals, can be
generated using the same decoding circuitry of fig-7.

Lecture-36
Memory Mapped I/O :
In this cases the I/O devices are not given separate addresses
other than memory i.e. 0000 to FFFF.(64k).but part of the space is
reserved for I/O devices. The advantage is any instruction that
references memory can also transfer data between an I/O device and
the ,as long as the I/O port is assigned to the memory address
space rather than to the I/O address space. The register associated
with the I/O port is simply treated as memory location register.
Consider an example in which address bit A15 designates
whether instructions reference memory or an I/O device.2f A15= 0, a
memory register is addressed; If A15= 1, than a memory mapped I/O
device is address .this assignment elevates the first 32kbytess of
memory address space to memory and second 32k to memory
mapped I/O devices. External logic generates devices select pulses
for memory mapped I/O only when = 0, the appropriate
address is on the address low and a or strobe occurs.
Input and output transfer using memory mapped I/O are not
limited to the accumulator. For example, same of 8085 A instructions
that can be used for input from memory mapped I/O ports.
MOV r, m move the connects of input port whose address is
available in (H,L) reg pair to any internal register.
LDA addr load the acc with the content of the input port whose
address is available as a second and third byte of the instruction.
Other instructions include, ANA M, ADD M, 1HD add (input from two
ports and store the contents is reg pair (L) and (H) ADD M and ANA
M provide input data transfer and computation in a single instruction.
same instruction that out the data from memory mapped ports are
MOV M,r
STA addr
MVI M, data
SHLD addr
LHLD and SHLD carry out 16- bit I/O transfers with single instructions
which reduce program executive time considerably. The price paid for
this added capability is a reduction in directly addressable main
memory and the necessity of decoding a 16- bit rather than an 8-bit
address.
When a microprocessor puts out an address and generates a
control strobe for a memory read, it has no way of determining
whether the device that responds with data is a memory device or an
I/O device; nor does it care. If only requires that the devices that
respond does so with in the allowable access time or uses the
READY line to request a sufficient number of WAIT states. The some
of true when a executives a write to memory.2f supplies an
address data, and a write strobe and continues its operations,
external logic determines whether memory, I/O or anything at all
receives the data transferred.

Example- 1:
In all the examples discussed in chapter 34, we have interfaced, an
I/O device using isolated I/O structure. Now let is interface the same
device using memory mapped I/O structure memory space allocated
for the memory location from A000 H to A0FF H has been allocated
to this device, the decoding circuitry using 8205 decoder and buffer is
shown in figure below:.

AO : 00 I/O = LOW; = LOW

AO : FF
1010 0000. Redundant bits
The following instruction sequence can be used to input an 8-bit data
from 8-toggle switches, when necessary:
a) LXI H, IPTSAO
MOV r, M
 b) On the other hand we can use LDA instruction using direct
addressing mode to input an 8-bit data
LDA IPTSAO
Note that whatever may be the memory reference instruction used for
inputting 8-bit data from fig 8, the page address ACH should be
maintained as higher order 8-bit while the lower order 8-bits are
redundant and can be anything from 00H to FF H.

Example-2:
We shall now take up a problem which involves ROM, RWM; input
devices
Design a CPU, PCB for a process control application which requires
the following,
1) 8085 A CPU whit 8212 latch.
2) 8k byte ROM consisting of two 4k byte 2732 ROMs.
3) 4k RWM consisting of two 6116 (each K x 8)
4) Two input devices connected through input ports.
5) Two output devices connected through two output ports.
6) A minimum of 32k byte memory space must be open for
further explain.
Use memory mapped I/O structure to design interfacing circuitry. Use
Fold back principles to simplify device circuitry,
2732 4 k 8 ROM 8K 8
6116 2 k 8 RWR 8K 8
Two Input Devices 8K
Two Output Devices 8K
The memory map for this problem is shown in figure.
A15A14A13A12 A11---- A0 Control Signals Address
0 0 0 0 0------0 CSROM0 0000H to 0FFFH
0 0 0 0 1------1
0 0 0 1 0------0 CSROM1 1000H to 1FFFH
0 0 0 1 1------1
0 0 1 0 0------0 CSRAM0 2000H to 2FFFH
0 0 1 0 1------1
0 0 1 1 0------0 CSRAM1 3000H to 3FFFH
0 0 1 1 1------1
0 1 0 0 0------0 IDSP1 4000H to 4FFFH
0 1 0 0 1------1
0 1 0 1 0------0 IDSP2 5000H to 5FFFH
0 1 0 1 1------1
0 1 1 0 0------0 ODSP1 6000H to 6FFFH
0 1 1 0 1------1
0 1 1 1 0------0 ODSP2 7000H to 7FFFH
0 1 1 1 1------1

Form above table we see that many control signals are to be

generated for proper to & from data transmission. Table also gives
the signals to be generated &the address on the address line for
these signals to become active low. Form the table at is obvious that
the MSB address digit consisting of 4 bit A15 A14 A13 A12 A11 decode
which of the control signal should become ACTIVE LOW. For
example should be com ACTIVE LOW whenever
A15A14A13A12 is 0000H. It should be HIGH otherwise. The table gives
address bit information for the corresponding control signal to
become ACTIVE LOW.
From this table the following points become clear,
1) For all these control signals, A15 bit should be a zero.
2) Since it is memory mapped, IO/A control signal should be LOW
to refer to these devices.
3) The 8 control signals depend open the 8 bit A14 A13 A12. 000 for
CSROMO to 001 for CSROM1, do this suggests as line to 8-line
decoder to be used for the decoding circuitry. INTEL 8205 is the
answer or the Texas instrument equivalent decider T4 LS138.
The complete interfacing circuitry using 3 line to 8- line decoder is
shown in figure.
Lecture-37
Unconditional parallel transfer of Information
An unconditional transfer is one in which an instruction transfer data
to or from an I/O port without determining whether the port is ready to
receive or transmit the data. The data transfer between CPU and an
I/O device is in parallel, a word at a time unconditional transfers
handle common information, status information, or other data
command information is transferred to external device from the to
control the operation of an I/O device. Status information is
transferred from an I/O device and is used by the to monitor the
state of the I/O device. Data is transferred in both directions and is
distinguished from command or status information by the manner in
which it is used by the
An example of an unconditional input data transfer is the input of data
from a set of manual switched. The assumes the switches are set
to their positions. An example of an unconditional output data transfer
is the transmissions of data from a does not ascertain. Whether
the display is ready to receive the data, it simply assumes the display
is ready.

Interfacing Output Display:

Common and simplest display device with IC logic is the light
emitting diodes (LED). LEDs are solid state devices p-n junctions
which emit light energy when stimulated by a low voltage dc. LEDs
are designed to emit light from ultraviolet to infrared. The most
efficient LED is in the visible spectrum and emits red light. It is most
commonly used for LED displays. The decimal digits & few alphabets
can be displayed using seven segments LED. These displays use an
LED for each segment and are represented in the form shown below.

The LEDs a, b, c, d, e, f, g are line segment LEDs while dp is a

decimal point LED. These 8 LED together can be connected in two
different from namely common cathode and common anode
configuration as shown in figure.
 The 8- LEDs can be directly driven from an output port or by a
decoder driver connected to an output port. Considering common
cathode configuration, let the LEDs connected to an output port to lit
any LED, (chip select signal) should be made low and
corresponding bit should be made high .eg, to display letter 5 the
data to be loaded in the register latch driver is 0110 1101 B or 6DH
and then is made low so that 5 is displayed similarly for common
anode configuration CS in ACTIVE HIGH signal. B.C.D to seven
segments & hex to seven segment decoder drivers are available for
driving seven segment displays for driving seven segment displays
(e.g. 7447, 7449).

Common anode configuration when a BCD code is sent to the

input of the 7447, it output lows on the segment required to display
the number represented by the BCD code. This circuit connection is
referred to as static display because current is being passed through
the display all time. Current limiting resistance as the value of the
resister can be calculated LED needs 20mA current & voltage drop is
about 1.6v. The output voltage for the 7447 is a maximum of 0.4v at
40mA. So assume that is about 0.2v and 20mA. The voltage across

the resistance is 5-1.6-0.2=3.2. The value of the resister is

=160 the voltage drop across the LED and 7447 are not exactly
predicable and the exact current through the LED is not critical as
long as we dont exceed its maximum rating. Therefore a standard
value of 150 is reasonable.
The circuit designed is suitable for driving just one or two LED
digits. However there are problems it we want to display 6 digits. The
first problem is power consumption for worst case calculation,
assume all six digits are display 8 so all seven segment are lit. Seven
augment times 20mA per segment gives a current of 140mA per digit
multiplying these 6 diets given a total current do 840mA. For the
static approach is that each display digit required a separate 7447
decode each of which uses another 12Ma. Therefore, the current
required by the decoders and LED display might be several times the
current required by the rest of the circuitry in the instrument.
To solve this problem of static display approach, we use a
multiplexing technique. The circuit for six digit only one 7447 bias
used and the segment output of the 7447 are the digits. The chip
select of all six digits are connected to six PNP transistors. The PNP
transistor in series with common anode is driven from another port.
The p first output the BCD code for digit 1 to 7447. The 7447
output the corresponding seven segment code on the segment bus
lines. The transistor connect to digit 1 is then turned on by outputting
a low to that pit of port A (a low turns on a PNP transistor). All other
bits are made high so other digits are in off state. After few ms digit 1
is turned off by outputting all high to port A. The BCD code for digit 2
is then input to the 7447 on port B and a word to turn on digit 2 is
output on port A. this process is repeated until all of the digits have
last digit in the display bus been turned ON , the cycle is repeated
starting with first digit. Each digit is turned or ON refreshed at a
frequency called the refresh rate. If a digit is refreshed at higher rate
then it appears to the human eye to be constantly ON. The minimum
practical refresh rate is unusually 100Hz for N digits refreshed at the
max ON time tD for each digit is
=
Let the digits to be displayed are stored in memory location starting
from DIGDI5 5.

The software for display such is:

** LXIH, DIDIS 5
MVI Bxx011111
MVIC, 06(IFH)
* XRA A
CMA
OUT port A
MOV A,M
OUT port B
MOV A,B
OUT PORT A
RAR
MOV,A
DCR H
CALL MS DELAY
DCR C
JNZ *
 JMP * *
A disadvantage of the software multi playing approach is that it puts
an additional burden an the CPU. Also, if CPU gets involved in doing
sane length task which cannot be interrupted to refresh the display,
only one digit of the display will be left on.
Lecture-38
CPU Initiated Conditional I/O Transfer
In conditional data transfer, execution of the I/O instruction
transferring the data is conditioned on the I/O device being ready for
the data transfer readiness is determined by an unconditional transfer
of information from the I/O device to the that proceeds state of the
I/O device hardware often 1 or 2 indicate the status of an I/O device.
A single bit of status information indicates when a single output port
has information available for input or when a single output port is
ready to receive information. The software that tests the status flag
increases the time associated with the I/O operation; the additional
time is the I/O overhead.

Consider, for example an input device that has data available at

input port 1(DATA) for transmission to a . To indicate availability
the input device sets a flag bit 7 of input port 0(STATUS).the use of
flags in controlling conditional therefore is referred to as handshaking
with programmed I/O ,it is the only way of knowing when new data is
available for input to the

PIN: IN STATU ; input status byte

ORA A ; set flags.
JP PIN ; check data available status bit (bit7),
; if data is not available, wait
IN DATA ;If data is available, input data clear data
; available flag.
MOV M, A ; transfer data to memory pointer
DCR B ; Increment counter
JNZ PIN ; Back to pin if more data is to be input
RET

To determine availability of data for inputs, the microprocessor

periodically input the status word at input port 0 and tests bit 7. If bit 7
is 1, data is available & an instruction input it from port 1. The input
device selects strobe that enables the data from port & also resets
the data available flag.
The frequency with which the status flag is checked determines
the minimum length of time it takes to transfer the data. An input
subroutine executes a tight loop to check the status flag. The
subroutine given above assumes that the number of bytes of data to
be transferred is in B and that (H, L) points to the starting address of
the data buffer in memory when the subroutine is called.
This problem is best illustrated by taking on example the example to
be considered is a direct interfacing of a tri state ADC the block
diagram is shown in fig-2

SOC start of conversion

EOC end of conversion
Successive approximation method of ADC is thy fast; in fig-2 and (7)
is analog input signal whose digital equivalent is desired. The 8-bit
digital equivalent is obtained internally as and when necessary by
(say) successive approximation. Principle and is made available at
the output terminals D7 D6 .when the chip enable signal is
ACTIVE LOW. when is HIGH, the D7 D6 terminals are tri stated
this ADC does not produce the digital equivalent always but it
requires, a start pulse designated START of CONVECSION, (SOC)
for an system SOC is sees and goes HIGH again this LOW to HIGH
transition an of SOC signal start the conversion process. One the
process starts the digital equivalent is not available instant an easily.
It take time, and the time taken to get the digital equivalent, once the
conversion starts is known as the conversion time. Normally for a
successive approximation ACD chip the conversion time TC is
around 100 sacs. It is assumed that the
Input is not deranging during this conversion time this is true in the
core of slow entangling, analog signals. In the case of fast changing,
analog input signal Va (+) of fig-2 shall be the output of a sample
and hold escort. Sample and hold escort is also available in the form
of an I.C chip. The external world must be told that the ADC is buy in
conversion once the conversion starts, ADC issues a control signal
output known as END OF CONVERSION signal (EOC) for this
purpose. EOC is normally LOW and goes ACTIVE HIGH when
conversion starts. It remains HIGH as long as the conversion is not
over and goes LOW again when the conversion is complete. The
complete timing signal are shown in fig-3
We shall use the timing signals shown in fig-3, to interface the ADC of
fig-2 directly to microprocessor.

Let as interface the given ADC through the C.P.U. initiated

polled I/O transfer. Let the memory spaced allocated to this device
page COH. It means that the complete memory space address
COOOH to CFFH is allocated to this device. Studding ig-2 and fig-3
we sec that there different control signals are to be generated at
appropriate times to read one byte of data from the given ADC. Let
use allocate the following locations, all falling written page COH to
generate these signals
1) SOC : CO X 2 H
2) EOC : CO X 1 H
3) : CO X 0 H
Having allocated the address we can now, drew the internal circuitry,
of given ADC of fig-2 for polled I/O transfer. Necessary interfacing
dig is shown in fig-4.
 A3 A2 A1 A0
X X 1 0 ------- SOC
X X 0 1 ------- EOC
X X 0 0 ------
Contents of accumulator are send to BDB during the operation
MONH, A. It is a fictitious write operation since it is used to generate
only a pulse and other device in not selected.
The producer to be followed to send one byte of data from the APC is
as follows:
1) Initiate the conversion by generality an SOC pulse this is
done by a fictitious write operation on to the address
COO2H.This is a fictitious write operation the control of BDB at
 this time is not written, anywhere but there operation is used
only to generate. SOC pulse. However fictitious write
operations are always performed to generate search pulses.
(Fictitious read operation is not performed to generate a pulse).
2) Having applied SOC pulse, should monitors, the EOC
signal continuously to find whether the conversion is complete.
This is done by the for fig-4 by reading from the memory
location. COOHH and clerking others. Do bit is zero.
3) It waits in step (o) continually monitoring the EOC signal AS
long as EOC is HIGH.
4) When EOC is from LOW a READ operation is performed
from the memory address COOOH to take in 8-bit of digital
equivalent of analog signal at that time the above process has
to be repeated for reading more than one sample of analog
signal.
The detailed flow chart for reading one byte of data from fig-4 through
polled I/O transfer is given in fig-5
The ALP corresponding to fig-5 is shown in fig-6
SOC EQU COO 2H
LXI H, SOC; (A, L) point to SOC
MOV M, A
DCR L
NEXT: MOV A, M
RRC
J C. NEXT
DCR L
MOV A, M

In the above discussions, we have interfaced the ADC directly & with
the bus. It is passable however to interface the ADC with the bus
through programmable peripheral interface support chip.
Lecture-39
INTERRUPT I/O TRANSFER

This is a device initiated p controlled I/O transfer. A p may be

communicating other time. In the case of CPU initiated polled I/O
transfer. Polling of I/O service request flags monopolizes a significant
amount of a microprocessor time. This reduces system through put
the total useful information processed or communicated during a
specified time period therefore, it is advantageous, in term of
increasing throughput as well as reducing program complexity, if an
I/O device demands service directly from the microprocessor.
Interrupts provide this capability essentially an interrupt is a
subroutine call initiated by external hardware device and is
asynchronous meaning it can be initiated at any time without
reference to the system clock however, the response to an interrupt is
directed or controlled by the p. A simple structure that allows a
single device to interrupt a microprocessor is shown fig.
 When an I/O device requires service, it sets its interrupt request
flip-flop. This flip-flop is functionally the same as the service request.
F/F except that instead of its output being connected to an input port,
it is connected to an interrupt pin of the microprocessor. Thus, the F/F
stores the I/O devices interrupt request until it is acknowledged by the
p

Since the interrupt request is asynchronous, it may occur at any

point in a programs execution. when an interrupt occurs, the
execution of the current instruction is completed, the interrupt is
acknowledged by the p, and the control is transferred to a
subroutine that services the interrupt .when the p responds to the
interrupt; the interrupt request F/F is cleared by a signal directly from
the p or by a device select pulse generated by the service
subroutine. To resume program execution at the proper point when
the I/O service subroutine is finished, the program counter is
automatically saved before control is transferred to the service
subroutine. The service subroutine saves the contents of any
registers it uses on the stack and restores the registers contents
before returning. The contents of the program counter, flag register,
accumulator, and general purpose registers together represent the
state of the microprocessor.
There are two types of interrupt input non-maskable and maskable.

When a logic signal is applied to a non maskable interrupt input, the

p is immediately interrupted. When a logic signal is applied to a
maskable interrupt input, the p is interrupted only if that particular
input is enabled maskable interrupts are enable or disabled under
program control.2f disabled an interrupt request is ignored by the p.
A non-maskable interrupt input can be masked externally by an
interrupt mask signal from an output port. The mask bit from an
output port shown in figure gates the interrupt signal. If an instruction
writes a 1 in the mask bit position, the interrupt is enabled if it writes a
0, it is disabled.
In response to an interrupt, the following operations occur:
1. The processing of amount instruction of the main program is
completed
2. An interrupt instruction cycle is executed during which the
program counter is saved and control is transferred to an
appropriate memory location.
3. The state of a p is saved.
4. 2f more than one I/O device is associated with the location
transferred to, the highest priority device requesting an interrupt
is identified.
5. A subroutine is executed which services the interruputi9ng I/O
this subroutine clears the interrupt service request F/F if it was
not cleared in step 2
6. The saved state of the p is restored
7. Control is returned to the instruction that follows the interrupted
instruction.
Each step requires a certain amount of time. The combined times for
a given p and external interrupt logic determine how quickly the p
responds to an I/O devices request for service.
Fig shows the timing involved in servicing the single interrupt.
 (1) Latency time
(2) Interrupt m/c cycle time or BIMC time
(3) Saved states
(4) Time taken to identify the device
(5) Actual servicing
(6) Restore states
(7) Return to previous procession of main program.

The time that elapses between the occurrence of the interrupt and the
beginning of the execution of the interrupt handling subroutine is the
response time, the sum of the times of steps (1) through (4)the
difference between the total time that the p is interrupted and the
service subroutine is referred to as overhead interrupt structures with
zero overhead allow greater throughput.

Latency time is the time between the occurrences of an

interrupt request the beginning of the interrupt m/c cycle
 As shown in fig, the interrupt signal must be valid for a time
greater or equal to the interrupt set up time tINs, before the falling
edge of CLK of the last state of the instruction cycle in order for the
next m/c cycle to be an interrupt m/c cycle. for the 8085 the minimum
value of tins is 160 n sec
If the interrupt becomes valid prcised, tins seconds before the
beginning of the next m/c cycle, than that cycle is an interrupt cycle
with a minimum latency time, t LATMIN=tins 2f ,however the interrupt
signal becomes valid just after this setup time, then it is not
responded to until after the next instruction is executed. the provides
a worst case latency time of
tLATMAX =160 ns + 18T.
This relationship assumes there are no WAIT and states in the
instruction cycle during which an interrupt request occurs. A further
assumption is, of course, that the interrupt is enabled when the
interrupt request occurs.
Lecture-40
8085 interrupt structure

There are five interrupt input TRAP,RST 75,SRT 65,RST 55

and IWTR. TRAP is a nonmaskable interrupt, that is, it cannot be
disabled by an instruction RST75,65,55 and INTR are maskable
interrupt i.e. they can be enabled or disabled by software. The 8085 A
interrupt structure is shown in fig.
INTE F/F :
When the power is ON for the first time, signal goes
Low.if resets the 8085.2f also resets the INTE F/F.so that the entire
interrupt structure is disabled. The INTE F/F can be SET or RESET
using instructions. When INTE F/F is reset, except for TRAR no other
interrupt signal can interrupt the p.

TRAP:
TRAP is a nonmaskable vectored interrupt.2f can interrupt the
p once the power is on. Most p interrupt input are level sensitive
however, some are edge sensitive and others are both edge and
level sensitive, the TRAP input is both edge sensitive and level
sensitive interrupt. 2f means that TRAP make a low to high trisection
and remain high until it is acknowledged. The positive edge of the
TRAP signal will set the D flip flop .because of the AND gate,
however the final TRAP also depends on a sustained high level
TRAP input. This is why the TRAP is both edge and level sensitive
this also avoids false triggering caused by noise and transients.

For example, suppose the 8085 is midway through an

instruction cycle with another s to completion 2f a 300 n sec noise
spike hits the TRAP input, it will edge triggered but not level trigger
the working on the current 8085 is still working on the TRAP input is
both edge and level sensitive the 8085 avoids responding top false
TRAPs.
 Since the TRAP input has the highest priority it is used for
catastrophic events such as power failure, partly errors, and other
events that require immediate attention. In the case of brief power
failure it may be possible to save critical data with parity errors, the
data may be resample or corrected before going on.
Whenever TRAP comes, p completes the current instruction,
pushes the program counter in the slack and branches to fixed
location 0054 H. once the 8085A p recognize a TRAP interrupts, it
will send a high TRAP ACKNWNLEDGE bit to the TRAP F/F ,thus
clears then F/F so that even of TRAP is high it is not recognize only if
it goes low, then high and remains high. The TRAP F/F is also
cleared when p is being reset during which goes low and
clears the F/F.

RST7.5, 6.5, &5.5:

These are maskable vectored interrupts. These interrupts can
be enabled or disabled through software. RST 7.5 has the highest
priority among these & RST 55 has the lowest priority.

RST 75 control signal input is rising edge sensitive interrupt

whenever LOW to HIGH instruction occurs, it can interrupt the p
D-F/F
.this LO to HI transaction is registered in second . The output of
this F/F is labelled I 7.5.whenever the other input are high the p
recognize this interrupt this request is remembered until (1).the 8085
A responds to the interrupt (when interrupt is acknowledged, it sends
a high RS77.5 ACKNOWLEDGE bit to the clear input this clears it for
future interrupts of D F/F.(2).or until the request is RESET by SIM
instruction (R 7.5 bit is made high through SIM instruction and the
F/F can be cleared).2f is for the user to make use pf these
facilities.(3).or until the p is being reset ie signal becomes
LOW whenever RST 7.5 is recognized, control is transferred to 003cH
RST 6.5 & 5.5 are also vectored masked interrupts and are HIGH
level sensitive interrupt control signal input. These are directly
connected to AND gate the signal at these inputs must be maintained
until the interrupt is acknowledged. Whenever RST 6.5 is recognized,
the control is transferred to 0034 H & whenever RST5.5 is
recognized, the control is transferred to 002CH.
The signals I7.5,6.5 & 5.5 are called pending interrupts .the
signal IE (bottom F/F) is called interrupt enable flag, it must be high to
active The AND gates, Also notice the M7.5,M6.5 & M5.5 signals,
they must be low to enable the AND gates.
e.g. to activate RST7.5 interrupt, I7.5 must be high, M7.5 must be low
and IE must be high.
The interrupt enable F/F can be set or reset through software then
F/F can be set using EI instruction. EI stands for enable interrupt
whenever EI is executed, it produces a high EI bit and sets the INTE
F/F and produces=a high IE output.
This f/F can be reset in three ways.
1). When the power is on for the first time or signal goes
low, it resets the INTE F/F so that that entire interrupt structure is
disabled. When INTE F/F is reset except for TRAP no other interrupt
can interrupt the p.
2).the INTE F/F can be reset using DI instruction. DI stands for
disable interrupt when executed it produces a high DI bit & clear the
INTE F/F
3).when the 8085 recognize an interrupt, it produces a high ANY
INTERRUPT ACKNOWLEDGE bit .this disables the interrupts.

Because the interrupts are automatically disabled by the ANY

INTERRUPT ACKNOWLEDGE bit programmer usually includes an
EI as the next to last instruction in the service subroutine. For
instance the last two instructions typically are
Subroutine: :
:
EI
RET
This subroutine cannot be interrupted (except by a TRAP) after
the EI is executed, the processing returns to the main program with
the interrupt system enabled.
M7.5, M 6.5 & M5.5 are mask F/F s these flip-flop are used
individually to mask the interrupts. where these F/Fs are set, then the
corresponding interrupt is masked (Q=1, =0) and the interrupt
control signal cannot interrupt the p .these mask F/Fs are SET to
during power ON by control signal going LOW these MASK
F/Fs can be individually and selectively clear to o through SIM
instruction. Mask set enable F/F is also set this (MSE) can also be
SET to 1 simultaneously using SIM instruction.
INTR:
INTR is a maskable interrupt. A HIGH level on this pin interrupt
the p.the interrupt signal input INTR is not affected by SIM
instruction only INTE F/F must be SET to 1 before this interrupt
comes. Thus, in 8085 we can write the LOGIC expression for the
LOGIC variable VALID INT.
VALID INT = TRAP + INTE,[INTR+R75. +RST 6.5. +RST
5.5. ]
Other than the F/F in the above, there is one more F/F in the p
called INTA F/F. this is used only for internal operation by the p
when first power is ON; their F/F is RESET by control
signal. Thereafter by the p, it always RESETs the INTE F/F and
then SETs the INTA F/F before further action.
Lecture-41
Interrupt I/O Transfer

Whenever any interrupt is recognized, it executes an interrupt

machine cycle. If the VALID INT is true due to either TRAP or RST
7.5, or RST 6.5 or RST 5.5 then the interrupt m/c cycle executed is
BUS IDLE m/c cycle of 6 states, during which the p initially
generates the operation code for a restart instruction with the
appropriate restart address.(eg 0024 H for TRAP)this OP code is
loaded in to the instruction register for execution the PC is not
increment during BI and thus contains the one address of the
instruction following the one being executed when the interrupt
occurs. The action of this internally generates instruction is as
follows;

RST (internal)
M [(SP)-1] (PCH)
M [(SP)-2] (PCL)
(SP) (SP)-2
(PC) restart address

he BI m/c cycle is like an OFMC except the line remains

high. The operation code which is generally read in during OFMC is
instead generated internally during the BI machine cycle by the
microprocessor.
 fter an RST is executed, the RC contains the address of the
starting location for the subroutine that handles the interrupt. This
procedure for identifying the interrupting device and directly
transferring control to the starting location is called a vectored
interrupt .since only a few memory location separate the different
vector addresses, there is usually a jump instruction at the vector
address that transfer control to another memory location where the
actual service subroutine begins.
n the case of an INTR interrupt, the interrupt m/c cycle entered
is an interrupt Acknowledged m/c cycle INA m/c cycle is similar to
OFMC except that IO/ =1, instead of the p generates an
strobe during T2 and T3 state and the value of the program counter is
not incremented during INA. Thus the PC contains the address of the
instruction following the one being executed when instruction
occurred.
In response to the strobe, external logic place an
instruction OP code on the data bus this op code may be of either
CALL ADDR or RST-n. CALL ADDR is 3byte call instruction and
RST-n is 1-byte call CALL ADDR is placed by 8259(PIC).2f the CALL
ADDR instruction is jammed on the data bus by the external device
then three INTA m/c cycle will be executed. First one will be of 6
states during which time the operation code.CDH is placed on the
data bus and loaded into the IR and in the sub request two m/c
cycles. Each of 3-states the lower order 8-bits of the address and the
higher order 8-bits are placed on the data bus and than stored in and
W registers, respectively. This addr being the starting address of the
service subroutine. So save the return address two more MWKMC
are executed. Each of 3states and the return address from PC is
saved at the top of stack.
When the OP code3 placed on the data bus is RST-n than only one
m/c is executed of 6 states.the restart instruction aRST n has
variation from 0 to 7.
RST (internal)
[(SP)-1] (PCH) .
M [(SP)-2] (PCL)
(SP) (SP)-2
(PC) 8xn
This instruction is essentially the same as the previously mentioned
internal restart, except for the restart address, and the fact that it is
generated by external hardware. Restart has the following bit pattern,
frequently referred to 11NNN111
as the restart or interrupt vector.

Where n=NNN is a 3 bit binary number. when this instruction is

executed the program counter is save on the stack, thus save the
return address and control is transferred to a location with an address
which is 8 times NNN, thus facilitating branch to any one of eight
fixed addresses 00, 08, 10,20,28,30 or 3.84 depending on the value
of NNN these addresses are referred to as restart location, 0, 1,
2.......7.
External logic control a tri-state buffer with the signal in order to
place a restart vector onto the data bus. 2f fig a single I/O device is
connected to the interrupt structure.the output of their interrupt
request F/F is directly connected to the INTR interrupt pin of the
microprocessor. The instruction RST-n can be selected by the 3-
toggle switches NNN (000 to 111) whenever the external input device
is ready to send the pulse of very short duration. This sets the
interrupt request F/F and the INTR signal becomes active then, the
completes execution of the current instruction and then initiates an
interrupt acknowledged m/c cycle. During this cycle, then internal
INTE F/F is cleared, disability further interrupt from affecting the
.the signal that is generated enables the three state buffer
and the RST n instruction code is placed on the data bus also
clears the interrupt request flip-flop.the inputs the restart vector,
saves the program counter and branches to desired memory location
JH subroutine that starts at location services the I/O devices.
Example:
Let us interface ADC in interrupt mode. The EOC, SOC, OE pulses
are as shown below.

The ADC is interfaced to 8085 through port as shown fig.

RST 7.5 interrupt is used. In the main program SOC pulse is

issued.(LO HI . RST7.5 interrupt is unmasked and interrupt
structure is enabled before SOC pulse is issued. The microprocessor
enters into the halt state. When EOC pulse comes the RS7.5 interrupt
becomes active and then microprocessor jump to ISS ie PC is loaded
with 003CH addr. In the subroutine the OE signal is issued and data is
near via port 00.
Lecture-42
INTEL 8255: (Programmable Peripheral Interface)

The 8255A is a general purpose programmable I/O device

designed for use with Intel microprocessors. It consists of three 8-bit
bidirectional I/O ports (24I/O lines) that can be configured to meet
different system I/O needs. The three ports are PORT A, PORT B &
PORT C. Port A contains one 8-bit output latch/buffer and one 8-bit
input buffer. Port B is same as PORT A or PORT B. However, PORT
C can be split into two parts PORT C lower (PC0-PC3) and PORT C
upper (PC7-PC4) by the control word. The three ports are divided in
two groups Group A (PORT A and upper PORT C) Group B (PORT B
and lower PORT C). The two groups can be programmed in three
different modes. In the first mode (mode 0), each group may be
programmed in either input mode or output mode (PORT A, PORT B,
PORT C lower, PORT C upper). In mode 1, the seconds mode, each
group may be programmed to have 8-lines of input or output (PORT
A or PORT B) of the remaining 4-lines (PORT C lower or PORT C
upper) 3-lines are used for hand shaking and interrupt control signals.
The third mode of operation (mode 2) is a bidirectional bus mode
which uses 8-line (PORT A only for a bidirectional bus and five lines
(PORT C upper 4 lines and borrowing one from other group) for
handshaking.
The 8255 is contained in a 40-pin package, whose pin out is
shown below:
 PIN Names

RESET Reset input

- Chip selected

- Read input

- Write input

A0 A1 Port Address

PA7 PA0 PORT A

PB7 PB0 PORT B

PC7 PC0 PORT C

VCC - +5v

GND - Ground
The block diagram is shown below:
Functional Description:
This support chip is a general purpose I/O component to interface
peripheral equipment to the microcomputer system bus. It is
programmed by the system software so that normally no external
logic is necessary to interface peripheral devices or structures.

Data Bus Buffer:

It is a tri-state 8-bit buffer used to interface the chip to the system
data bus. Data is transmitted or received by the buffer upon execution
of input or output instructions by the CPU. Control words and status
information are also transferred through the data bus buffer. The data
lines are connected to BDB of p.

Read/Write and logic control:

The function of this block is to control the internal operation of the
device and to control the transfer of data and control or status words.
It accepts inputs from the CPU address and control buses and in turn
issues command to both the control groups.

Chip Select:
A low on this input selects the chip and enables the communication
between the 8255 A & the CPU. It is connected to the output of
address decode circuitry to select the device when it (Read). A
low on this input enables the 8255 to send the data or status
information to the CPU on the data bus.
 (Write):
A low on this input pin enables the CPU to write data or control words
into the 8255 A.

A1, A0 port select:

These input signals, in conjunction with the and inputs,
control the selection of one of the three ports or the control word
registers. They are normally connected to the least significant bits of
the address bus (A0 and A1).
Following Table gives the basic operation,
A1 A0 Input operation

0 0 0 1 0 PORT A Data bus

0 1 0 1 0 PORT B Data bus
1 0 0 1 0 PORT C Data bus
Output operation
0 0 1 0 0 Data bus PORT A
0 1 1 0 0 Data bus PORT B
1 0 1 0 0 Data bus PORT C
1 1 1 0 0 Data bus control

All other states put data bus into tri-state/illegal condition.

RESET:
A high on this input pin clears the control register and all ports (A, B &
C) are initialized to input mode. This is connected to RESET OUT of
8255. This is done to prevent destruction of circuitry connected to
port lines. If port lines are initialized as output after a power up or
reset, the port might try to output into the output of a device
connected to same inputs might destroy one or both of them.

PORTs A, B and C:
The 8255A contains three 8-bit ports (A, B and C). All can be
configured in a variety of functional characteristic by the system
software.
PORTA:
One 8-bit data output latch/buffer and one 8-bit data input latch.
PORT B:
One 8-bit data output latch/buffer and one 8-bit data input buffer.
PORT C:
One 8-bit data output latch/buffer and one 8-bit data input buffer (no
latch for input). This port can be divided into two 4-bit ports under the
mode control. Each 4-bit port contains a 4-bit latch and it can be used
for the control signal outputs and status signals inputs in conjunction
with ports A and B.
Group A & Group B control:
The functional configuration of each port is programmed by the
system software. The control words outputted by the CPU configure
the associated ports of the each of the two groups. Each control block
accepts command from Read/Write content logic receives control
words from the internal data bus and issues proper commands to its
associated ports.
Control Group A Port A & Port C upper
Control Group B Port B & Port C lower
The control word register can only be written into No read operation if
the control word register is allowed.

Operation Description:

Mode selection:
There are three basic modes of operation that can be selected by the
system software.
Mode 0: Basic Input/output
Mode 1: Strobes Input/output
Mode 2: Bi-direction bus.

When the reset input goes HIGH all poets are set to mode0 as input
which means all 24 lines are in high impedance state and can be
used as normal input. After the reset is removed the 8255A remains
in the input mode with no additional initialization. During the execution
of the program any of the other modes may be selected using a
single output instruction.
The modes for PORT A & PORT B can be separately defined, while
PORT C is divided into two portions as required by the PORT A and
PORT B definitions. The ports are thus divided into two groups Group
A & Group B. All the output register, including the status flip-flop will
be reset whenever the mode is changed. Modes of the two group
may be combined for any desired I/O operation e.g. Group A in mode
1 and group B in mode 0.
The basic mode definitions with bus interface and the mode definition
format are given in fig (a) & (b),
Lecture-43
Intel 8255A: Programming and Operating Modes

The format for the control word is,

Single bit/set/Reset feature:

Any of the right bits of PORT C can be set (High) or Reset
(Low) using a single OUTPUT instruction without affecting other bits.
This feature reduces software requirement in control based
application. When PORT C is being used as status /control for PORT
A or B, these bit can be set or reset by using the bit set/reset
operation just as if they were data output ports. The bit set/reset
format is given below:

An example for interfacing 8255A with CPU:

If 8255 is programmed in isolated I/O mapped manner, then IN &OUT
instructions are used for data transfer. When these instruction are
executed the 8085 A duplicates the PORT number on the address
bus and on the address data bus. Thus,
A15 A8 = AD7 AD0
This equation is called the duplication equation. Therefore PORT A is
read if
A15 A8 = AD7 AD0
XXXXXX 00
We may allocate any address to 8255. Let us assume A15- A11 bits to
be 00000 for generating the chip select signal along with IO/ = 1.
Therefore PORT A is accessed when address bus is having A15- A8
be 00000X00. Therefore, primary addr for PORT A is 00H and fold
back addr is 04H.The PORT B , PORT C and control register are
selected with address 01(05),02(06) fold back address. Normally
primary addresses are used.

Example:
Configure 8255 A in following I/O mode.
PORT A; Input; POET B: output
PCU output; PCL: Input
The control word with I/O modes as mode0 will be
1 00 1 00 012 = 91H
The control word will be outputted to control word register having add
03H.The relevant instruction will be follows:
MVI A, 91H
OUT 03H
For the above example, set bit PC0 High through bit set/reset. Note
PCU is configured in output mode. Only the bit of the PORT C,
configured in output mode can be set/reset. The relevant control word
will be 0XXX 110 1 = 0DH. The instructions to SET the port bit PC1
will be
MVI A, 0DH
OUT 03H

Operating Modes:

Mode0 (Basic Input/output)

This mode provides simple input/output operation for three ports.
After the mode is set, data is simple read from or written to the ports.
The mode0 functional definitions are,
1. Any poet can be input or output.
2. Two 8-bit ports and two 4-bit ports.
3. Outputs are latched.
4. Inputs are not latched.
5. 16 different 2 input/output configurations are possible.
6. Writing to the mode register resets any bits that are output.
Mode 1 (Strobed Input/Output Mode)
In this mode data can be transformed to and from 8255A with the use
of handshaking signals or strobes. In mode 1, PORT A & PORT B
use the lines of on PORT C to generate or accept these handshaking
signals. The mode 1 functional conditions are as follows.
1. Two groups Group A & Group B can be set independently.
2. Each group contains an 8-bit data port and a 4-bit control/data
port.
3. The 8-bit ports can be used as either input or output. Both input
& output are latched.
4. The 4-bit port is used for control & status of the 8-bit data port.

Strobes Input Mode:

Fig illustrates an 8255 set up with Group A & Group B both in input
strobes mode i.e. Mode1.
Input control signal definitions:
The functions of the port c lines as determined by the mode are as
described below:
PORT C bit 4 (PC4) Input strobe is pulsed LOW the data
prevented to the PORT A lines is latched into PORT A latch.
PC5: IBF A
Input buffer full PORT A. This line goes HIGH after the data is strobes
into port A by the signal. The bit becomes LOW by the using
edge of the input ie when CPU reads data from PORT D. Their
signal is used to identify when data can be written into PORT A by an
external device.
PC3: INTRA
Interrupt request PORT A. A high on this output can be used to
interrupt the CPU when an input device is requesting service. This
signal will go HIGH after IBFA line goes HIGH; is HIGH and
interview interrupt enable is set. The interrupt enables is controlled by
the bit set/reset of port C bit 4 (PC4). When this signal is set, INTR
will follow INTA. If the bit reset, INTRA will always be low. INTRA can
therefore be used as a mask able interrupt to the CPU to indicate a
data transferred into port A.
PC2 Input strobe for PORT B.
PC1 Input buffer full port B.
PC0 INTR B Interrupt request PORT B.
Interrupt enable bit is set by PC2
In case PC4/PC2 bit is reset, the concerned interrupt will be disabled.
PORT C bits 6&7 are not used as control or status lines and therefore
they can be used as either input or output bit 3 of the control word
determines whether these lines are input or output.
The control word to program PORT A & B in strobed input mode is
(1 0 11 1 1 1 X) 2 =BAH
 Fig shows the timing diagram under strobed input mode. The
pay device that is inputting the data puts the data at PORT A (or
PORT B) pins and then sends a low strobe to indicate to the 8255
that data is available. This loads the data into the concerned input
port buffer. The 8255A acknowledges receiving the data by sending
IBF HIGH back to the peripheral device. When the externally
generated strobe signal goes back to HIGH, the INTR is set high
(provided, if the INTE f/f was initially set to enable the interrupts). This
INTR signal interrupts the CPU (provided the concerned interrupt of
8085 been unmasked earlier). The 8085 CPU when ready, reads
(input) the data into assumable by generating a low . The INTR is
reset to low disabling the interrupt at the start of low . The IBF is
reset to low at the instant of going high again.
Lecture-44
Strobed output mode
Fig illustrate on 8255 set up with both port A & B as mode1 output.
The mode word to set up this condition is also given in the figure.

Output control definitions:

The functions of the PORT C lines as determined by the mode are
described below.
PC7 :
Output buffer full PORT A when data is written into port A by the
CPU, this signal goes low to indicate that data is available at port A.
PC6 :
Acknowledge PORT A. When this signal goes low it indicates that an
external device has accepted the data that has written output A. This
signal going low, will result the signal back HIGH.
PC5 INRA:
Interrupt request PORT A. This bit is set HIGH when goes
HIGH after a data transfer an d if its interrupt enable PORT C bit
when set. This signal can used as a CPU interrupt to indicate that
been accepted by an external device. This means that the CPU can
now load the next output word into port A.
PC1 output buffer full PORT B.
PC2 Acknowledge request PORT B.
PC0 INTRB interrupt request PORT B.
The internal INTE f/f is set by PC2.
PORT C bits 4&5 are not used as control or status lines and therefore
they can be used as either input or output. Their direction is
determined by bit 3 of the control word.

The basic output timing diagram is a shown in fig. Whenever 8255 is

programmed in mode 1 (output) the INTR signal goes HIGH if internal
INTE f/f is set be the corresponding bit. If CPU interrupt is enabled, it
interrupt the . The CPU, which has been interrupted by INTR
interrupt, writes (output) the data to port A or B; this setting the
corresponding line to go low, indicating that data is available. It
also reset the INTR line. When the external device has read the data,
it acknowledges it by sending low. The trailing edge of
causes to go HIGH. The empty output buffer ( high)
together with high and high reinitiates the INTR (
INTR=high) and the complete process is recycled. When CPU
accepts these in the OBF the can also by the CPU. If it is high the
buffer is empty and of data can be written to 8255.
Data transfer from system 1 to another system 2 is possible
through through 8255 ports programmed in strobed mode. The two
systems, each having 8255 can be connected as shown in fig. below:

The output and input ports of the two systems, acting as data lines,
are connected. The OBF of system 1 is connected to STB of system
2. The IBF of system 2 is connected to ACK of system 1 through
inverter. The interrupt outputs are connected to any interrupt of the
system. Here, they are connected to RST7.5.
The flow charts for data transfer in this manner are given below:
The waveforms for during data transfer are shown in figure below:
Lecture-45

Mode 2: (Strobed Bidirectional bus I/O)

This functional configuration provides means for communicating with
a peripheral device on a single 8-bit data bus for both transmitting
and receiving data control and status lines (hg and shake signal) are
provided to handily the flows of data on the I/O bus. Interrupt
generation and enable/ disable functions are also available. The
mode2 functional definitions are as follows:
1. Used by Group A only/
2. An 8-bit bidirectional I/O port (PORT B) and a 5-bit control port
(PORTC).
3. Both input & outputs are latched.
4. The 5-bits of PORT C are used for control and status of PORT
A.
5. PORT B is available for either mode 0 or mode 1 operation.
Fig shows an 8255 set up with PORT A on mode 2,
Control signal definitions:
The functions of PORT C as determined by mode 2 are shown below.

OUTPUT operation
PC7: output buffer full PORT A.
The output will go low to indicate that the CPU has written data
lim
out to specified port. The will be set by the rising edge of
input and reset by input being low.
PC7: Acknowledge port A
A low on this input informs the 8255, the data from port A has been
accepted. The difference between in mode 1& mode 2 is that
in mode 2 the output of the PORT A is normally in a tri-state
condition, so the signal enables the output buffer of PORT A in
addition to indicating that the external device has accepted the PORT
A data.
INTE F/F 1:
The interrupt enable INTE f/f associated with OBF. It is controlled by
bit set/reset of PC6.

Input operation:
PC4:
Input strobe for PORT A. A low on this input loads data into the input
latch.
PC5: IBFA
Input is full PORT A. A high in this output indicate that data has been
loaded into the input latch.
INTEL 2:
(The interrupt enable INTE f/f associated with IBF). It is controlled by
bit set/reset of PC4.
PC3 INTRA: Interrupt request port A
A high on this output can be used to interrupt the CPU for both input
output operations. When PC6 is set, this signal indicates that the data
written into port A by the CPU has been accepted by the external
device. When PC4 is set this signal indicates that the data has been
written into PORT A by an external device. By proper control of
PC4&PC6 bits an interrupt driven bidirectional 8-bit data bus between
the CPU& a peripheral device or even another CPU can be
established.
The timing diagram is shown below:
Special mode combination consideration:
There are several combinations of modes when not all of the
bits in port C are used foe control as status. The remaining bits can
be used as follows:
If programmed as inputs. All the input lines can be accessed
during a normal PORT C read. If programmed as outputs. Bits is
upper (PC3-PC0) must be individually accessed using the bit
set/reset function. Bits in a lower (PC3-PC0) can be accessed using
the bit set/reset function or accessed as a three some by writing into
PORT C.
Reading PORT C status:
In mode 0 port C transfers data to or from the peripheral
device. When the 8255 is programmed to function in mode 1 or 2,
ports C generates or accept handshaking signals with the peripheral
device. Reading the contents of PORT C allows the programmer to
test or verify the status of each peripheral device and change the
program flow accordingly. There is no special instruction to read the
status information from port C. A normal read operation of PORT C is
executed to perform this function.
Mode 1 Status word
Input configuration
I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
Group A Group B
Output configuration
INTEA I/O I/O INTRA INTEB INTRB

Group A Group B

Mode 2 Status word

D7 D6 D5 D4 D3 D2 D1 D0
INTE1 IBFA INTE2 INTRA X X X

Group A Group B
Lecture-46
INTEL 8253: Programmable Timer

INTEL 8253 programmable Timer/ counter is a specially designed

chip for C applications which require timing and counting operation.
These timing and counting functions can be implemented through
software. eg. A C is required to execute N different tasks. Suppose
it is required after executing Task i. The software solution would be to
call a delay routine to count out a T seconds interval after Task i is
completed and then do Task j. In order to maintain the precision of
the delay, it will not be possible for R to execute any other task
during this interval. If there are more such tasks, then C will be busy
most of the time to execute the delay routines. If C has to perform
some other useful task during (calculation) then it is very difficult.
The other possible solution is use of external timer. The C may start
this timer after exactly the Task I then C is free to do something
else. The extern timer after a delay of task interrupts the P. The C
executes task j once it get this interrupt. Such external device is
called a programmable timer 8253. The Intel 8253 is a programmable
counter/timer chip designed for use as an Intel C peripheral. The
main uses of 8253 are as follows:
1). Interrupt a time sharing operating system at evenly spaced
intervals so that it can switch a program.
2). Programmable on shot generator
3). Serve as a programmable baud rate generator.
4). Measure time delays between external events
5). Count the number of times an event occurs.
6). Causes the processer to be interrupted after a programmed
number of external events have occurred.
7). Real time clock.
INTEL 8253 chip consists of three identical 16-bit timers. Each timer
may be programmed to operator in one of the sic modes,
independent of the mode of operation of the other two timers. The
timers are software programmable.
The maximum clock input to the timer is 2.6
The pin-configuration of 8253 is shown in fig.
The functional block diagram is shown below:

Functional description & Pin details:

Data Bus buffer:
The data bus buffer is bidirectional, 8-bit buffer and is used to
interface the 8253 to the system data bus. The operation of this buffer
is controlled by the chip select line ( ) which tells the 8253 that the
is trying to transfer information to or from it even though is part
of the READ/WRITE logic. Data is transmitted or received by the
buffer upon execution of INPUT instruction from CPU. The data bus
buffer has three basic functions,
(i). Programming the modes of 8253.
(ii). Loading the count value in times
(iii).Reading the count value from timers.
The data bus buffer is connected to using - pins which are
also bidirectional. The data transfer is through these pins. These pins
will be in high-impedance (or this state) condition until the 8253 is
selected by a LOW or . And either the read operation requested by
a LOW on the input or a write operation requested by the
input going LOW.
Read/ Write Logic:
It accepts inputs for the system control bus and in turn generation the
control signals for overall device operation. It is enabled or disabled
by so that no operation can occur to change the function unless
the device has been selected as the system logic.
:
The chip select input is used to enable the communicate between
8253 and the by means of data bus. A low an enables the data
bus buffers, while a high disables the buffer. The input does not
have any affect on the operation of three times once they have been
initialized. The normal configuration of a system employs an decode
logic which actives line, whenever a specific set of addresses that
correspond to 8253 appear on the address bus.
& :
The read ( ) and write pins central the direction of data transfer
on the 8-bit bus. When the input pin is low. Then CPU is inputting
data from 8253 in the form of counter value. When pins is low,
then CPU is sending data to 8253 in the form of mode information or
loading counters. The & should not both be low
simultaneously. When & pins are HIGH, the data bus buffer is
disabled.
A0 & A1:
These two input lines allow the to specify which one of the internal
register in the 8253 is going to be used for the data transfer. Fig
shows how these two lines are used to select either the control word
register or one of the 16-bit counters. Eg, if there is a 1 on both A0 &
A1, and a 0 an , then the is writing a control word to the control
word register. These two pins are usually connected to the address
bus lines of the same name (A0 & A1).
A1 A0 operation

0 1 0 0 0 Load counter 0
0 1 0 0 1 Load counter 1
0 1 0 1 0 Load counter 2
0 1 0 1 1 Write mode word
0 0 1 0 0 Read TM0
0 0 1 0 1 Read TM1
0 0 1 1 0 Read TM2
0 0 1 1 1 No- operation 3- state
1 X X X X Disable -- state
0 1 1 X X No- operation 3- state
Control word register:
It is selected when A0 and A1 re 11. It the accepts information from
the data bus buffer and stores it in a register. The information stored
in then register controls the operation mode of each counter,
selection of binary or BCD counting and the loading of each counting
and the loading of each count register. This register can be written
into, no read operation of this content is available.
Counters:
Each of the times has three pins associated with it. These are CLK
(CLK) the gate (GATE) and the output (OUT).
CLK:
This clock input pin provides 16-bit times with the signal to causes the
times to decrement maxm clock input is 2.6MHz. Note that the
counters operate at the negative edge (H1 to L0) of this clock input. If
the signal on this pin is generated by a fixed fq oscillator then the
user has implemented a standard timer. If the input signal is a string
of randomly occurring pulses, then it is called implementation of a
counter.
GATE:
The gate input pin is used to initiate or enable counting. The exact
effect of the gate signal depends on which of the six modes of
operation is chosen.
OUTPUT:
The output pin provides an output from the timer. It actual use
depends on the mode of operation of the timer. The counter can be
read in the fly without inhibiting gate pulse or clock input.
Lecture-47
System Interface:
To interface 8253 with 8085, signal is to be generated.
Whenever , chip is selected and depending upon A1, A0 one of
the internal register is enabled. Since in isolated I/O mapped
interfacing, IN & OUT instructions are used, therefore address is
duplicated.
A15 - A8 = A7 - A0
Since A1 A0 select the internal register, these bits are not used to
generate . Again let us consider, A15 A11 be 000100. Therefore,
the address for timer 0 would be 0001x00 i.e either 10H or 14H
Similarly, counter 1 address = 11H or 15H
Counter 2 address = 12H or 16H
Command word register address = 13H or 17H

Using these addresses, interfacing circuit can be developed. The

interfacing circuit for 8253 is shown below:
The other possibility circuit may have IO/ combined with and
to generate and and these signals are then
connected to and . N this case IO/ need not be used for
generating .
Initialization:
Each of the three times of an 8253 can be individually programmed to
operate in six mode of operation. To initialize the times, writes a
command to control word register (one CW for each timer) to select
the operational parameters for the counter, that is, to specify which of
the six modes is to specify which of the six modes is to be used and
to select either binary or BCD decrementing and a code to specify
what operation that counter should perform.( load the count or read
the count ). When the power is first turned ON, 8253 is in undefined
states.
The control word format is shown below:
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RL1 RL0 M2 M1 M0 BCD

SC1 & SC0 These bits indicate whether the control word is
intended for counter , or .
SC1 SC0
0 0 Select counter 0
0 1 Select counter 1
1 0 Select counter 2
1 1 illegal
RL1, RL0:
Each of the 8253s counters has 16 bits. Since they are accessed via
a 8-bit data bus, two spate read or write operations are required to
completely access one counter. The 8253 allows the user a
substantial degree of freedom in this regard. The various choices are
decided by the values of RL1 and RL0 as shown below:
RL1 RL0
0 0 Counter latching operation
0 1 Read/ Load least significant byte only
1 0 Read/ Load most significant byte only
1 1 Read/ Load least significant byte first, then
most significant byte.

If RL1=RL0=0 is programmed, the four lower order bits ( M2, M1, M2,
BCD) are dont cares.

M2, M1, M0:

The mode of operation of the timer is selected by these three bits.
M2 M1 M0 Mode
0 0 0 Mode 0
0 0 1 Mode 1
X 1 0 Mode 2
X 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5
BCD:
A 0 in this bit command the selected counter to operate as a 16-bit
binary counter. The max value in binary is A 1 in this bit commands
the selected counter to operate as a 4-digit BCD. The max value in
BCD is 9999 the 16-bit counter are down counter. This means that
number in a counter will be decrement by each clock pulse. After the
control word reg has been programmed, the 8253 expects the count
to be located into the counter as specified in the RL bits of control
word. If more than one counter is to be programmed at one time, the
software may be written to write a control word to each counter and
then load the count into each and counter or each counter may be
programmed completely with a control word and the count value
before initializing the other counter.

Modes of operation:
Each of the three counters of 8253 can be programmed to operate in
six modes of operation to produce the desired output. Each timer
requires a clock input. The counters are negative edge triggered
down counter is whenever there is H1 L0 transition at the CLK
input, the count value is decremented by 1. The down counting is
controlled by the gate. The output pin can be used as an interrupt
request signal in the interrupt related modes.

Counter Loading:
The counter register is not loaded until the output value written is
followed by a rising edge and a following edge of the clock input to
the counter.
Mode0: Interrupt on terminal count
The output of the counter will go low when mode 0 has been
programmed. After the count is loaded the counter will remain low. If
the gate is low the counting is disabled the counter will start down
counting as soon as both bytes have been loaded and the gate is
mode HIGH. The output remains zero until count value reaches 0.
When the terminal count is reached (count value =0) the output will
go high and remains high until the selected counter is reloaded with
the mode or a new count value the mode is loaded. After the counter
has reached zero it will continue to count down from FFFF value but
will not change the output signal.
Inputting GATE=0; disables the counter. The count value stays frozen
if GATE goes low during counting. i.e. the counter stops counting .
Counting resumes from the from frozen value. When GATE returns to
1.
A+B =4
The count value may be changed at any instant even when the
counting operation is going on. Loading a new count value essentially
restart the counter with this new value. Note that if the counter value
to be loaded is 8 bits the effect of loading the new count value is
immediately. If the count value to be loaded is 16- bits the counter
stops counting after the first byte is loaded and resumes counting
only after the second byte is loaded.
Expect for mode0 in all other modes:
i) Retriggering of gate will cause the counter to reset to full count
and start down counting.
ii) The output will be high initially.
Lecture-48
Mode1 programmable one shot:
In this mode, counter acts as a retrigger able, programmable one
shot programming this mode sets the output high. Whenever there is
a rising edge at the gate, the counter starts down counting. The
output of the counter goes low and remains low during down
counting. When terminal count is reached, the output goes high.
Therefore, the output is low for the no. Of clock pulses whose value is
loaded in counter.

If a new count value is lowed while the output is low, it will not affect
the period of one shot pulse until the succeeding trigger. The one
shot is retriggerable, hence the output will remain low for the full
count value after any rising edge of the gate input.
Mode 2 Rate generator or divide by N counter:
This mode of operation provides a device by N- counter of the
counter is loaded initially with N count value. After loading the counter
and triggering it, the output will be high till the last one period (i.e. the
output will be high for (N-1) clock pulses and then it will go low for
one cycle of input clock and then return HIGH and the count value
(W) is automatically reloaded into the counter. Once again, the OUT
stay high for (N-1) clock pulses before going low for one clock pulse.
Thus the period from one output pulse to the next equal the number
of input in the count register. If the count register is reloaded between
the output pulses the present period will not be affected but the
subsequent period will reflect the new value. The gate input can be
used to control the counter. If the gate is low, the output will be HIGH
and no counting will be performed. When GATE input goes L0 H1,
the counter will start counting from the initial value and GATE=1,
enables counting. Thus this gate can be used by external hardware to
synchronize the counting.

Mode 3 Square Wave Generator:

This mode is similar to mode 2 except that the output signals will be
a square wave shape (HIGH & LOW foe equal times). This is
accomplished internally by decrementing the counter by two on the
falling edge of each pulse and then complementing the signal. If the
count value loaded was an Del, then the output signal will be HIGH
for (N+1)/2 counter and low. For (N+1)/2 counter. Thus In fact the first
clock decrement will has 1 and subsequent clock pulses by 2 an old
value will introduce a small amount of asymmetry into the waveform.
The rising edge of the gate will initiate the counting and the counting
and the output will continue as long as the gate is HIGH.
Mode 4: Software triggered strobe:
After the mode is set, the output will be high. In this case GATE=1,
enables the counting and gate 0, disables counting. As the new count
value is loaded in the counter the counter starts down counting. Once
the terminal count is reached, OUT goes LOW for one clock pulse
and then return to HIGH. This output pulse may be used as a strobe
in a particular application. Note that in this mode the generation of the
strobe signal at the out is triggered by the act of writing the count
value into the counter. This is the reason why this mode is referred to
be software triggered.
GATE=1:
If the count value is reloaded during down counting, the new count
will be loaded on the next CLK pulse. The count will be inhibited
when the gate input is low.

Mode 5: hardware triggered strobe

He output of the counter goes HIGH when programmed. In this mode,
the counting starts at the rising edge of the gate signal. The output
will go low. When counter reaches zero, and remains LOW for one
input clock period. The counter is retriggerable by activating the
trigger line before the terminal count has been reached. The rising
edge of the gate will causes the counter to be reloaded with the count
value and counting to start again.
 Note, unlike mode 4, the trigger comes from the hardware i.e. L0
H1 edge of GATE, that is why it is called hardware triggered strobe.
The functions of gate input in each mode of operation are given in
table.
Signal Status/ Zero or Rising High
Mode going low
0,4 Disable counting ........ Enable
counting
1,4 ....... Initiates counting ..............
Reset output after
the next clock
2,3 Disable counting Initiates counting Enable
sets output counting
immediately high
5 ........... Initiates counting ...............
Lecture-50
Reading the counter:
When the counter is active, it is often desirable to read. The
current value of the timer. This is complicated on the 8253 because a
16-bit number must be read using a 8-bit data bus. This means the
must read the 16-bit is two separate bytes. Trying to read the
timers as it is in the process of counting down can often yidd
erroneous results. E.g. If the timer had a value of 2000 when the first
byte of 00 was read (the least significant byte is read first), then the
timer is decrement to 1FFF, and if the second byte was then read, it
would have a value of 1F (the most significant byte of the current
counter contents). This would make the user think that the timer
contained a value of 1F00 instead of 2000 or 1FFF, which is a
considerable error.
There are two methods to read the value (content) of the
counter during down counting. In the first method, the selected
counter must be inhibited either by controlling the gate input or
inhibiting clock input. The counter stop counting and then correct
value can be read.
The 8253 provides a special READ operation (read on the fly)
that transfers the contents of the counter into a temporary storage
and lets the to read the data from the register. The timer continues
to count down. To latch the current counter value a special mode
control word is issued to the timer. The control word for latch is
shown below. It uses only from MSB of the control word rest we dont
cares. Bits 7&6 (SC1&SC0) selects the counter to be read and bits
and 4 (RL1&RL0) are set to 00 to indicate a latching instruction. After
the count has been latched, either or both of the bytes can be read
using I/O read instructions. Note that it is mandatory to do the entire
read operation as specified by the RL1&RL0 bits of the original mode
set command. The counter latching command must be issued every
time the wants to first latch the counter contents and then read it.
If the 8253 is in mode 3, it counts down by 2; in all other modes the
count decrements. Reading the count in mode 3 can give an
ambiguous reading. Thus mode 3 should be used for generating
square waves only and not for counting.
SC1 SC0 RL1 RL0 X X X X

Example:
Configures timer / counter No.1 in mode 0 and load it with 2 msec
period at 1.5MHz clock frequency.
2ms at 1.5MHz = 3000 cycles
= 0BBS H
Therefore, CW will be
(01 11 00 00)2 = 70 H
The necessary instructions for loading the count value are
MVI A, 70
OUT 13
MVI A, 08
OUT 11
MVI A, 0B
OUT 11
Read the counter 1 on the fly and store the value in (B, C) pair
CW (01 00 XX XX) = 40H
The necessary statements are,
MVI A, 40H
OUT 13H
IN 11
MOV C. A
IN 11
MOV B, A
INTEL 8254:
This chip also consists of 3- 16-bit down counters. Each
counter is software in different modes. Each counter has a clock
input, a gate control input and an output. The maxm clock input is
10MHz. This chip is identified to 8253 in all respect (pin configuration
and modes of operation) except the read function.
All counter in an 8253/8254 have latches on their outputs.
Reading the counter means actually reading the data on the output of
these latches. These latches are normally enabled during counting so
that the latch outputs just follow the counter outputs. If we read, the
count value during counting, the count may change between reading
the LSB&MSb. There are three ways to read the count value.
The first is to stop the counting by inhibiting the clock signal or
making the gate input low with external hardware. The counting is
then stopped. There method has the disadvantages that it requires
external hardware.
The second way of reading a stable value from a counter is to
latch the current count with a counter latch command, and then read
the latched count. A counter is latched a control word to the control
register. A counter latch command is specified by making the RW1 &
RW0 bits both0. The SC1 & SC0 bits specify which counter we want
to latch. The lower 4 bits of the control word are dont cares. When a
counter latch command is sent, the latched count is held until it is
read. When the count is read from the latches, the counter outputs
return to following the counter outputs.
The third method of reading a stable count from a counter is to
latch the count with a read back command. This command is
available only in 8254, but not in 8253.
The read-back command allows the user to check the count
value, programmed mode, and current state of the out pin and Null
count flag of the selected counter. The command is written into the
control word register and has the format shown in fig,
D7 D6 D5 D4 D3 D2 D1 D0
1 1 CNT2 CNT1 CHT0 0

D5: 0 = Latch count of selected counter

D4: 0 = Latch status of selected counter
D3: 1 = Selected counter 2
D2: 1 = Selected counter 1
D1: 1 = Selected counter 0
D0: = Reserved for future expansion must be 0
The 1s in bits D7 and D6 identify this as a read back command word.
The command applies to the counters selected by setting their
corresponding bits D3, D2, D1 = 1.
 `The read back command may be used to latch multiple output
latches (OL) by setting bit D5 = 0 and selecting desired
counter (s). This single command is equivalent to several counter
latch commands, are for each counter latched. The advantage of their
control word is that one can latch one, two or three counters by
putting 1s in the appropriate bits. Each counters latched counter is
held until it is read. That counter is automatically unlatched when
read, but other counter remains latched until they are read. If multiple
count read back command are issued to the same counter without
reading the count, then all but the first are ignored ie the count which
will be read is the count at the time the first lead back command was
issued.
The read back command may also be used to latch status
information of selected counter (s) by setting bit D4 = 0.
Status must be latched to be read status of a counter is accessed by
a read from that counter. The counter status format is shown in fig,
D7 D6 D5 D4 D3 D2 D1 D0
OUTPUT NULL RW1 RW0 M2 M1 M0 BCD
COUNT

Bit D5 through D0 contains the counters programme mode

exactly as written in the last mode control word. OUTPUT bit D7
contains the current state of the output pin. This allows the used to
monitor the counters output via software, possibly eliminating same
hardware from a system.
Null count bit D6 indicates when the last count written to the
counter register (CR) has been loaded into the counting element (D6
= 1 Null count D6 = 0 count available for reading). The exact time this
happens depends on the mode of the counter and is described in the
mode definition but until the count is loaded into the counting element
it cant be read from the counter. If the count is latched or read before
this time, the count value will not reflect the new value just written.
The operation of the null count is shown below:
This action
A. Write the control word register causes NULL count = 1 (only word
will have its NULL COUNT set to 1. Null count bits of other counter
are unaffected).
B. Write to the count register Null count = 1 (If the counter is
programmed for two most significant byte null count goes to 1
when the second byte is written).
C. New count is loaded into CE. Null count = 0. If multiple status latch
operation of the counter (s) are performed without reading the
status, all but the first are ignored i.e. the status that will be read is
the status of the counter at time the first status read back
command was issued.
Both count and status of the selected counter (s) may be
latched simultaneously by setting both & bits D5. D5
= 0. If multiple count and/or status read back commands are issued
to the same counter (s) without any intervening reads all but the first
are ignored.
If both count & status of a counter are latched, the first read
operation of that counter will return latched status, regardless of
which was latched first. The next one or two reads (depending on
whether the counter is programmed for one or two bytes) return
latched count subsequent reads return unlatched count.

Lecture-50
Priority Interrupt Controller:
In general in any application the data transfer between CPU &
I/O devices is interrupt driven. The number of interrupts in any
application depends upon the requirement.
In reality, these interrupt are asynchronous, they do not occur
are at a time in an orderly fashion. Microprocessors have certain
priorities established for their various inputs. A priority interrupt
structure distinguishes among several devices simultaneously
requesting service and assures that the device with the highest
assigned priority is serviced first.
The five interrupt inputs have an internally established, fixed
multilevel priority structure. From highest to lowest they or TRAP,
RST7.5, RST6.5, RST5.5 and INTR. TRAP, since it is not mask able,
is usually reserved to handle catastrophic events such as power
failures. I/O devices are associated with the other four interrupt inputs
in such a way that the highest priority device is connected to RST7.5,
the next highest priority device to RST 6.5 and so on. Devices that
require the fastest response time or that interrupt the microprocessor
with greatest frequency are usually given the highest priority.
Once an interrupt occurs, the internal interrupt enable flip-flop,
INTE f/f, is automatically cleared, allowing no more interrupt until an
EI instruction is executed. However if for example, an RST7.5
interrupt occurs, and the service subroutine for that interrupt
subsequently enables the microprocessor interrupt features before its
completion, the microprocessor can be interrupted by a lower priority,
for instance, an RST5.5.
 Several I/O devices can be connected to a single
microprocessor interrupt input by ORing their interrupt request occurs
at such an input, the particular device requesting an interrupt must be
identified. For INTR of the 8085A, identification and transfer of control
to the starting address if the service subroutine are done in a
vectored manner for as many as eight devices. Each of the eight is
assigned a different interrupt vector in the RST n instruction. The
appropriate RST n instruction op code is placed on the data bus in
response to
 In fig, the restart instruction is generated with the aid of a
priority encoder that supplies the three bits, NNN of the interrupt
vector. An 8 line3 to 3 line priority encoder allows the highest priority
device with its interrupt request flag set, to generate NNN, and thus
be identified immediately.
An interrupt must be identified for INTR of the 8085A,
identification and transfer of control to the starting address of the
service subroutine are many in a vectored manner for as many eight
devices. Each of the eight is assigned a different interrupt vector in
the RST n instruction. The appropriate RST n instruction OP code is
placed on the data bus in response to , the I/O devices interrupt
request F/F outputs are ORed together and connected to the
interrupt input if fig. The restart instruction is generated with the aid of
priority encoder that supplies the three bits. NNN of the interrupt
vector. An 8 line to 3 line priority devices with its interrupt request flag
set-to generate NNN and thus be identified immediately.

The truth table for an 74148 priority encoder is shown in .there

are eight active low input to the priority encoder. When an input is
held low, the 3-bit code representing its complement appears at
2, 1, 0.when two or more inputs are active the output is the
complement of the input with the highest numerical value.
 Priority 74148 Input RST
Highest 7 0
6 1
5 2
4 3
3 4
2 5
1 6
Lowest 0 7

The D-type positive level triggered latch allows the input to the
priority latch allows the input to the priority encoder to follow the Q
outputs of the interrupt flags until an occurs. The signal
forces the latch output to retain the values that existed at the leading
edge of the , and enables the three state buffer, placing an RST
instruction on the data bus. The input this instruction on the rising
edge of and control is transferred to the location association
with the RSTn instruction.
The priority encoder establishes priority among interrupt that
occur simultaneously. That is, if one device sets its interrupt request
flag, causing an interrupt, and another device sets its flag before the
interrupt acknowledge ( occurs). The serviced the one
connected to the highest number input of the priority encoder.
The instruction RST0 transfers control the first memory
location, the same location used when an external reset is applied to
the system. Thus, RSTo is usually not used for interrupts. The priority
encoder establishes priority among interrupt that occur
simultaneously. That is, if one device sets it interrupt request flag,
causing an interrupt, and another device also sets its flag before the
interrupt acknowledge occurs. The device serviced is the one
connected to the highest number input of the priority encoder.
The INA m/c cycle automatically disables the INTE F/F so that
no other interrupts can occur until the one being processed is
completed. The interrupt request F/F of the device being serviced
must be cleared. is gated with 1- out of 8 decoder to clear the
appropriate F/F however a programmed pulse generated by each
device is service subroutine would have the same effect. The next to
last instruction in the service subroutine enables the interrupt, the last
instruction transfers control back to the instruction following the one
that was interrupted. The lower priority of the two interrupt request will
then cause another INA m/c cycle to occur. The low priority interrupt
will then be serviced.
Lecture-51
INTEL 8259A Programmable Interrupt Controller
The 8259A is a programmable interrupt controller designed to work
with Intel microprocessor 8080 A, 8085, 8086, 8088. The 8259 A
interrupt controller can
1) Handle eight interrupt inputs. This is equivalent to providing
eight interrupt pins on the processor in place of one INTR/INT
pin.
2) Vector an interrupt request anywhere in the memory map.
However, all the eight interrupt are spaced at the interval of
either four or eight location. This eliminates the major
drawback, 8085 interrupt, in which all interrupts are vectored to
memory location on page 00H.
3) Resolve eight levels of interrupt priorities in a variety of modes.
4) Mask each interrupt request individually.
5) Read the status of pending interrupts, in service interrupts, and
masked interrupts.
6) Be set up to accept either the level triggered or edge triggered
interrupt request.
7) Mine 8259 as can be cascade in a master slave configuration to
handle 64 interrupt inputs.

The 8259 A is contained in a 28-element in line package that requires

only a compatible with 8259. The main difference between the two is
that the 8259 A can be used with Intel 8086/8088 processor. It also
induces additional features such as level triggered mode, buffered
mode and automatic end of interrupt mode. The pin diagram and
interval block diagram is shown below:

The pins are defined as follows:

: Chip select
To access this chip, is made low. A LOW on this pin
enables & communication between the CPU and the 8259A.
This pin is connected to address bus through the decoder logic
circuits. INTA functions are independent of .
:
A low on this pin. When is low enables the 8259 A to accept
command words from CPU.
 :
A low on this pin when is low enables these 8259 A to release
status on to the data bus for the CPU. The status in dudes the
contents of IMR, ISR or TRR register or a priority level.
D7-D0:
Bidirectional data bus control status and interrupt in a this bus. This
bus is connected to BDB of 8085.
CAS0-CAS2:
Cascade lines: The CAS lines form a private 8259A bus to control a
multiple 8259A structure ie to identify a particular slave device. These
pins are outputs of a master 8259A and inputs for a slave 8259A.
/ : Salve program/enable buffer:
This is a dual function pin. It is used as an input to determine whether
the 8259A is to a master ( / = 1) or as a slave ( / = 0). It is
also used as an output to disable the data bus transceivers when
data are being transferred from the 8259A to the CPU. When in
buffered mode, it can be used as an output and when not in the
buffered mode it is used as an input.
INT:
This pin goes high whenever a valid interrupt request is asserted. It is
used to interrupt the CPU, thus it is connected to the CPUs interrupt
pin (INTR).
:
Interrupt: Acknowledge. This pin is used to enable 8259A interrupt
vector data on the data bus by a sequence of interrupt request pulses
issued by the CPU.
IR0-IR7:
Interrupt Requests: Asynchronous interrupt inputs. An interrupt
request is executed by raising an IR input (low to high), and holding it
high until it is acknowledged. (Edge triggered mode).or just by a high
level on an IR input (levels triggered mode).
A0:
A0 address line: This pin acts in conjunction with the , &
pins. It is used by the 8259A to send various command words from
the CPU and to read the status. If is connected to the CPU A0
address line. Two addresses must be reserved in the I/O address
space for each 8259 in the system.

Functional Description:

The 8259 A has eight interrupt request inputs, TR2 IR0. The 8259 A
uses its INT output to interrupt the 8085A via INTR pin. The 8259A
receives interrupt acknowledge pulses from the at its input.
Vector address used by the 8085 A to transfer control to the service
subroutine of the interrupting device, is provided by the 8259 A on the
data bus. The 8259A is a programmable device that must be
initialized by command words sent by the. After initialization the 8259
A mode of operation can be changed by operation command words
from the.
The descriptions of various blocks are,

Data bus buffer:

This 3- state, bidirectional 8-bit buffer is used to interface the 8259A

to the system data bus. Control words and status information are
transferred through the data bus buffer.

Read/Write & control logic:

The function of this block is to accept OUTPUT commands from the

CPU. It contains the initialization command word (ICW) register and
operation command word (OCW) register which store the various
control formats for device operation. This function block also allows
the status of 8159A to be transferred to the data bus.
Interrupt request register (IRR):

IRR stores all the interrupt inputs that are requesting service.
Basically, it keeps track of which interrupt inputs are asking for
service. If an interrupt input is unmasked, and has an interrupt signal
on it, then the corresponding bit in the IRR will be set.

Interrupt mask register (IMR):

The IMR is used to disable (Mask) or enable (Unmask) individual

interrupt inputs. Each bit in this register corresponds to the interrupt
input with the same number. The IMR operation on the IRR. Masking
of higher priority input will not affect the interrupt request lines of
lower priority. To unmask any interrupt the corresponding bit is set 0.

In service register (ISR):

The in service registers keeps tracks of which interrupt inputs are

currently being serviced. For each input that is currently being
serviced the corresponding bit will be set in the in service register.
Each of these 3-reg can be read as status reg.

Priority Resolver:

This logic block determines the priorities of the set in the IRR. The
highest priority is selected and strobed into the corresponding bit of
the ISR during pulse.

Cascade buffer/comparator:

This function blocks stores and compare the IDS of all 8259As in the
reg. The associated 3-I/O pins (CAS0-CAS2) are outputs when
8259A is used a master. Master and are inputs when 8259A is used
as a slave. As a master, the 8259A sends the ID of the interrupting
slave device onto the cas2-cas0. The slave thus selected will send its
pre-programmed subroutine address on to the data bus during the
next one or two successive pulses.
Lecture-52
Interrupt sequence:
The powerful features of the 8259A in a system are its
programmability and the interrupt routine address capability. It allows
direct or indirect jumping to the specific interrupt routine requested
without any polling of the interrupting device.
Before considering the details of programming the 8259A, the
sequence of events that occur in response to an interrupt request at
one of the IR inputs of an initialized 8259A are considered. The
sequence of events during an interrupt depends on the type of CPO
being used. The events occur as follows in 8085 system.
1) One (or more) of the interrupt request lines (IR0-IR7) is one
mate logic1 by devices requesting service. The corresponding
bits in the interrupt request register (IRR) is set i.e. when an
interrupt request has been received, it is first latched into the
IRR.
2) The priority resolver and control logic use information from the
ISR and IMR to determine if the should be interrupted. If so,
INT becomes logic 1.
3) If the 8085As INTR interrupt is enabled, the completes the
execution of the current instruction and then executes an
interrupt acknowledge, INA machine cycle. During the INA the
8085A acknowledges the interrupt with an pulses.
4) In response to the the 8259A sets the highest priority ISR,
bit and reset the corresponding IRR bit. The 8259A also places
 the CALL instruction op code CDH on the 8-bit data bus through
D7-D0 pins.
5) When the 8085A receives a CALL instruction OP code during
the INA m/c cycle, it generates two more INA m/c cycles.
During the second & a third are generated by the 8085A.
6) In response to the second pulses, the 8259A places the
low address of a pre-programmed subroutine address on the
data bus. The high address on the data bus in response to the
third pulses.
7) This completes the 3-byte CALL instruction released by the
8259A. If the 8259A is in AEOI (autocratic end of interrupt)
mode, the ISR bit is reset at the end of the third pulses.
Otherwise the ISR bit remains set until an appropriate EOI
command is issued by the 8085A at the end of interrupt service
subroutine.
8) The 8085A executes the CALL instruction by saving the PC
(return address) an the stack and transferring control to the pre-
programmed address.

The events occurring is an 8086 system are as follows:

1) The IRR latches the incoming interrupt request. After a bit in the
IRR is set to 1 it is compared with the corresponding mask bit in
the IMR. If the mask bit is 0, the request is passed on to the
priority resolver, but if it is 1, the request is blocked. When an
interrupt request is input to the priority resolver its priority is
examined and, if according to the current state of the priority
 resolver the interrupt is to be sent to the 86 CPU, the INT line is
activated. Assuming that the interrupt flag (IF) in the CPU is 1,
the CPU will enter its interrupt sequence at the completion of
the current instruction and issues on pulses.
4) Upon receiving an from the CPU, the IRR latches are
disabled so that the IRR will ignore further signals on the IR1-
IR0 lines. This state is maintained until the end of the second
pulses. Also, the first pulses will cause the
appropriate ISR bit to be set and the corresponding IRR bit to
be reset. The 8259A not drive the data bus during this cycle.
5) The CPU will then, initiate a second pulses. During this
pulse, the 8259A release an 8-bit pointer on to the data bus
where it is read by the CPU (interrupt byte).
6) This completes the interrupt cycle, in the AROI mode the ISR
bit is reset at the end of the second pulses. There wise,
the ISR bit remains set until an appropriate EOI command is
issued at the end of the interrupt subroutine. If no interrupt
request is present at the step 4of either sequence, (i.e. the
request was too short in duration). The 8259A will issue an
interrupt level 7. Both the vectoring bytes and the CAS lines
will look like an interrupt level 7 was requested.

Programming the 8259A:

It accepts two types of command words generated by the CPU. The
8259A is initialized by a sequence of initialization command words
(ICWS). The initialization command word formats are shown in fig.
When a byte is issued with A0=0 and bit 4 (D4) = 1, it is interrupted as
initialization command word 1, ICW1. ICW1 starts the initialization
sequence during which the following automatically occur.
a) The edge sense circuit is reset, which means that following
initialization, an interrupt request (IR) input must make a low to
high transition to generate an interrupt.
b) The interrupt mask register (IMR) is cleared.
c) IR7 input is assigned priority 7.
d) The slave mode address is set to 7.
e) Special mask mode is cleared and status read is set to IRR.

Initialization Control Word 1 (ICW1)

If ICW=0, then all functions selected in ICW4 are set to zero. This
puts the 8259A in the 80/85 mode, with no AEOI (automatic end of
interrupt), and non buffered operation. No ICW4 would then be sent
in their initialization sequence. For an 8086/8088 system their bit
must always be set to 1.Bit 1 (SNGL) indicates whether or not. The
8259A is cascade with other 8259As. If SNGL=1, only one 8259A is
in the interrupt system. In this case no ICW3 is needed. Bit 2 (ADI)
(CALL address interval) is used in 8080/85 system only and not in
8086. In 80/85 system, the 8 interrupts will generates CALL to 8
locations equally spaced in memory. The separation interval between
the eight vector addresses may be 4 or 8 bytes. Thus the 8 interrupt
routines will occupy a page of 32 or 64 bytes, respectively. The
desired interval is selected by bit 2 of ICW1.

If ADI=1 then interval = 4 and If ADI = 0 then interval = 8. The routine

address is 2 bytes long (A15-A0). When interval chosen is 4, A0-A4 are
automatically inserted by the 8259A as per table given below, while
A5-A15 are programmed externally.
A4 A3 A2 A1 A0 Interrupt
0 0 0 0 0 IRO
0 0 1 0 0 IR1
0 1 0 0 0 IR2
0 1 1 0 0 IR3
1 0 0 0 0 IR4
1 0 1 0 0 IR5
1 1 0 0 0 IR6
1 1 1 0 0 IR7
When the interval chosen is 8, A5-A0 are automatically inserted by the
8259A as per table given below while A6-A15 are programmed
externally.
A5 A4 A3 A2 A1 A0 Interrupt
0 0 0 0 0 0 IRO
0 0 1 0 0 0 IR1
0 1 0 0 0 0 IR2
0 1 1 0 0 0 IR3
1 0 0 0 0 0 IR4
1 0 1 0 0 0 IR5
1 1 0 0 0 0 IR6
1 1 1 0 0 0 IR7

The 8- byte interval will maintain compatibility with current software,

while the 4-byte interval is best for a compact jump table.
If the interval chosen is 4, then the values of address bits A5-A7 are
specified in ICW1. If the interval chosen is 8, the values of A6-A7 bits
are specified in ICW1.
In 8086 A15-A11 are inserted in the five most significant bits of the
vectoring byte and the 8259A sets the three least significant bits
according to the interrupt level.
A2 A1 A0 IRO

0 0 0 IR1

. . . .

. . . .

1 1 1 IR7
A10-A3 are ignored and ADI has no effected.
LTIM: If LTIM =1, then the 8259A will operate in the level interrupt
mode. If LTIM = 0, then the interrupt are edge triggered.

Initialization Control Word 2 (ICW2)

The format for ICW2 is shown below, It is issued to an address
having A0=1. (odd address)

A15/T2 A14/T6 A13/T5 A12/T4 A11/T3 A10 A9 A8

A15-A8 specify the higher byte addr of the interrupt for 80/85 system
only. For 8086, T7-T3 are used to specify the interrupt vector address.
Thus, an 8085A system using a single 8259A could be programmed
with only two ICWs; ICW1 & ICW2. eg. if
ICW1 = 0001 00102 and ICW2 = 0000 01002
with these initialization command words, the interrupt request inputs
are programmed for edge triggered mode. In addition, the 8259As
priority instruction would be operating in the fully rested mode i.e. IR0
having the highest priority.
Lecture-53
Initialization Control Word 3 ICW3:
This word is read only where there is mode than one 8259A in the
system and one cascading is used in which case SNGL=0. It will load
the 8-bit slave register.
The functions of this register are:
a) In the master mode (either when SP= 1 or in buffered mode
when M/S=1 in ICW4) a 1 is set for each slave in the system.
The master will then release byte 1 of the CALL sequence
(80/85 system only) and will enable the corresponding slave to
release bytes 2 and 3 through the address lines (In 86/88 only
two bytes). The format of ICW3 in this case is,
S7 S6 S5 S4 S3 S2 S1 S0

If Si =1, IR input has a slave and if Si=0, IR input does not have
a slave.
b) In the slave mode (either when = 0 or if BUF =1 and M/S =0
in ICW4) bits 2-0 identify the slave. The slave compares its
cascade input with these bits and if they are equal bytes 2&3 of
the CALL sequence are released by it on the data bus.
0 0 0 0 0 ID2 ID1 ID0

The three identification bits ID2, ID1, and ID0 tells the slave 8259A to
which master input, slave is connected.
Initialization Control Word 3 ICW4:
ICW4 is output to only if ICW4 in ICW1 is set to 1. Otherwise
the contents of ICW4 are cleared. The bits in ICW4 are defined as
follows:

0 0 0 SFNM BUF MS AEUI

Bits 7-5: always set to zero.

Bit 4(SFNM): If set to 1, the special fully nested mode is used. This
mode is utilized in system having more than one 8259A. If set to 0, it
is not specific fully nested mode.
Bit 3(BUF): If BUF id set1, the buffered mode is programmed,
otherwise non buffered mode. In this mode / becomes an
enable output and the master/slave determination is by M/S.
Bit 2(M/S): If buffered mode is selected, M/S =1 means the 8259A is
programmed to be a master. M/S =0, means the 8259A is
programmed to be a slave. If BUF=0, M/S has no function.
Bit 1(AEOI): If AEOI =1, the automatic end of interrupt mode is
programmed.
Bit 0( ): Microprocessor mode, if =0, it sets 8259A for 8085
system operation, If =1, it sets the 8259A for 8086 system
operation.
The sequences of routine are,

Operation command words (OCWs):

After the 5259 has been initialized, it is ready to accept interrupt
requests at its ready input lines .during operation the 8259A can be
commanded to operate in different modes using OCWA. These are
three OCWS.
Operation Control Word 1 OCW1: OCW1 sets and cleans the make
bits in the interrupt mask register (IMR).M7 M0 represents the eight
mask bits M=1 indicates the channel is masked (inhibited), M=0
indicates they channel is enabled .OCW1 is output to odd address.
There is no ambiguity in ICW2, ICW3, ICW4 and OCW1 all using the
odd address because the initialization words must always follow
ICW1as detected by the initialization sequence and an output to
OCW1 cannot occur in the middle of this sequence. The format is
given bellow. Masking an IR channel does not affect the other
channel operation.

M7 M6 M5 M4 M3 M2 M1 M0

If Mi = 1 corresponding Interrupt Mask is Set and if Mi = 0

corresponding Interrupt Mask is Reset

OCW2 and OCW3 :( operation control word 2 and 3)

OCW2 & OCW3 are used for controlling the mode of the 8259A
and receiving EOI command OCW2&OCW3 are sent to even address
the format of OCW2&OCW3 are given bellow:

OCW2 (operation control word 2):

R SL EOI 0 0 L2 L1 L0

R, SL and EOI stands for rotate, set level, and end of Interrupt and
the bit combination of these decides the manner in which ISR bit is
cleared. L2, L1, and L0 decides the interrupt level to be acted upon if
SL bit is made 1.
 R SL EOI Interrupt Mode
0 0 1 Non-specified EOI command
End of Interrupt
0 1 1 specified EOI command
1 0 1 Rotates on non-specified EOI
1 0 0 Rotate in AEOI mode (set) Automatic rotation
0 0 0 Rotate in AEOI mode (clear)
1 1 1 Rotate on specific EOT command
specific rotation
1 1 0 Set priority command
0 1 0 No-Operation

Interrupt Level to be acted upon

L2 L1 L0 Interrupt Level
0 0 0 Interrupt 0
0 0 1 Interrupt 1
0 1 0 Interrupt 2
0 1 1 Interrupt 3
1 0 0 Interrupt 4
1 0 1 Interrupt 5
1 1 0 Interrupt 6
1 1 1 Interrupt 7

OCW3 (operation control word 3):

0 0 ES MH SMH 0 1 P RR RIS

The combination of different bits decides the mode in which Intel

8259A will operate:
ESMM SMM Operation
0 0 No Action
0 1 No-Action
1 0 Reset Special Mask Mode
1 1 Set Special Mask Mode

RR RIS Operation
0 0 No Action
0 1 No-Action
1 0 Read Interrupt Request Register on next RD pulse
1 1 Read In-service Register on next RD pulse

P Operation
0 No Poll Command
1 Poll Command

OCW2 is designed from OCW3 by the contents of bit 3 of the

data. Byte if bit 3 is 0, the byte is put in OCW2, and if it is 1, it is put in
OCW3. Both OCW2 &CCW3 are distinguished from ICW1, which
also uses the even address by the contents of bit 4 of the data. If bit 4
is 0,then the byte is put on OCW2 or OCW3 according to bit 3 the bit
is OCW2 only temporally retained by 8259A until the action specified
by them are carried out.
Lecture-54
Fully nested mode:
This mode is entered after initialized unless another is programmed
.the interrupt request are ordered in priority from 0 through I (0
highest). When an interrupt is acknowledged the highest priority
request is determined and its never placed on the bus. In addition to
this, the corresponding bit of is it. Their bit remains set until the
issues an end of interrupt (EOI) command immediately before
returning from the service routine, on if AEOI bit is set, until the
having edge of the last . While the ISS bit is set, all further
interrupt of the same or lower priority are inhibited, while higher levels
will generate an interrupt (which will be acknowledge only if the
internel interrupt enable f/f has been re-enabled through software.
After the initialization sequence, IRO has the highest priority and IRY
the lowest priorities can be changed, in the rotating priority mode.

How the priority resolves the ISR set to allow service un interrupting
device .Will be clean by the following example.
Suppose IR2 and IR4 are unmasked and that an interrupt
signal comes in on the IR4 input .since IR4 is unmasked bit 4 of the
IRR will be sort. The priority resolves will detect that these bit is set
and seen. If any location needs to be taken. To do if checks the bits
in the in-service register (ISR) to see if a higher priority interrupt are
being serviced if a higher priority interrupt is being serviced if a higher
priority interrupt is being serviced. If a higher priority interrupt is being
serviced received as indicated by a being set for that input in the ISR,
then the priority resolves will take no action. If no higher priority
interrupt is being serviced. Then the priority resolve will activate the
circularly which send an interrupt signal to 8085 executes the IR4
interrupt service subroutine.
Now ,suppose that while the 8085 executing the TR4 arrives at
the IR2 input of the 8259 A since we assumed for this example that
IR2 was unmasked bit 2 if the IRR will be set .the priority resolve will
detect that this bit in the IRR is set and make a decision whether to
send interrupt to the processor. To make the decision ,the priority
resolves looks at the in-service register .If a higher priority bit is set
,then it means a higher priority interrupt is being service .the priority
resolves will wait until the higher priority bit in the ISR is reset before
be sending an interrupt signal to the . For the new interrupt input .if
the priority resolves finds that the new interrupt has higher priority.
Than the highest priority then the highest priority interrupts being
serviced, it will set the appropriate bit in the ISR and then it sends.
A new INT signal to CPU in this example,IR2 has a higher
priority than IR4 so the priority resolves will set the bit 2 of the ISR
and send new INT signal. If 8085 interrupt function has been enabled
(EI) at the start if IR4 service sub routine, then this new INT will again
interrupt the CPU. Upon receiving PIC sends the address if IR2
subroutine and CPU starts execution IR2 sub routine.
If the end of IR2 subroutine we send the PIC a command word
that resets the PIC a command word that resets bit 2 ISR so that
lower priority interrupts can be serviced A RESET instruction at the
end of the Ir4 subroutine return execution to the main program.
 If IR4 procedure did not enable the interrupt input either EI
instruction the CPU would not expand to the IR2 caused INT signal
until it finished executing the IR4 dub-routine.

End of the interrupt (EOI):

The in service bit can reset automatically following the
trailing edge of the last in sequence pulse (when AEOI bit in
ICWI is set) if AEOI=0, then ISR can be reset by a command word
that must be issued to the 8159A before returning from a service
routine (EOI command) an EOI command must be issued twice if in
the cascade mode, once for the master and for the corresponding
slave .there are two form if EOI command. Specified and non-
specified .when the 8259 A is operated in modes which procedure the
fully nested structure, it can determine which IS bit to reset on EOI.
When a non specific EOI commands is issued the 8259A will
automatically reset the highest IS bit of those that are set. Since in
the fully nested mode the highest IS level was necessary the last
level acknowledge & serviced .a non-specific EOI can be issued with
OCW2 (EOI=1, SL=0, R=0).
When a mode is used which may disturb the fully nested
structure, the 8259A may no longer may be able to determine the last
level acknowledged. In this case a specific and on interrupt must be
issued which includes as a part of the command the IS level to be
reset. A specific EOI can be issued with OCW2 ((EOI=1, SL=0, R=0)
L2-L0 IS the binary level of the IS bit to be reset.
It should be noted that an IS bit that is masked by an IMR bit
will not be cleaned by a non-specific EOI if the 8259A is the special
mask mode.

Automatic end of interrupt (AEOI) mode:

If AEOI=1in ICW4, then the 8259A will operate in AEOI mode
continuously until reprogrammed by ICW4,in this mode the 8259A will
automatically perform a non-specific EOI operation at the trailing
edge of the last interrupt acknowledge pulse(third pulse in
80/85,second in 86). Note that from a system start point. This mode
should be used only when a nested multilevel interrupt structure is
not required within a signal 8259A.
The AEOI mode can be used in a master 8259A and not a slave.
Automatic rotation: (equal priority devices)
If some application there are a number of interrupting device s
if equal priority .in this mode a device, after being serviced, receivers
the lowest priority, so advice requesting an interrupt will have to wait.
In the worst case until each other devices are serviced at most once.
For example if the priority and in service status is:
Before rotate (IR4 the highest priority requiring service);

IS states IS7 IS6.......................................IS0

0 1 0 1 0 0 0 0

Priority status 7 6 5 4 3 2 1 0

After rotate (IR4 was serviced, all other priorities rotated

correspondingly)
IS states IS7 IS6.......................................IS0
0 1 0 0 0 0 0 0

Priority status 2 1 0 7 6 5 4 3

There are two ways to accomplish automatic rotation using OCW2,

the rotation or non-specific EOI command(R=1,SL=0,EOI=1) and the
rotate in automatic EOI mode which is set by (R=1,SL=0,EOI=1)and
cleared by (R=1,SL=0,EOI=1).
Specific rotation: (specific priority)
The programmer can change priorities by programming the
bottom priority and these fixing all other priority device, then IR6 will
have the highest one.
The set priority command is issued in OCW2 where R=1,
SL=0,L0-L2 is the binary priority level code with bottom priority
device.
Observe that in this mode internal status is updated by software
control during OCW2.however it is independent if the end if interrupt
(EOI) command (also executed by OCW2). Priority changes can be
executed during an EOI command by using the rotate on specific EOI
command in OCW2 (R=1, SL=1, EOI=1) &L2- L0=IR level to receive
bottom priority.

Special mask mode:

Some application may require interrupt service routine to
dynamically after the system priority structure during its execution
under software content. For example, the routine may which to inhibit
lower priority requests for a portion of its execution but enable some
of them for another portion.
The difficulty here is that if an interrupt request is acknowledged
and an End of interrupt command did not resets its IS bit (i.e., while
executing a service routine) the 8259A would have inhibited. All lower
priority request with no easy way for the routine to enable them.
That is where the special mask mode comes in. In the special
mask mode, when a mask bit is set in OCW1, it inhibit further
interrupts at level and enables interrupts from all other levels(lower as
well as higher) that are not masked. Thus, any interrupts may be
relatively enabled by loading the mask register.
The special mask mode is set by OCW3 where ESMM=1,
SMM=1, and cleared where ESMM=1, SMM=0.
Lecture-55
Poll Command:
In this mode the INT output is not used for the microprocessor
internal interrupt enable F/F is reset, disabling its interrupt input,
service to device is achieved by software using a poll command.
The poll command using a poll command setting p=1 in OCW3. The
8259A (i.e., =0, =0)as an interrupt acknowledge ,sets the
appropriate is bit if there is a request ,and reads the priority level
.interrupt is frozen from to .

The word enabled onto the data bus during is

D7 D6 - - - - - D0
I - - - - W2 W1 W0

W0 W2: binary code of the highest priority level requesting service.

I: equal to 1if there is an interrupt.
This mode useful if there is a routine command .its several levels so
that the sequence is not needed. (ROM space). Another
application is to use the poll mode to expand the number of priority
levels to more than 64.

Reading the 8259A status:

The input status of several internal registers can be read to update
the uses the information on the system. The following registers can
be read via OCW3 (IRR and IBR 0r OCW1 [IMR]).
Interrupt Request Register (IRR):
8-bit register which contains the levels requesting an interrupt to be
acknowledged. The highest request level is reset from the IRR when
an interrupt is acknowledged (not affected by IMR).

In- service register (ISR):

8-bit register which contains the priority levels that are being serviced.
The ISR bit is updated when an End of interrupt command is issued.

Interrupt mask register (IMR):

8-bit register which contain the interrupt request which contain the
interrupt request lines which are masked.
The IRR can be read when, prior to the pulse, a read
register command is issued with OCW3 (RR=1, RIS=1).
There is no need to write an OCW3 before every status read
operation, as long as the status read corresponds with the previous
one, i.e., the IRR or ISR has been previously selected by the OCW3.
This is not true when poll is used. After initialization the 8259A is set
to IRR.
For reading the IMR, no OCW3 is needed. The output data bus
will contain the IMR whenever is active and A0=1(OCW1). Polling
over side status read when P=1, RR=1 in OCW3.

Edge & Level Triggered Modes:

This mode is programmed using bit 3 in ICW1. If LTIM=0, an
interrupt request will be recognized by a low to high transfer on an IR
input. The IR input can remain high without generatively another
interrupt.
If LTIM=1, an interrupt request will be recognized by a high
level on input and there is no need for an edge detection. The
interrupt request must be removed before the EOI command is
issued or the CPU interrupt is enabled to prevent a second interrupt
from occurring.
In the both the edge & level triggered modes the IR input must
remain high until after the falling edge of the first INTA. If the IR input
goes low before this time a DEFAULT IRT will occur even the CPU
acknowledges the interrupt. This can be a useful safe guard for
detecting interrupts caused by previous noise glitches on the IR
inputs. To implement this feature the IR7 routine is used for clean
up simply executing a return instruction, thus ignoring the interrupts.
If IR7 is needed for the other purpose a difficult IR7 can still be
detected by reading the ISR. A normal IR7 interrupt will set the
corresponding ISR bit, a difficult IRT unit. If a default IR7 routine
occurs during a normal IR7 routine, however the ISR bit will remain
set. In this case it is necessary to keep track of whether or not the IR7
routine was previously entered. If another IRT occurs it is a default.

The special fully nested mode:

This mode will be used in the case of a big system where
cascading is used, and the priority has to be conserved within each
slave. In their fully nested mode will be program to the master (using
ICW4). This mode is similar to the normal nested mode with the
following exception:
 a) When an interrupt request from a certain slave is in service this
slave is not locked out from the masters priority logic and
further interrupt requests from higher priority IRs within the
slave will be recognized by the master and initiate interrupts to
the processor (in the normal nested mode a slave is masked
out when its requests from the same slave can be serviced).
b) When exciting the interrupt hence routine the software has to
check whether the interrupt service was the only one from that
slave. This is done rending a non-specific. EOI command to the
slave and then reading it in service register and checking for
zero it is empty, a non- specific EOI can be sent to the master
too if not, EOI should be sent.

Buffered mode:
When the 8259A is user in a large system where bus during
buffer is required on the data bus and the cascading mode is used,
there the problem of enabling buffers. The buffered mode will
structure the 8259A to send an enable signal to / output
becomes active.
These modification forces the use of software programming to
determine whether the 8259A is a master or a slave. Bit 3 of ICW4
programs the buffered mode, & bit 2 in ICW4 determines whether it is
a master or a slave.
Cascade mode:
The 8259A can be easily internal connected in a system of one
master with up to 0 slaves. To handle up to 64 priority levels. When
designing the address decoder logic, each 8259A must be given its
can address pair (even &odd) is the I/O address space. The / of
all the slaves are connected to GND. The slave interrupt outputs are
connected to the master I Request inputs.
The master controls the slave through the 3 line cascade bus.
The cascade bus acts like chip selects to the slaves during the
sequence.
In a multiple 8259A system the slaves must be initialized as
well as the master. The master would be initialize in the same way as
indicate earlier except that NGL would be set to 0 and ICW3 would
needed to be filled A1would be put in each ICW3 bit for which the
corresponding IR bit is connected to a slave and 0A would be put in
the remaining bits. The SFNM bit may be set to 0 where initializing
the slaves thus, an ICW3 will be require for each slave, but for a
slave ICW3 has a different meaning for a slaves ICW3 has the form

0 0 0 0 0 ID2 ID1 ID0

where the 3 least significant bits provides the slave with an

identification number. The identification numbers given to slave
should be the same as the number of the master request line to
which INT pin is connected.
When a slave puts a 1 anis INT pin, this signal is send to
appropriate IR pin on the master. Assuming the DMR & priority do not
block this signal. It is doing not the CPU through the INT pin ON the
master. When the CPU returns the signal the mask will not only
set the appropriate ISR bit and clear the corresponding IRR it will also
check the corresponding bit in ICW3 to determine whether or not the
interrupt came from the plane. If so, the master will place number of
the IR level on the CAS 2- CAS 0 lines 1 if not, it will put the address
of the interrupt from the master directly during 2nd&3nd. Pulse

and no signals will be applied to the CAS 2-CAS 0 LINES. The

signal also be received by the entire slave, but only that slave whos
ID matches over the CAS 2-CAS 0 will accept the signal. In the
selected slave the appropriate ISR bit will be set the corresponding
IRR bit will be cleared, and the slave relives the device routine
address during bytes 2nd &3rd of INTA (bytes 2 only for 06/88).
 The cascade lines are normally low and will contain the slave
address code from the hailing edge of the 1st pulse to the

trailing edge of the 3rd pulse.

An EOI command must be issued twice: once for the master
and once for the corresponding slave if AEOI=0. An address decoder
is required to activate the chip select (CS) input of each 8259A.