Combinational

Logic Circuit
Applications
DECODER, ENCODER, MULTIPLEXER, DEMULTIPLEXER ,
CODE CONVERTER, EX -OR &PARITY CIRCUITS,
COMPARATORS, ADDERS/ SUBTRACTORS , ETC
Decoders
A decoder is a multiple-input, multiple-output logic circuit which
converts coded inputs into coded/known outputs, where the input
and output codes are different.
The input code generally has fewer bits than the output code.
Each input code word produces a different output code word, i.e.,
there is one-to-one mapping from input code words into output
code words. This one-to-one mapping can be expressed in a truth
table.

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Encoder
An encoder is a digital circuit that
performs the inverse operation of a
decoder.
It has 2n input lines and n output lines.
In encoder the output lines generate
the binary code corresponding to the
input value.

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Priority Encoder
A priority encoder is a circuit or algorithm that compresses multiple
binary inputs into a smaller number of outputs. The output of a priority
encoder is the binary representation of the ordinal number starting
from zero of the most significant input bit. They are often used to
control interrupt requests by acting on the highest priority request.

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a single bit 4 to 2 encoder takes in 4 bits and outputs
2 bits

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Three State Devices
A three state (tri-state) device is a digital circuit that exhibits three
states such as logic 1, logic 0, high impedance state.
The high impedance state means the output appears to be
disconnected like an open circuit. In this state, the circuit has no logic
significance. The three-state device has a control input that can place
into a high-impedance state. The high impedance state is represented
by Z.

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Three State Device

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Multiplexer
A device that selects one of several
analog or digital input signals and
forwards the selected input into a single
line.
A multiplexer is also called a data
selector.

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Demultiplexer
A demultiplexer (or demux) is a device
taking a single input signal and selecting
one of many data-output-lines, which is
connected to the single input.
A multiplexer is also called a data
distributor.

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Mux & Demux

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Where they are used
Multiplexers
Selectors for routing data to the processor, memory, I/O
Multiplexers route the data to the correct bus or port.
Decoders
are used for selecting things like a bank of memory and then the
address within the bank. This is also the function needed to decode
the instruction to determine the operation to perform.
Encoders
are used in various components such as keyboards.

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Code Converters
A BCD to Excess-3 code converter
BCD-to-7-segment decoder

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BCD-to-Excess-3 Code
converter
BCD is a code for the decimal digits 0-9
Excess-3 is also a code for the decimal digits

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Formulation of BCD-to-Excess-
3
Excess-3 code is easily formed by adding a binary 3 to the binary or BCD
for the digit.
There are 16 possible inputs for both BCD and Excess-3.
It can be assumed that only valid BCD inputs will appear so the six
combinations not used can be treated as dont cares.

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 Optimization BCD-to-Excess-
3
Lay out K-maps for each output, W X Y Z

A step in the digital circuit design process.

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Two level circuit
implementation
Have equations
W = A + BC + BD = A + B(C+D)
X = BC + BD + BCD = B(C+D) + BCD
Y = CD + CD
Z = D

Factoring out (C+D) and call it T

Then T = (C+D) = CD
W = A + BT
X = BT + BT
Y = CD + T
Z = D

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 Create the digital circuit
Implementing the second set of
equations where T=C+D results
in a lower gate count.
This gate has a fanout of 3

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BCD to 7 segment code
converter
Input: A 4-bit binary value that is a BCD coded input.
Outputs: 7 bits, a through g for each of the segments of the display.
Operation: Decode the input to activate the correct segments.

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Formulation
Construct a truth table

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Error-Detection Code
One of the ways to achieve error-detection is by means of a parity bit.
Parity bit is an extra bit included with a message to make the total
number of 1s transmitted either odd or even.
The parity bit is helpful in detecting errors during the transmission of
information from one location to another.
A message of four bits and a parity bit P are shown:

If an odd parity is adopted, the P

bit is chosen such that the total
number of 1s is odd in the five
bits that constitute the message
and P.
If an even parity is adopted, the P
bit is chosen to the total number
of 1s in the five bits is even.
In a particular situation, one or
the other parity is adopted, with
even parity being more common.
 Error-Detection Code
An even parity bit is generated in the sending end for each
message transmission. The message , together with the parity bit,
is transmitted to its destination.
The parity of the received data is checked in the receiving end. If
the parity of the received information is not even, it means that
at least one bit has changed value during the transmission.
This method detects one, three, or any odd combination of errors
in each message that is transmitted. An even combination of
errors is undetected.
Additional error-detection schemes may be needed to take care
of an even combination of errors.
 Exclusive OR and Exclusive NOR Gates

XOR :
X Y X 'Y X Y ' X

XNOR : F
( X Y )' X Y X 'Y '

Truth Table : Y

XOR
X Y XOR XNOR X
0 0 0 1 F
0 1 1 0
1 0 1 0
1 1 0 1
Y
XOR

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 XOR and XNOR Symbols
Equivalent Symbols of XOR gate

Equivalent Symbols of XNOR gate

Any 2 signals (inputs or outputs) may be

complemented without changing the resulting logic
function

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SSI XOR and XNOR
74x86 :
4 XOR gates

74x266:
4 XNOR gates with open collector or open drain output

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 XOR Application: Parity Circuit
Odd Parity Circuit : The output is 1 if odd number of inputs are 1
Even Parity Circuit : The output is 1 if even number of inputs are 1
Example : 4-bit Parity Circuit

I0
I1 EVEN I0 EVEN

I2 I1 ODD
ODD
I3 I2
I3
Daisy-Chain Structure Tree structure
Input : 1101 Odd Parity output : 1
Even Parity output : 0

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MSI Parity Circuit : 74x280

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Parity-Checking Application: memory

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Comparator
A digital comparator or magnitude comparator is a hardware
electronic device that takes two numbers as input in binary form
and determines whether one number is greater than, less than or
equal to the other number. Comparators are used in a central
processing units (CPU) and microcontrollers. Examples of digital
comparator include the CMOS 4063 and 4585 and the TTL 7485 and
74682-'89.
The analog equivalent of digital comparator is the voltage
comparator.

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The operation of a single bit digital comparator can be
expressed as a truth table:

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 Comparators
Compares Two binary words and indicate if they are equal

A
Comparator A=B?
Magnitude Comparators
B :

A A=B
Comparator A>B
B A<B

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Equality Comparators

1-bit comparator

4-bit comparator

EQ_L

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 MSI Comparator : 74x85
4 bit comparator 74x85

A<BIN A<BOUT
3 outputs : A=B, A<B, A>B
A=BIN A=B OUT
3 Cascading inputs A>BIN A>BOUT
A0
Functional Output equations :
(A>B OUT)= (A>B)+(A=B).(A>B IN) B0
(A<B OUT)= (A<B)+(A=B).(A<B IN) A1
(A=B OUT)= (A=B).(A=B IN) B1
A2
Cascading inputs initial values :
B2
(A=B IN) =1
A3
(A>B IN) =0
(A<B IN) =0 B3

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8 bit Comparator
+5V

74x85 74x85

A<BIN A<BOUT A<BIN A<BOUT A<B

A=BIN A=B OUT A=BIN A=B OUT A=B
A>BIN A>BOUT A>BIN A>BOUT A>B
A0 A0 A4 A0
B0 B0 B4 B0
A1 A1 A5 A1
B1 B1 B5 B1
A2 A2 A6 A2
B2 B2 B6 B2
A3 A3 A7 A3
B3 B3 B7 B3
Least Significant bits Most Significant bits
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8-bit Magnitude
Comparator

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Adders/Subtractors
Half Adder
Full Adder
Ripple Adder

Full Subtractor
Ripple Subtractor
Adder/ Subtractor Circuit
Other
conditions

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 The half adder
The half-adder adds two binary digits at a time and thus is a basic circuit for adders.
The two binary digits, an

addend aaugend, a sum digit (S) a carry digit (C)

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The full adder
A gate structure that adds three binary digits at a time is called a
full adder. Thus a full adder also has a carry input. The addition of two mod-2
numbers of N digit, A = A N1 A N2 A0 and B = B N1 B N2 B0, is
illustrated

There are two outputs namely, sum and carry, of the Boolean equations
are given by
Sum = A B C Carry = AB + (A B) C
Therefore, sum is 1 when number of input 1s is odd; carry is a 1 when
two or more inputs are 1s
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 A full-adder Circuit using two half-adders

Subtraction of Binary Numbers

The subtraction of a number A from B is, in fact, the addition of A and

B. Thus an adder complements the magnitude of B and then
magnitude of uncomplemented number (A) is added to the magnitude
of the complement, B

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In order to subtract two four-bit binary numbers, e.g. subtraction of
B3B2B1B0 from A3A2A1A0, we first invert each B-bit to get 1s
complement of B3B2B1B0, i.e. B3B2B1B0 and then add to A3A2A1A0.
Here A is the minuend, B the subtrahend, D = A B the difference, and
C the borrow.
When A = 0 and B = 1, it is
necessary to borrow 1 from
the minuend of the next
higher order to allow the
subtraction to be effected

A Full Adder Circuit

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Half subtractor
Half subtractor can subtract two digits at a time and produce an
output of a difference and a borrow. It accepts A and B as inputs and
yields d and b as outputs. From the truth table of a half subtractor, it
follows that
d = A B, b=B

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 Full subtractor
A full subtractor accepts the minuend (A), the subtrahend (B), and a
borrow from a previous order (c) as inputs. Two half-subtractor may
be combined to construct a full-subtractor, as shown below. One half-
subtractor yields Ai Bi, while the second half-subtractor produces (Ai
Bi) Ci1. A borrow must be transferred to the next higher order if
either or both of the subtractions results in a borrow. Thus, the two
individual borrow outputs are transferred to the next order through an
OR gate.

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 Half Adder: adds two 1-bit
operands
Truth table :

X Y HS=(X+Y) CO
0 0 0 0 X
HS
0 1 1 0 Y
1 0 1 0
1 1 0 1 CO

HS X Y
CO X Y
 Full Adders: provide for carries
between bit positions
Basic building block is full adder
1-bit-wide adder, produces sum and carry outputs

Truth table:
 Full Adders: provide for carries
between bit positions
Basic building block is full adder
1-bit-wide adder, produces sum and carry outputs

Truth table:
X Y Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Full Adders: provide for carries
between bit positions
Basic building block is full adder
1-bit-wide adder, produces sum and carry outputs

Truth table:
X Y Cin S Cout
S is 1 if an odd number 0 0 0 0 0
of inputs are 1. 0 0 1 1 0
0 1 0 1 0
COUT is 1 if two or 0 1 1 0 1
more of the inputs are 1 0 0 1 0
1. 1 0 1 0 1
Recall: Table 2-3, pp32 1 1 0 0 1
1 1 1 1 1
Full-adder circuit
Full-adder circuit
Full-adder circuit
 Ripple adder

Speed limited by carry chain

Faster adders eliminate or limit carry chain
2-level AND-OR logic ==> 2n product terms
3 or 4 levels of logic, carry look-ahead
 74x283
4-bit adder
Uses carry look-ahead
internally
16-bit group-
ripple adder
Subtraction
Subtraction is the same as addition of the twos complement.
The twos complement is the bit-by-bit complement plus 1.
Therefore, X Y = X + Y + 1
Full Subtractor = full adder, almost

X,Y are n-bit unsigned binary numbers

Addition : S=X+Y
Subtraction : D = X - Y = X + (-Y) =
= X+ (Twos Complement of Y)
= X+ (Ones Complement of Y) + 1
= X+ Y+ 1
Full Subtractor = full adder, almost

X,Y are n-bit unsigned binary numbers

Addition : S=X+Y
Subtraction : D = X - Y = X + (-Y) =
= X+ (Twos Complement of Y)
= X+ (Ones Complement of Y) + 1
= X+ Y+ 1
Using Adder as a Subtractor
Ripple Adder can be used as a Subtractor by inverting Y and setting the initial
carry ( CIN ) to 1
Using Adder as a Subtractor
Ripple Adder can be used as a Subtractor by inverting Y and setting the initial
carry ( CIN ) to 1
 MSI Arithmetic Logic Units (ALU )
74x181
ALU performs Arithmetic and Logical Functions
- A , B : 4 bits inputs S0
- S3,S2,S1,S0 : Function select S1
- M=0 : Arithmetic operations +=Plus , - = Minus G
S2
M=1 : Logical operations : += OR , . =AND P
S3
Example : M A=B
Inputs Functions CIN
S3 S2 S1 S0 M=0 M=1 A0 F0
0 0 0 0 F= A-1+CIN F=A B0 F1
0 1 1 0 F= A-B-1+CIN F=A XOR B F2
A1
1 0 0 1 F= A+B+CIN F=A XOR B F3
B1
1 0 1 1 F=(A OR B)+ CIN F=A+B
1 1 0 0 F= A+A+CIN F= 0000 A2 COUT
1 1 1 1 F=A+CIN F=A B2
A3
B3