Digital Design with the Verilog HDL

Chapter 0: Introduction

Dr. Phm Quc Cng

Computer Engineering CSE HCMUT 1

 Instructor & TAs
Instructor:
Dr. Phm Quc Cng
cuongpham@hcmut.edu.vn
www.cse.hcmut.edu.vn/~cuongpham
TA:
MEng. Trn Thanh Bnh (thanhbinh@hcmut.edu.vn)

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 About

System Architecture - Dr. Cuong Pham-

Quoc
 About

System Architecture - Dr. Cuong Pham-

Quoc
 About

System Architecture - Dr. Cuong Pham-

Quoc
 HDL
Q: What is HDL?
A: Hardware Description Language used to describe
hardware components

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 HDL (cont.)
Definition:
Computer language (not a programming language)
Describe structure and operation of a digital circuit
Simulate and verify a digital circuit

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 HDL (cont.)
Advantages:
Manage large and complex circuits easily
Portable and technology-independence
Reuse predefine modules
Automated synthesized circuit
VerilogTM & VHDL
IEEE standard
Supported by synthesis tools for both ASICs and FPGA

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 The Course
Contents:
Combination circuits design with the Verilog HDL
Sequential circuits design with the Verilog HDL
Simulation and errors check
State transaction machine
Digital circuits design with the Verilog HDL
Memory design with the Verilog HDL
Clock generation

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 Course Outcomes
Using the Verilog HDL to design combinational and
sequential digital circuits
Analyzing and modeling problems by state-
transaction-machine
Using simulation tools to verify designed circuits

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 Learning Materials
Slides: www.cse.hcmut.edu.vn/~cuongpham or BKeL
Textbooks

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 Assessment
Lab & Project: 30% (TA: MEng. Trn Thanh Bnh)
Active learning (quiz/homework): 10% (mandatory)
Mid-term: 20% (mandatory) multiple choices,
closed books
Final exam: 40% (mandatory) multiple choices,
closed books

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