IENTED TEST TECHNIQUE FOR VLSI'S USING ATE
Yasuji Oyama, Toshinobu Kanai, Hironobu Niijima
ADVANTEST CORPORATION
Ohtone, Saitama, Japan
Abstract
A new test technique to localize failures of devices
with scan design easily and quickly using LSI tester is
proposed. This technique allows device designers or
test engin- to localize the scan Flip Flops that failed
Using expressions based on the scan design of the
device. These devices are defined by the Boundary
Scan Description Language (BSDL) or an extension to
BSDL proposed in this paper, This technique can be
applied to standard boundary scan designs and to
ad-hoc internal scan implementations. Furthermore.
restrictions ftom limited tester resources has been
solved by technique. As a result, it is possible to
speed-up of the failure analysis resulting in a decrease
of the test costs.
Keywords
Scan design, U 1 tester, Scan test, BSDL, JTAG
1 Introduction
As large scale LSI devices have increased in
complexity in recent years, the difficulty of test and
failure analysis has also increased in commensurate
proportions. DFT(Design For Testability) has been a
significant solution for increasing testability of these
IC's [l].Scan design is a well known implementationof
DFT that has gained in popularity with the use of ATPG
(Automatic Test Pattern Generation) design software.
In such situations, when a device with the scan design
(hereafter called the scan device) is tested on an LSI
tester,it had to support the long test patterns generated
by the ATPG tool. When failures were detected. it has
been a time consuming task to convert the failure
information provided by the tester into a physical
element of the circuit design.
Tester environments to test or analyze scan failures
have not been fully developed. Usually, the functional
test result &om the LSI tester contains information
about the test pattern addresses or device pin which
failed 121.
INTERNATIONAL TEST CONFERENCE
$5.00 1996 IEEE
0-7803-3540-6196
The actual information required by design and
product engiueers is as follows:
(a) The scan chain where the failure occurred
(b) The actual Scan Flip Flop where the failure
occurred.
(c) "he time at which the failure cccurred relative to
the start of the pattern. This requirement is
because the ATPG software does not represent
test events as cyclized intervals, as most testers
do.
To obtain the required information, the results from
the LSI tester are fed back to the DFT tool to identify
the Scan Flip Flops where the failure occurred. This
Flip Flop is referred to as the discrepant scan Flip Flop
in this paper. It is not easy to identify the fault time and
to analyze the scan device complex faults
completely due to the restriction of limited hardware
resources in the LSI tester.
It is almost impossiblefor an LSI test engineer using
the data log of a test r d t from an LSI tester to answer
the previously mentioned s (a), (b). and (c). They
must rely on time consuming manud analysis tech-
niques to convert the tester failure result from the
application of test pattems circuit information that
identifies a failed circuit, or area on the circuit.
Real waveforms output from a device might need to
be comparedwith the waveformsfrom a logic simulator
to analyze the failures. In this eal waveforms
from the device are shown with
using an original time ed at a simulation run
pond the waveforms
, and for analysis by
the test engineer.Furthennore,
a tester using long test pattern
tool, it is possible that the
analysis.
To solvethese problems, the authorshave developed
Paper 17.1
453
 a new test technique for identification of the scan Flip
Flop that failed using the scan design information on a
conventional LSI tester,using the Scan test patterns. We
incorporated the concept of BSDL(Boundary Scan
Design Language) [3][43[51 in accordance with the
IEEE1149.1 standard in our technique to deal with the
scan design information. Also, devices with full or
partial scan can be also supported by this technique. In
this paper, the authors present this new test technique
along with a functional explanation of a system
developed to verify the effectiveness. The paper
concludes with a recommendation about extending
BSDL to improve the usage of this method.
utline of the Scan Analysis System
The testerusing the technique proposed in this paper
is called the Scan Analysis System. This isdis-
thguished fiom general-purpose LSI testers not using
this technique. New software has been developed in
order to realize the Scan Analysis System. Figure 1
shows the basic system configuration. The LSI tester is
a general-purpose one containing a failure memory and
a pattern generator. The software is composed of four
modules, the test pattern information extraction
module, the acquisition range information generation
module, the scan data log 1 generation module and the
scan data log 2 generation module. They are installed
on an LSI tester using a UNIX-based workstation for
mter control and data processing. This system uses
the data log output from the system, which contains
failure information described in a testeroriented
mmer. The functions of each element of the Scan
LSI TESTER 1I
I
I Workstation
(Conventional Logic Tester) I Test Pattern Information
I ' I
- 4
Scan Device
Under Test
I
uration of Scan Analysis System
Paper 17. I
454
Analysis System are descriked below [a.
Test pattern information extraction module: This
extracts the test pattern information by interpreting the
between the test pattern and the scan design
Acquisition range information generation module:
This module applies failure acquisition conditions to
uire informationon discrepant scan Flip Hops from
given test program.
Scan data log 1 generation module: This module
uses a test result from an LSI tester to identify the
discrepant scan Flip Flops, and creates a log file
containing this information.
Scan data log 2 generation module: This module
generatesthe final output log file, called scan data log 2.
This file uses added time information and scan circuit
design information(scan cell name) to the scan data log
1 data.
Figure 2 shows the flow of processing using the
above-mentioned software modules. We describe this
technique in this figure, and in sections 3 and 4.
3 ation
'Ikro preparations are requjred for localizing the
discrepant scan Flip Flops.
3.1 Extraction of Test Pattern Information
Localizing discrepant scan Flip Flops in a scan
device is not easy using only the test result from an LSI
tester. Scan circuit design information about the device
is available only from outside of the Scan Analysis
System. Devices designed with JTAG use the scan
1
Extraction Module
Data prepared
Module
--::::::i::2.:j.,i: ...................... :,:.:.,.
I
circuit information described in BSDL, which is
directly ported to this system. On the other hand
devices using non-standard scan designs, such as those
developed internally by a semiconductor maker, have
the scan circuit information described in accordance
with that description specification. We originally
supported the specification of BSDL for input to the
Scan Analysis System. In this case, the number of scan
chains which can be connected between TDI and TDO
is only one, according to the JTAG standard The
description for parallel scan is supported in this system.
Thus, for test logic other than BSDL a description for
scan devices is provided that enhances the functionality
provided by BSDL. This is an applicable description
specification for different test circuit designs.
Pattern address information on the test pa is
converted into scan c h i t information using the
above-mentioned test pattern information emaction

1
Acquisition Range
Information
I
II
L
I
l

t
+ I
+ + I r -
t +
Scan Data Log 2
Generahon Module

Scan Data Log 2

L.- /
t
Figure 2 Flow of Processing

Paper 17.1
455
 module. This module classifies the pattern address
information per scan chain. Such data are preserved in
the test pattenn information file for the subsequent
processing as shown Step A of in Figure 2.
3.2 Generation of Acquisition Range Information
When executing scan testing on an LSI tester, test
p a t are executed as functional tests. In this case, a
test number is assigned to each one. This system was
designed to allow arbitrary specification of the test
number for which you desireto get a scan data log (Step
B of Figure 2). In addition, the scan chain can be also
specified with each test number for output of failure
information in the scan data log. In this case, we were
able to enta the scan chain name based on scan circuit
design information of the scan device. This prevents the
user from having to carefully interpret inhexent
expressions in the output result, which are specified in
terms of the testers resources. The acquisition range
specification has been introduced for realizing this
method. An example is shown in Figure 3.
(1) pPdatalogl(log1);
(2) pPmainjrogram(check);
(3) Wtat-number( 100,l,data);
FFget~scanE(devX,rl);
FFget~scanff(devx,reg3_21;
Fpget-scanff (vX,gTCK) ; by referring to the status bits, which are provided by the
FFget-scanff (devX,r2);
(3) pPt~t_number(200,2.all;
[
(4) FFget-scanff(devX,BCR2);
FFget-scanff(devX,LASTl);
Figure3 Example of Acquisition Range Information
In Figure 3, the file name of the scan data log 1 is
specified on line (1) and the test program name is
specified on line (2). The test number of the scan test is
specified on line (3) and the scan chain name to be
acquired in the test number is specified on line (4)The
acquisition range information is necessary for pro-
cessing the failure data. The processed data is output by
the acquisition range information generation module.
4 Failure Data Acquisition
After the preparations mentioned above are
completed, the actual scan test can be made using an
LSI tester, for identification of the discrepant scan Flip
Flop(s). The following information is generated.
4.1 Generation of Scan Data Log 1
Paper 17.1
456
At Step C of Figure 2. the scan data log 1generation
module is executed to get the scan data log. Lwalizing
the discrepant scan Flip Flop is done in this execution
result. The scan data log 1 generation module sorts the
data of the discrepant sean Flip Flops according to the
scan chain to which they belong. This information is
written into the log file. As a result, readability can be
improved.
To acquire all of the fail data, an automatic control
method has been designed to overcome the limited
failure memory built into an LSI tester, making this
limited resource an effectively infinite resource. This
method is guaranteedto operate completely,even if the
capacity of the Testers failure memory is exceeded by
the number of actual failures. This is common when a
scan testis carried out using longer test patterns
generated by an A W G tool.
Figure 4 shows how to acquire all of the failure data
using the automatic control method. In the figure, N
words of failure memory are used to stack the failure
data. As shown in Figure 4 (a), at the 1st test rwn, the
data of N failures sequentially follows the acquisition
from start point C. based on the data stored in the failure
memory. Then. N failure data are written into the data
log 1 file using the data processing of the data log 1
generation module. Then, the data log 1 generation
module determines the necessity of the second test run
tester. This is for checking out whether the numbers of
failures have exceeded N. In this case, the data log 1
generation module requests the tester to make the next
test run,in order to recognizes more than N failures
(Figure 4(b)). This results in data from the next N
failures, as shown in Figure4(c). The datalog 1
generation module then transfers the data on the second
set of failures from the tester into the data log 1 file as a
#2 data. In this way, the required number of failure data
are collected by automated repetition of the test pattern.
Thoughboth the output from the scan datalog 1
generation module and the one from the scan data log 2
generation module are of the form of the scan data log,
the former is the data log acquired from an LSI tester
while the latter is the log data given by merging the
additional information into it. When failures can be
easily localized by the content of scan data log 1,it may
not be necessary to use the scan data log 2 generation
module.
4.2 Generation of Scan Data Log 2
The logging of the discrepant scan Flip Flops from
every scan chain is achieved by executing above-
mentioned Step C. The next step is executed to simplify
the merging additional information into the result given
fromStepC.Forthispurpose. the scan data log 2
generation module has been implemented (Step D of
Figure 2).
Additional information is roughly divided into time
and logical name information about the discrepant scan
Flip Flops. Time information is given by converting the
test pattern address where a failure occurred into a red
time value (Figure 5). In addition, strobe timing is also
provided.
We defined the failure time Time3 as follows:
Time-F = Time-A + Time-%
(1)
Time-A is the total timeup to the start of the cycle
corresponding to the failure address of interest. Time-B
is the strobe timing of that failure address. The
computation of 'Iime-A is based on the test period 121
of each test patkm cycle, and the test pattern count

(b) Automatic Start of Next Run

(c) 2nd Test Run

I
atie Control Meth

Paper 17.1
457
 Pattern start
Evample of Timing Set

Time-A Total time up to starting edge

timing of failure address
Time-A %e-B
F IC l3me-B: Strobe timing at ahin&: set

ion

0 [ 2 ] , which number of executions of each
individual test vector. In this way, test patterns are
expanded flatly along a time axis.
N as a unique cell name or net name. Although the
TimeP = R, x C, (i=1,2,3,...,PI)
k- 1
Ri is the test rate for timing set i ,Ci is the total
number of timing sets and N is the maximum number of
timing set for the pattern count (PCNT-1) variable. All
of information to calculate Tie-A along the equation
(2) can be obtained from the tester. Because the time
information is used to specify the failure it is possible to
compare the fail information with the simulation
waveforms for all of the fail timings.
The logical name of the discrepant scan Flilp Flop is
localizedby the logical name in the circuit design, such
(2)
location of discrepant scan Flip Hop in the scan chain
in the scan data log 1 it is shown by the
numerical value. The logical name information should
be added into the scan data log 2 to be easily compre-
hensible by the device designer. For this, the file called
Scan Hip Hop List which describes the logicalname of
all scan Flip Hops built in the device can be fecl into the
scan data log 2 generation module externally. The Scan
Flip Hop List can be described by this newly defined
format in an ASCII file.

STEV INDEX PCNT DAT PIN RATE [PSI (STRB[PSI 1

#OOOOOC(#OOOOOA) # 0 0 0 0 0 5 ( # 0 0 0 0 0 5 ) #OOOOOOlD H(L) 030 (030) 20,000,000 ( 8 0 0 , 0 0 0 )
#OOOOOD (#OOOOOA) #000001(#000006) #OOOOOOlE 2 (L) 030 (030) 21,000,000 (800,000)
#OOOOOE (#OOOOOA) l000002 ( # 0 0 0 0 0 8 ) # O O O O O O Z O H (L) 030 (030) 23,000,000 ( 8 0 0 , 0 0 0 )
#000013 (#OOOOOF) #OOOOOl (#OOOOOl) #00000034 H (L) 015 (015) 33,500,000 (400,000)

Chain-Name: dewX,reg3-2,15,38(38) ,15 (15)

STEV INDEX PCNT DAT FP "l'E[ps] (STRB[ps]) [FF,CELL,ENA]

#OOOOOS (#OOOOOS) #000002(#000002) #OOOOOOOE H (L) 001-00001 7,000,000 ( 8 0 0 , 0 0 0 ) [fl-1, cl-l,el-l]
#000020 (#OOOOlC) #OOOOOl (#OOOOOl) #00000050 H (L) 002-00001 47,500,000 (400,000) [fl 1,cl 1,el I]
iboooo7~( ~ 0 0 0 0 ~ 5#oooooi
) (~oooooi)#OOOOOOECH (L) 003-ooooi 172,500,ooo ( 8 0 0 , 0 0 0 ) [i-1, Ci-i,Z-il
#00007F (#000065) # 0 0 0 0 0 3 (#000003) #OOOOOOEE H (L) 003-00003 174,500,000 (800,000) [fl-3, c1-3,e1-3]
(1) 1000080 (#000065) #000001(#000007) #OOOOOOF2 2 (L) 003-00007 178,500,000 ( 8 0 0 , 0 0 0 ) [fl 7,cl 7,al 71
#000081(#000065) #000002 (#000009) #000000F4 H (L) 003-00009 180,500,000 ( 8 0 0 , 0 0 0 ) [fl~9,cl~9,el~9l

Paper 17.1
458
 The Scan data log 2 generation module outputs data
classiiied into the scan operation fail data, and the
functional failure data from other internal logical
operations.Figure 6 showsthe example of scan data log
2. In this figure, the upper part shows the internal
logical failures, while the lower part shows the scan
failures. The information on the discrepant scan Flip
Flop is included in scan operation mode data. Each line
contains one failure. The firsthalf of the line shows test
pattern address, and the expected value. The time
information is shown in the colum with the header
named RATE.The numerical value of time is given by
Ips resolution. As shown in the figure, the line named
ChainName shows the scan chain name, while the
column with the header named Flip Flop is added to
show the failure data in the scan operation mode. In this
example, the scan chain name of interest is reg3-2. In
addition to the scan chain name, the devicename is aIso
indicated by devx in this example. The data shown at
the Flip Flop column containsthe repetition number of
this chain and the location of the discrepant scan Flip
Flop. 003-oooO7 at the line (1) means that the failure
occurred during the 3rd repetition of this chain, and the
discrepant scan Flip Flop is located at the 7th stage of
the scan chain. Various logical names concerning the
scan Flip Flop being localized, such as a scan cell name,
are shown in [ I put at the end of the line. In the figure,
ff. cell and h a mean the cell type,scan cell name Figure8, reg5 in which the scan Flip Flops are
and the node name of enable port, respectively.
This scan data log 2 becomesthe final output result
of this system. It can be utilized with a variety of
analysis techniques.One can transfer the scan data log
2 data to a CAD-linked E-Beam prober 171 to identify a
faulty primitive cell or transistor within the scan chain
of inmest. In this case, the fault backtracking can be
made using the data input node of the scan Flip Flop.
The source of the fault can be found in a short time.
It is also possible to feed the scan data log2 data back
to the users fault simulator to determine the frdt
source. From this point of view, the contribution level
of this system to testing and debugging is quite high.
5 Extended function to BSDL
To use the Scan Analysis System with designs other
than JTAG, we enabled b e description of scan circuit
information concerning those test logic architectures.
The method has been introduced by defining additional
syntax as a subset of BSDL. For example, devices
designed with scan using a special external pin. other
than DIED0 of the JTAG circuit, can be defined by
Using this additional syntax as shown in Figure 7. This
description means that the scan chain called reg3
CLKl
D(2)
40)
TDI TDO
TCK
attribute IAL-FU3GISTER of devX :entity is
reg3[8OO](D( l),D(2),CLKl),&
regX[5OOI(Q(l),Q(2).T~;
Figure 7 Scan Circuit with Special Extemal Pins
Other Than TDUTDO
consists of 800 stages of scan Flip Flops, and has an
extra external input terminal and output terminal, port
D(1) and D(2) respectively. The shift clock is at the port
CLKl. In this case, TCK is declared as a shift clock in
re@ to scan the circuit. It is also possible to scan it by
synchronizing with SHIFT-DR in the TAP status of
JTAG.
Moreover. the chain name can be dehed by
dividing the scan chain further as shown in Figure 8. In
connected in series is divided into 2 parts, that is, r l
containing50 stagesof scan Flip Flop and 12containing
150 stages, though reg5 is composed of the 200 stages
of scan Flip Flop.
If several instructions are required to access a scan
chain, our subset of BSDL eflables the definition for it,
too. as shown in Figure 9. The data in register reg1 is
accessed by setting the instruction opcode opl in
JTAGs instsuction register (left figure in Figure 9) first,
and then the data selreg2 to select reg2 is given to reg 1
(center figure in Figure 9). As a result, reg2 is assigned
as the scan chain to be tested (right figure in Figure 9).
I r2 rl I
attribute REGISTEX-ACCESS-2 of devX : entity is
reg5[200(r1[501+r2[1501)1(opcode>;
Figure 8 Description to Divide Scan Chain
Paper 17.1
459
 TDI
TCK
attribute REGISTER-ACCESS-2 of devX : entity is
reg1[5l(opl),&
reg2[1001(ogl+DR selreg2);
Figure 9 Selecting Scan Chain by Multi-Description
Not discussed above is the definition for gaining
access to a scan chain having a particular external
control pin and the mode definitions such as Enable/
Disable.
As mentioned above, the extension to BSDL that the
authors showed here enables the analysis of different
kinds of devices with scan designs other than JTAG.
However, our extension is not a standardized one. It
may not be possible for certain users to employ our
extension because of the scan design they are using. We
believe that the logic of the scan testing can be designed
without specialized skills, which is one of the features
desirable with scan testing. So, we suggest that semi-
s original scan design style can be
standardized in many ways using this extended
function.
A new test technique to localize failures of devices
with scan designs easily and quickly using an existing
LSI tester was prop&. Though much time has been
spent up until now to localize the discrepant scan Flip
Flops, this technique allows you to obtain such Mor-
mation promptly using the scan design data. The
authors have developed the Scan Analysis System
supporting standardized BSDL, and an extended BSDL
was specified to confirm the effectiveness of this
technique. Restrictions caused by the limitation of
tester resources is solved in this system. Right now, this
system is under benchmark testing at a customer site.
Extension of BSDL shown in this paper enabled test
and analysis of different devices having scan design
other than JTAG. The authors are thinking that this
extension can be applied to scan devices from many of
Paper 17.1
460
TDI TDO
TCK
semiconductor makers. Enhancementof the extensi-
bility of our proposed description and application to
a variety of scan devices are planned for future work.
Acknowledgments
The authors would Iike to thank Yoshiyuki Suzuki,
Takakiyo Inoue, Fumio Iijima and Kunihiko Qhkuma
for their technical advice. We would also like to thank
Atsuo Niinuma and Taka0 Tadokoro for their helpful
conunents and suggestions.
References
111 W. M. Needham. Designers Guide to Testable
ASIC Devices, Van Nostrand Reinhold. 1991.
C2l For example, 3324 VLSI Test System Product
Description, ADVANTEST CORPORATION,
1990.
131 IEEE Standard 1149.1-1990, IEJEE Standard Test
Access Port and Boundary-Scan Architecture,
E Standards Board, May, 1990.
, et al., A Language for Describing
an Devices, Roc. ITC. pp.222-234,
C5l IEEE Standard 11 1994,Supplement to IEEE
Std 1149.1-1990, Standard Test Access Port
and Boundary-Scan Architecture, IEEE Standards
Board, Sep., 1994.
161 User Interface Specification of Scan Analysys
Tool, ADVANmT internal report, 1996.
171 Novel CAD Layout Image-Based Silicon
Debugging Approach with E-Beam Prober, To be
published. 1996.