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Features Description
n 67.6dBFS SNR The LTC2153-12 is a 310Msps 12-bit A/D converter
n 88dB SFDR designed for digitizing high frequency, wide dynamic
n Low Power: 378mW Total range signals. It is perfect for demanding communications
n Single 1.8V Supply applications with AC performance that includes 67.6dB
n DDR LVDS Outputs SNR and 88dB spurious free dynamic range (SFDR). The
n 1.32V
P-P Input Range 1.25GHz input bandwidth allows the ADC to undersample
n 1.25GHz Full Power Bandwidth S/H high frequencies with good performance. The latency is
n Optional Clock Duty Cycle Stabilizer only six clock cycles.
n Low Power Sleep and Nap Modes
DC specs include 0.6LSB INL (typ), 0.1LSB DNL (typ)
n Serial SPI Port for Configuration
and no missing codes over temperature. The transition
n Pin-Compatible 12-Bit Versions
noise is 0.6LSBRMS.
n 40-Lead (6mm 6mm) QFN Package
The digital outputs are double data rate (DDR) LVDS.
Applications The ENC+ and ENC inputs can be driven differentially with
n Communications a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
n Cellular Basestations clock duty cycle stabilizer allows high performance at full
n Software Defined Radios speed for a wide range of clock duty cycles.
n Medical Imaging L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
n High Definition Video Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
LTC2153-12 32K Point 2-Tone FFT,
fIN = 71MHz and 69MHz, 310Msps
VDD
0
OVDD
D10_11 20
12-BIT
ANALOG CORRECTION OUTPUT DDR
S/H PIPELINED
AMPLITUDE (dBFS)
CLOCK/DUTY OGND 80
CLOCK CYCLE
CONTROL
GND 100
215312 TA01a
120
0 20 40 60 80 100 120 140
FREQUENCY (MHz)
215312 TA01b
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PAR/SER
D10_11+
D10_11
D8_9+
D8_9
GND
SDO
Analog Input Voltage
SCK
SDI
CS
AIN+, AIN , PAR/SER, 40 39 38 37 36 35 34 33 32 31
ENC+
ENC
GND
OF
OF +
NC
NC
D0_1+
OVDD
D0_1
UJ PACKAGE
40-LEAD (6mm 6mm) PLASTIC QFN
TJMAX = 150C, JA = 33C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2153CUJ-12#PBF LTC2153CUJ-12#TRPBF LTC2153UJ-12 40-Lead (6mm 6mm) Plastic QFN 0C to 70C
LTC2153IUJ-12#PBF LTC2153IUJ-12#TRPBF LTC2153UJ-12 40-Lead (6mm 6mm) Plastic QFN 40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
215312fa
Analog
Input The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ AIN) 1.74V < VDD < 1.9V 1.32 VP-P
VIN(CM) Analog Input Common Mode (AIN+ + AIN)/2 Differential Analog Input (Note 8) l VCM 20mV VCM VCM + 20mV V
VSENSE External Voltage Reference Applied to SENSE External Reference Mode l 1.230 1.250 1.270 V
IIN1 Analog Input Leakage Current 0 < AIN+, AIN < VDD, No Encode l 1 1 A
IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l 1 1 A
IIN3 SENSE Input Leakage Current 1.23V < SENSE < 1.27V l 1 1 A
tAP Sample-and-Hold Acquisition Delay Time 1 ns
tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 psRMS
CMRR Analog Input Common Mode Rejection Ratio 75 dB
BW-3B Full-Power Bandwidth 1250 MHz
Dynamic Accuracy
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25C. AIN = 1dBFS. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 15MHz Input 67.6 dBFS
70MHz Input 67.1 dBFS
140MHz Input l 65.8 67.0 dBFS
SFDR Spurious Free Dynamic Range 2nd or 3rd 15MHz Input 88 dBFS
Harmonic 70MHz Input 85 dBFS
140MHz Input l 70 80 dBFS
Spurious Free Dynamic Range 4th Harmonic 15MHz Input 98 dBFS
or Higher 70MHz Input 95 dBFS
140MHz Input l 80 90 dBFS
S/(N+D) Signal-to-Noise Plus Distortion Ratio 15MHz Input 67.1 dBFS
70MHz Input 67.0 dBFS
140MHz Input l 65 66.9 dBFS
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Power
Requirements The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 9) l 1.74 1.8 1.9 V
OVDD Output Supply Voltage (Note 9) l 1.74 1.8 1.9 V
IVDD Analog Supply Current l 182 205 mA
IOVDD Digital Supply Current 1.75mA LVDS Mode l 28 34 mA
3.5mA LVDS Mode l 48.5 52 mA
PDISS Power Dissipation 1.75mA LVDS Mode l 378 430 mW
3.5mA LVDS Mode l 415 463 mW
PSLEEP Sleep Mode Power Clock Disabled <5 mW
Clocked at fS(MAX) <5 mW
PNAP Nap Mode Power Clocked at fS(MAX) 124 mW
Digital
Inputs And Outputs The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC)
VID Differential Input Voltage (Note 8) l 0.2 V
VICM Common Mode Input Voltage Internally Set 1.2 V
Externally Set (Note 8) l 1.1 1.5 V
RIN Input Resistance (See Figure 2) 10 k
CIN Input Capacitance (Note 8) 2 pF
DIGITAL INPUTS (CS, SDI, SCK)
VIH High Level Input Voltage VDD = 1.8V l 1.3 V
VIL Low Level Input Voltage VDD = 1.8V l 0.6 V
IIN Input Current VIN = 0V to 3.6V l 10 10 A
CIN Input Capacitance (Note 8) 3 pF
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200
IOH Logic High Output Leakage Current SDO = 0V to 3.6V l 10 10 A
COUT Output Capacitance (Note 8) 4 pF
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Timing
Characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 9) l 10 310 MHz
tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 1.5 1.61 50 ns
Duty Cycle Stabilizer On l 1.2 1.61 50 ns
tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 1.5 1.61 50 ns
Duty Cycle Stabilizer On l 1.2 1.61 50 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: VDD = OVDD = 1.8V, fSAMPLE = 310MHz, differential ENC+/ENC =
may cause permanent damage to the device. Exposure to any Absolute 2VP-P sine wave, input range = 1.32VP-P with differential drive, unless
Maximum Rating condition for extended periods may affect device otherwise noted.
reliability and lifetime. Note 6: Integral nonlinearity is defined as the deviation of a code from a
Note 2: All voltage values are with respect to GND with GND and OGND best fit straight line to the transfer curve. The deviation is measured from
shorted (unless otherwise noted). the center of the quantization band.
Note 3: When these pin voltages are taken below GND or above VDD, they Note 7: Offset error is the offset voltage measured from 0.5LSB when the
will be clamped by internal diodes. This product can handle input currents output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2s
of greater than 100mA below GND or above VDD without latchup. complement output mode.
Note 4: When these pin voltages are taken below GND they will be Note 8: Guaranteed by design, not subject to test.
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input Note 9: Recommended operating conditions.
currents of greater than 100mA below GND without latchup.
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1.5
20
1.0 0.25
AMPLITUDE (dBFS)
DNL ERROR (LSB)
40
INL ERROR (LSB)
0.5
0 0 60
0.5
80
1.0 0.25
100
1.5
LTC2153-12: 32K Point FFT, LTC2153-12: 32K Point FFT, LTC2153-12: 32K Point FFT,
fIN = 70MHz, 1dBFS, 310Msps fIN = 150MHz, 1dBFS, 310Msps fIN = 185MHz, 1dBFS, 310Msps
0 0 0
20 20 20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
40 40 40
60 60 60
80 80 80
LTC2153-12: 32K Point FFT, LTC2153-12: 32K Point FFT, LTC2153-12: 32K Point FFT,
fIN = 223MHz, 1dBFS, 310Msps fIN = 383MHz, 1dBFS, 310Msps fIN = 421MHz, 1dBFS, 310Msps
0 0 0
20 20 20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
40 40 40
60 60 60
80 80 80
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20 20 20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
40 40 40
60 60 60
80 80 80
14000 100 60
dBFS
12000 50
80
SFDR (dBFS)
SNR (dBFS)
10000
COUNT
40
60 dBc
8000 dBc
30
6000 40
20
4000
20 10
2000
0 0 0
2052 2056 2060 2064 90 80 70 60 50 40 30 20 10 0 70 60 50 40 30 20 10 0
OUTPUT CODE AMPLITUDE (dBFS) AMPLITUDE (dBFS)
215312 G13 215312 G14 215312 G15
70 65
60
SFDR (dBFS)
SNR (dBFS)
60
50
40 55
30
50
20
45
10
0 40
0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz) 215312 G16
INPUT FREQUENCY (MHz) 215312 G17
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IOVDD (mA)
IVDD (mA)
170 40
2.5
160 35
LVDS CURRENT 3.0
30
150 1.75mA
25 3.5
140 4.0
20
130 15 4.5
0 62 124 186 248 310 0 50 100 150 200 250 300 100 1000
SAMPLE RATE (Msps) SAMPLE RATE (Msps) INPUT FREQUENCY (MHz)
215312 G18 215312 G19 215312 G20
Pin Functions
VDD (Pins 1, 2): 1.8V Analog Power Supply. Bypass to ENC (Pin 12): Encode Complement Input. Conversion
ground with 0.1F ceramic capacitor. Pins 1, 2 can share starts on the falling edge.
a bypass capacitor. NC (Pins 16, 17): Not Connected.
GND (Pins 3, 6, 10, 13, 35, Exposed Pad Pin 41): ADC OVDD (Pins 20, 30): 1.8V Output Driver Supply. Bypass
Power Ground. The exposed pad must be soldered to the each pin to ground with separate 0.1F ceramic capacitors.
PCB ground.
OGND (Pin 21): LVDS Driver Ground.
AIN+ (Pin 4): Positive Differential Analog Input.
SDO (Pin 36): Serial Interface Data Output. In serial
AIN (Pin 5): Negative Differential Analog Input. programming mode, (PAR/SER = 0V), SDO is the optional
SENSE (Pin 7): Reference Programming Pin. Connecting serial interface data output. Data on SDO is read back from
SENSE to VDD selects the internal reference and a 0.66V the mode control registers and can be latched on the falling
input range. An external reference between 1.23V and edge of SCK. SDO is an open-drain N-channel MOSFET
1.27V applied to SENSE selects an input range of 0.528 output that requires an external 2k pull-up resistor from
VSENSE. 1.8V to 3.3V. If readback from the mode control registers
is not needed, the pull-up resistor is not necessary and
VREF (Pin 8): Reference Voltage Output. Bypass to ground
SDO can be left unconnected.
with a 2.2F ceramic capacitor. Nominally 1.25V.
SDI (Pin 37): Serial Interface Data Input. In serial pro-
VCM (Pin 9): Common Mode Bias Output; nominally equal
gramming mode, (PAR/SER = 0V), SDI is the serial
to 0.439 VDD. VCM should be used to bias the common
interface data input. Data on SDI is clocked into the mode
mode of the analog inputs. Bypass to ground with a 0.1F
control registers on the rising edge of SCK. In parallel
ceramic capacitor.
programming mode (PAR/SER = VDD), SDI selects 3.5mA
ENC+ (Pin 11): Encode Input. Conversion starts on the or 1.75mA LVDS output current (see Table 2).
rising edge.
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D10_11
12-BIT
ANALOG CORRECTION OUTPUT DDR
S/H PIPELINED
INPUT LOGIC DRIVERS LVDS
ADC
D0_1
VCM
0.1F VCM OGND
BUFFER
BUFFER
GND
CLOCK/DUTY CS
CLOCK SCK
CYCLE CONTROL
SPI SDI
VREF SDO
2.2F PAR/SER
1.25V
REFERENCE
GND GND
RANGE
SENSE SELECT
215312 F01
tAP
N N+3
N+2
N+1
tH tL
ENC
ENC+
CLKOUT+
CLKOUT
tC
D0_1
D0N-6 D1N-6 D0N-5 D1N-5 D0N-4 D1N-4
D0_1+
tD
D10_11
D10N-6 D11N-6 D10N-5 D11N-5 D10N-4 D11N-4
D10_11+
OF
OFN-6 INVALID OFN-5 INVALID OFN-4 INVALID
OF+
215312 TD01
tSKEW
CS
SCK
tDO
SDI R/W A6 A5 A4 A3 A2 A1 A0 XX XX XX XX XX XX XX XX
SDO D7 D6 D5 D4 D3 D2 D1 D0
HIGH IMPEDANCE
CS
SCK
SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SDO
215312 TD02
HIGH IMPEDANCE
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10
VCM
0.1F
0.1F LTC2153-12
T1 4.7
LTC2153-12 IN 1:1 AIN+
VDD
25
RON
2pF 10pF
20
0.1F
AIN+ 25
4.7
2pF AIN
VDD
T1: MACOM ETC1-1T 215312 F03
RON 2pF
20
AIN Figure 3. Analog Input Circuit Using a Transformer.
2pF Recommended for Input Frequencies from 5MHz to 70MHz
VDD
10
VCM
1.2V 0.1F
0.1F LTC2153-12
4.7
10k IN AIN+
ENC+
45
ENC 100
0.1F
45
0.1F
4.7
AIN
215312 F02 T2: MABA T1: WBC1-1L
007159-000000 215312 F04
50 50
0.1F Encode Input
3pF
LTC2153-12
The signal quality of the encode inputs strongly affects
0.1F
4.7 the A/D noise performance. The encode inputs should
INPUT AIN+ be treated as analog signalsdo not route them next to
3pF
0.1F
4.7 digital traces on the circuit board.
AIN
3pF The encode inputs are internally biased to 1.2V through
215312 F06
10k equivalent resistance (Figure 8). If the common mode
of the driver is within 1.1V to 1.5V, it is possible to drive
Figure 6. Front-End Circuit Using a High the encode inputs directly. Otherwise a transformer or
Speed Differential Amplifier
coupling capacitors are needed (Figures 9 and 10). The
maximum (peak) voltage of the input signal should never
exceed VDD +0.1V or go below 0.1V.
LTC2153-12 VDD
LTC2153-12
VREF 5
1.25V 1.2V
2.2F
10k
SCALER/ ADC ENC+
BUFFER REFERENCE
SENSE
SENSE
DETECTOR
ENC
LTC2153-12 VDD
1.2V
0.1F 10k
50
100
0.1F 50
T1: MACOM
ETC1-1-13 215312 F09
LTC2153-12 VDD
1.2V
0.1F 10k
ENC+
PECL OR
LVDS INPUT 100
0.1F
ENC
215312 F10
ENC+
D0-D13, OF
PHASE MODE CONTROL BITS
SHIFT CLKINV CLKPHASE1 CLKPHASE0
0 0 0 0
45 0 0 1
90 0 1 0
135 0 1 1
CLKOUT+
180 1 0 0
225 1 0 1
270 1 1 0
315 1 1 1
215312 F11
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PC BOARD
CLKOUT CLKOUT CLKOUT FPGA
OF OF OF
D11 D11/D0
D11/D0
LTC2153-12 D11
D10 D10/D0
D10/D0
D10
RANDOMIZER
ON D1/D0
D1
D1/D0
D1
D0
D0
D0 D0
Figure 12. Functional Equivalent of Digital Output Randomizer Figure 13. Decoding a Randomized Digital Output Signal
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All 0s: All outputs are 0 Wake-up time from nap mode is guaranteed only if the
clock is kept running, otherwise sleep mode wake-up
Alternating: Outputs change from all 1s to all 0s on conditions apply.
alternating samples
Nap mode is enabled by setting register A1 in the serial
Checkerboard: Outputs change from 1010101010101 programming mode.
to 0101010101010 on alternating samples.
The digital output test patterns are enabled by serially DEVICE PROGRAMMING MODES
programming mode control register A4. When enabled, The operating modes of the LTC2153-12 can be pro-
the test patterns override all other formatting modes: grammed by either a parallel interface or a simple serial
2s complement, randomizer, alternate-bit polarity. interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
Output Disable
is more limited and can only program some of the more
The digital outputs may be disabled by serially program- commonly used modes.
ming mode control register A3. All digital outputs includ-
ing OF and CLKOUT are disabled. The high impedance Parallel Programming Mode
disabled state is intended for long periods of inactivity, To use the parallel programming mode, PAR/SER should
it is not designed for multiplexing the data bus between be tied to VDD. The CS, SCK and SDI pins are binary logic
multiple converters. inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V
Sleep Mode CMOS logic. Table 2 shows the modes set by CS, SCK
The A/D may be placed in sleep mode to conserve power. and SDI.
In sleep mode the entire A/D converter is powered down, Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
resulting in < 5mW power consumption. If the encode PIN DESCRIPTION
input signal is not disabled, the power consumption will CS Clock Duty Cycle Stabilizer Control Bit
be higher (up to 5mW at 310Msps). Sleep mode is enabled 0 = Clock Duty Cycle Stabilizer Off
by mode control register A1 (serial programming mode), 1 = Clock Duty Cycle Stabilizer On
or by SCK (parallel programming mode). SCK Power Down Control Bit
The amount of time required to recover from sleep mode 0 = Normal Operation
depends on the size of the bypass capacitor on VREF . For 1 = Sleep Mode (entire ADC is powered down)
the suggested value in Figure 1, the A/D will stabilize after SDI LVDS Current Selection Bit
0.1ms + 2500 tp where tp is the period of the sampling 0 = 3.5mA LVDS Current Mode
clock. 1 = 1.75mA LVDS Current Mode
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SDO
SDI
SCK
CS
PAR/SER
D10_11+
D10_11
D8_9+
D8_9
VDD
0.2F
TP3 R9 OVDD
PAR/SER 40
CS 39
SCK 38
SDI 37
SDO 36
GND 35
D10_11+ 34
D10_11 33
D8_9+ 32
D8_9 31
1k 0.1F
SENSE
C13 1
VDD 30
2.2F OVDD
2
VDD 29
R14 3 D6_7+ D6_7+
GND 28
10
4 D6_7 D6_7
AINA+ AINA+ 27
5 CLKOUT+ CLKOUT+
AINA 26
R16 6 LTC2153-12 CLKOUT CLKOUT
R19 100 GND 25
SENSE 7 D4_5+ D4_5+
10 SENSE 24
AINA
8 D4_5 D4_5
VREF 23
9 D2_3+ D2_3+
C16 VCM 22
2.2F 10 D2_3 D2_3
10 GND 21
41 OGND
VCM GND
18 D0_1
19 D0_1+
DD
11 CLK+
12 CLK
13 GND
14 OF
15 OF +
C21
16 NC
17 NC
20 OV
0.1F
OVDD
0.1F
OF
OF +
NC
NC
D0_1
D0_1+
215312 TA02
0.1F 0.1F
100
CLK+ CLK
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UJ Package
40-Lead Plastic QFN (6mm 6mm)
(Reference LTC DWG # 05-08-1728 Rev )
0.70 0.05
6.50 0.05
5.10 0.05
4.42 0.05 4.50 0.05
(4 SIDES)
4.42 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
4.42 0.10
215312fa
215312fa
23
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection of itsinformation www.linear.com/LTC2153-12
circuits as described herein will not infringe on existing patent rights.
LTC2153-12
Typical Application
VDD LTC2153-12: 32K Point 2-Tone FFT,
OVDD fIN = 71MHz and 69MHz, 310Msps
0
D10_11
12-BIT 20
ANALOG CORRECTION OUTPUT DDR
S/H PIPELINED
INPUT LOGIC DRIVERS LVDS
ADC
AMPLITUDE (dBFS)
D0_1 40
60
CLOCK/DUTY OGND
CLOCK CYCLE
CONTROL 80
GND
215312 TA03a
100
120
0 20 40 60 80 100 120
FREQUENCY (MHz)
215312 TA03b
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215312fa
24
Linear Technology Corporation LT 1214 REV A PRINTED IN USA