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Sequential Circuits I

Sequential Elements
Timing
Examples

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Set
Sensor
Memory On Off
Alarm
element
Reset

Figure 7.1. Control of an alarm system.

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A B

Figure 7.2. A simple memory element.

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Load

A B
Data Output
TG1

TG2

Figure 7.3. A controlled memory element.

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Reset

Set Q

Figure 7.4. A memory element with NOR gates.

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R S R Qa Qb
Qa
0 0 0/1 1/0 (no change)
0 1 0 1
1 0 1 0
Qb 1 1 0 0
S

(a) Circuit (b) Truth table

t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

1
R
0

1
S
0

1
Qa ?
0

1
Qb ?
0

Time
(c) Timing diagram

Figure 7.5. A latch built with NOR gates.

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Figure 7.6. Gated SR

latch.

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S
Q

Clk

Q
R

Figure 7.7. Gated SR latch with NAND gates.

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Figure 7.8. Gated

D latch.

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t su
th

Clk

Figure 7.9. Setup and hold times.

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Master Slave U M & A saxeT
Qm Qs
D D Q D Q Q

Clock Clk Q Clk Q Q

(a) Circuit

Clock

Figure 7.10. D
Master-slave D Qm
flip-flop. Q = Qs

(b) Timing
diagram

D Q

(c) Graphical symbol

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1 P3

P1
2
5 Q

Clock

P2 6 Q
3

D Q

4 P4 Clock Q
D

(a) Circuit (b) Graphical symbol

Figure 7.11. A positive-edge-triggered D flip-flop.

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D D Q Qa

Clock Clk Q Qa

D Q Qb
Figure 7.12. Q Qb
Comparison of
level-sensitive D Q Qc
and edge-trigged
Q Qc
D storage
elements. (a) Circuit

Clock

Qa

Qb

Qc

(b) Timing diagram

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Preset

D
Q

Clock

Clear

(a) Circuit

Preset

D Q

Clear

(b) Graphical symbol

Figure 7.13. Master-slave D flip-flop with Clear and Preset.

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D D Q Qa

Clock Clk Q Qa

D Q Qb
Figure 7.14. Positive-edge- Q Qb
triggered D flip-flop with
Clear and Preset. D Q Qc

Q Qc

(a) Circuit

Clock

Qa

Qb

Qc

(b) Timing diagram

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Figure 7.15. Timing for a flip-flop.

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D Q Q

T
Q Q

Clock
Figure 7.16. T
(a) Circuit
flip-flop.

T Q( t + 1) T Q
0 Q( t )
1 Q( t ) Q

(b) Truth table (c) Graphical symbol

Clock

Fundamentals of Digital Logic Brown-Vranesic

(d) Timing diagram
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J
D Q Q
K Q Q

Clock

(a) Circuit

J K Q ( t + 1)
0 0 Q (t) J Q
0 1 0
1 0 1
K Q
1 1 Q (t )

(b) Truth table (c) Graphical symbol

Figure 7.17. JK flip-flop.

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Q1 Q2 Q3 Q4
In D Q D Q D Q D Q Out

Clock Q Q Q Q

(a) Circuit

In Q1 Q2 Q3 Q4 = Out
t0 1 0 0 0 0
t1 0 1 0 0 0
t2 1 0 1 0 0
t3 1 1 0 1 0
t4 1 1 1 0 1
t5 0 1 1 1 0
t6 0 0 1 1 1
t7 0 0 0 1 1

(b) A sample sequence

Figure 7.18. A simple shift register.

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Parallel output

Q3 Q2 Q1 Q0

D Q D Q D Q D Q

Q Q Q Q

Serial Clock
input Shift/Load Parallel input

Figure 7.19. Parallel-access shift register.

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1 T Q T Q T Q

Clock Q Q Q

Q0 Q1 Q2

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 6 7 0

(b) Timing diagram

Figure 7.20. A three-bit up-counter.

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1 T Q T Q T Q

Clock Q Q Q

Q0 Q1 Q2

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 7 6 5 4 3 2 1 0

(b) Timing diagram

Figure 7.21. A three-bit down-counter.

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Clock cycle Q2 Q1 Q0
Q1 changes
0 0 0 0
1 0 0 1 Q2 changes
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

Table 7.1. Derivation of the synchronous up-counter.

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1 T Q T Q T Q T Q
Q0 Q1 Q2 Q3
Clock Q Q Q Q

(a) Circuit

Clock

Q0

Q1

Q2

Q3

Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1

(b) Timing diagram

Figure 7.22. A four-bit synchronous up-counter.

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Enable T Q T Q T Q T Q

Clock Q Q Q Q

Clear

Figure 7.23. Inclusion of Enable and Clear capability.

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0
Enable D Q Q0
D0 1

0
1 D Q Q1
D1
Q

0
Figure 7.25. A 1 D Q Q2
D2
counter with parallel- Q
load capability.

0
1 D Q Q3
D3
Q

Output
carry
Load
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Clock
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1 Enable
0 D0 Q0
0 D1 Q1
0 D2 Q2
Load
Clock
Clock

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 0 1

(b) Timing diagram

Figure 7.26. A modulo-6 counter with synchronous reset.

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1 Enable
0 D0 Q0
0 D1 Q1
BCD0
0 D2 Q2
0 D3 Q3

Load
Clock
Clock

Clear Enable
0 D0 Q0
0 D1 Q1
BCD 1
0 D2 Q2
0 D3 Q3

Load
Clock

Figure 7.28. A two-digit BCD counter.

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Start

D Q D Q D Q

Q Q Q

Clock

(a) An n -bit ring counter

Figure 7.29. Ring Q0 Q1 Q2 Q3

counter.
y0 y1 y2 y3

2-to-4 decoder
w1 w0 En

Q1 Q0
Clock Clock
Two-bit up-counter

Start Clear

Fundamentals of Digital Logic Brown-Vranesic (b) A four-bit ring counter

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Data
Clock

Latch

Figure 7.32. Gated D latch generated by CAD tools.

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