SSRG International Journal of Electronics and Communication Engineering (SSRG-IJECE) Volume 3 Issue 8 August 2016

A Review on Bi-CMOS Technology

Abdurrahman#1, Amit Jain#2
#1-B.tech final year student, #2-Assistant Professor
Department of Electronics and Communication Engineering
Poornima Institute of Engineering & Technology, Jaipur, Rajasthan, India

Abstract-At present time speed is a big issue for the
electronics technology. If speed is increasing then
performance of the electronics devices are
increasing. In the electronics field we use the
semiconductor for making an IC substrate. For
making an IC we use the metal oxide as a layer by
this process we make a MOS (metal oxide
semiconductor). With the help of MOS we are
making the CMOS (complementary metal oxide
semiconductor). In the process of making CMOS
we use PMOS and NMOS. In the PMOS we use the
P (positive) type substrate and in the NMOS we use
the N (negative) type substrate. By the combination
of PMOS and NMOS we make the CMOS. Speed of
CMOS is greater than the PMOS and NMOS. By
the increasing of speed of CMOS we use the
generally CMOS rather than PMOS and NMOS.
After that we are making the BI-CMOS whose
speed, current gain and performance is superior
than the CMOS technology. BI-CMOS is a
technology in which we use the BI polar process
with CMOS process. With the working BI polar
process we increase the speed of CMOS
technology.
Keywords: CMOS; BI-CMOS; BI POLAR; PMOS;
NMO; LSI; MOS
I. INTRODUCTION
BI-CMOS is an electronic technology in
which we use the BI polar technology and CMOS
technology. Firstly BI-CMOS technology was used
in 1983 in this both the BI polar devices and MOS
devices are fabricated on the same chip. Due to this
speed and performance of electronic devices are
increased and power is less consumed. CMOS
technology basically used for the fabrication of
memories and microcomputer because CMOS has
low power consumption and density is high. But
speed performance is not better. To increase the
speed performance we use the BI polar device with
the CMOS device. BI-CMOS devices are
fabricated on the LSIs (large scale integration) chip
[1]. In this technology we generally increase the
speed, current gain and performance of the devices
for this the BI polar devices such as transistor is
used. When an input voltage (V1n) is apply on the
BI polar transistor in the output section of BI-
CMOS gate circuit makes the transition from high
to low, then the output (Vout) goes from high to
low after some delay. During this delay time
emitter-base junction is on reverse biased situation.
This emitter-base reverse biased condition allows a
large reverse current. In the reverse biased
condition base current increases and due to this hot-
carrier injected into the SIO2 layer. Due to this
current gain decreases and current gain directly
depends upon the temperature means current gain
varies according to applying input temperature
[2].So finally we say that BI-CMOS is a versatile
technology by which we increase the speed of
electronic devices and we decrease the power
consumption due to electronic devices. Due to BI
polar technology switching speed of electronic
devices are increased and current gain is also
increased. Due to combination of BI polar
technology and CMOS technology sound of
devices are reduces. If noises are reduces then the
speed of the devices are by design increased. In the
distinction of CMOS and BI-CMOS noise in the
CMOS technology is better than the BI-CMOS
technology so speed of BI-CMOS is greater than
the CMOS technology.
II. FUNDAMENTALOF BI-
CMOSTECHNOLOGY [3]
In this section, we know that process in which BI
polar equipment and CMOS equipment are
combined and making a new technology called BI-
CMOS technology.
A. BI-POLAR TECHNOLOGY
BI polar process is used for the fabrication of BI-

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SSRG International Journal of Electronics and Communication Engineering (SSRG-IJECE) Volume 3 Issue 8 August 2016
CMOS. Generally BI polar is used because of its
matching capacity is good involving devices. With
the using of BI polar technology noise will be
reduces and by this current gain will be enlarged.
Its transconductance capacity is more than the
MOS technology. By the using of BI polar
technology power utilization is also less. BI polar
devices are fundamental to voltage reference
circuit, such as band gap reference.
B. CMOS TECHNOLOGY
CMOS technology is also used for fabrication of
BI-CMOS. CMOS is used very frequently because
of having excellent switching capacity and when it
is in on condition then no voltage drop will be
there. Its packaging density is high and it has low
transconductance because of transconductance is
directly depends on the input voltage.
g V
m in.(1)
By the above equation we see that
transconductance is directly depends upon input
voltage.
C. BI-CMOS TECHNOLOGY
BI-CMOS process is a fusion of BI polar and
CMOS process. Its speed and performance is more
than CMOS technology. It has high gain and low
noise level. It has low power dissipation than
purely BI polar technology. Current gain is
improved over CMOS technology. Packing density
is improved over BI polar technology.
III. BLOCK DIAGRAM OF BI-CMOS
FABRICATION PROCESS
In this section we see that how the BI-CMOS
technology is fabricated.
ISSN: 2348 8549 www.internationaljournalssrg.org
Figure1: BlockDiagram of BI-CMOS manufacture
Technology [4]
By the above block diagram we see that how
the BI-CMOS is fabricated. For the fabrication
process first we select the P/P+ substrate. P type
means positive type substrate we select; in this
substrate positive ion concentration is more than
the negative ion concentration. After that we
provide the isolation for making inductive
substrate. Then CMOS tub is implanted. After that
gate terminal is fabricated. Gate terminal is
fabricated using ion implantation method or using
UV (ultra violet) rays for the process of deposition
of polysilicon metal then gate terminal is etched for
making pure gate terminal. After that we implant
the LDD (lightly doped drain). For implanting the
drain terminal we make the firstly NMOS and
PMOS drain then combining this drain terminal we
make the drain terminal of CMOS. For making the
NMOS and PMOS drain we use the SiGe BI polar
technology in which we firstly implanted the NPN
tub such that NPN transistor then emitter window is
etched after that SiGe epitaxial layer is selected.
After that emitter and base will be defined of NPN
section. After that CMOS space is defined. After
that source and drain is defined in the specified
space. Source and drain terminal is interchangeable
means in the specified space in anywhere source
and drain will be placed. After that metal contact is
provided to the source, drain and gate terminal.
Metallization is the process in which we provide
the metal contact to the source, drain and gate
terminal by the ion implantation method. For
metallization process we use thick inductive metal.
At the end BI-CMOS is fabricated and used as a
speed gainer technology.
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SSRG International Journal of Electronics and Communication Engineering (SSRG-IJECE) Volume 3 Issue 8 August 2016

IV. InP BI-CMOS TECHNOLOGY

InP BI-CMOS technology is used for integration of

wafer of InP and CMOS technology. With this
technology, we use fully III-IV group compound to
increase the speed.

Figure 4:Fabrication and heterogeneous integration

[5].

Above diagram is the entire process of produce

of InP BI-CMOS technology. This technology uses
Figure 2: Schematic figure of heterogeneous the heterogeneous integration process. In the above
integrationprocess consisting of diagram we see that P+ substrate is used, heat
a) Epitaxial growth, b) temporary spreader is also used [6].
Wafer bonding to a handle wafer, c) growth
V. COMPARISION BETWEEN BI-CMOS AND
substrate removal [5]
CMOS TECHNOLOGY
Comparison between BI-CMOS and CMOS is
Above figure shows that how the heterogeneous
necessary because of we should know how much
integration is processed. First of all we make the
speed is increased and how much less area is
epitaxial growth after that we handle the by the
covered.
process of wafer bonding. After that we remove the
growth substrate.

Figure 3:Permanent bonding to CMOS after heat

spreader deposition [5]
Above diagram is that in which we see that how the
permanent bonding is provided to CMOS with the
help of heat spreader deposition. Heat is speeded
on the adhesive layer of Si CMOS. Figure 5: Comparison between CMOS & Bi-
CMOS Technology [1]

In the first graph we compared the speed of BI-

CMOS and CMOS technology. In the first graph
we see that speed of the BI-CMOS is additional
than the CMOS technology.

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SSRG International Journal of Electronics and Communication Engineering (SSRG-IJECE) Volume 3 Issue 8 August 2016

In the second graph we compare the delay

characteristic of BI-CMOS and CMOS technology.
In this graph we see that delay in the CMOS
technology is larger than the BI-CMOS technology.

In the third graph we compare the area of BI-

CMOS and CMOS technology using. In this graph
we see that area consumed by BI-CMOS is less
than that of CMOS technology.

VI. CONCLUSION
This paper concludes that speed and performance
of BI-CMOS is more than the CMOS technology.
In the BI-CMOS technology BI polar technology is
used who increase the switching speed, increase the
current gain per unit area and increase the
transconductance. CMOS technology is also used
who decrease the power dissipation, increase the
packing density and its switching capacity is ideal.
By the combination of these two technology we
construct the BI-CMOS technology. BI-CMOS
technology is used in the SRAM (static random
access memory), DRAM (dynamic random access
memory) and REGISTERS. Finally we say that BI-
CMOS technology is very helpful technology in the
field of electronics.

REFERENCES

[1] Ikuromasuda, Katsumi ogiue, Shinji Kadono, HIGH

PERFORMANCE BI-CMOS TECHNOLOGY AND ITS
APPLICATION.
[2] Hisayo sasakimomose, Hiroshi iwai, ANALYSIS OF
THE TEMPERATURE DEPENDENCE OF HOT
CARRIER INDUCED DEGRADATION IN BI POLAR
TRANSISTOR FOR BI-CMOS, IEEE transaction on
electron devices, vol.41, No 6, JUNE 1994.
[3] T. Watanabe et al., "High speed BICMOSVLSI technology
with buried twin wellstructure," IEDM Tech. Dig., 1985,
pp.423-426.
[4] I. Masuda et al., "High speed logic circuitsCombining
bipolar and CMOS technology, Trans. Inst. Electron.
CommunicationEngineers Japan, vol. J67-C, no. 12,
pp.999-1005, Dec. 1984.
[5] Y.Royter, P.R.Patterson, J.C.Li, K.R.Elliott, T.Hussain,
M.F.Boag-OBrien, J.R.Duvall, M.C.Montes, D.A.Hitko,
J.S.Sewell, M.Sokolich, D.H.Chow, P.D.Brewer, DENSE
HETROGENEOUS INTEGRATION FOR InP BI-CMOS
TECHNOLOGY.
[6] T. Hussain et al, 2006 IPRM Proceedings, p. 85.

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