Certify Reference PDF

Certify Multi-FPGA
Prototyping Software
Certify Reference
September 2016
http://solvnet.synopsys.com
Preface
Copyright Notice and Proprietary Information

2016 Synopsys, Inc. All rights reserved. This software and documentation
contain confidential and proprietary information that is the property of
Synopsys, Inc. The software and documentation are furnished under a
license agreement and may be used or copied only in accordance with the
terms of the license agreement. No part of the software and documentation
may be reproduced, transmitted, or translated, in any form or by any means,
electronic, mechanical, manual, optical, or otherwise, without prior written
permission of Synopsys, Inc., or as expressly provided by the license agree-
ment.
Destination Control Statement

All technical data contained in this publication is subject to the export
control laws of the United States of America. Disclosure to nationals of other
countries contrary to United States law is prohibited. It is the readers
responsibility to determine the applicable regulations and to comply with
them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY
KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Trademarks
Synopsys and certain Synopsys product names are trademarks of Synopsys,
as set forth at
http://www.synopsys.com/Company/Pages/Trademarks.aspx.
All other product or company names may be trademarks of their respective
owners.
LO
2016 Synopsys, Inc. Certify Reference Manual

2 September 2016
Preface
Third-Party Links
Any links to third-party websites included in this document are for your
convenience only. Synopsys does not endorse and is not responsible for such
websites and their practices, including privacy practices, availability, and
content.
Synopsys, Inc.
690 East Middlefield Road
Mountain View, CA 94043
www.synopsys.com
September 2016
Certify Reference Manual 2016 Synopsys, Inc.

September 2016 3
Preface
LO

4 September 2016
Contents
Chapter 1: Product Overview

The Synopsys FPGA Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overview of the Synthesis Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
BEST Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Graphic User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Projects, Implementations, and Workspaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Starting the Certify Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Starting the Certify Tool in Interactive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Starting the Certify Tool from the Command Line . . . . . . . . . . . . . . . . . . . . . . . 26
Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chapter 2: User Interface Overview

Windows and Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Project View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Tcl Script Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Message Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Certify Partition View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Certify Trace Assignment Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Certify CPM Assignment Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
RTL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
FSM Viewer Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Dockable GUI Entities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Text Editor View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
FSM Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
When to Use FSM Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Where to Use FSM Compiler (Global and Local Use) . . . . . . . . . . . . . . . . . . . . 52
Using the Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Using Mouse Strokes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Using the Mouse Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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Using The Mouse Wheel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Setting User Interface Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Managing Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Toolbars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Project Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Analyst Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
View Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
FSM Viewer Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Text Editor Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Buttons and Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Chapter 3: User Interface Commands

Command Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
File Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
New Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Load Prototyping File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Create Image Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Build Project Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Open Project Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Edit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Find Command (Text) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Find Command (In Project) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Find Command (HDL Analyst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Find in Files Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Replace Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Goto Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
View Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Toolbar Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
View Sheets Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
View Log File Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Project Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Add Source File Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Change File Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Set VHDL Library CommandLO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Import IP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Add Implementation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Remove Implementation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

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Contents
Archive Project Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Un-Archive Project Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Copy Project Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Implementation Options Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Partitioning Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Implementation Results Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Verilog Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
VHDL Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Device Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Prototyping Tools Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Options Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
FPGA Synthesis Options Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Constraints Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Timing Report Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Run Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Run Tcl Script Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Translate Constraints Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Job Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Log File Message Filter Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Tools Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Launch SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SYNCore FIFO Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SYNCore RAM Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SYNCore Byte-Enable RAM Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
SYNCore ROM Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
SYNCore Adder/Subtractor Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
SYNCore Counter Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Analysis Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Timing Report Generation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
HDL Analyst Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
HDL Analyst Menu->RTL View Submenus . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
HDL Analyst Menu: Hierarchical and Current Level Submenus . . . . . . . . . . . . 189
HDL Analyst Menu: Filtering and Flattening Commands . . . . . . . . . . . . . . . . . 191
HDL Analyst Menu: Analysis Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
HDL Analyst Menu: Selection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
HDL Analyst Menu: FSM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Options Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Configure Synplify Launch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Project View Options Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Editor Options Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

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HDL Analyst Options Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Configure External Programs Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
P&R Environment Options Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Certify Preferences Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Tech-Support Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Submit Support Request Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Web Support Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Web Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Help Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Preferred License Selection Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Tip of the Day Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Popup Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Project View Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
File Options Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Copy File Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Change Implementation Name/Copy Implementation Command . . . . . . . . . . 231
Project Options Popup Menu Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Tcl Window Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Text Editor Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Log File Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
RTL View Popup Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Partition View Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
FSM Viewer Popup Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Chapter 4: Input and Result Files

Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
HDL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
The Synopsys FPGA Generic Technology Library . . . . . . . . . . . . . . . . . . . . . . 247
Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Errors, Warnings, Notes, and Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Clock Buffering Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Net Buffering Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Gated Clock Conversion Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
LO
Timing Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Timing Report Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

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Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Detailed Clock Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Asynchronous Clock Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Constraint Checking Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Certify-Specific Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Chapter 5: Constraints
Constraint Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
FDC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Methods for Creating Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Constraint Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Constraint Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Database Object Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Forward Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Chapter 6: SCOPE Constraints Editor

SCOPE User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
SCOPE Tabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Generated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Collections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Delay Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
TCL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Industry I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Industry I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Delay Path Timing Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Multicycle Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
False Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

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Specifying From, To, and Through Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

Timing Exceptions Object Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
From/To Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Through Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Product of Sums Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Clocks as From/To Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Conflict Resolution for Timing Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
SCOPE User Interface (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
SCOPE Tabs (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Clocks (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Clock to Clock (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Inputs/Outputs (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Registers (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Delay Paths (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Other (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Chapter 7: HDL Analyst Tool

HDL Analyst Views and Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Filtered and Unfiltered Schematic Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Accessing HDL Analyst Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Schematic Objects and Their Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Object Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Sheet Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Primitive and Hierarchical Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Transparent and Opaque Display of Hierarchical Instances . . . . . . . . . . . . . . 353
Hidden Hierarchical Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Schematic Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Basic Operations on Schematic Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Finding Schematic Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Selecting and Unselecting Schematic Objects . . . . . . . . . . . . . . . . . . . . . . . . . 360
Crossprobing Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Multiple-sheet Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Controlling the Amount of Logic on a Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Navigating Among Schematic Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Multiple Sheets for Transparent Instance Details . . . . . . . . . . . . . . . . . . . . . . . 366
Exploring Design Hierarchy . . .LO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Pushing and Popping Hierarchical Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Navigating With a Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Looking Inside Hierarchical Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

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Filtering and Flattening Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

Commands That Result in Filtered Schematics . . . . . . . . . . . . . . . . . . . . . . . . 374
Successive Filtering Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Returning to The Unfiltered Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Commands That Flatten Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Selective Flattening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Filtering Compared to Flattening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Chapter 8: Utilities
sdc2fdc Tcl Shell Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
sdc2fdc Tcl Shell Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Examples of sdc2fdc Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
FPGA Design Constraint (FDC) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Synopsys FPGA Archive Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Tcl synhooks Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Altera qsf2sdc Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
QSF2SDC Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Supported QSF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Example of Translated QSF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Encryption Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Encryption and Decryption Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
The encryptP1735 Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
The encryptIP Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Chapter 9: RAM and ROM Inference

Guidelines and Support for RAM Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Block RAM Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Block RAM Mode Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Single-Port Block RAM Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Single-Port RAM with Read Address Registered Example . . . . . . . . . . . . . . . 420
Single-Port RAM with RAM Output Registered Examples . . . . . . . . . . . . . . . . 421
Dual-Port Block RAM Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
True Dual-Port RAM Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
LUTRAM Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Synchronous Read Single-Port RAM, Unregistered Output . . . . . . . . . . . . . . . 429
Asynchronous Read Single-Port RAM, Unregistered Output . . . . . . . . . . . . . . 430
Simple Synchronous Dual-Port RAM, Unregistered Output . . . . . . . . . . . . . . . 430
Simple Asynchronous Dual-Port RAM, Unregistered Output . . . . . . . . . . . . . . 431

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RAM with Control Signals Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

Dual-Port RAM with Read Enable and Clock Enable . . . . . . . . . . . . . . . . . . . . 432
Single-Port RAM with Clock Enable Controlling Read . . . . . . . . . . . . . . . . . . . 434
Dual-Port RAM with Read Enable, Write Enable, and Common Clock Enable 435
Distributed RAM Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Single-Port Distributed RAM with Asynchronous Read Port . . . . . . . . . . . . . . 438
Dual-Port Distributed RAM with One Write and Two Asynchronous Reads . . . 438
Asymmetric RAM Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Example 1 (Read Width > Write Width): Coding Style 1 . . . . . . . . . . . . . . . . . 440
Example 1 (Read Width > Write Width): Coding Style 2 . . . . . . . . . . . . . . . . . 441
Example 2 (Read Width < Write Width): Coding Style 1 . . . . . . . . . . . . . . . . . 442
Example 2 (Read Width < Write Width): Coding Style 2 . . . . . . . . . . . . . . . . . 443
Limitations for Asymmetric RAM Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Byte-Enable RAM Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Byte-Wide Write Enable RAM Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Byte-Wide Write Enable RAM Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Initial Values for RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
RAM Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Initialization Data File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Forward Annotation of Initial Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Initial Values for Asymmetric RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
RAM Instantiation with SYNCORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
ROM Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Chapter 10: Timing Constraint Syntax

FPGA Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Naming Rule Syntax Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Synplify-Style Timing Constraints (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Object Naming Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Chapter 11: FPGA Design Constraint Syntax

Chapter 12: Tcl Find, Expand, and Collections
Tcl find Command . . . . . . . . . . .LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Tcl Find Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Tcl Find Syntax Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

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Tcl Find -filter Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

Tcl expand Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Collection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
c_diff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
c_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
c_intersect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
c_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
c_print . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
c_symdiff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
c_union . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
get_prop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
define_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
define_scope_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Object Query Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
all_clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
all_inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
all_outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
all_registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
get_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
get_clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
get_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
get_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
get_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Synopsys Standard Collection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
Appendix A: Designing with Altera

Basic Support for Altera Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
Input for Altera Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Altera Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Altera RAMs and ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Altera LPMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
DSP Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Altera Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Altera Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Forward-annotation to Altera Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

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Integration with Altera Tools and Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

Altera Place-and-route Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Clearbox Support in Synplify Pro and Synplify Premier . . . . . . . . . . . . . . . . . . 634
Greybox Support in Synplify Pro and Synplify Premier . . . . . . . . . . . . . . . . . . 635
Stratix Device Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
Stratix Device Mapping Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
Stratix File Format Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
set_option Command for Altera Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
project Command for Altera Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
Altera Attribute and Directive Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Appendix B: Designing with Xilinx

Basic Support for Xilinx Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Xilinx Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Xilinx I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Synthesis Constraints and Attributes for Xilinx Designs . . . . . . . . . . . . . . . . . . 652
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
IP Core Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Startup Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
IOB Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Initial Value Support for Xilinx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Xilinx Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Macros and Black Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
Xilinx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
DDR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Dynamic Shift Register Lookup (SRL) Table Inference . . . . . . . . . . . . . . . . . . 664
Latch Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
DSP Components in Virtex Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Advanced LUT Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Wide Adders in Virtex-5 and Virtex-6 Designs . . . . . . . . . . . . . . . . . . . . . . . . . 668
Control Sets in Virtex Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
Xilinx RAMs and ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
ROM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Xilinx RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Xilinx I/O Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
LO
I/Os and Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Using Xilinx Macro Libraries with Verilog and VHDL . . . . . . . . . . . . . . . . . . . . 677
Instantiating I/O Pads With Different Standards . . . . . . . . . . . . . . . . . . . . . . . . 677

14 September 2016
Contents
Specifying Pin Locations and Inserting I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

Specifying Relative Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Xilinx Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Fanout Limits in Xilinx Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Pipelining in Xilinx Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Retiming in Xilinx Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Xilinx Gated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Xilinx Generated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Sequential Optimizations in Xilinx Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Verification Mode in Xilinx Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Compile Point Remapping in Xilinx Designs . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Output Files and Forward-annotation for Xilinx . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Xilinx Resource Usage Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Xilinx Net Buffering Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Virtex-5 and Virtex-6 Detailed Clock Path Report . . . . . . . . . . . . . . . . . . . . . . 695
Custom Timing Reports for Xilinx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
Forward-annotation of Xilinx Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Forward-annotation of Port Names in EDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Integration with Xilinx Tools and Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Xilinx ISE Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Xilinx Xflow and Xtclsh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Virtex and Spartan-3 Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Virtex and Spartan-3 Device Mapping Options . . . . . . . . . . . . . . . . . . . . . . . . 698
Virtex and Spartan-3 set_option Tcl Command . . . . . . . . . . . . . . . . . . . . . . . . 700
Virtex and Spartan-3 project Tcl Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
Xilinx Attribute and Directive Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

September 2016 15
Contents
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16 September 2016
CHAPTER 1
Product Overview
This document is part of a documentation set that includes reference and

procedural information for the Certify tool. The reference manual details the
synthesis tool user interface and features. The user guide contains how-to
information, emphasizing user tasks, procedures, design flows, and results
analysis. A separate command reference details the Tcl command syntax for
all of the Certify commands. Tutorials, provided on the SolvNet web site, help
you become familiar with the tool and includes extended examples.
The following provide an introduction to the synthesis tools.

The Synopsys FPGA Product Family, on page 18
Overview of the Synthesis Tools, on page 21
Starting the Certify Tool, on page 25
Getting Help, on page 28

September 2016 17
Chapter 1: Product Overview The Synopsys FPGA Product Family
The Synopsys FPGA Product Family

The Synopsys product family is based on core logic synthesis technology,
and shares a common look and feel.
FPGA DSP Prototyping
FPGA Synthesis DSP Design ASIC RTL Prototyping
Synphony
Synplify Model Certify
Compiler
Synplify Pro
RTL Prototyping Debugging
Physical Synthesis Identify

for FPGAs
Synplify
Premier Design Planner
RTL Debugging
Identify
Synplify and Synplify Pro Tools

The Synplify and Synplify Pro products are logic synthesis tools for FPGAs
(field programmable gate arrays) and CPLDs (complex programmable logic
devices). The Synplify Pro tool is an advanced version of the Synplify tool,
with many additional features for managing and optimizing complex FPGAs.
These tools accept high-level input written in industry-standard hardware

description languages (Verilog and VHDL), and using the Synopsys Behavior
Extracting Synthesis Technology (BEST) algorithms, convert the designs
into small, high performance design netlists for popular technology vendors.
They can also write VHDL and Verilog netlists after synthesis, which you can
then simulate in order to verify functionality.
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18 September 2016
The Synopsys FPGA Product Family Chapter 1: Product Overview
Synplify Premier Tool

The Synplify Premier product is a physical synthesis tool that offers a
push-button, graph-based methodology for improving overall device perfor-
mance while simultaneously delivering tight correlation between pre-route
timing estimates and final post place-and-route results The essence of the
graph-based approach is that preexisting wires, switches and placement sites
used for routing an FPGA can be represented as a detailed routing resource
graph. The notion of distance then changes to a measure of delay and avail-
ability of wires. Graph-based physical synthesis technology merges optimiza-
tion, placement and routing to generate a fully placed and physically
optimized netlist, providing rapid timing closure and increased timing
improvement. Enabling physical re-timing provides an additional perfor-
mance boost.
The Synplify Premier product supports the following flows:

Graph-based physical synthesis a fully automated flow for incremental
performance improvement producing a design with detailed placement.
Graph-based physical synthesis with a design plan a graph-based
physical synthesis flow that is guided by a design plan. This flow also
produces a design with detailed placement. The Design Planner is a
separately licensed option to the Synplify Premier product.
Design plan-based physical synthesis an interactive flow that lets you
perform physical synthesis optimization using the Design Planner view.
Design plan-based physical synthesis produces a design with coarse
placement. The Design Planner is a separately licensed option to the
Synplify Premier product.
Prototyping the Synplify Premier product supports a complete design
and debugging environment featuring the product along with automated
HDL code translation for Synopsys DesignWare components. Using
the Synplify Premier prototyping solution, you can quickly and automat-
ically bring ASIC HDL code into high-capacity FPGAs, and then debug it
with real-time feedback from the FPGA. Because the feedback from the
debugger goes directly into the RTL code, the integration of logic
synthesis lets you correct the code and retest it in the FPGA in record
time.

September 2016 19
Chapter 1: Product Overview The Synopsys FPGA Product Family
Identify Tool Set

The Identify tool sets help you debug any design that is implemented by an
electronically programmable logic device such as an FPGA or PLD. With the
Identify tools, you can debug live hardware within the target system at target
speed with the internal design visibility you need while using intuitive debug-
ging techniques.
The Identify tool set is dual-component systems that allows you to probe your
HDL design directly in the target environment. The tool set consists of two
software tools:
Instrumentor tool allows you to select your design instrumentation at the
HDL level and then create an on-chip hardware probe.
Debugger tool interacts with the on-chip hardware probe and allows you
to perform live debugging of your design.
The combined system fits easily into your existing design flow with only
minor modifications and allows you to debug designs faster, easier, and more
efficiently.
Synphony Model Compiler Tool

The Synphony Model Compiler product is a high-level tool for hardware DSP
design. It is an add-on to the Simulink product from The MathWorks, and
provides the designer with an automated path from high-level design and
simulation to an optimized, synthesizable, technology-independent,
system-level HDL implementation. This tool provides performance and
productivity benefits for designers who are implementing DSP circuits and
targeting programmable logic devices. The software achieves significantly
higher performance than alternative solutions and provides the designer with
a mechanism to make high-level area/performance tradeoffs. The output is
synthesizable HDL code ready for use with the Synopsys Synplify Pro
software.
Certify Tool
The Certify product is a tool for system-design, system-on-a-chip (SoC), and
ASIC teams that require hardware prototypes of their project early in the
LO
design phase. It produces a functional ASIC prototype partitioned among
multiple FPGAs from RTL code. The Certify tool includes many unique
advantages for prototyping, including a feature that combines the gated
clocks, which are characteristic of ASIC designs, onto the global clock

20 September 2016
Overview of the Synthesis Tools Chapter 1: Product Overview
resources of the FPGAs. Unlike traditional ASIC prototyping techniques, the

Certify tool enables prototype delivery before ASIC synthesis to allow a design
team to recognize and correct problems earlier in the design flow. The Certify
tool uses Synplify Premier as its synthesis engine.
Overview of the Synthesis Tools

The Synopsys FPGA synthesis tools have the following built-in features:
The HDL Analyst RTL analysis and debugging environment, a graphical
tool for analysis and crossprobing. See RTL View, on page 42, in
Chapter 12, Analyzing Logic in HDL Analyst of the User Guide.
The Text Editor window, with a language-sensitive editor for writing and
editing HDL code. See Dockable GUI Entities, on page 47.
The SCOPE (Synthesis Constraint Optimization Environment) tool,
which provides a spreadsheet-like interface for managing timing
constraints and design attributes. See SCOPE User Interface, on
page 286.
FSM Compiler, a symbolic compiler that performs advanced finite state
machine (FSM) optimizations. See FSM Compiler, on page 51.
The FSM Viewer, for viewing state transitions in detail. See FSM Viewer
Window, on page 45.
The Tcl window, a command line interface for running TCL scripts. See
Tcl Script Window, on page 35.
The Timing Analyst window, which allows you to generate timing
schematics.
Other special windows, or views, for analyzing your design, including
the Message Viewer (see Windows and Views, on page 32).Advanced
analysis features like crossprobing and probe point insertion.
BEST Algorithms
The Behavior Extracting Synthesis Technology (BEST ) feature is the under-
lying proprietary technology that the synthesis tools use to extract and imple-
ment your design structures.

September 2016 21
Chapter 1: Product Overview Overview of the Synthesis Tools
During synthesis, the BEST algorithms recognize high-level abstract struc-

tures like RAMs, ROMs, finite state machines (FSMs), and arithmetic opera-
tors, and maintain them, instead of converting the design entirely to the gate
level. The BEST algorithms automatically map these high-level structures to
technology-specific resources using module generators. For example, the
algorithms map RAMs to target-specific RAMs, and adders to carry chains.
The BEST algorithms also optimize hierarchy automatically.
Graphic User Interface

The initial Certify graphical user interface (GUI) is shown below
Menus
Toolbars
Project window Flow/Results

Buttons window
Tcl window Message/Status

window
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22 September 2016
Overview of the Synthesis Tools Chapter 1: Product Overview
The following table shows where you can find information about different
parts of the GUI, some of which are not shown in the above figure. For more
information, see the User Guide.
For information about... See...

Project window Project View, on page 32
RTL view RTL View, on page 42
Text Editor view Dockable GUI Entities, on page 47
FSM Viewer window FSM Viewer Window, on page 45
Tcl window Tcl Script Window, on page 35
Certify Partition view Certify Partition View, on page 39
SCOPE spreadsheet SCOPE User Interface, on page 286
Other views and windows Project View, on page 32
Menu commands Menus, on page 76

and their dialog boxes
Toolbars Toolbars, on page 59
Buttons Buttons and Options, on page 77
Context-sensitive popup menus Popup Menus, on page 225

and their dialog boxes
Online help Use the F1 keyboard shortcut or click the Help
button in a dialog box.

September 2016 23
Chapter 1: Product Overview Overview of the Synthesis Tools
Projects, Implementations, and Workspaces

Projects contain information about the synthesis run, including the names of
design files, constraint files (if used), and other options you have set. A project
file (prj) is in Tcl format. It points to all the files you need for synthesis and
contains the necessary optimization settings. In the Project view, a project
appears as a folder.
An implementation is one version (also called a revision) of a project, run with

certain parameter or option settings. You can synthesize again, with a
different set of options, to get a different implementation. In the Project view,
an implementation is shown in the folder of its project. The active implemen-
tation has a green arrow next to it. You can display multiple implementations
in the same Project view. The output files generated for the active implemen-
tation are displayed in the Implementation Results view on the right.
A Place and Route implementation, located in the project implementation

hierarchy, is created automatically for supported technologies. To view the
P&R implementation, select the plus sign to expand the project implementa-
tion hierarchy. To add, remove, or set options, right-click on the P&R imple-
mentation. You can create multiple P&R implementations for each project
implementation. Select a P&R implementation to activate it.
A workspace allows you to group related projects together. Although a

workspace can contain a set of projects, only one implementation is active at
a time. All commands operate on the active project and its implementation.
You can open a project independently of the workspace it belongs to, if
needed. In the Project view, a workspace is shown as a folder at one level
above the project folder.
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24 September 2016
Starting the Certify Tool Chapter 1: Product Overview
Starting the Certify Tool

This section describes starting the Certify tool in interactive and batch mode.
Before you can start the tool, you must install it and set up the software
license appropriately. How you start the tool depends on your environment.
For details, see the installation instructions for the tool.
Starting the Certify Tool in Interactive Mode

You can start interactive use of the Certify tool in any of the following ways:
To start the synthesis tool from the Microsoft Windows operating
system, choose
Start->Programs->Synopsys->Certify version
To start the tool from a DOS command line, specify the executable:
certifyInstallationDir\bin\certify.exe
The executable name is the name of the product followed by an exe file
extension.
To start the Certify tool from a Linux platform, type certify at the system
prompt.
For information about using the synthesis tool in batch mode, see Starting
the Certify Tool from the Command Line, on page 26.

September 2016 25
Chapter 1: Product Overview Starting the Certify Tool
Starting the Certify Tool from the Command Line

The command to start the Certify tool from the command line includes a
number of command line options. These options control tool action on
startup and, in many cases, can be combined on the same command line. To
start the synthesis tool, use the following syntax:
certify [-option ... ] [projectFile]
ProjectFile is the name of the project (prj) file to open and, if omitted, defaults
to the last project file opened. Option is any of the following command line
options:
[-batch projectFile |tclScriptName]

[-compile]
[-evalhostid]
[-help]
[-history historyLogFilename]
[-impl implementationName]
[-ip_license_wait timeInSeconds]
[-licensetype licenseFeatureName]
[-license_wait [timeInSeconds]]
[-log logFilename]
[-run implementationName]
[-runall]
[-shell][-tcl projectFile|tclScriptName]
[-tclcmd tclCommandName]
[-verbose_log]
[-version]
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26 September 2016
Starting the Certify Tool Chapter 1: Product Overview
The following table describes the command line options.
Option Description
-batch Starts the synthesis tool in batch mode from the specified project
or Tcl file without opening the Project window.
-compile Compiles the project, but does not map it (equivalent to Run
Preparation).
-evalhostid Reports host ID for floating licenses.
-help Lists available command line options and descriptions.
-history Records all Tcl commands and writes them to the specified
history log file when the command exits.
-impl Runs only the specified implementation. You can use this option
in conjunction with the -batch keyword.
-ip_license_wait Specifies how long to wait for an available DesignWare IP license.
You can use this option in conjunction with the -batch keyword.
For details, see License Queuing.
-licensetype Specifies a license if you work in an environment with multiple
Synopsys licenses. You can use this option in conjunction with
the -batch keyword.
-license_wait Specifies how long to wait for a Synopsys FPGA license. License
queuing allows you to wait until a license becomes available or
specify a wait time in seconds. For details, see License Queuing.
-log Writes all output to the specified log file.
-runall Runs all the implementations in the project file.
-shell Starts Certify in shell mode.
-tcl Starts the synthesis tool in the graphical user interface using the
specified project or Tcl file.
-tclcmd Specifies Tcl command to be executed on startup.
-verbose_log Writes messages to stdout.log in verbose mode.
-version Reports version of specified synthesis tool.

September 2016 27
Chapter 1: Product Overview Getting Help
Getting Help
Before calling Synopsys Support, look through the documented information.
You can access the information online from the Help menu, or refer to the
corresponding manual. The following table shows you how the information is
organized.
Finding Information
For help with... Refer to the...
How to... User Guide and various application notes available on the
Synopsys support web site
Tutorials Synplicity Technical Resource Center (Web menu
commands from within the software)
Flow information User Guide and various application notes available on the
Synopsys support web site
Product updates Synplicity Technical Resource Center (Web menu
commands from within the software)
Licensing Copyright and License Agreement and the Synopsys
FPGA Licensing User Guide
Language and syntax Reference Manual
Attributes and Reference Manual
directives
Tcl language Online help (Help->Tcl Help)
Synthesis Tcl Command Reference Manual or type help followed by the
commands command name in the Tcl window
Using tool-specific User Guide
features and attributes
Error and warning Click on the message ID code
messages
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28 September 2016
Getting Help Chapter 1: Product Overview
Contacting Customer Support

If you have a problem, question, or enhancement request, use either of these
methods to contact Synopsys Customer Support:
Go to the SolvNet web site at https://solvnet.synopsys.com
Write to us at this address:
Synopsys Inc.
700 East Middlefield Road
Mountain View, CA 94043, USA

September 2016 29
Chapter 1: Product Overview Getting Help
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30 September 2016
CHAPTER 2
User Interface Overview
This chapter presents tools and technologies that are built into the Synopsys
FPGA synthesis software to enhance your productivity.
These are the topics in this chapter:

Windows and Views, on page 32
FSM Compiler, on page 51
Using the Mouse, on page 53
Setting User Interface Preferences, on page 57
Toolbars, on page 59
Keyboard Shortcuts, on page 66
Buttons and Options, on page 73

September 2016 31
Chapter 2: User Interface Overview Windows and Views
Windows and Views

The Certify tool includes a graphical user interface (GUI) with windows and
views that help you manage input and output files, direct the synthesis
process, and analyze your design and its results. The following windows and
views are presented here, except for the SCOPE spreadsheet. For information
on the SCOPE spreadsheet, see SCOPE User Interface, on page 286.
Project View, on page 32
Tcl Script Window, on page 35
Message Window, on page 36
Certify Partition View, on page 39
Certify Trace Assignment Window, on page 41
RTL View, on page 42
Hierarchy Browser, on page 44
FSM Viewer Window, on page 45
Dockable GUI Entities, on page 47
Project View
You use the Project view to create or open projects, prepare designs, manage
partitioning, and generate SLP projects. The project view is the main
synthesis tool view. It contains a list of files you use, and has buttons for
quick access to common commands and operations. For information about
setting display options in the Project view, see Setting User Interface Prefer-
ences, on page 57.
The following figure shows the Certify project view:
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32 September 2016
Windows and Views Chapter 2: User Interface Overview
Management Project Flow Graph/

Buttons Management Result Directory
The Project view includes the following major components:

Management buttons give you immediate access to some of the more
common commands. Buttons are grouped by management function. See
Buttons and Options, on page 73 for details.
The Project Management view lists your projects, workspaces, and
implementations as well as their associated HDL source files and
constraint files. See Projects, Implementations, and Workspaces, on
page 24 for details.
The Flow Graph view (shown) is shared with the Implementation Results
view and graphically illustrates the progress of the various operations
during the design flow.
The Implementation Results view (not shown) is shared with the Flow
Graph view and lists the result files for the active implementation. You
can only view one set of implementation results at a time. Click an
implementation in the Project view to make it active and view its result
files.
The Implementation Results view lists the names and types of the result
files, and the dates they were last modified. You can click a column

September 2016 33
heading to sort the file list accordingly. Click again to reverse the sort
direction. An arrow in the column header displays the sorting direction.
Flow Graph View

The flow graph view graphically illustrates the progress of the various opera-
tions during the design flow. During operation, the individual blocks change
colors to indicate progress:
yellow shows an operation in progress
green shows a successfully completed operation
red shows an operation that failed to complete
Flow graphics are provided for Run Preparation and SLP Generation as well
as individual operations including area estimation and system-level timing.
When a flow graph is complete, you can view the corresponding log file for
that operation by right clicking within a graph and selecting View Logfile from
the popup menu. Selecting Properties displays the Job Options dialog box which
displays properties associated with the selected flow block. Selecting Properties
for the Optimize Design block additionally provides N-filter option selection.
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34 September 2016
Tcl Script Window

The Tcl Script window is an interactive command shell that implements the
Tcl command-line interface. You can type or paste Tcl commands at the
prompt (%). For a list of the available commands, type help * (without the
quotes) at the prompt. For general information about Tcl syntax, choose
Help->TCL.
The Tcl script window displays each command executed in the course of
running the tool, regardless of whether it was initiated from a menu, button,
or keyboard shortcut.Right-clicking inside the Tcl window displays a popup
menu with the Copy, Paste, Hide, and Help commands.

September 2016 35
Message Window
To display errors, warnings, and notes after running the synthesis tool, select
View->Messages Window. You can float the Messages window by clicking in the
title bar and then dragging the window to float it anywhere on the screen.
Double clicking in the title bar returns the window to its initial position in the
Project view.
Icon Shows Error Location in

Message Type Message ID Source
Grouped Log File

Common IDs Location
Interactive tasks in the Messages window include:

Click on the ID entry to open online help for the error, warning, or note.
Click on a Source Location entry to go to the section of code in the source
HDL file that is responsible for the message.
Click on a Log Location entry to go to its location in the log file.
Resize each column by placing the cursor on the line between two
columns until a cursor with a double arrow appears. Click and drag the
column to resize.
The following table describes the contents of the Messages window. You can
sort the messages by clicking the column headers. For further sorting, use
Find and Filter. For details about
LO using this window, see Checking Results in
the Message Viewer, on page 839 of the User Guide.

36 September 2016
Item Description
Find Type into this field to find errors, warnings, or notes.
Filter Opens the Warning Filter dialog box. See Messages Filter, on
page 38.
Apply Filter Enable/disable the last saved filter.
Group Common Enable/disable grouping of repeated messages. Groups are

IDs indicated by a number next to the type icon. There are two types
of groups:
The same warning or note ID appears in multiple source files
indicated by a dash in the source files column.
Multiple warnings or notes in the same line of source code
indicated by a bracketed number.
Type The icons indicate the type of message:
Error
Warning
Note
Advisory
A plus sign next to an icon indicates that repeated messages are
grouped together. Click the plus sign to expand and view the
various occurrences of the message.
ID This is the message ID. You can select a blue, underlined ID to
launch help on the message.
Message The error, warning, or note message text.
Source Location The HDL source file that generated the error, warning, or note
message.
Log Location The location of the error, warning, or note message in the log
file.
Time The time the error, warning or note message was recorded in the
log file.
Report Indicates which section of the Log File report the error appears.
For example Compiler or Mapper.

September 2016 37
Messages Filter
You filter which errors, warnings, and notes appear in the Messages window
using match criteria for each field. The selections are combined to produce
the result. You can elect to hide or show the warnings that match the criteria
you set. See Checking Results in the Message Viewer, on page 839 of the User
Guide.
Item Description
Hide Filter Matches Hides matched criteria in the Messages Panel
Show Filter Matches Shows matched criteria in the Messages Panel
Syntax Help Gives quick syntax descriptions
Apply Applies the filter criteria to the Messages Panel report,

without closing the window
Type, ID, Message, Log file report criteria to use when filtering
Source Location, Log
Location, Time,
Report
LO

38 September 2016
The following is a filtering example.
Show Filter
Matches
Hide Filter
Matches
Certify Partition View

The Certify prototyping tool has a Partition view that is specific to the Certify
product. The Partition view consists of the following:
a Partition Tree view that displays a hierarchical view of the board.
a Partition Info view that provides information about FPGA area and pin
usage.
a Partition Device view that shows the physical board devices and inter-
connect.
an Impact Analysis panel (not shown) that shows the impact of
assigning blocks of logic to the available FPGAs; the panel is toggled on
or off by Ctrl-F3.

September 2016 39
a Partition Management control panel that selects the various parti-

tioning phases and displays partitioning information for the parti-
tion-management interface.
For more information about using these views and how to use them effec-
tively, refer to the Certify User Guide.
Partition Info View Partition Tree View Partition Device View
LO

40 September 2016
Certify Trace Assignment Window

The Trace Assignment window is available after the database has been loaded
(Run Preparation complete). Normally, the Trace Assignment window is used
after a design has been partitioned to define the net-to-trace assignments.
You can, however, use the window prior to partitioning or after partial parti-
tioning to reserve nets or traces. For information on using the Trace Assign-
ment window, see Chapter 7, Trace Assignment in the Certify User Guide.
Certify CPM Assignment Window

The CPM Assignment window is available only after partitioning and is used
to define CPM assignments for time-delay multiplexing. For information on
using the CPM Assignment window, see Chapter 8, Time-Domain Multiplexing
in the Certify User Guide.

September 2016 41
RTL View
The RTL view provides a high-level, technology-independent, graphic repre-
sentation of your design after compilation, using technology-independent
components like variable-width adders, registers, large multiplexers, and
state machines. RTL views correspond to the srs netlist files generated during
compilation. RTL views are only available after your design has been success-
fully compiled (Run Preparation process complete).
To display an RTL view, select HDL Analyst->RTL and choose Hierarchical View,
Flattened View, or Partitioned View; for a hierarchical view, you can also click the
RTL icon ( ) in the menu bar.
An RTL view has two panes: a Hierarchy Browser on the left and an RTL
schematic on the right. You can drag the pane divider with the mouse to
change the relative pane sizes.
LO For more information about the Hierarchy
Browser, see Hierarchy Browser, on page 44. Your design is drawn as a set of
schematics. The schematic for a design module (or the top level) consists of

42 September 2016
one or more sheets, only one of which is visible in a given view at any time.
The title bar of the window indicates the current hierarchical schematic level,
the current sheet, and the total number of sheets for that level.
Sheet # of total # Movable pane divider
Hierarchy Browser Schematic
The design in the RTL schematic can be hierarchical, flattened, or a parti-

tioned view. Further, the view can consist of the entire design or part of it.
Different commands apply, depending on the kind of RTL view.
The following table lists where to find further information about the RTL view:

Hierarchy Browser Hierarchy Browser, on page 44
Procedures for RTL view Working in the Schematic View, on page 306 of the User
operations such as Guide
crossprobing, searching,
pushing/popping,
filtering, flattening, etc.
Explanations or HDL Analyst Tool, on page 347
descriptions of features
such as object display,

September 2016 43

Commands for RTL view Accessing HDL Analyst Commands, on page 349,
operations such as HDL Analyst Menu, on page 188
Viewing commands such View Menu: RTL View Commands, on page 97
as zooming, panning,
etc.
History commands: Back View Menu: RTL View Commands, on page 97
and Forward
Search command Find Command (HDL Analyst), on page 88
Hierarchy Browser
The Hierarchy Browser is the left pane in the RTL view. (See RTL View, on
page 42). The Hierarchy Browser categorizes the design objects in a series of
trees, and lets you browse the design hierarchy or select objects. Selecting an
object in the Browser selects that object in the schematic. The objects are
organized as shown in the following table, with a symbol that indicates the
object type. See Hierarchy Browser Symbols, on page 45 for common
symbols.
Instances Lists all the instances and primitives in the design.
Ports Lists all the ports in the design
Nets Lists all the nets in the design.
Clock Tree Lists all the instances and ports that drive clock pins in an RTL view. If
you select everything listed under Clock Tree and then use the Filter
Schematic command, you see a filtered view of all clock pin drivers in
your design. Registers are not shown in the resulting schematic,
unless they drive clocks. This view can help you determine what to
define as clocks.
A tree node can be expanded or collapsed by clicking the associated icons:

the square plus ( ) or minus ( ) icons, respectively. You can also expand
or collapse all trees at the same time by right-clicking in the Hierarchy
Browser and choosing Expand All or Collapse All.
LO

44 September 2016
You can use the keyboard arrow keys (left, right, up, down) to move between
objects in the Hierarchy Browser, or you can use the scroll bar. Use the Shift
or Ctrl keys to select multiple objects. See Navigating With a Hierarchy
Browser, on page 370 for more information about using the Hierarchy
Browser for navigation and crossprobing.
Hierarchy Browser Symbols

Common symbols used in Hierarchy Browsers are listed in the following
table.
Symbol Description Symbol Description

Folder Buffer
Input port AND gate
Output port NAND gate
Bidirectional port OR gate
Net NOR gate
Other primitive instance XOR gate
Hierarchical instance XNOR gate
Technology-specific primitive Adder
or inferred ROM
Register Multiplier
or inferred state machine
Multiplexer Equal comparator
Tristate Less-than comparator
Inverter Less-than-or-equal comparator
FSM Viewer Window

Pushing down into a state machine primitive in the RTL view displays the
FSM Viewer and enables the FSM toolbar. The FSM Viewer contains graphical
information about the finite state machines (FSMs) in your design. The
window has a state-transition diagram and tables of transitions and state
encodings.

September 2016 45
State-Transiti
on Diagram
Transitions
and
Encodings
Tables
Note: For the FSM Viewer to display state machine names for a Verilog
design, you must use the Verilog parameter keyword. If you specify
state machine names using the define keyword, the FSM Viewer
displays the binary values for the state machines, rather than
their names.
You can toggle display of the FSM tables on and off with the Toggle FSM Table
icon ( ) on the FSM toolbar. The FSM tables are in the following panels:
The Transitions panel describes, for each transition, the From State, To State,
and Condition of transition.
The RTL Encodings panel describes the correlation, in the RTL view, between
the states (State) and the outputs (Register) of the FSM cell. The following table
describes FSM Viewer operations.
To accomplish this . . . Do this . . .

Open the FSM Viewer Run the FSM Compiler or the FSM Explorer. Use the
push/pop mode in the RTL view to push down into
the FSM and open the FSM Viewer window.
Hide/display the table LO the FSM icons.
Use
Filter selected states and Select the states. Right-click and choose the filter
their transitions criteria from the popup, or use the FSM icons.

46 September 2016
To accomplish this . . . Do this . . .

Display the encoding Select a state. Right-click to display its encoding
properties of a state properties (RTL or Mapped).
Display properties for the Right-click the window, outside the state-transition
state machine diagram. The property sheet shows the selected
encoding method, the number of states, and the total
number of transitions among states.
Crossprobe Double-click a register in an RTL view to see the
corresponding code. Select a state in the FSM view to
highlight the corresponding code or register in other
open views.
See also:
Pushing and Popping Hierarchical Levels, on page 367, for information on
the operation of pushing into a state machine.
FSM Viewer Toolbar, on page 64, for information on the FSM icons.
See Using the FSM Viewer, on page 362 of the User Guide for more infor-
mation on using the FSM viewer.
Dockable GUI Entities

Some of the main GUI entities can appear as either independent windows or
docked elements of the main application window. These entities include the
menu bar, Tcl and Messages windows, and various toolbars (see the descrip-
tion of each entity for details). Docked elements function effectively as panes
of the application window: you can drag the border between two such panes
to adjust their relative areas.
Text Editor View

The Text Editor view displays text files. These can be constraint files, source
code files, or other informational or report files. You can enter and edit text in
the window. You use this window to update source code and fix syntax or
synthesis errors. You can also use it to crossprobe the design.

September 2016 47
Opening the Text Editor

To open the Text Editor to edit an existing file, do one of the following:
Double-click a source code file (v or vhd) in the Project view.
Choose File->Open. In the dialog box displayed, double-click a file to
open it.
With the Windows operating system, you can instead drag and drop a
source file from a Windows folder into the gray background area of the
GUI (not into any particular view).
To open the Text Editor on a new file, select File->New, then specify the type of
text file you want to create. The Text Editor colors HDL source code keywords
such as module and output blue, and colors comments green.
Text Editor Features

The Text Editor has the features listed in the following table.
LO

48 September 2016
Feature Description
Color coding Keywords are blue, comments green, and strings red. All
other text is black.
Editing text You can use the Edit menu or keyboard shortcuts for
basic editing operations like Cut, Copy, Paste, Find, Replace,
and Goto.
Completing keywords To complete a keyword, type enough characters to make
the string unique and then press the Esc key.
Indenting a block of text The Tab key indents a selected block of text to the right.
Shift-Tab indents text to the left.
Inserting a bookmark Click the line you want to bookmark. Choose Edit->Toggle
Bookmark, type Ctrl-F2, or click the Toggle Bookmark icon
( ) on the Edit toolbar.
The line number is highlighted to indicate that there is a
bookmark at the beginning of the line.
Deleting a bookmark Click the line with the bookmark. Choose Edit->Toggle
Bookmark, type Ctrl-F2, or click the Toggle Bookmark icon
( ) on the Edit toolbar. The line number is no longer
highlighted, after the bookmark is deleted.
Deleting all bookmarks Choose Edit->Delete all Bookmarks, type Ctrl-Shift-F2, or click
the Clear All Bookmarks icon ( ) on the Edit toolbar. The
line numbers are no longer highlighted, after the
bookmarks are deleted.
Editing columns Press and hold Alt, then drag the mouse down a column of
text to select it. On some platforms, Alt is replaced by a
different key, such as Meta.
Commenting out code Choose Edit->Advanced->Comment Code. The rest of the
current line is commented out: the appropriate comment
prefix is inserted at the current text cursor position.
Checking syntax Use Run->Syntax Check to highlight syntax errors, such as
incorrect keywords and punctuation, in source code. If
the active window shows an HDL file, then only that file is
checked. Otherwise, the entire project is checked.
Checking synthesis Use Run->Synthesis Check to highlight hardware-related
errors in source code, like incorrectly coded flip-flops. If
the active window shows an HDL file, then only that file is
checked. Otherwise, the entire project is checked.

September 2016 49
See also:
Editor Options Command, on page 203, for information on setting Text
Editor preferences.
File Menu, on page 78, for information on printing setup operations.
Edit Menu Commands for the Text Editor, on page 85, for information
on Text Editor editing commands.
Text Editor Popup Menu, on page 232, for information on the Text
Editor popup menu.
Project View Popup Menu, on page 226, for information on the
command Open as Text, which opens a file in the Text Editor even if there
is a different default method of opening it. An example is opening a
constraint (sdc) file.
Text Editor Toolbar, on page 65, for information on bookmark icons of
the Edit toolbar.
Keyboard Shortcuts, on page 66, for information on keyboard shortcuts
that can be used in the Text Editor.
LO

50 September 2016
FSM Compiler Chapter 2: User Interface Overview
FSM Compiler
The FSM Compiler performs proprietary, state-machine optimization
techniques (other synthesis tools treat state machines as regular logic). You
enable the FSM compiler to take advantage of these techniques; you do not
need special directives or attributes to locate the state machines in your
design. You can also, however, enable the FSM compiler selectively for
individual state machines, using synthesis directives in the HDL description.
The FSM compiler examines your design for state machines. It looks for regis-
ters with feedback that is controlled by the current value of the register, such
as case or if-then-else statements that test the current value of a state register.
It converts state machines to a symbolic form that provides a better starting
point for logic optimization. Several proprietary optimizations are performed
on each symbolic state machine.
Converting from an encoded state machine to a one-hot state machine often

produces better results. However, one-hot implementations are not always
the best choice for FPGAs. An example where the one-hot implementation
can be detrimental in an FPGA is a state machine that drives a large decoder,
generating many output signals. For example, in a state machine with 16
states, the output decoder logic might reference eight signals in a one-hot
implementation, but only four signals in an encoded representation.
During synthesis, a state encoding for an FSM is determined based on certain

predefined characteristics of the state machine. The optional FSM Explorer
feature enhances this capability by automatically determining and using the
best encoding styles for the state machines based on the design constraints
and the area/delay requirements. You can force the use of a particular
encoding style for a state machine by including the appropriate directive in
the HDL description.
The log file contains a description of each state machine extracted, including
a list of the reachable states and the state encoding method used.

September 2016 51
Chapter 2: User Interface Overview FSM Compiler
When to Use FSM Compiler

Use the symbolic FSM compiler to generate better results for state machines,
or to debug state machines. If you do not want to use the symbolic FSM
compiler on the final circuit, you can use it only during initial synthesis to
check that the state machines are described correctly. Many common state
machine description errors result in unreachable states, which are optimized
away during synthesis, resulting in a smaller number of states than you
expect. Reachable states are reported in the log file.
To view a textual description of a state machine in terms of inputs, states,

and transitions, select the state machine in the RTL view, right-click, then
choose View FSM Info File in the popup menu. You can view the same informa-
tion graphically with the FSM viewer. The graphical description of a state
machine makes it easier to verify behavior.
See also:
Log File, on page 250, for information on the log file.
RTL View Popup Menu Commands, on page 236, for information on the
command View FSM Info File.
FSM Viewer Window, on page 45, for information on the FSM Viewer.
Where to Use FSM Compiler (Global and Local Use)

Enable the FSM Compiler check box in the Project view to turn on FSM
synthesis. This allows the tool to recognize, extract, and optimize the state
machines in the design.
The following table summarizes the operations you can perform. For more
information, see Deciding when to Optimize State Machines, on page 598 of
the User Guide.
To... Do this...
Globally enable (disable) Enable (disable) the FSM Compiler check box on the
the FSM Compiler Options tab.
Enable (disable) the FSM Disable (enable) the FSM Compiler check box and set
compiler for a specific LOVerilog syn_state_machine directive to 1 (0), or
the
register the VHDL syn_state_machine directive to true (false),
for that instance of the state register.

52 September 2016
Using the Mouse Chapter 2: User Interface Overview
Using the Mouse

The Synopsys FPGA tools provide support for:
Using Mouse Strokes, on page 53
Using the Mouse Buttons, on page 55
Using The Mouse Wheel, on page 57
Using Mouse Strokes

Mouse strokes are used to quickly perform simple repetitive commands.
Mouse strokes are drawn by pressing and holding the right mouse button as
you draw the pattern. The stroke must be at least 16 pixels in width or height
to be recognized. You will see a green mouse 'trail' as you draw the stroke (the
actual color depends on the window background color).
Some strokes are context sensitive. That is, the interpretation of the stroke
depends upon the window in which the stroke is started. For example, in an
Analyst view, the right stroke means "Next Sheet." In a dialog box, the right
stroke means "OK."
For information on each of the available mouse strokes, consult the Mouse
Stroke Tutor.
The strokes you draw are interpreted on a grid of one to three rows. Some
strokes are similar, differing only in the number of columns or rows, so it may
take a little practice to draw them correctly. For example, the strokes for Redo
and Back differ in that the Redo stroke is back and forth horizontally, within a
single-row grid, while the Back stroke involves vertical movement as well.
Redo Last Operation Back to Previous View

September 2016 53
Chapter 2: User Interface Overview Using the Mouse
The Mouse Stroke Tutor

Do one of the following to access the Mouse Stroke Tutor:
Help->Stroke Tutor
Draw a question mark stroke ("?")
Scribble (Show tutor when scribbling must be enabled on the Stroke Help
dialog box)
The tutor displays the available strokes along with a description and a
diagram of the stroke. You can draw strokes while the tutor is displayed.
Mouse strokes are context sensitive. When viewing the Stroke Tutor, you can
choose All Strokes or Current Context to view just the strokes that apply to the
context of where you invoked the tutor. For example, if you draw the "?"
stroke in an Analyst window, the Current Context option in the tutor shows only
those strokes recognized in the Analyst window.
You can display the tutor while working in a window such as the Analyst RTL
view. However you cannot display the tutor while a modal dialog is displayed,
as input is restricted to the modal dialog.
LO

54 September 2016
Using the Mouse Chapter 2: User Interface Overview
Using the Mouse Buttons

The operations you can perform using mouse buttons include the following:
You select an object by clicking it. You deselect a selected object by

clicking it. Selecting an object by clicking it deselects all previously
selected objects.
You can select and deselect multiple objects by pressing and holding the
Control key (Ctrl) while clicking each of the objects.
You can select a range of objects in a Hierarchy Browser, as follows:
select the first object in the range
scroll the tree of objects, if necessary, to display the last object in the
range
press and hold the Shift key while clicking the last object in the range
Selecting a range of objects in a Hierarchy Browser crossprobes to the
corresponding schematic, where the same objects are automatically
selected.
You can select all of the objects in a region by tracing a selection
rectangle around them (lassoing).
You can select text by dragging the mouse over it. You can alternatively
select text containing no white space (such as spaces) by
double-clicking it.
Double-clicking sometimes selects an object and immediately initiates a
default action associated with it. For example, double-clicking a source
file in the Project view opens the file in a Text Editor window.
You can access a contextual popup menu by clicking the right mouse
button. The menu displayed is specific to the current context, including
the object or window under the mouse.
For example, right-clicking a project name in the Project view displays a

popup menu with operations appropriate to the project file.
Right-clicking a source (HDL) file in the Project view displays a popup
menu with operations applicable to source files.
Right-clicking a selectable object in an HDL Analyst schematic also

selects it, and deselects anything that was selected. The resulting popup
menu applies only to the selected object. See RTL View, on page 42 for
information on HDL Analyst views.

September 2016 55
Chapter 2: User Interface Overview Using the Mouse
Most of the mouse button operations involve selecting and deselecting

objects. To use the mouse in this way in an HDL Analyst schematic, the
mouse pointer must be the cross-hairs symbol: . If the cross-hairs pointer
is not displayed, right-click the schematic background to display it.
LO

56 September 2016
Setting User Interface Preferences Chapter 2: User Interface Overview
Using The Mouse Wheel

If your mouse has a wheel and you are using a Microsoft Windows platform,
you can use the wheel to scroll and zoom, as follows:
Whenever only a horizontal scroll bar is visible, rotating the wheel
scrolls the window horizontally.
Whenever a vertical scroll bar is visible, rotating the wheel scrolls the
window vertically.
Whenever both horizontal and vertical scroll bars are visible, rotating
the wheel while pressing and holding the Shift key scrolls the window
horizontally.
In a window that can be zoomed, such as a graphics window, rotating
the wheel while pressing and holding the Ctrl key zooms the window.
Setting User Interface Preferences

The following table lists the commands with which you can set preferences
and customize the user interface.
Preferences Description For option descriptions, see...

Text Editor Fonts and colors Editor Options Command
HDL Analyst tool HDL Analyst options HDL Analyst Menu
(RTL view)
Project view Organization and Project View Options
display of project files Command

September 2016 57
Chapter 2: User Interface Overview Setting User Interface Preferences
Managing Views
As you work on a project, you move between different views of the design. The
following guidelines can help you manage the different views you have open.
1. Enable the option View->Workbook Mode.
Below the Project view are tabs, one for each open view. The icon accom-
panying the view name on a tab indicates the type of view. The example
below shows tabs for four views: the Project view, an RTL view, a Verilog
Text Editor view, and an active Partition view.
2. To bring an open view to the front and make it the current (active) view,
click any visible part of the window, or click the tab of the view.
If you previously minimized the view, it will be activated, but will remain
minimized. To display the view, double-click the minimized view.
3. To activate the next view and bring it to the front, type Ctrl-F6. Repeating
this keyboard shortcut cycles through all open views. If the next view
was minimized it remains minimized, but it is brought to the front so
that you can restore it.
4. To close a view, type Ctrl-F4 in the view, or choose File->Close.
5. You can rearrange open windows using the Window menu: you can
cascade them (stack them, slightly offset), or tile them horizontally or
vertically.
LO

58 September 2016
Toolbars Chapter 2: User Interface Overview
Toolbars
Toolbars provide a quick way to access common menu commands by clicking
their icons. The following standard toolbars are available:
Project Toolbar Project control and file manipulation.
Analyst Toolbar Manipulation of the RTL views.
View Toolbar Viewing and hierarchy navigation.
FSM Viewer Toolbar Display of finite state machine (FSM) informa-
tion.
Text Editor Toolbar Text Editor bookmark commands.
You can enable or disable the display of individual toolbars see Toolbar
Command, on page 99.
Project Toolbar
The Project toolbar provides the following icons:
Constraint Save
File (new) Open All Copy Undo
Open Board
Project Wizard Save Cut Paste Redo
Launch
Identify Launch Partitioned
Find Instrumentor SynCore RTL View
Constraint Launch RTL Implementation

Check Identify View SRP View
Debugger

September 2016 59
Chapter 2: User Interface Overview Toolbars
Icon Description
Open Project Displays the Open Project dialog box to create a
new project or to open an existing project.
Same as File->Open Project.
New Constraint File Opens the SCOPE spreadsheet with a new,
empty constraint file.
Same as File->New, Constraint File (SCOPE).
Board Wizard Creates a board description file or selects an
existing, off-the-shelf board for a project.
Open Displays the Open dialog box, to open a file.
Same as File->Open.
Save Saves the current file. If the file has not yet
been saved, this displays the Save As dialog
box, where you specify the filename. The kind
of file depends on the active view.
Same as File->Save.
Save All Saves all files associated with the current
design.
Same as File->Save All.
Cut Cuts text or graphics from the active view,
making it available to Paste.
Same as Edit->Cut.
Copy Copies text or graphics from the active view,
making it available to Paste.
Same as Edit->Copy.
Paste Pastes previously cut or copied text or
graphics to the active view.
Same as Edit->Paste.
Undo Undoes the last action taken.
Same as Edit->Undo.
Redo Performs the action undone by Undo.
LO Same as Edit->Redo.

60 September 2016
Icon Description
Find Finds text in the Text Editor or objects in an
RTL view.
Same as Edit->Find.
Constraint Check Checks the syntax and applicability of the
timing constraints in the sdc file for your
project and generates a report
(projectName_cck.rpt).
Same as Run->Constraint Check.
Launch SYNCore Launches the SYNCore IP wizard. This tool
helps you build IP blocks such as memory
models for your design.
For more information, see Launch SYNCore,
on page 146.
Analyst Toolbar
The Analyst toolbar becomes active after a design has been compiled. The
toolbar provides the following icon:
Partitioned
RTL View
RTL View Implementation

SRP View

September 2016 61
The following table describes the default Analyst icons.
Icon Description
RTL View Opens a new, hierarchical RTL view: a register
transfer-level schematic of the compiled design,
together with the associated Hierarchy Browser.
Same as HDL Analyst->RTL->Hierarchical View.
Partitioned RTL View Displays the current logic assignments.
Implementation SRP View Displays the SRP file created for the active
implementation.
View Toolbar
The View toolbar lets you zoom in and out of your schematic, and traverse its
hierarchy in various ways. It provides the following icons, by default:
Filter Filter on Forward Zoom Zoom Push/Pop Next

Schematic Selected Gates (history) In Full Hierarchy Sheet
Show Back Zoom Zoom Zoom Previous

Critical Path (history) 100% Out Selected Sheet
The following table describes the default View icons. Each is available in HDL
Analyst views, and each is equivalent to a View menu command available
there see View Menu, on page 95, for more information. Zoom icons are also
available in some other views.
LO

62 September 2016
Icon Description
Timing Analyst... Displays the Timing Report Generation dialog box
following time-budget estimation when performing
system-level timing analysis.
Same as Analysis->Timing Analyst.
Filter on Selected Gates Filters your entire design to show only the selected
objects. The result is a filtered schematic.
Same as HDL Analyst->Filter Schematic.
Back Goes backward in the history of displayed sheets of the
current HDL Analyst view.
Same as View->Back.
Forward Goes forward in the history of displayed sheets of the
Same as View->Forward.
Zoom 100% Zooms in at a 1:1 ratio and centers the active view
where you click. If the view is already normal size, it
re-centers the view at the new click location.
Same as View->Normal View.
Zoom In Zooms the view in or out. Buttons stay active until
deselected.
Zoom Out Same as View->Zoom In or View->Zoom Out.
Zoom Full Zoom that reduces the active view to display the entire
design or partition.
Same as View->Full View.
Zoom Selected When selected, zooms in on only the selected objects to
the full window size.
Push/Pop Hierarchy Toggles traversing the hierarchy using the push/pop
mode.
Same as View->Push/Pop Hierarchy.
Previous Sheet Displays the previous sheet of a multiple-sheet
schematic.
Same as View->Previous Sheet.
Next Sheet Displays the next sheet of a multiple-sheet schematic.
Same as View->Previous Sheet.

September 2016 63
FSM Viewer Toolbar

When you push down into a state machine primitive in an RTL view, the FSM
Viewer displays and enables the FSM toolbar. The FSM Viewer graphically
displays the states and transitions. It also lists them in table form. By
default, the FSM toolbar provides the following icons, providing access to
common FSM Viewer commands.
Toggle FSM Table Filter by outputs
Unfilter FSM
The following table describes the default FSM icons. Each is available in the
FSM viewer, and each is equivalent to a View menu command available there
see View Menu, on page 95, for more information.
Icon Description
Toggle FSM Table Toggles the display of state-and-transition tables.
Same as View->FSM Table.
Unfilter FSM Restores a filtered FSM diagram so that all the states and
transitions are showing.
Same as View->Unfilter.
Filter by outputs Hides all but the selected states, their output transitions,
and the destination states of those transitions.
Same as View->Filter->By output transitions.
LO

64 September 2016
Text Editor Toolbar

The Edit toolbar is active whenever the Text Editor is active. You use it to edit
bookmarks in the file. (Other editing operations are located on the Project
toolbar see Project Toolbar, on page 59.) The Edit toolbar provides the
following icons, by default:
Toggle Bookmark Previous Bookmark
Next Bookmark Clear All Bookmarks
The following table describes the default Edit icons. Each is available in the
Text Editor, and each is equivalent to an Edit menu command there see Edit
Menu Commands for the Text Editor, on page 85, for more information.
Icon Description
Toggle Bookmark Alternately inserts and removes a bookmark at the line
that contains the text cursor.
Same as Edit->Toggle bookmark.
Next Bookmark Takes you to the next bookmark.
Same as Edit->Next bookmark.
Previous Bookmark Takes you to the previous bookmark.
Same as Edit->Previous bookmark.
Clear All Bookmarks Removes all bookmarks from the Text Editor window.
Same as Edit->Delete all bookmarks.

September 2016 65
Chapter 2: User Interface Overview Keyboard Shortcuts
Keyboard Shortcuts
Keyboard shortcuts are key sequences that you type in order to run a
command. Menus list keyboard shortcuts next to the corresponding
commands. For example, to check syntax, you can press and hold the Shift
key while you type the F7 key, instead of using the menu command
Run->Syntax Check.
The following table describes the keyboard shortcuts.
Keyboard Description
Shortcut
b In an RTL view, shows all logic between two or more selected
objects (instances, pins, ports). The result is a filtered
schematic. Limited to the current schematic.
Ctrl-++ In the FSM Viewer, hides all but the selected states, their output
(number pad) transitions, and the destination states of those transitions.
Same as View->Filter->By output transitions.
Ctrl-+- In the FSM Viewer, hides all but the selected states, their input
(number pad) transitions, and the origin states of those transitions.
Same as View->Filter->By
LO input transitions.

66 September 2016
Keyboard Shortcuts Chapter 2: User Interface Overview
Shortcut
Ctrl-+* In the FSM Viewer, hides all but the selected states, their input
(number pad) and output transitions, and their predecessor and successor
states.
Same as View->Filter->By any transition.
Ctrl-1 In an RTL view, zooms the active view, when you click, to full
(normal) size. Same as View->Normal View.
Ctrl-a Centers the window on the design. Same as View->Pan Center.
Ctrl-b In an RTL view, shows all logic between two or more selected
objects (instances, pins, ports). The result is a filtered
schematic. Operates hierarchically, on lower levels as well as the
current schematic.
Ctrl-c Copies the selected object. Same as Edit->Copy. This shortcut is
sometimes available even when Edit->Copy is not. See, for
instance, Find Command (HDL Analyst), on page 88.)
Ctrl-d In an RTL view, selects the driver for the selected net. Operates
hierarchically, on lower levels as well as the current schematic.
Ctrl-e In an RTL view, expands along the paths from selected pins or
ports, according to their directions, to the nearest objects (no
farther). The result is a filtered schematic. Operates
Ctrl-Enter (Return) In the FSM Viewer, hides all but the selected states. Same as
View->Filter->Selected (see View Menu, on page 95).
Ctrl-f Finds the selected object. Same as Edit->Find.
Ctrl-F2 Alternately inserts and removes a bookmark to the line that

contains the text cursor.
Same as Edit->Toggle bookmark (see Edit Menu Commands for the
Text Editor, on page 85).
Ctrl-F3 Toggles the Impact Analysis panel on and off in the Partition
Device view.
Ctrl-F4 Closes the current window. Same as File->Close.
Ctrl-F6 Toggles between active windows.

September 2016 67
Shortcut
Ctrl-g In the Text Editor, jumps to the specified line. Same as Edit->Goto
(see Edit Menu Commands for the Text Editor, on page 85).
In an RTL view, selects the sheet number in a multiple-page
schematic. Same as View->View Sheets (see View Menu: RTL View
Commands, on page 97).
Ctrl-h In the Text Editor, replaces text. Same as Edit->Replace (see Edit
Menu Commands for the Text Editor, on page 85).
Ctrl-i In an RTL view, selects instances connected to the selected net.
Operates hierarchically, on lower levels as well as the current
schematic.
Ctrl-j In an RTL view, displays the unfiltered schematic sheet that
contains the net driver for the selected net. Operates
Ctrl-l In the FSM Viewer, or an RTL view, toggles zoom locking. When
locking is enabled, if you resize the window the displayed
schematic is resized proportionately, so that it occupies the
same portion of the window.
Same as View->Zoom Lock (see View Menu Commands: All Views,
on page 95).
Ctrl-m In an RTL view, expands inside the sub-design, from the
lower-level port that corresponds to the selected pin, to the
nearest objects (no farther).
Ctrl-n Creates a new file or project. Same as File->New.
Ctrl-o Opens an existing file or project. Same as File->Open.
Ctrl-p Prints the current view. Same as File->Print.
Ctrl-q In an RTL view, toggles the display of visual properties of

instances, pins, nets, and ports in a design.
Ctrl-r In an RTL view, expands along the paths from selected pins or
ports, according to their directions, until registers, ports, or
black boxes are reached. The result is a filtered schematic.
Operates hierarchically, on lower levels as well as the current
schematic.
Ctrl-s LOView, saves the file. Same as File->Save.
In the Project
Ctrl-t Toggles display of the Tcl window.

Same as View->Tcl Window (see View Menu, on page 95).

68 September 2016
Shortcut
Ctrl-u In the Text Editor, changes the selected text to lower case. Same
as Edit->Advanced->Lowercase (see Edit Menu Commands for the
Text Editor, on page 85).
In the FSM Viewer, restores a filtered FSM diagram so that all
the states and transitions are showing. Same as View->Unfilter
(see View Menu: FSM Viewer Commands, on page 97).
Ctrl-v Pastes the last object copied or cut. Same as Edit->Paste.
Ctrl-x Cuts the selected object or objects, making them available to

paste. Same as Edit->Cut.
Ctrl-y In an RTL view, goes forward in the history of displayed sheets

for the current HDL Analyst view. Same as View->Forward (see
View Menu: RTL View Commands, on page 97).
In other contexts, performs the action undone by Undo. Same as
Edit->Redo.
Ctrl-z In an RTL view, goes backward in the history of displayed sheets

for the current HDL Analyst view. Same as View->Back (see View
Menu: RTL View Commands, on page 97).
In other contexts, undoes the last action. Same as Edit->Undo.
Ctrl-Shift-F2 Removes all bookmarks from the Text Editor window. Same as
Edit->Delete all bookmarks (see Edit Menu Commands for the Text
Editor, on page 85).
Ctrl-Shift-h In an RTL view, shows all pins on selected transparent
hierarchical (non-primitive) instances. Pins on primitives are
always shown. Available only in a filtered schematic.
Ctrl-Shift-i In an RTL view, selects all instances on the current schematic
level (all sheets). This does not select instances on other levels.
Same as HDL Analyst->Select All Schematic->Instances (see HDL
Analyst Menu, on page 188).
Ctrl-Shift-p In an RTL view, selects all ports on the current schematic level
(all sheets). This does not select ports on other levels.
Same as HDL Analyst->Select All Schematic->Ports (see HDL Analyst
Menu, on page 188).
Ctrl-Shift-u In the Text Editor, changes the selected text to lower case.
Same as Edit->Advanced->Uppercase (see Edit Menu Commands
for the Text Editor, on page 85).

September 2016 69
Shortcut
d In an RTL view, selects the driver for the selected net. Limited to
the current schematic.
Same as HDL Analyst->Current Level->Select Net Driver (see HDL
Delete (DEL) Removes the selected files from the project. Same as
Project->Remove Files From Project.
e In an RTL view, expands along the paths from selected pins or

ports, according to their directions, to the nearest objects (no
farther). Limited to the current schematic.
Same as HDL Analyst->Current Level->Expand (see HDL Analyst
Menu, on page 188).
F1 Provides context-sensitive help. Same as Help->Help.
F2 In an RTL view, toggles traversing the hierarchy using the

push/pop mode. Same as View->Push/Pop Hierarchy (see View
Menu: RTL View Commands, on page 97).
In the Text Editor, takes you to the next bookmark. Same as
Edit->Next bookmark (see Edit Menu Commands for the Text
Editor, on page 85).
F3 In the RTL and Partition Device views, toggles display of the
connectivity matrix.
F4 In the Project view, adds a file to the project. Same as
Project->Add Source File (see Build Project Command, on
page 83).
In an RTL, zooms the view so that it shows the entire design or
partition. Same as View->Full View (see View Menu: RTL View
F5 Displays the next source file error.
Same as Run->Next Error/Warning (see Run Menu, on page 140).
F7 Compiles the design and board files.
Same as Run->Preparation (see Run Menu, on page 140).
F9 Obtains area utilization for the design.
Same as Run->Estimate Area: (see Run Menu, on page 140).
LO

70 September 2016
Shortcut
F10 In the Project view, runs the FSM Explorer to determine
optimum encoding styles for finite state machines. Same as
Run->FSM Explorer (see Run Menu, on page 140).
In an RTL view, lets you pan (scroll) the schematic by dragging it
with the mouse. Same as View->Pan (see View Menu: RTL View
F11 Toggles zooming in.
Same as View->Zoom In (see View Menu: RTL View Commands,
on page 97).
F12 In an RTL view, filters your entire design to show only the
selected objects.
i In an RTL view, selects instances connected to the selected net.
Limited to the current schematic.
Same as HDL Analyst->Current Level->Select Net Instances (see HDL
j In an RTL view, displays the unfiltered schematic sheet that
contains the net driver for the selected net.
Same as HDL Analyst->Current Level->Goto Net Driver (see HDL
r In an RTL view, expands along the paths from selected pins or
ports, according to their directions, until registers, ports, or
black boxes are reached. The result is a filtered schematic.
Limited to the current schematic.
Same as HDL Analyst->Current Level->Expand to Register/Port (see
HDL Analyst Menu, on page 188).
Shift-F2 In the Text Editor, takes you to the previous bookmark.
Shift-F4 Allows you to add source files to your project (Project->Add Source
Files).
Shift-F5 Displays the previous source file error.

Same as Run->Previous Error/Warning (see Run Menu, on
page 140).
Shift-F7 Checks source file syntax.
Same as Run->Syntax Check (see Run Menu, on page 140).
Shift-F8 Checks synthesis.
Same as Run->Synthesis Check (see Run Menu, on page 140).

September 2016 71
Shortcut
Shift-F10 Checks the timing constraints in the constraint files in your
project and generates a report (projectName_cck.rpt).
Same as Run->Constraint Check (see Run Menu, on page 140).
Shift-F11 Toggles zooming out.
Same as View->Zoom Out (see View Menu, on page 95).
Shift-Left Arrow Displays the previous sheet of a multiple-sheet schematic.
Shift-Right Arrow Displays the next sheet of a multiple-sheet schematic.
Shift-s Dissolves the selected instances, showing their lower-level

details. Dissolving an instance one level replaces it, in the
current sheet, by what you would see if you pushed into it using
the push/pop mode. The rest of the sheet (not selected) remains
unchanged.
The number of levels dissolved is the Dissolve Levels value in the
Schematic Options dialog box. The type (filtered or unfiltered) of the
resulting schematic is unchanged from that of the current
schematic. However, the effect of the command is different in
filtered and unfiltered schematics.
LO

72 September 2016
Buttons and Options Chapter 2: User Interface Overview
Buttons and Options

The Project view contains a series of buttons grouped into logical functions:
Project management
Partition Management
SLP Management
The following table describes the Project view buttons and options.
Project Management Action

Run Preparation Compiles the design and board files and optimizes the
design.
Partition Management Selects Partition, CPM, or Trace Assignment views based
on current design status.
SLP Generation Generates individual SLP projects for synthesis; design
must be completely partitioned and net-to-trace
assignment must be complete.

September 2016 73
Chapter 2: User Interface Overview Buttons and Options
Project Management Action

Run SLP Projects Calls the Synplify Premier tool to synthesizes all SLP
projects.
Cancel Jobs Cancels any executing job.
Open Project... Opens a new or existing project.

Same as File->Open Project (see Open Project Command, on
page 83).
Close Project Closes the current project.
Same as File->Close Project (see Run Menu, on page 140).
Add File... Adds a source file to the project.
Same as Project->Add Source File (see Build Project
Command, on page 83).
Change File... Replaces one source file with another.
Same as Project->Change File (see Change File Command,
on page 105).
Add Implementation ... Creates a new implementation.
Implementation Displays the Implementation Options dialog box, where you

Options ... can set various options for synthesis.
Same as Project->Implementation Options (see Implementation
Options Command, on page 114).
View Logs Action
View Log Opens the log file.
Same as View->View Log File.
SLP Generation Log Opens the SLP generation log file (projName_slpgen.srr).
LO

74 September 2016
CHAPTER 3
User Interface Commands
The following sections describe the menu commands and ways to access
these commands in the graphical user interface (GUI).
Command Access, on page 76
File Menu, on page 78
Edit Menu, on page 85
View Menu, on page 95
Project Menu, on page 101
Implementation Options Command, on page 114
Run Menu, on page 140
Tools Menu, on page 146
Analysis Menu, on page 176
HDL Analyst Menu, on page 188
Options Menu, on page 197
Tech-Support Menu, on page 216
Web Menu, on page 221
Help Menu, on page 222
Popup Menus, on page 225

September 2016 75
Chapter 3: User Interface Commands Command Access
Command Access
The product interface provides access to the commands in the following ways:
Menus, on page 76
Context-sensitive Popup Menus, on page 77
Toolbars, on page 77
Keyboard Shortcuts, on page 77
Buttons and Options, on page 77
Tcl Command Equivalents, on page 77
Menus
The set of commands on the pull-down menus in the menu bar varies
depending on the view, design status, task to perform, and selected object.
For example, the File menu commands in the Project view differ slightly from
those in the RTL view. Menu commands that are not available for the current
context are grayed out. The menu bar in the Project view is shown below:
The individual menus, their commands, and the associated dialog boxes are
described in the following sections:
File Menu, on page 78
Edit Menu, on page 85
Project Menu, on page 101
Run Menu, on page 140
Tools Menu, on page 146
Analysis Menu, on page 176
HDL Analyst Menu, on LO
page 188
Options Menu, on page 197

76 September 2016
Command Access Chapter 3: User Interface Commands
Tech-Support Menu, on page 216

Web Menu, on page 221
Help Menu, on page 222
Context-sensitive Popup Menus

Popup menus, available by right-clicking, offer access to commonly used
commands that are specific to the current context. See Popup Menus, on
page 225, for information on individual popup menus.
Toolbars
Toolbars contain icons associated with commonly used commands. For more
information about toolbars, see Toolbars, on page 59.
Keyboard Shortcuts
Keyboard shortcuts are available for commonly used commands. The
shortcut appears next to the command in the menu. See Keyboard Shortcuts,
on page 66 for details.
Buttons and Options

The Project view has buttons for quick access to commonly used commands
and options. See Buttons and Options, on page 73 for details.
Tcl Command Equivalents

The Tcl (Tool Command Language) commands can be entered directly in the
Tcl window or included in Tcl scripts that you can run in batch mode. For
information about Tcl commands, see the Certify Command Reference.

September 2016 77
Chapter 3: User Interface Commands File Menu
File Menu
Use the File menu for opening, creating, saving, and closing projects and files.
The following table describes the File menu commands.
Command Description
New Creates one of the following types of files: Verilog, VHDL, text,
Tcl script, Xilinx options, Synopsys design constraints,
compiler directives, constraint, analysis design constraints,
project, or prototyping tool.
Load Prototyping Explicitly loads a board, netlist. area estimation, or timing
File estimation file into the project; also specifies board options
(HSTDM, DIFF I/O) for board loaded. This option is only available
with the partition-management interface.
Open Opens a project or file.
Close Closes projects.

Save Saves a project or a file.
Save As Saves a project or a file to a specified name.
Save All Saves all projects or files.
Print Prints a file. For more information about printing, see the
operating system documentation.
Print Setup Lets you specify print options.
Create Image Available only in the RTL, FSM, and Partition Device views.
Creates an image of a region you define in the view. A camera
pointer ( ) appears. Drag a selection rectangle around the
region to image or simply click in the view to image the entire
view. A dialog box allows the image to be copied, saved, or
printed. See Load Prototyping File, on page 81.
Build Project Creates a new project based on the file open in the Text Editor
(if active), or lets you choose files to add to a new project. See
Build Project Command, on page 83.
Open Project Opens a project. See Open Project Command, on page 83.
LO

78 September 2016
File Menu Chapter 3: User Interface Commands
Command Description
New Project Creates a new project. If a project is already open, it prompts
you to save it before creating a new one. If you want to open
multiple projects, select Allow multiple projects to be opened in the
Project View dialog box. See Project View Options Command, on
page 199.
Close Project Closes the current project.
Recent Projects Lists recently accessed projects. Choose a project listed in the
submenu to open it.
Recent files Lists the last six files you opened as separate menu items.
(listed as separate Choose a file to open it.
menu items)
Exit Exits the session.
New Command
Select File->New to display the New dialog box where you can select a file type
to be created. For most file types, a text editor window opens to allow you to
define the file contents. You must provide a file name. You can automatically
add the new file to your project by enabling the Add To Project checkbox before
clicking OK.

September 2016 79
File Type Opens Window Directory Name Extension
Verilog Text Editor Verilog .v

VHDL Text Editor VHDL .vhd
Tcl Script Text Editor Tcl Script .tcl
Text Text Editor Other .txt
Xilinx Options Text Editor P&R Options .opt
Compiler Directives Modified Text Editor Compiler Directive .cdc
FPGA Design SCOPE Logic Constraints (FDC) .fdc
Constraints
Analysis Design SCOPE Analysis Design Constraint .adc

Constraints
LO
Project None None .prj
Prototyping Tool Bit Slice UI Prototyping Constraint .ptf

80 September 2016
Load Prototyping File

Select File->Load Prototyping File to display the Load Prototyping File dialog box,
where you can select the prototyping file for the project (board, netlist, area
estimation, or timing estimation). The name of the prototyping file is entered
into the Specify File field. When the Board type radio button is selected, the
Board Options field is enabled to select HSTDM, differential I/O, and/or HAPS
functional groups. The file selection is added by clicking the Load button.
Create Image Command

Select File->Create Image to create a capture image from any of the following
views:
Partition Device view
RTL view
FSM Viewer
Drag the camera cursor to define the area for the image. When you release
the cursor, the Create Image dialog box appears. Use the dialog box to copy the
image, save the image to a file, or to print the image.

September 2016 81
Field/Option Description
Copy to Clipboard Copies the image to the clipboard so you can paste it into a
selected application (for example, a Microsoft Word file).
When you copy an image to the clipboard, a green check
mark appears in the Copy To Clipboard field.
Save to File Saves the image to the specified file. You can save the file in
a number of formats (platform dependent) including bmp,
jpg, png, ppm, tif, xbm, and xpm.
Add to Project Adds the saved image file to the Images folder in the Project
view. This option is enabled by default.
Save to File button You must click this button to save an image to the specified
file. When you save the image, a green check mark appears
in the Save To File field.
LO

82 September 2016
Print Prints the image. When you print the image, a green check
mark appears in the Print field.
Options Allows you to select the resolution of the image saved to a
file or copied to the clipboard. Use the Max Pixels slider to
change the image resolution.
Caption Allows you to enter a caption for a saved or copied image.
The caption is overlayed at the top-left corner of the image.
Build Project Command

Select File->Build Project to build a new project. This command behaves differ-
ently if an HDL file is open in the Text Editor.
When an active Text Editor window with an HDL file is open, File->Build
Project creates a project with the same name as the open file.
If no file is open, File->Build Project prompts you to add files to the project
using the Select Files to Add to New Project dialog box. The name of the new
project is the name of the first HDL file added. See Add Source File
Open Project Command

Select File->Open Project to open an existing project or to create a new project.

September 2016 83
Existing Project Displays the Open Project dialog box for opening an existing
project.
New Project Creates a new project and places it in the Project view.
LO

84 September 2016
Edit Menu Chapter 3: User Interface Commands
Edit Menu
You use the Edit menu to edit text files (such as HDL source files) in your
project. These operations include cutting, copying, pasting, finding, and
replacing text, manipulating bookmarks, and commenting-out code lines.
The Edit menu commands available at any time depend on the active window
or view (Project, Text Editor, SCOPE spreadsheet, RTL, or Partition).
The following table describes all of the Edit menu commands:
Command Description
Basic Edit Menu Commands
Undo Cancels the last action.
Redo Performs the action undone by Undo.
Cut Removes the selected text and makes it available to

Paste.
Copy Duplicates the selected text and makes it available to

Paste.
Paste Pastes text that was cut (Cut) or copied (Copy).
Delete Deletes the selected object.
Find Searches the file for text matching a given search

string; see Find Command (Text), on page 86. In the
RTL view, opens the Object Query dialog box, which lets
you search your design for instances, symbols, nets,
and ports, by name; see Find Command (HDL
Analyst), on page 88. In the project view, searches files
for text strings; see Find Command (In Project), on
page 87.
Find Next Continues the search initiated by the last Find.
Find in Files Performs a string search of the target files (see Find in
Files Command, on page 91).
Prototyping Context Selects the Partition Management context among
partitioning, CPM assignment, and trace assignment.
Edit Menu Commands for the Text Editor
Select All Selects all text in the file.

September 2016 85
Chapter 3: User Interface Commands Edit Menu
Command Description
Replace Finds and replaces text. See Replace Command, on
page 93.
Goto Goes to a specific line number. See Goto Command, on
page 94.
Toggle bookmark Toggles between inserting and removing a bookmark on
the line that contains the text cursor.
Next bookmark Takes you to the next bookmark.
Previous bookmark Takes you to the previous bookmark.
Delete all bookmarks Removes all bookmarks from the Text Editor window.
Advanced->Comment Code Inserts the appropriate comment prefix for the selected
text.
Advanced->Uncomment Deletes the corresponding comment prefix from the
Code selected text.
Advanced->Uppercase Makes the selected string all upper case.
Advanced->Lowercase Makes the selected string all lower case.
Edit Menu Commands Partition View

Clear All Assignments Clears all assignments from the selected FPGA
Unassign from Device Deletes the instance or instances selected in the

Partition Tree or Partition Info view.
Partition Board View Presents an abstraction of the board for interactive
partitioning. See Chapter 6, Layout of the Certify
Partition Board View.
Find Command (Text)

Select Edit->Find to display the Find dialog box. In the SCOPE window, the FSM
view, and the Text Editor window, the command has basic text-based search
capabilities. Some search features, like regular expressions and line-number
highlighting, are available only in the Text Editor. See Find Command (In
Project), on page 87, to searchLOfor files in the Project
The HDL Analyst Find command is different; see Find Command (HDL
Analyst), on page 88 for details.

86 September 2016
Find what Search string matching the text to find. In the text editor,
you can use the pull-down list to view and reuse search
strings used previously in the current session.
Match whole word only When enabled, matches the entire word rather than a
portion of the word.
Match case When enabled, searching is case sensitive.
Regular expression When enabled, wildcard characters (* and ?) can be used in

the search string: ? matches any single character; * matches
any string of characters, including an empty string.
Direction Changes search direction. In the text editor, buttons select
the search direction (Up or Down).
Find Next Initiates a search for the search string (see Find What/Search
for). In the text editor, searching starts again after reaching
the end (Down) or beginning (Up) of the file.
Mark All Highlights the line numbers of the text matching the search
string and closes the Find dialog box.
Find Command (In Project)

Select Edit->Find to display the Find File dialog box. In the Project view, the
command has basic text-based search capabilities to locate files in the
project.

September 2016 87
All or part of the file Search string matching the file to find. You can specify all or
name part of the file name.
Look in Search for files in all projects or limit the search to files only in
the specified project.
Match Case When enabled, searching is case sensitive.
Search up Searches in the up direction (search terminates when an end

of tree is reached in either direction).
Exclude path Excludes the path name from the search.
Find Next Initiates a search for the file name string.
Find Command (HDL Analyst)

In the RTL view, use Edit->Find to display the Object Query dialog box. For a
detailed procedure about using this command, see Using Find for Hierarchical
and Restricted Searches, on page 329 of the User Guide.
LO

88 September 2016
Type of objects
to find
Level to
search
Objects Objects to find

matching filter in schematic
(search (and select)
candidates)
Filter string
Get more
candidates
The available Find menu commands vary, depending on your current view.
The following table describes all of the Find menu commands:
Instances, Tabbed panels for finding different kinds of objects. Choose a panel
Symbols, for a given object type by clicking its tab. In terms of memory
Nets, Ports consumption, searching for Instances is most efficient, and searching
for Nets is least efficient.
Search Where to search: Entire Design, Current Level & Below, or Current Level
Only. See Using Find for Hierarchical and Restricted Searches, on
page 329 of the User Guide.
UnHighlighted Names of all objects of the current panel type, in the level chosen to
Search, that match the Highlight Search (*?) filter. This list is populated
by the Find 200 and Find All buttons.
To select an object as a candidate for highlighting, click its name in
this list. The complete name of the selected object appears near the
bottom of the dialog box. You can select part or all of this complete
name, then use the Ctrl-C keyboard shortcut to copy it for pasting.
You can select multiple objects by pressing the Ctrl or Shift key while
clicking; press Ctrl and click a selection to deselect it. The number of
objects selected, and the total number listed, are displayed above the
list, after the UnHighlighted: label: # selected of # total.
To confirm a selection for highlighting and move the selected objects
to the Highlighted list, click the -> button.

September 2016 89
Highlight Determines which object names appear in the UnHighlighted area,
Search (*?) based on the case-sensitive filter string that you enter. For tips
about using this field, see Using Wildcards with the Find
Command, on page 332 of the User Guide.
The filter string can contain the following wildcard characters:
* (asterisk) matches any sequence of characters;
? (question mark) matches any single character;
. (period) does not match any characters, but indicates a change
in hierarchical level.
Wildcards * and ? only match characters within the current
hierarchy level; a*b*, for example, will not cross levels to match
alpha.beta (where the period indicates a change in hierarchy).
If you must match a period character occurring in a name, use \.
(backslash period) in the filter string. The backslash prevents
interpreting the period as a wildcard.
The filter string is matched at each searched level of the hierarchy
(the Search levels are described above). Use filter strings that are as
specific as possible to limit the number of unwanted matches.
Unnecessarily extensive search can be costly in terms of memory
performance.
-> Moves the selected names from the UnHighlighted area to the
Highlighted area, and highlights their objects in the RTL view.
<- Moves the selected names from the Highlighted area to the
UnHighlighted area, and unhighlights their objects in the RTL view.
All -> Moves all names from the UnHighlighted to the Highlighted area, and
highlights their objects in the RTL view.
<- All Moves all names from the Highlighted to the UnHighlighted area, and
unhighlights their objects in the RTL view.
Highlighted Complementary and analogous to the UnHighlighted area. You select
object names here as candidates for moving to the UnHighlighted list.
(You move names to the UnHighlighted list by clicking the <- button
which unselects and unhighlights the corresponding objects.)
When you select a name in the Highlighted list, the view is changed to
show the (original, unfiltered) schematic sheet containing the object.
Un-Highlight Complementary and analogous to the Highlight Search area: selects
Selection (*?) names in the Highlighted
LO area, based on the filter string you input
here.

90 September 2016
Jump to When enabled, jumps to another sheet if necessary to show target
location objects.
Name Space: Searches for the specified name using the output netlist file.
Netlist
Find 200 Adds up to 200 more objects that match the filter string to the
UnHighlighted list. This button becomes available after you enter a
Highlight Search (*?) filter string. This button does not find objects in
HDL Analyst views. It matches names of design objects against the
Highlight Search (*?) filter and provides the candidates listed in the
UnHighlighted list, from which you select the objects to find.
Using the Enter (Return) key when the cursor is in the Highlight
Search (*?) field is equivalent to clicking the Find 200 button.
Usage note:
Click Find 200 before Find All to prevent unwanted matches in case the
Highlight Search (*?) string is less selective than you expect.
Find All Places all objects that match the Highlight Search (*?) filter string in the
UnHighlighted list. This button does not find objects in HDL Analyst
views. It matches names of design objects against the Highlight
Search (*?) filter and provides the candidates listed in the
UnHighlighted list, from which you select the objects to find. (Enter a
filter string before clicking this button.) See Usage Note for Find 200,
above.
For more information on using the Object Query dialog box, see Using Find for
Hierarchical and Restricted Searches, on page 329 of the User Guide.
Find in Files Command

The Find in Files command searches the defined target for the occurrence of a
specified search string. The list of files containing the string is reported in the
display area at the bottom of the dialog box. For information on using this
feature, see Searching Files, on page 123 of the User Guide.

September 2016 91
Find what: Text string object of search.
Files Contained in Drop-down menu listing the source project of the files to be
Project searched.
Implementation Drop-down menu restricting project search to a specific

Directory implementation or all implementations.
Directory Identifies directory for files to be searched.
Result Window Allows a secondary search string (Find what) to be applied to

the targets reported from the initial search.
Include sub-folders When checked,
LO extends the search to sub-directories of the
for directory searches target directory.
File filter Excludes files from the search by filename extension.

92 September 2016
Search Options Standard string search options; check to enable.
Find Initiates search.
Result Display List of files containing search string. The preceding status
line lists the number of matches in each file and the number
of files searched.
Replace Command
Use Edit->Replace to find and optionally replace text in the Text Editor.
Feature Description
Find what Search string matching the text to find. You can use the
pull-down list to view and reuse search strings from the
current session.
Replace with The text that replaces the found text. You can use the
pull-down list to view and reuse replacement text from the
current session.
Match whole word Finds only occurrences of the exact string (strings longer than
only the Find what string are not recognized).
Match case When enabled, searching is case sensitive.
Regular expression When enabled, wildcard characters (* and ?) can be used in

the search string: ? matches any single character; * matches
any string of characters, including the empty string.
Selection Replace All replaces only the matched occurrence.

September 2016 93
Feature Description
Whole file Replace All replaces all matching occurrences.
Find Next Initiates a search for the search string (see Find What).
Replace Replaces the found text with the replacement text, and locates
the next match.
Replace All Replaces all text that matches the search string.
Goto Command
Use Edit->Goto to go to a specified line number in the Text Editor.
LO

94 September 2016
View Menu Chapter 3: User Interface Commands
View Menu
Use the View menu to set the display and viewing options, choose toolbars,
and display result files. The commands in the View menu vary with the active
view. The following tables describe the View menu commands in various
views.
View Menu Commands: All Views, on page 95
View Menu: Zoom Commands, on page 96
View Menu: RTL View Commands, on page 97
View Menu: FSM Viewer Commands, on page 97
View Menu: Partition View Commands, on page 98
View Menu Commands: All Views

Command Description
Font Size Changes the font size in the Project UI. You can select one of
the following options:
Increase Font Size
Decrease Font Size
Reset Font Size (default size)
Toolbars Displays the Toolbars dialog box, where you specify the
toolbars to display. See Toolbar Command, on page 99.
Status Bar When enabled, displays context-sensitive information in the
lower-left corner of the main window as you move the mouse
pointer over design elements. This information includes
element identification.
Output Windows Displays or removes the Tcl Script and Messages/Job Status
windows simultaneously in the Project view. Refer to the Tcl
Window and Messages options for more information.
Tcl Window When enabled, displays the Tcl window. All commands you
execute in the Project view appear in the Tcl window. You can
enter or paste Tcl commands and scripts in the Tcl window.
Message Window When enabled, displays the Messages/Job Status window.

September 2016 95
Chapter 3: User Interface Commands View Menu
Command Description
View Log File Displays a log file report that includes compiler, mapper, and
timing information on your design. See View Log File
View Result File Displays a detailed netlist report.
View Area Displays the area-estimation file available after running area
Estimation File estimation.
View Partitioning Displays the partitioning script (prt file).

Script
View CPM script Displays the CPM script (cpm file).
View Trace Displays the trace-assignment script (tra file).

Assignment Script
View Menu: Zoom Commands

The following View menu zoom commands are available when the partition,
FSM viewer, or RTL view is active.
Command Description
Zoom->Zoom In Lets you Zoom in or out. When selected, a Z-shaped
mouse pointer ( ) appears. Zoom in or out on the view
by clicking or dragging a box around (lassoing) the
Zoom->Zoom Out region. Clicking zooms in or out on the center of the view;
lassoing zooms in or out on the lassoed region.
Right-click to exit zooming mode.
Zoom->Pan Lets you pan (scroll) a schematic, or partition or FSM
view using the mouse. If your mouse has a wheel feature,
use the wheel to pan up and down. To pan left and right,
use the Shift key.
Zoom->Full View Zooms the active view so that it shows the entire design
or partition.
Zoom->Normal View Zooms the active view to normal size and centers it where
you click. If the view is already normal size, clicking
centers the view.
LO

96 September 2016
View Menu: RTL View Commands

These commands are available when the RTL view is active. These commands
are available in addition to the commands described in View Menu
Commands: All Views, on page 95 and View Menu: Zoom Commands, on
page 96.
Command Description
Push/Pop Traverses design hierarchy using the push/pop mode see
Hierarchy Exploring Design Hierarchy, on page 320 of the User Guide.
Previous Sheet Displays the previous sheet of a multiple-sheet schematic.
Next Sheet Displays the next sheet of a multiple-sheet schematic.
View Sheets... Displays the Goto Sheet dialog box where you can select a
sheet to display from a list of all sheets. See View Sheets
Visual Properties Toggles the display of information for nets, instances, pins,
and ports in the HDL Analyst view. To customize the
information displayed, set the values with Options->HDL Analyst
Options->Visual Properties. See Visual Properties Panel, on
page 212.
Back Goes backward in the history of displayed sheets for the
Forward Goes forward in the history of displayed sheets for the current
HDL Analyst view.
Filter Filters the RTL view to display only the selected objects.
Analyst Connectivity Toggles the connectivity matrix on or off in the RTL view.
View
View Menu: FSM Viewer Commands

The following commands are available when the FSM viewer is active. These
commands are in addition to the common commands described in View
Menu Commands: All Views, on page 95 and View Menu: Zoom Commands,
on page 96

September 2016 97
Command Description
FSM Table Toggles display of the transition table.
FSM Graph Toggles FSM state diagram on or off.
Annotate Transitions Toggles display of state transitions on or off on FSM state

diagram
Filter->Selected Hides all but the selected state(s).
Filter->By output Hides all but the selected states, their output transitions,
transitions and the destination states of those transitions.
Filter->By input Hides all but the selected states, their input transitions, and
transitions the origin states of those transitions.
Filter->By any Hides all but the selected states, their input and output
transition transitions, and their predecessor and successor states.
Unfilter Restores a filtered FSM diagram so that all the states and
transitions are showing.
Select All States Selects all the states.
Unselect All Unselects all states and transitions.
Cross Probing Enables cross probing between FSM nodes and RTL view
schematic.
View Menu: Partition View Commands

These commands are available when the Partition view is active. These
commands are available in addition to the commands described in View Menu
Commands: All Views, on page 95 and View Menu: Zoom Commands, on
page 96.
Command Description
Impact Analysis Toggles the Impact Analysis window.
View
Partition Toggles the Partition Device view connectivity matrix.
Connectivity View LO

98 September 2016
Toolbar Command
Select View->Toolbars to display the Toolbars dialog box, where you can:
choose the toolbars to display
customize their appearance
Feature Description
Toolbars Lists the available toolbars. Select (check) the toolbars that you
want to display.
Show Tooltips When selected, a descriptive tooltip appears whenever you position
the cursor over an icon.
Large Buttons When selected, large icons are used.
View Sheets Command

Select View->View Sheets to display the Goto Sheet dialog box and select a sheet
to display. The Goto Sheet dialog box is only available in an RTL view, and only
when a multiple-sheet design is present.

September 2016 99
To see if your design has multiple sheets, check the sheet count display at
the top of the schematic window.
View Log File Command

Select View->View Log File to display the log file report for your project. The log
file is available in either text (project_name.srr) or HTML (project_name.htm)
format. To enable or disable the HTML file format for the log file, select the
View log file in HTML option in the Options->Project View Options dialog box.
When opening the log file in HTML format, a table of contents appears.
Selecting an item from the table of contents takes you to the corresponding
HTML page. To go back to the table of contents, right-click on the HTML page
and select Back from the menu.
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100 September 2016
Project Menu Chapter 3: User Interface Commands
Project Menu
You use the Project menu in the Project View to set implementation options,
add or remove files from a project, change project filenames, create new
implementations, and archive or copy a project.
The following table describes the Project menu commands.
Command Description
Implementation Options... Displays the Implementation Options dialog box, where you
set options for implementing your design. See
Implementation Options Command, on page 114.
Add Source File... Displays the Select Files to Add to Project dialog box. See
Add Source File Command, on page 102.
Remove File From Project Removes selected files from your project.
Change File... Replaces the selected file in your project with another
that you choose. See Change File Command, on
page 105.
Set VHDL Library... Displays the File Options dialog box, where you choose
the library (Library Name) for synthesizing VHDL files. The
default library is called work. See Set VHDL Library
Import IP Package Imports an IP package into your project. You need to
consolidate the IP core files into a single folder or a
compressed zip file before importing. See Import IP
Package, on page 106.
Add Implementation... Creates a new implementation for a current design.
Each implementation pertains to the same design, but it
can have different options settings and/or constraints
for synthesis runs.
Remove Implementation ... Removes the selected implementation from the project.

September 2016 101
Chapter 3: User Interface Commands Project Menu
Command Description
Archive Project... Archives a design project. Use this command to archive
a full or partial project, or to add files to or remove files
from an archived project. See Archive Project
Command, on page 107 for a description of the utility
wizard options.
Un-Archive Project... Loads an archived project file to the specified directory.
See Un-Archive Project Command, on page 109 for a
description of the utility wizard options.
Copy Project... Creates a copy of a design project. Use this command to
create a copy of a full or partial project. See Copy Project
Command, on page 112 for a description of the utility
wizard options.
Add Source File Command

Select Project->Add Source File to add source files to your project. This selection
displays the Select Files to Add to Project dialog box.
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102 September 2016
Choose
Directory
Select files to add
Specify file type
Add file
buttons
Files to be
Added Remove file
buttons
Feature Description
Look in The directory of the file to add. You can use the pull-down
directory list or the Up One Level button to choose the
directory.
File name The name of a file to add to the project. If you enter a name
using the keyboard, then you must include the file-type
extension.
Files of type The type (extension) of files to be added to the project.
Only files in the active directory that match the file type
selected from the drop-down menu are displayed in the list
of files. Use All Files to list all files in the directory.
Files to add to project The files to add to the project. You add files to this list with
the <- Add and <- Add All buttons. You remove files from this
list with the Remove -> and Remove All -> buttons.
For information about adding files to logical folders, see
Creating Custom Folders, on page 78.

September 2016 103
Feature Description
Use relative paths When you add files to the project, you can specify either to
use the relative path or full path names for the files.
Add files to Folders When you add files to the project, you can specify whether
or not to automatically add the files to folders. See the
Folder Options described below.
Folder Options When you add files to folders, you can specify the folder
name as either the:
Operating System (OS) folder name
Parent path name from a list provided in the display
For details, see Folder Options, on page 104.
Folder Options
When you click on the Folder Options button of the Add Files to Project dialog box,
the Folders Options dialog box is displayed. Select a method for naming folders
here.
Feature Description
Use OS Folder Name The directory of the file to add. Use this option to specify
the folder containing the file as the logical folder name for
the directory.
Use Parent Path The directory of the file to add. Select the folder from the
(select from list below) display LO
window to determine the level of hierarchy
reflected in the logical folder path name.

104 September 2016
Change File Command

Select Project->Change File to replace a file in the project files list with another
of the same type. This command displays the Source File dialog box, where you
specify the replacement file. You must first select the file to replace, in the
Project view, before you can use this command.
First, select a file in the Project view
Then, choose the

replacement file
Set VHDL Library Command

Select Project->Set VHDL Library to display the File Options dialog box, where you
view VHDL file properties and specify the VHDL library name. See File
Options Command, on page 229. This is the same dialog box as that
displayed by right-clicking a VHDL filename in the Project view and choosing
File Options.

September 2016 105
Import IP Package
Use the Import IP Package command to help you import IP core files to your
Project view.
The following table describes the Import IP Package menu options.
Command Description
IP Package Location of the consolidated ZIP file containing the
IP core files. The file format can be zip or sar. Use
the Browse button to help you locate the IP
package.
IP Directory Directory location of the consolidated IP core files.
Use the Browse button to help you locate the IP
directory.
Package Name The name of the top-level module for the IP core.
Add Implementation Command

Select Project->Add Implementation to create a new implementation for the
selected project. This selection displays the Select Flow dialog box where you
define the flow for the project (currently, only the RTL partition flow is
supported).
LO

106 September 2016
Click OK to display the Add Implementation dialog box where you define the
implementation options for the project see Implementation Options
Command, on page 114. This is the same dialog box as that displayed by
Project->Implementation Options, except that there is no list of Implementations to
the right of the tabbed panels.
Remove Implementation Command

Select Project->Remove Implementation to remove the selected implementation
from the project. You are prompted to confirm the removal.
Archive Project Command

Use the Project->Archive Project command to store files for a design project into
a single archive file in Synopsys Proprietary Format (sar). You can archive an
entire project or selected files from the project.
The Archive Project command displays the Certify Archive Utility wizard consisting
of either two (all files archived) or three (custom file selection) tabs.

September 2016 107
Option Description
Project Path and Filename Path and filename of the prj file.
Root Directory Top-level directory that contains the project files.
Destination Directory Path name of the directory to store the archive sar file.
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108 September 2016
Option Description
Archive Style The type of archive:
Create a fully self-contained copy all project files are
archived; includes project input files and result files.
If the project contains more than one implementation:
- All Implementation includes all implementations in the
project.
- Active Implementation includes only the active
implementation.
Customized file list only project files that you select are
included in the archive.
Local copy for internal network only project input files are
archived, no result files will be included.
Create Project using If you select the Customized file list option in the wizard,
you can choose one the following options on the second
tab:
Source Files Includes all design files in the archive.
You cannot enable the SRS option if this option is
enabled.
SRS Includes all srs files (RTL schematics) in the
archive. You cannot enable the Source Files option if
this option is enabled.
Add Extra Files If you select the Customized file list option in the wizard,
you can use this button on the second tab to add
additional files to the archive.
For step-by-step details on how to use the archive utility, see Archive Project
Un-Archive Project Command

Use the Project->Un-Archive Project command to extract the files from an
archived design project.
This command displays the Certify Un-Archive Utility wizard.

September 2016 109
Option Description
Archive Filename Path and filename of the prj file.
Project Name Read-only field that specifies the project name.
Original File Reference/ Displays the files in the archive that will be extracted.
Resolved File Reference You can exclude files from the sar by unchecking the
file in the Original File Reference list. Any unchecked files
are commented out in the prj file.
If there are unresolved reference files in the sar file, you
must fix (Resolve button) or uncheck them. Or, if there
are files that you want the change when project files are
extracted, use the Change button and select files, as
appropriate. See Resolve File Reference, next for more
details.
LO
For step-by-step details on how to use the un-archive utility, see Un-Archive a
Project, on page 130 in the User Guide.

110 September 2016
Resolve File Reference

When you use the Un-Archive Utility wizard to extract a project, if there are
unresolved file references, use the Resolve button next to the file to point to a
new file location. You can also optionally replace project files in the destina-
tion directory by clicking the Change button next to the file you want to
replace. The Change and Resolve buttons bring up the following dialog box:
Option Description
Filename Specifies the path and name of the file you want to
change or resolve.
Original Directory Specifies the location of the project at the time it was
archived.
Replace directory with Specifies the new location of the project files you want to
use to replace files.
Final Filename Specifies the path name of the directory and the file
name of the replace file.
Replace buttons Replace replaces only the file specified in the Filename
field when the project is extracted.
Replace Unresolved replaces any unresolved files in the
project, with files of the same name from the Replace
directory.
Replace All replaces all files in the archived project
with files of the same name from the Replace directory.
To undo any replace-file references, clear the Replace
directory with field, then click Replace. This causes the
utility to point back to the Original Directory and
filenames.

September 2016 111
Copy Project Command

Use the Project->Copy Project command to create a copy of a design project. You
can copy an entire project or selected files from the project.
The Copy Project command displays the Synopsys Copy Utility wizard consisting of
either two (all files copied) or three (custom file selection) tabs.
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112 September 2016
Option Description
Project Path and Filename Path and filename of the prj file.
Root Directory Top-level directory that contains the project files.
Copy Style The type of archive:

Create a fully self-contained copy all project files are
archived; includes project input files and result files.
If the project contains more than one implementation:
- All Implementation includes all implementations in the
project.
- Active Implementation includes only the active
implementation.
Customized file list only project files that you select are
included in the archive.
Local copy for internal network only project input files are
archived, no result files will be included.
Create Project using If you select the Customized file list option in the wizard,
you can choose one the following options on the second
tab:
Source Files Includes all design files in the archive.
You cannot enable the SRS option if this option is
enabled.
SRS Includes all srs files (RTL schematics) in the
archive. You cannot enable the Source Files option if
this option is enabled.
Add Extra Files If you select the Customized file list option in the wizard,
you can use this button on the second tab to add
additional files to the archive.
For step-by-step details on how to use the copy utility, see Copy a Project, on
page 133 in the User Guide.

September 2016 113
Chapter 3: User Interface Commands Implementation Options Command
Implementation Options Command

You use the Implementation Options dialog box to define the implementation
options for the current project. You can access this dialog box from
Project->Implementation Options, by clicking the button in the Project view, or by
clicking the text in the Project view that lists the current technology options.
The dialog box includes the following panels:

Partitioning Panel, on page 115
Implementation Results Panel, on page 117
Verilog Panel, on page 117
VHDL Panel, on page 126
Device Panel, on page 129
LO
Prototyping Tools Panel, on page 130
Options Panel, on page 133

114 September 2016
Implementation Options Command Chapter 3: User Interface Commands
FPGA Synthesis Options Panel, on page 134

Constraints Panel, on page 136
Timing Report Panel, on page 138
Partitioning Panel
You use the Partitioning panel of the Implementation Options dialog box to select
the board file, the SLP generation options, and any existing partition
command files for partitioning, CPM assignment, and trace assignment. For
more information, see Setting Partitioning Options, on page 87 in the User
Guide.

September 2016 115
Board Files
The Board Files section selects the board file for the current implementation.
The Add Board file button opens the Select Board File dialog box to allow
browsing. Click the checkbox to enable selection.
SLP Generation Options

The SLP Generation Options section selects the srp file and the SLP generation
mode. Both Generate SLP Mixed Projects and Generate SLP Database Projects can be
selected concurrently.
Board Options
The Board Options section allows selection of HSTDM (available only with
HAPS-50, HAPS-60, and HAPS-70 series boards) and differential I/O. The
HAPS Functional Groups selection determines when HAPS-specific functional
groups are included for the board:
Default system determines default behavior (-include_haps_fg not speci-
fied with load_board command).
Enable functional groups defined (-include_haps_fg 1 specified with
load_board command).
Disable functional groups not defined (-include_haps_fg 0 specified with
load_board command).
Netlist Preload
The Netlist Preload section is part of the partial netlist load feature and deter-
mines the hierarchy depth to search for modules that can be fully contained
within a single FPGA prior to partitioning.
Partition Management Files

The Partition Management Files section allows existing partitioning, CPM, and
trace assignment files to be specified for a project.
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116 September 2016
Implementation Results Panel

You use the Implementation Results panel to specify the implementation name
(default: proto), the results directory, and the name of the top-level output
netlist file (Result Base Name). You can also specify output constraint and
netlist files. See Specifying Result Options, on page 99 of the User Guide for
details.
The results directory is a subdirectory of the project file directory. Clicking

the Browse button brings up the Select Implementation Directory dialog box to
allow you to browse for the results directory. You can change the location of
the results directory, but its name must be identical to the implementation
name.
Enable optional output file check boxes to generate the corresponding Verilog
netlist, VHDL netlist, or vendor constraint files.
Option Description
Implementation Displays implementation name, directory path for results,
Name and the base name for the result files.
Results Directory
Result Base Name
Verilog Panel
You use the Verilog panel in the Implementation Options dialog box to specify
various language-related options. With mixed HDL designs, the VHDL and
Verilog panels are both available. See Setting Verilog and VHDL Options, on
page 100 of the User Guide for details.

September 2016 117
Feature Description
Top Level Module The name of the top-level module of your design.
Tcl equivalent: set_option -top_module moduleName
Compiler Directives and Shows design parameters extracted with Extract
Parameters Parameters. You can override the default and set a new
LO
value for the parameter. The value is valid for the
current implementation.

118 September 2016
Feature Description
Extract Parameters Extracts design parameters from the top-level module
and displays them in the table. See Compiler Directives
and Design Parameters, on page 122.
Compiler Directives Provides an interface where you can enter compiler
directives that you would normally enter in the code with
ifdef and define statements. See Compiler Directives and
Design Parameters, on page 122.
Verilog Language When enabled, the default Verilog standard for the
Verilog 2001 project is Verilog 2001. When both Verilog 2001 and
SysyemVerilog are disabled, the default standard is
Verilog 95. For information about Verilog 2001, see
Verilog 2001 Support, on page 34. You can override the
default project standard on a per file basis, by selecting
the file, right-clicking, and selecting the File Options
command (see File Options Command, on page 229).
Tcl equivalent: set_option -vlog_std v2001
Verilog Language When enabled, the default Verilog standard for the
System Verilog project is SystemVerilog (SystemVerilog is the default
standard for all new projects). Selecting this option
automatically selects Verilog 2001. For information about
SystemVerilog, see SystemVerilog Feature Summary,
on page 112.
Tcl equivalent: set_option -vlog_std sysv
Incremental Compile When enabled, lets you run the incremental compiler to
reduce compiler runtime for large designs. The software
recompiles only relevant srs files when a design change
is made and reuses the compiler database. For details,
see Using the Incremental Compiler, on page 55 in the
User Guide.
Tcl equivalent: set_option -incremental 0|1
Push Tristates When enabled (default), tristates are pushed across
process/block boundaries. For details, see Push
Tristates Option, on page 124.
Tcl equivalent: set_option -compiler_compatible 0|1

September 2016 119
Feature Description
Allow Duplicate Modules Allows the use of duplicate modules in your design.
When enabled, the last definition of the module is used
by the software and any previous definitions are ignored.
You should not use duplicate module names in your
Verilog design, therefore, this option is disabled by
default. However, if you need to, you can allow for
duplicate modules by enabling this option.
Tcl equivalent: set_option -dup 0|1
Multiple File Compilation When enabled, the Verilog compiler uses the compilation
Unit unit for modules defined in multiple files.
See SystemVerilog Compilation Units, on page 165 for
additional information.
Tcl equivalent: set_option -multi_file_compilation_unit 0|1
Support Bind & Force When enabled, the bind construct can be used to insert a
verification object into a design hierarchy without having
to modify the RTL code itself. The force function allows
you to override existing drivers of internal signals in the
design hierarchy with new drivers. (See Bind Function,
on page 28 and Force Function, on page 31.)
Tcl equivalent: set_option -bindandforce 0|1
Beta Features for Verilog Enables use of any Verilog beta features included in the
release. Enabling this checkbox is equivalent to
including a set_option -hdl_define -set
_BETA_FEATURES_ON_ directive in the project file.
Tcl equivalent: set_option -beta_vfeatures 0|1
Loop Limit Overrides the default compiler loop limit value of 2000.
Loop limits are applied using the Verilog loop_limit
directive or the VHDL syn_looplimit directive.
Tcl equivalent: set_option -looplimit loopLimitValue
Auto Infer Blackbox Selects how undefined modules are treated. Selecting
With BIDIR ports (the default) creates a black box for the
undefined module and generates a warning message,
but allows the operation to continue; selecting None
causes the compiler to error out when an undefined
module is encountered.
Tcl equivalent: set_option -auto_infer_blackbox 0|1
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120 September 2016
Feature Description
Include Path Order Specifies the search paths for the include commands in
the Verilog design files of your project. Use the buttons
in the upper right corner of the box to add, delete, or
reorder the paths. The include paths are relative.
Library Directories Specifies all the paths to the directories which contain
the Verilog library files to be included in your design for
the project.
Library Extensions (space Adds library extensions to Verilog library files included
separated) in your design for the project and searches the directory
paths you specified that contain these Verilog library
files. To use library extensions, see Using Library
Extensions for Verilog Library Files, on page 42 in the
User Guide.
Tcl equivalent: set_option -libext .libextName1
.libextName1...
Design Compiler Specifies the path to the Synopsys DesignWare
Installation Location foundation library building blocks. Do not use this field
[$SYNOPSYS=:] if the $SYNOPSYS environment variable is defined.
Tcl equivalent: set_option -dc_root pathToDesignWare
Use DesignWare Indicates that Synopsys DesignWare foundation library
Foundation Library building blocks are to be used as the source for any
DesignWare models in the design.
Tcl equivalent: set_option -dw_foundation 0|1
Use DesignWare Indicates that a corresponding building block from the
MinPower Library Synopsys minPower library is to be used in place of its
equivalent standard DesignWare foundation library
building block. Selecting this option automatically
selects the Use DesignWare Foundation Library checkbox.
Tcl equivalent: set_option -dw_minpower 0|1
Stop synthesis if no Used with the Synopsys DesignWare foundation library
DesignWare license is to specify how to treat a DesignWare building block
found encountered in a design when no DesignWare license is
available (DesignWare support is licensed separately). If
checked, synthesis is stopped with an error; if
unchecked (the default), the DesignWare building block
is treated as a black box and synthesis is allowed to
continue.
Tcl equivalent: set_option -dw_stop_on_nolic 0|1

September 2016 121
Compiler Directives and Design Parameters

When you click the Extract Parameters button in the Verilog panel, parameter
values are extracted from the top-level module and displayed in the table.
You can override the default and set a new value for the parameter. The value
is valid for the current implementation only.
The Compiler Directives field provides an interface where you can enter compiler
directives that you would normally enter in the code using ifdef and define
statements. Use spaces to separate the statements. The directives you enter
are stored in the project file. For example, if you enter
size=32 test_impl
the software writes the following statement to the project file:
set_option -hdl_define -set "size=32"
To define multiple variables in the GUI, enclose each directive in quotes and
use a space delimiter. For example:
hdl_define -set "SIZE=32" "WIDTH=8"
The software writes the following statement to the prj file:
set_option -hdl_define -set {"size=32" "width=8"}
IGNORE_VERILOG_BLACKBOX_GUTS Directive
When you use the syn_black_box directive, the compiler parses the contents of
the black box to determine if illegal syntax or incorrect code is defined within
the black box and, if either is present, generates an error message.
However, if you do not want the tool to check for illegal syntax in your black
box, set the:
Built-in compiler directive IGNORE_VERILOG_BLACKBOX_GUTS in the
Compiler Directives field of the Verilog panel.
The software writes the following statements to the project file:
set_option -hdl_define -set "IGNORE_VERILOG_BLACKBOX_GUTS"

`define IGNORE_VERILOG_BLACKBOX_GUTS
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directive in the Verilog file.
This option is implemented globally for the project file.

122 September 2016
Example of the IGNORE_VERILOG_BLACKBOX_GUTS Directive

Note that the IGNORE_VERILOG_BLACKBOX_GUTS directive ignores the
contents of the black box. However, whenever you use this directive you must
first define the ports for the black box correctly. Otherwise, the IGNORE_VER-
ILOG_BLACKBOX_GUTS directive will generate an error. See the following valid
Verilog example:
`define IGNORE_VERILOG_BLACKBOX_GUTS
module b1_fpga1 (A,B,C,D) /* synthesis syn_black_box */;
input B;
output A;
input [2:0] D;
output [2:0] C;
temp;
assign A = B;
assign C = D;
endmodule
module b1_fpga1_top (inout A, B, inout [2:0] C, D);

b1_fpga1 b1_fpga1_inst(A,B,C,D);
endmodule
_BETA_FEATURES_ON_ Directive
Beta features for the Verilog, SystemVerilog, or VHDL language must be
explicitly enabled. In the UI, a Beta Features checkbox is included on the VHDL
or Verilog tab of the Implementations Options dialog box. A _BETA_FEATURES_ON_
compiler directive is also available. This directive is specified with a set_option
-hdl_define command added to the project file as shown below:
set_option -hdl_define -set _BETA_FEATURES_ON_
_SEARCHFILENAMEONLY_ Directive
This directive provides a workaround for some known limitations of the
archive utility.
If Verilog 'include files belong in any of the following categories, you may
encounter problems when compiling a design after un-archiving:
1. The include paths have relative paths to the project file.
ìnclude "../../../defines.h"

September 2016 123
2. The include paths have absolute paths to the project file.
ìnclude "c:/temp/params.h"
ìnclude "/remote/sbg_home/user/params.h"
3. The include paths have the same file names, but are located in different
directories relative to the project file.
ìnclude "../myflop.v"

ìnclude "../../myflop.v"
Use the _SEARCHFILENAMEONLY_ directive to resolve categories 1 and 2

above. Category 3 is a known limitation; in this case it is recommended that
you adopt standard coding practices to avoid files with the same name and
different content.
When you un-archive a sar file that contains relative or absolute include
paths for the files in the project, you can add the _SEARCHFILENAMEONLY_
compiler directive to the unarchived project; this has the compiler remove the
relative/absolute paths from the 'include and search only for the file names.
This directive is specified with a set_option -hdl_define command added to an

implementation within the project file as shown below:
set_option -hdl_define -set "_SEARCHFILENAMEONLY_"
The directive can also be added to the Compiler Directives field of the Verilog
panel as shown below.
The compiler generates the following warning message whenever it extracts

include files using this directive:
@W: | Macro _SEARCHFILENAMEONLY_ is set: fileName not found

attempting to search for base file name fileName
Push Tristates Option

Pushing tristates is a synthesis optimization option you set with Project->Imple-
mentation Options->Verilog or VHDL.
When the Push Tristates option is enabled, the Certify compiler pushes tristates
LO
through objects such as muxes, registers, latches, buffers, nets, and tristate
buffers, and propagates the high-impedance state. The high-impedance
states are not pushed through combinational gates such as ANDs or ORs.

124 September 2016
Push Tristates off:

tristate is not pushed
through the flip-flop
Push Tristates on:

tristate is pushed
through the flip-flop
so that the result
matches RTL
simulation
If there are multiple tristates, the software muxes them into a single tristate
and pushes it through. The software pushes tristates through loops and
stores the high impedance across multiple cycles in the register.
Advantages and Disadvantages

The advantage to pushing tristates to the periphery of the design is that you
get better timing results because the software uses tristate output buffers.
The Certify software approach to tristate inference matches the simulation

approach. Simulation languages are defined to store and propagate 0, 1, and
Z (high impedance) states. Like the simulation tools, the Certify tool propa-
gates the high-impedance states instead of producing tristate drivers at the
outputs of process (VHDL) or always (Verilog) blocks.
The disadvantage to pushing tristates is that you might use more design
resources.

September 2016 125
Effect on Other Synthesis Options

Tristate pushing has no effect on the syn_tristatetomux attribute. This is
because tristate pushing is a compiler directive, while the syn_tristatetomux
attribute is used during mapping.
VHDL Panel
You use the VHDL panel in the Implementation Options dialog box to specify
various language-related options. With mixed HDL designs, the VHDL and
Verilog panels are both available. See Setting Verilog and VHDL Options, on
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126 September 2016
The following table describes the options available:
Feature Description
Top Level Entity The name of the top-level entity of your design.
If the top-level entity does not use the default work
library to compile the VHDL files, you must specify the
library file where the top-level entity can be found. To
do this, the top-level entity name must be preceded by
the VHDL library followed by a period (.). To specify
VHDL library files, see Project Menu, on page 101 for
the Set VHDL Library command, or the File Options
Tcl equivalent: set_option -top_module topLevelName
Default Enum Encoding The default enumeration encoding to use. This is only
for enumerated types; the FSM compiler automatically
determines the state-machine encoding, or you can
specify the encoding using the syn_encoding attribute.
Tcl equivalent: set_option -default_enum_encoding
encodingType
Incremental Compile When enabled, lets you run the incremental compiler to
reduce compiler runtime for large designs. The software
recompiles only relevant SRS files when a design
change is made and reuses the compiler database. For
details, see Using the Incremental Compiler, on
Tcl equivalent: set_option -incremental 0|1
Push Tristates When enabled (default), tristates are pushed across
process/block boundaries. For more information, see
Push Tristates Option, on page 124.
Tcl equivalent: set_option -compiler_compatible 0|1
Synthesis On/Off When enabled, the software ignores any VHDL code
Implemented as Translate between synthesis_on and synthesis_off directives. It
On/Off treats these third-party directives like
translate_on/translate_off directives (see
translate_off/translate_on, on page 278 for details).
Tcl equivalent: set_option -synthesis_onoff_pragma 0|1
VHDL 2008 When enabled, the VHDL 2008 extensions are
recognized by the VHDL compiler. For information
about VHDL 2008, see VHDL 2008 Language Support,
on page 315.
Tcl equivalent: set_option -vhdl2008 0|1

September 2016 127
Feature Description
Implicit Initial Value Support When enabled, the compiler passes init values through
a syn_init property to the mapper. For more information,
see VHDL Implicit Data-type Defaults, on page 241.
Tcl equivalent: set_option -supporttypedflt 0|1
Beta Features for VHDL Enables use of any VHDL beta features included in the
release. Enabling this checkbox is equivalent to
including a set_option -hdl_define -set
_BETA_FEATURES_ON_ directive in the project file.
Tcl equivalent: set_option -beta_vhfeatures 0|1
Loop Limit Overrides the default compiler loop limit value of 2000.
Loop limits are applied using the Verilog loop_limit
directive or the VHDL syn_looplimit directive.
Tcl equivalent: set_option -looplimit loopLimitValue
Generics Shows generics extracted with Extract Generic Constants.
You can override the default and set a new value for the
generic constant. The value is valid for the current
implementation.
Extract Generic Constants Extracts generics from the top-level entity and displays
them in the table.
Design Compiler Installation Specifies the path to the Synopsys DesignWare
Location [$SYNOPSYS=:] foundation library building blocks. Do not use this field
if the $SYNOPSYS environment variable is defined.
Tcl equivalent: set_option -dc_root pathToDesignWare
Use DesignWare Indicates that Synopsys DesignWare foundation library
Foundation Library building blocks are to be used as the source for any
DesignWare models in the design.
Tcl equivalent: set_option -dw_foundation 0|1
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128 September 2016
Feature Description
Use DesignWare MinPower Indicates that a corresponding building block from the
Library Synopsys minPower library is to be used in place of its
equivalent standard DesignWare foundation library
building block. Selecting this option automatically
selects the Use DesignWare Foundation Library checkbox.
Tcl equivalent: set_option -dw_minpower 0|1
Stop synthesis if no Used with the Synopsys DesignWare foundation library
DesignWare license is found to specify how to treat a DesignWare building block
encountered in a design when no DesignWare license is
available (DesignWare support is licensed separately). If
checked, synthesis is stopped with an error; if
unchecked (the default), the DesignWare building block
is treated as a black box and synthesis is allowed to
continue.
Tcl equivalent: set_option -dw_stop_on_nolic 0|1
Device Panel
You use the Device panel to set device mapping options for the selected
technology. The Technology, Part, Package, and Speed options are defined by the
board file and appear as read-only fields on the Device panel. The available
options and the implementation of these options can vary from technology to
technology.
Option Description
Force Generated Clock Enables the conversion of generated clock-driven datapath
Conversion latches to a flip-flop and multiplexer when the
generated-clock logic/datapath latch is set or reset by
asynchronous signals (by default, generated-clock-driven
datapath latches with asynchronous control signals are
not converted).
Disable Sequential Enables or disables the sequential optimizations for the
Optimizations design.
Verification Mode Ensures that your synthesis output files are compatible
with the verification tools. See Verification Mode in Xilinx
Designs for details.

September 2016 129
Option Description
Time Budget Effort Sets the effort level for estimating timing constraints for
Level the individual FPGAs. This step automatically budgets the
top-level timing constraints for each FPGA and annotates
this information into the individual synthesis constraint
(*_timing.sdc) files.
Estimate Area Effort Sets the effort level for area estimation. The low and
medium values use fast estimation; the default is high
(normal estimation).
Resolve Mixed Drivers When a net is driven by a VCC or GND and active drivers,
enable this option to connect the net to the VCC or GND
driver.
Automatic Read/Write Enabling this option automatically inserts bypass logic
Check Insertion for when required to prevent simulation mismatch in
RAM read-during-write scenarios. For asynchronous clock
groups going to the RAM, the tool will not generate bypass
logic which can cause unintended CDC paths between the
clocks. For example, the following will not generate bypass
logic:
create_clock {p:clkr} -period {10}
create_clock {p:clkw} -period {20}
set_clock_groups -derive -asynchronous -name
{async_clkgroup} -group { {c:clkw} }
See syn_ramstyle, on page 199 in the Reference Manual
for detailed information.
Prototyping Tools Panel

The Prototyping Tools panel of the Implementation Options dialog box specifies if
gated and generated clocks are to be converted, netlist prototyping options
(Enable prototyping tools check box must be checked), and any prototyping tool
files or Tcl files to compile with the design. A Certify-specific section contains
clock synchronizer IP options and distributed instrumentation selection. Use
the Add Prototype file button to add prototyping tool files and Tcl files to the
project. See Setting Prototyping Tools Options, on page 106 of the User Guide
for details.
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130 September 2016

September 2016 131
Feature Description
Clock Conversion Performs gated and generated clock optimization when
enabled. See Working with Gated Clocks and Optimizing
Generated Clocks for details.
Force Generated Clock When enabled, gated-clock conversion occurs regardless
Conversion with of the presence of asynchronous set/reset signals in
Asynchronous Signals generated-clock logic or datapath latches. When disabled
(the default), conversion is inhibited when asynchronous
set/reset signals on generated-clock logic have signals
different from the asynchronous signals on the driven
datapath latches.
Convert MUX/XOR Gates Performs gated-clock conversion on muxes or OR gates
Clock Tree for HAPS in the clock tree when enabled. This option can only be
Technology (Beta) selected when a Synopsys HAPS technology is used.
Error if unassigned pins Used during auto-HSTDM assignment to set message

are found in HSTDM mode severity. Enabling the option (the default) causes the
assignment to error out when there is an insufficient
number of traces remaining for other (non-CPM) and
top-level ports. Disabling the option allows the
assignment to continue with a warning.
Do error checking on Performs error checking on HAPS Clock Synchronizer IP.
HAPS Clock Synchronizer
IP.
Halt when error detected Halts when errors are detected in the HAPS Clock
in HAPS Clock Synchronizer IP.
Synchronizer IP.
If HAPS Clock Inserts logic to synchronize the release of reset when
Synchronizer IP is present, HAPS Clock Synchronizer IP is present.
insert logic to synchronize
the release of reset.
Feedthrough optimization Eliminates I/O pins associated with signals that pass
through a design block without driving any logic or that
are unnecessarily routed through a block.
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132 September 2016
Feature Description
Create always/process Creates an additional level of hierarchy based on the
level hierarchy always (Verilog) or process (VHDL) blocks in the source
RTL design file. Allows large modules or entities that
cannot be partitioned into a single FPGA to be broken up
into a set of logical submodules that can be more easily
partitioned among the available FPGAs.
Remove Duplicate Drivers Removes duplicate drivers (i.e., two instantiated buffers
driving the same net).
Add Prototype file Adds prototyping tool files (bit-slice definition) and Tcl
files to the project.
Options Panel
You use the Options panel of the Implementation Options dialog box to define
general options for synthesis optimization. See Setting Optimization Options,
on page 91 of the User Guide for details.
The following table shows you where to find more information for each option:
Option See...
Fast Synthesis Determines if the tool speeds up runtime in logic synthesis
mode. Enabling the option reduces the number of mapper
optimizations, and could result in reduced QoR.
Available only when Physical Synthesis is disabled. See Fast
Synthesis, on page 137 of the User Guide for information
about using it.
Continue On Error Allows the compilation process to continue for certain,
non-syntax-related compiler errors. See Continue on Error,
on page 93 of the User Guide.
Auto Compile Point Improves timing estimation execution times for compile
Timing Estimation points in specific designs.
FSM Compiler See FSM Compiler, on page 51 and Optimizing State

Machines, on page 598 of the User Guide.
Resource Sharing See Sharing Resources, on page 593 of the User Guide.

September 2016 133
Option See...
Pipelining Refer to the Synplify Premier documentation.
Retiming Refer to the Synplify Premier documentation.
Reserve I/O Pads Reserves pins on predefined boards. See Reserving Pins
with the Reserve I/O Pads Option, on page 204 of the User
Guide.
FPGA Synthesis Options Panel

The FPGA Synthesis Options panel sets a variety of synthesis options that are
targeted to Synplify Premier.
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134 September 2016
Option Description
Enhanced Compile When enabled, allows enhanced gated-clock conversion with
Point Support the compile-point flow.
Fanout Guide Sets a global fanout limit for the entire design.
Disable I/O Insertion When enabled, it prevents automatic I/O insertion during
synthesis. By default, it is disabled. See Xilinx I/O Insertion
for details.
Use Xilinx Partition Determines whether to use compile points with the Xilinx
Flow Partition flow, which compares partitions or modules in the
previous and current implementations. Partitions that have
not changed are preserved from the previous
implementation. This feature saves a significant amount of
time in that place and route for the entire design does not
need to be rerun. For details, see Xilinx Partition Flow.
Enable Advanced Prepares the netlist for advanced LUT combining in Virtex-5
LUT Combining and Spartan-6 or newer designs, so that Xilinx ISE
place-and-route tool can pack into the LUT6_2 depending
on available resources. The default is on. See Advanced LUT
Combining for additional details.
Write Mapped Verilog Generates mapped Verilog netlist files.
Netlist
Write Mapped VHDL Generates mapped VHDL netlist files.
Netlist
Enable Place and Enables place-and-route for SLP projects.
Route
Enable Back Enables backannotation following place-and-route.
Annotation after P&R
Default P&R Options Specifies the default editable text file containing
File place-and-route option information to use when running
Xilinx place-and-route with Xflow. For the newer xtclsh flow,
a Tcl file is used instead.

September 2016 135
Constraints Panel
You use the Constraints panel of the Implementation Options dialog box to specify
target frequency and timing constraint files for design synthesis. See Speci-
fying Global Frequency and Constraint Files, on page 98 of the User Guide for
details.
Option Description
Frequency Sets the default global frequency. You can either set the
global frequency here or in the Project view. To override the
default you set here, set individual clock constraints from the
SCOPE interface.
Auto Constrain When enabled and no clocks are defined, the software
automatically constrains the design to achieve the best
possible timing (not available when a prt file is present). It
does this by reducing periods of each individual clock and the
timing of any timed I/O paths in successive steps.
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136 September 2016
Option Description
Use clock period for Determines when default constraints are used for I/O ports
unconstrained IO that do not have user-defined constraints.
When disabled, only define_input_delay or define_output_delay
constraints are considered during synthesis or
forward-annotated after synthesis.
When enabled, the software considers any explicit
define_input_delay or define_output_delay constraints, as before.
In addition, for all ports without explicit constraints, it uses
constraints based on the clock period of the attached
registers. Both the explicit and implicit constraints are used
for synthesis and forward-annotation.
The default is off (disabled) for new designs. For designs
created with older versions of the software the default is on,
to maintain backwards compatibility.
Use clock period for Determines when default constraints are used for I/O ports
unconstrained IO for that do not have user-defined constraints during time
Time-budgeting budgeting.
Generate IO & Clock

Generating
Component
Placement for
Physcial Plus
Constraint Files Specifies which constraints files to use for an
implementation. Enable the checkbox to select a file. The
constraint file types are on separate tabs.
FPGA Constraints Specifies which Synopsys standard timing constraints (FDC)
(FDC) files to use for the implementation. Enable a checkbox to
select the corresponding file.
SDC Specifies which legacy timing constraints (SDC) files to use
for the implementation. Enable a checkbox to select the
corresponding file.
Constraints (UCF) Specifies which Xilinx user constraints (UCF) files to use for
the implementation. Select a check box to select the
corresponding file.
Power Specifies which Activity Analysis for Power Optimization
report (SAIF) files to use for the implementation. Enable the
checkbox to select a file

September 2016 137
Option Description
Compiler (CDC) Specifies which compiler directives (CDC) files to use for the
implementation. Enable a checkbox to select the
corresponding file.
Timing Report Panel

You use the Timing Report panel (Implementation Options dialog box) to set criteria
for the (default) output timing report. You specify the number of critical paths
and the number of start and end points to appear in the timing report. See
Specifying Timing Report Output, on page 100 of the User Guide for details.
For a description of the report, see Timing Reports, on page 254.
Option Description
Number of Critical Set the number of critical paths you want the software to
Paths report.
Number of Start/End Specify the number of start and end points you want to see
Points reported in the critical path sections.
See also:
Timing Reports, on pageLO254, for more information on the default timing
report, which is affected by the Timing Report panel settings.

138 September 2016
Analysis Menu, on page 176, information on creating additional custom

timing reports for certain device technologies.

September 2016 139
Chapter 3: User Interface Commands Run Menu
Run Menu
You use the Run menu to perform tasks such as the following:
Compile the board and design files in preparation for partitioning
Estimate the area of modules and primitives
Estimate the time budgets between FPGAs
Check design syntax and synthesis code, and check source code errors
Check constraint syntax and how/if constraints are applied to the
design
Launch the Synplify Premier synthesis tool
Run Tcl scripts
Run SLP projects
Check the status of the current job
The following table describes the Run menu commands.
Command Description
Run Preparation Compiles the board and design files for the project if
necessary.
Run Preparation (Rebuild Compiles the board and design files for the project.
All)
Estimate Area Estimates the area requirements for modules and
primitives.
Estimate Time-Budgets Estimates time budgets between FPGAs following
synthesis by Synplify Premier.
FSM Explorer Analyzes finite state machines contained in a design, and
selects the optimum encoding style. This menu command
is not available in some views.
Synthesize SLP Project Invokes the Synplify Premier tool to synthesize the
selected SLP project following SLP generation.
Synthesize SLP Project LO the Synplify Premier tool to synthesize the
Invokes
(Parallel) selected SLP project using a separate license (if available).

140 September 2016
Run Menu Chapter 3: User Interface Commands
Command Description
Synthesize All SLP Invokes the Synplify Premier tool to synthesize all SLP
Projects projects in the active implementation following SLP
generation.
Synthesize All SLP Invokes the Synplify Premier tool to synthesize all SLP
Projects (Parallel) projects in the active implementation using a separate
license (if available) for each synthesis task.
Syntax Check Runs a syntax check on design code. The status bar at
the bottom of the window displays any error messages. If
the active window shows an HDL file, then the command
checks only that file; otherwise, it checks all project
source code files.
Synthesis Check Runs a synthesis check on your design code. This
includes a syntax check and a check to see if the
synthesis tool could map the design to the hardware. No
optimizations are carried out. The status bar at the
bottom of the window displays any error messages. If the
active window shows an HDL file, then the command
checks only that file; otherwise, it checks all project
source code files.
Constraint Check Checks the syntax and applicability of the timing
constraints in the sdc file in your project and generates a
report (projectName_cck.rpt). The report contains
information on the constraints that can be applied,
cannot be applied because objects do not exist, and
wildcard expansion on the constraints.
See Constraint Checking Report, on page 260.
Generate Clock Report Reports the clocks in the design database.
Arrange VHDL files Reorders the VHDL source files for synthesis.
Translate Constraints Displays a dialog box where you an Altera PIN or Xilinx
PAD file to translate to a Synopsys constraint file (sdc).
See Translate Constraints Command, on page 143.
Run Tcl Script... Displays the Open dialog box, where you choose a Tcl
script to run. See Run Tcl Script Command, on
page 142.

September 2016 141
Command Description
Job Status During compilation, tells you the name of the current job,
and gives you the runtime and directory location of your
design. This option is enabled during synthesis. See Job
Status Command, on page 143. Clicking in the status
area of the Project view is a shortcut for this command.
Next Error/Warning Shows the next error or warning in your source code file.
Previous Error/Warning Shows the previous error or warning in your source code
file.
Log File Message Filter Brings up the Log File Filter dialog box to allow the
severity of a message to be elevated/lowered or to
suppress the message from the log file.
Run Tcl Script Command

Select Run->Run Tcl Script to display the Open dialog box, where you specify the
Tcl script file to execute. The File name area is filled automatically with the
wildcard string *.tcl, corresponding to Tcl files.
This dialog box is the same as that displayed with File->Open, except that no
Open as read-only check box is present. See Open Project Command, on
page 83, for an explanation of the features in the Open dialog box.
Choose the directory
*.tcl matches Tcl files
Specify Tcl file type
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142 September 2016
Translate Constraints Command

Select Run->Translate Constraints to translate a Xilinx PAD or Altera PIN file into
a Synopsys FPGA SCOPE spreadsheet-compatible constraint file. Selecting
this command displays the corresponding translation dialog box (Translate
Xilinx PAD File to Synplicity Scope (SDC) File or Translate Altera PIN File to Synplicity
Scope (SDC) File the two boxes are essentially the same), where you specify
the input and output files for the translation. Enable Add to project to add the
constraint file to your project. Refer to the User Guide for further details.
Job Status Command

Select Run->Job Status to monitor the jobs that are running, their run times,
and their associated commands. This information appears in the Job Status
dialog box. This information is also displayed in the combined Messages-Job
Status window.
To cancel a job, select it,

then click the Cancel button
You can cancel a displayed job by selecting the entry in the dialog box and
clicking Cancel Job.

September 2016 143
Log File Message Filter Command

The Log File Message Filter command brings up the Log File Filter dialog box to
allows messages in the current session to be promoted or demoted in severity
or suppressed from the log files for subsequent sessions. For additional infor-
mation on using this dialog box, see Log File Message Controls, on page 845
of the User Guide.
The following table describes the dialog box functions.
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144 September 2016
Function Description
Log File Displays the message ID and text and the default message type
Messages of messages generated during the current session.
window
Suppress Suppresses the selected note, warning, or advisory message. The
Message button selected message is removed from the upper Log File Messages
window and displayed in the lower window with the Override
column indicating suppress status. Note that error messages
cannot be suppressed.
Make Error button Promotes the status of the selected warning (or note) to an error.
The selected message is removed from the upper Log File
Messages window and displayed in the lower window with the
Override column indicating error status.
Make Warning Promotes the status of the selected note to a warning. The
button selected message is removed from the upper Log File Messages
column indicating warning status.
Make Note button Demotes the status of the selected warning to a note. The
selected message is removed from the upper Log File Messages
column indicating note status.
Remove Override Removes the override status on the selected message in the lower
button window and returns the message to the upper Log File Messages
window.
lower window Lists the status of all messages that have been promoted,
demoted, or suppressed.
OK button Updates the status of any changed messages in the pfl file. Note
that you must recompile/resynthesize the design before any
message status changes become effective.

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Chapter 3: User Interface Commands Tools Menu
Tools Menu
Within the Partition view, the Tools menu provides interfaces for CPM assign-
ment.
The table below describes the Tools menu commands, available in the Parti-
tion view.
Command Description
Trace Usage Report Generates the Signal-to-Trace assignment
report. See Trace Usage Reporting, on page 206
of the User Guide.
Show Replicated Brings up the Assignments dialog box showing
Assignments replicated assignments. See Listing Replicated
Assignments, on page 161 of the User Guide.
Automatic CPM Performs automatic CPM on the partitioned
design.
CPM Fast Clock Estimator Runs the CPM fast clock estimator to estimate
the CPM clock frequency after CPM insertion.
See Partition Flow with Legacy CPM, on
Launch SYNCore Opens the Synopsys IP Core Wizard. This tool
helps you build IP blocks such as memory or
FIFO models for your design.
See the Launch SYNCore, on page 146 for
details.
Launch SYNCore
The SYNCore wizard helps you build IP cores. Currently, the wizard can
compile RAM and ROM memories, a FIFO, an adder/subtractor, and a
counter. The resulting Verilog models can be synthesized and simulated. For
details about using the wizard to build these models, see the following
sections in the user guide:
Specifying FIFOs with SYNCore, on page 484
LO
Specifying RAMs with SYNCore, on page 507
Specifying Byte-Enable RAMs with SYNCore, on page 523

146 September 2016
Tools Menu Chapter 3: User Interface Commands
Specifying ROMs with SYNCore, on page 534

Specifying Adder/Subtractors with SYNCore, on page 545
Specifying Counters with SYNCore, on page 563
To start the SYNCore wizard, select Run->Launch SYNCore and:
Select sfifo_model and click Ok to start the FIFO wizard described in
SYNCore FIFO Wizard, on page 148.
Select ram_model and click Ok to start the RAM wizard described in
SYNCore RAM Wizard, on page 158.
Select byte_en_ram and click Ok to start the byte-enable RAM wizard
described in SYNCore Byte-Enable RAM Wizard, on page 161.
Select rom_model and click Ok to start the ROM wizard described in
SYNCore ROM Wizard, on page 165.
Select addnsub_model and click Ok to start the adder/subtractor wizard,
described in SYNCore Adder/Subtractor Wizard, on page 169.
Select counter_model and click Ok to start the counter wizard described in
SYNCore Counter Wizard, on page 173.

September 2016 147
Each SYNCore wizard has two tabs at the top, and some buttons below,
which are described here:
model Parameters Consists of a multiple-screen wizard that lets you set

parameters for that model. See SYNCore FIFO Wizard, on
page 148, SYNCore RAM Wizard, on page 158, SYNCore
Byte-Enable RAM Wizard, on page 161, SYNCore ROM
Wizard, on page 165, SYNCore Adder/Subtractor Wizard, on
page 169, or SYNCore Counter Wizard, on page 173 for details
about the options you can set.
Core Overview Contains basic information about the kind of model you are
creating.
Generate Generates the model with the parameters you specify in the
wizard.
Sync FIFO Info, Opens a window with technical information about the
RAM Info, ROM corresponding model.
Info, ADDnSUB
Info, COUNTER
Info
SYNCore FIFO Wizard

The following describe the parameters you can set in the FIFO wizard, which
opens when you select sfifo_model:
SYNCore FIFO Parameters Page 1, on page 148
SYNCore FIFO Parameters Page 1

The page 1 parameters define the FIFO. Data is written/read on the rising
edge of the clock.
LO

148 September 2016
Parameter Function
Component Name Specifies a name for the FIFO. This is the name that you
instantiate in your design file to create an instance of the
SYNCore FIFO in your design. Do not use spaces.
Directory Indicates the directory where the generated files will be
stored. Do not use spaces.
Filename Specifies the name of the generated file containing the HDL
description of the generated FIFO. Do not use spaces.
Width Specifies the width of the FIFO data input and output. It
must be within the valid range.
Depth Specifies the depth of the FIFO. It must be within the valid
range.

September 2016 149
LO

150 September 2016
The page 2 parameters let you specify optional handshaking flags for FIFO
write operations. When you specify a flag, the symbol on the left reflects your
choice. Data is written/read on the rising edge of the clock.
Parameter Function
Full Flag Specifies a Full signal, which is asserted when the FIFO
memory queue is full and no more writes can be performed
until data is read.
Enabling this option makes the Active High and Active Low
options (FULL_FLAG_SENSE parameter) available for the
signal. See Full/Almost Full Flags, on page 497 and FIFO
Parameters, on page 494 for descriptions of the flag and
parameter.
Almost Full Flag Specifies an Almost_full signal, which is asserted to indicate
that there is one location left and the FIFO will be full after
one more write operation.
options available for the signal (AFULL_FLAG_SENSE
parameter. See Full/Almost Full Flags, on page 497 and
FIFO Parameters, on page 494 for descriptions of the flag
and parameter.
Overflow Flag Specifies an Overflow signal, which is asserted to indicate
that the write operation was unsuccessful because the FIFO
was full.
options available for the signal (OVERFLOW_FLAG_SENSE
parameter). See Handshaking Flags, on page 498 f and
and parameter.
Write Acknowledge Specifies a Write_ack signal, which is asserted at the
Flag completion of a successful write operation.
options (WACK_FLAG_SENSE parameter) available for the
signal. See Handshaking Flags, on page 498 and FIFO
parameter.
Active High Sets the specified signal to active high (1).
Active Low Sets the specified signal to active low (0).

September 2016 151

read operations. Data is written/read on the rising edge of the clock.
Parameter Function
Empty Flag Specifies an Empty signal, which is asserted when the
memory queue for the FIFO is empty and no more reads
can be performed until data is written.
options (EMPTY_FLAG_SENSE parameter) available for the
signal. See Empty/Almost Empty Flags, on page 497 and
and parameter.
LO

152 September 2016
Parameter Function
Almost Empty Flag Specifies an Almost_empty signal, which is asserted when
there is only one location left to be read. The FIFO will be
empty after one more read operation.
options (AEMPTY_FLAG_SENSE parameter) available for the
signal. See Empty/Almost Empty Flags, on page 497 and
and parameter.
Underflow Flag Specifies an Underflow signal, which is asserted to indicate
that the read operation was unsuccessful because the FIFO
was empty.
options (UNDRFLW_FLAG_SENSE parameter) available for the
parameter.
Read Acknowledge Specifies a Read_ack signal, which is asserted at the
Flag completion of a successful read operation.
options (RACK_FLAG_SENSE parameter) available for the
parameter.

September 2016 153
programmable full operations. To use these options, you must have a Full
signal specified. See FIFO Programmable Flags, on page 500 for details and
FIFO Parameters, on page 494 for a list of the FIFO parameters. Data is
written/read on the rising edge of the clock.
Parameter Function
Programmable Full Specifies a Prog_full signal, which indicates that the FIFO
Flag has reached a user-defined full threshold.
You can only enable this option if you set Full Flag on page 2.
When it is enabled, you can specify other options for the
Prog_Full signal (PFULL_FLAG_SENSE parameter). See
Programmable Full, on page 501 and FIFO Parameters, on
page 494 for descriptions of the flag and parameter.
LO

154 September 2016
Parameter Function
Single Programmable Specifies a Prog_full signal with a single constant defining the
Full Threshold assertion threshold (PGM_FULL_TYPE=1 parameter). See
Constant Programmable Full with Single Threshold Constant, on
Enabling this option makes Full Threshold Assert Constant
available.
Multiple Programmable Specifies a Prog_full signal (PGM_FULL_TYPE=2 parameter),
Full Threshold with multiple constants defining the assertion and
Constant de-assertion thresholds. See Programmable Full with
Multiple Threshold Constants, on page 502 for details.
Enabling this option makes Full Threshold Assert Constant and
Full Threshold Negate Constant available.
Full Threshold Assert Specifies a constant that is used as a threshold value for
Constant asserting the Prog_full signal It sets the PGM_FULL_THRESH
parameter for PGM_FULL_TYPE=1 and the
PGM_FULL_ATHRESH parameter for PGM_FULL_TYPE=2.
Full Threshold Negate Specifies a constant that is used as a threshold value for
Constant de-asserting the Prog_full signal (PGM_FULL_NTHRESH
parameter).
Single Programmable Specifies a Prog_full signal (PGM_FULL_TYPE=3 parameter),
Full Threshold Input with a threshold value specified dynamically through a
Prog_full_thresh input port during the reset state.
SeeProgrammable Full with Single Threshold Input, on
Enabling this option adds the Prog_full_thresh input port to
the FIFO.
Multiple Programmable Specifies a Prog_full signal (PGM_FULL_TYPE=4 parameter),
Full Threshold Input with threshold assertion and deassertion values specified
dynamically through input ports during the reset state.
See Programmable Full with Multiple Threshold Inputs, on
Enabling this option adds the Prog_full_thresh_assert and
Prog_full_thresh_negate input ports to the FIFO.

September 2016 155

These options specify optional handshaking flags for FIFO programmable
empty operations. To use these options, you first specify an Empty signal on
page 3. See FIFO Programmable Flags, on page 500 for details and FIFO Param-
eters, on page 494 for a list of the FIFO parameters. Data is written/read on
the rising edge of the clock.
Parameter Function
Programmable Empty Specifies a Prog_empty signal (PEMPTY_FLAG_SENSE
Flag parameter), which indicates that the FIFO has reached a
user-defined empty threshold. See Programmable Empty,
on page 503 and FIFO Parameters, on page 494 for
descriptions of the flag and parameter.
Enabling this option makes the other options available to
specify LO
the threshold value, either as a constant or through
input ports. You can also specify single or multiple
thresholds for each of these options.

156 September 2016
Parameter Function
Single Programmable Specifies a Prog_empty signal (PGM_EMPTY_TYPE=1
Empty Threshold parameter), with a single constant defining the assertion
Constant threshold. See Programmable Empty with Single Threshold
Constant, on page 504 for details.
Enabling this option makes Empty Threshold Assert Constant
available.
Multiple Programmable Specifies a Prog_empty signal (PGM_EMPTY_TYPE=2
Empty Threshold parameter), with multiple constants defining the assertion
Constant and de-assertion thresholds. See Programmable Empty
with Multiple Threshold Constants, on page 504 for
details.
Enabling this option makes Empty Threshold Assert Constant
and Empty Threshold Negate Constant available.
Empty Threshold Specifies a constant that is used as a threshold value for
Assert Constant asserting the Prog_empty signal. It sets the
PGM_EMPTY_THRESH parameter for PGM_EMPTY_TYPE=1
and the PGM_EMPTY_ATHRESH parameter for
PGM_EMPTY_TYPE=2.
Empty Threshold Specifies a constant that is used as a threshold value for

Negate Constant de-asserting the Prog_empty signal (PGM_EMPTY_NTHRESH
parameter).
Single Programmable Specifies a Prog_empty signal (PGM_EMPTY_TYPE=3
Empty Threshold Input parameter), with a threshold value specified dynamically
through a Prog_empty_thresh input port during the reset
state. See Programmable Empty with Single Threshold
Input, on page 505 for details.
Enabling this option adds the Prog_full_thresh input port to
the FIFO.
Multiple Programmable Specifies a Prog_empty signal (PGM_EMPTY_TYPE=4
Empty Threshold Input parameter), with threshold assertion and deassertion
values specified dynamically through
Prog_empty_thresh_assert and Prog_empty_thresh_negate input
ports during the reset state. See Programmable Empty
with Multiple Threshold Inputs, on page 505 for details.
Enabling this option adds the input ports to the FIFO.

September 2016 157
Parameter Function
Number of Valid Data Specifies the Data_cnt signal for the FIFO output. This signal
in FIFO contains the number of words in the FIFO in the read
domain.
SYNCore RAM Wizard

The following describe the parameters you can set in the RAM wizard, which
opens when you select ram_model:
SYNCore RAM Parameters Page 1, on page 158
SYNCore RAM Parameters Pages 2 and 3, on page 160
SYNCore RAM Parameters Page 1
LO

158 September 2016
Component Specifies the name of the component. This is the name that you
Name instantiate in your design file to create an instance of the
SYNCore RAM in your design. Do not use spaces. For example:
ram101 <ComponentName> (
.PortAClk(PortAClk)
, .PortAAddr(PortAAddr)
, .PortADataIn(PortADataIn)
, .PortAWriteEnable(PortAWriteEnable)
, .PortBDataIn(PortBDataIn)
, .PortBAddr(PortBAddr)
, .PortBWriteEnable(PortBWriteEnable)
, .PortADataOut(PortADataOut)
, .PortBDataOut(PortBDataOut)
);
Directory Specifies the directory where the generated files are stored. Do
not use spaces. The following files are created:
filelist.txt lists files written out by SYNCore
options.txt lists the options selected in SYNCore
readme.txt contains a brief description and known issues
syncore_ram.v Verilog library file required to generate RAM
model
testbench.v Verilog testbench file for testing the RAM model
instantiation_file.vin describes how to instantiate the wrapper file
component.v RAM model wrapper file generated by SYNCore
Note that running the Memory Compiler wizard in the same
directory overwrites the existing files.
description of the compiled RAM. Do not use spaces.
Data Width Is the width of the data you need for the memory. The unit used is
the number of bits.
Address Width Is the address depth you need for the memory. The unit used is
the number of bits.
Single Port When enabled, generates a single-port RAM.

September 2016 159
Dual Port When enabled, generates a dual-port RAM.
Single Clock When enabled, generates a RAM with a single clock for dual-port
configurations.
Separate Clocks When enabled, generates separate clocks for each port in
for Each Port dual-port RAM configurations.
SYNCore RAM Parameters Pages 2 and 3

The port implementation parameters on pages 2 and 3 are identical, but page
2 applies to Port A (single- and dual-port configurations), and page 3 applies
to Port B (dual-port configurations only). The following figure shows the
parameters on page 2 for Port A.
Read and Write Specifies that the port can be accessed by both read and write
Access operations
Read Only Access Specifies that the port can only be accessed by read operations.
Write Only Access Specifies that

LO the port can only be accessed by write operations
Use Write Enable Includes write-enable control. The RAM symbol on the left
reflects the selections you make.

160 September 2016
Register Read Adds registers to the read address lines. The RAM symbol on the
Address left reflects the selections you make.
Register Outputs Adds registers to the write address lines when you specify
separate read/write addressing. The register outputs are always
enabled. The RAM symbol on the left reflects the selections you
make.
Synchronous Individually synchronizes the reset signal with the clock when
Reset you enable Register Outputs. The RAM symbol on the left reflects
the selections you make.
Read before Write Specifies that the read operation takes place before the write
operation for port configurations with both read and write
access (Read And Write Access is enabled). For a timing diagram,
see Read Before Write, on page 520.
Read after Write Specifies that the read operation takes place after the write
operation for port configurations with both read and write
see Write Before Read, on page 521.
No Read on Write Specifies that no read operation takes place when there is a
write operation for port configurations with both read and write
see No Read on Write, on page 522.
SYNCore Byte-Enable RAM Wizard

The following describes the parameters you can set in the byte-enable RAM
wizard, which opens when you select byte_en_ram.
SYNCore Byte-Enable RAM Parameters Page 1, on page 162
SYNCore Byte-Enable RAM Parameters Pages 2 and 3, on page 163

September 2016 161
SYNCore Byte-Enable RAM Parameters Page 1
LO

162 September 2016
Component Specifies the name of the component. This is the name that you
Name instantiate in your design file to create an instance of the
SYNCore byte-enable RAM in your design. Do not use spaces.
Directory Specifies the directory where the generated files are stored. Do
not use spaces. The following files are created:
syncore_be_ram_sdp.v SystemVerilog library file required to
generate single or simple dual-port, byte-enable RAM model
syncore_be_ram_tdp.v SystemVerilog library file required to
generate true dual-port byte-enable RAM model
testbench.v Verilog testbench file for testing the byte-enable
RAM model
instantiation_file.vin describes how to instantiate the wrapper file
component.v Byte-enable RAM model wrapper file generated by
SYNCore
Note that running the byte-enable RAM wizard in the same
directory overwrites the existing files.
description of the compiled byte-enable RAM. Do not use spaces.
Address Width Specifies the address depth for Ports A and B. The unit used is
the number of bits; the default is 2
Data Width Specifies the width of the data for Ports A and B. The unit used is
the number of bits; the default is 2
Write Enable Specifies the write enable width for Ports A and B. The unit used
Width is the number of byte enables; the default is 2, the maximum is 4.
Single Port When enabled, generates a single-port, byte-enable RAM

(automatically enables single clock).
Dual Port When enabled, generates a dual-port, byte-enable RAM
(automatically enables separate clocks for each port).
SYNCore Byte-Enable RAM Parameters Pages 2 and 3

The port implementation parameters on pages 2 and 3 are identical, but page
2 applies to Port A (single- and dual-port configurations), and page 3 applies
to Port B (dual-port configurations only). The following figure shows the
parameters on page 2 for Port A.

September 2016 163
Read and Write Specifies that the port can be accessed by both read and write
Access operations (only mode allowed for single-port configurations).
Read Only Access Specifies that the port can only be accessed by read operations
(dual-port mode only).
Write Only Access Specifies that the port can only be accessed by write operations
(dual-port mode only).
Register address Adds registers to the read address lines.
bus AddrA/B
Register output Adds registers to the read data lines. By default, the read data
data bus register is enabled.
RdDataA/B
LO

164 September 2016
Reset for Specifies the reset type for registered read data:
RdDataA/B Reset type is synchronous when Reset for RdDataA/B is
enabled
Reset type is no reset when Reset for RdDataA/B is disabled
Specify output Specifies reset value for registered read data (applies only when
data on reset RdDataA/B is enabled):
Default value of 1 for all bits sets read data to all 1s on reset
Specify Reset value for RdDataA/B specifies reset value for read
data; when enabled, value is entered in adjacent field.
Write Enable for Specifies the write enable level for Port A/B. Default is Active
Port A/B High.
SYNCore ROM Wizard

The following describe the parameters you can set in the ROM wizard, which
opens when you select rom_model:
SYNCore ROM Parameters Page 1, on page 166
SYNCore ROM Parameters Pages 2 and 3, on page 167
SYNCore ROM Parameters Page 4, on page 169

September 2016 165
SYNCore ROM Parameters Page 1
Component Name Specifies the name of the component. This is the name that
you instantiate in your design file to create an instance of
the SYNCore ROM in your design. Do not use spaces.
Directory Specifies the directory where the generated files are stored.
Do not use spaces. The following files are created:
syncore_rom.v Verilog library file required to generate ROM
model
testbench.v Verilog testbench file for testing the ROM model
instantiation_file.vin describes how to instantiate the wrapper
file
component.v ROM model wrapper file generated by
SYNCore
Note that running the ROM wizard in the same directory
overwrites the existing files.
File Name Specifies
LOthe name of the generated file containing the HDL
description of the compiled ROM. Do not use spaces.

166 September 2016
Read Data Width Specifies the read data width of the ROM. The unit used is
the number of bits and ranges from 2 to 256. Default value
is 8. The read data width is common to both Port A and Port
B. The corresponding file parameter is DATA_WIDTH=n.
ROM address width Specifies the address depth for the memory. The unit used
is the number of bits. Default value is 10. The
corresponding file parameter is ADD_WIDTH=n.
Single Port Rom When enabled, generates a single-port ROM. The
corresponding file parameter is CONFIG_PORT="single".
Dual Port Rom When enabled, generates a dual-port ROM. The
corresponding file parameter is CONFIG_PORT="dual".
SYNCore ROM Parameters Pages 2 and 3

The port implementation parameters on pages 2 and 3 are the same; page 2
applies to Port A (single- and dual-port configurations), and page 3 applies to
Port B (dual-port configurations only).

September 2016 167
Register address bus Used with synchronous ROM configurations to register the
AddrA read address. When checked, also allows chip enable to be
configured.
Register output data Used with synchronous ROM configurations to register the
bus DataA data outputs. When checked, also allows chip enable to be
configured.
Asynchronous Reset Sets the type of reset to asynchronous (Configure Reset
Options must be checked). Configuring reset also allows the
output data pattern on reset to be defined. The
corresponding file parameter is
RST_TYPE_A=1/RST_TYPE_B=1.
Synchronous Reset Sets the type of reset to synchronous (Configure Reset Options
must be checked). Configuring reset also allows the output
data pattern on reset to be defined.The corresponding file
parameter is RST_TYPE_A=0/RST_TYPE_B=0.
Active High Enable Sets the level of the chip enable to high for synchronous
ROM configurations. The corresponding file parameter is
EN_SENSE_A=1/EN_SENSE_B=1.
Active Low Enable Sets the level of the chip enable to low for synchronous ROM
configurations. The corresponding file parameter is
EN_SENSE_A=0/EN_SENSE_B=0.
Default value of '1' for Specifies an output data pattern of all 1s on reset. The
all bits corresponding file parameter is
RST_DATA_A={n{1'b1} }/RST_DATA_B={n{1'b1} }.
Specify reset value for Specifies a user-defined output data pattern on reset. The
DataA/DataB pattern is defined in the adjacent field. The corresponding
file parameter is RST_TYPE_A=pattern/RST_TYPE_B=pattern.
LO

168 September 2016
SYNCore ROM Parameters Page 4
Binary Specifies binary-formatted initialization file.
Hexadecimal Specifies hexadecimal-formatted initial file.
Initialization File Specifies path and filename of initialization file. The

corresponding file parameter is INIT_FILE="filename".
SYNCore Adder/Subtractor Wizard

The following describe the parameters you can set in the adder/subtractor
wizard, which opens when you select addnsub_model:
SYNCore Adder/Subtractor Parameters Page 1, on page 170
SYNCore Adder/Subtractor Parameters Page 2, on page 171

September 2016 169
SYNCore Adder/Subtractor Parameters Page 1
Component Name Specifies a name for the adder/subtractor. This is the name
that you instantiate in your design file to create an instance
of the SYNCore adder/subtractor in your design. Do not use
spaces.
stored. Do not use spaces. The following files are created:
syncore_ADDnSUB.v Verilog library file required to
generate adder/subtractor model
testbench.v Verilog testbench file for testing the
adder/subtractor model
instantiation_file.vin describes how to instantiate the
wrapper file
component.v adder/subtractor model wrapper file
generated by SYNCore
Note that running the wizard in the same directory
overwrites any existing files.
Filename LOthe name of the generated file containing the HDL
Specifies
description of the generated adder/subtractor. Do not use
spaces.

170 September 2016
Adder When enabled, generates an adder (the corresponding file

parameter is ADD_N_SUB ="ADD")
Subtractor When enabled, generates a subtractor (the corresponding
file parameter is ADD_N_SUB ="SUB")
Adder/Subtractor When enabled, generates a dynamic adder/subtractor (the
corresponding file parameter is ADD_N_SUB ="DYNAMIC")
SYNCore Adder/Subtractor Parameters Page 2

September 2016 171
Port A Width Specifies the width of port A (the corresponding file

parameter is PORT_A_WIDTH=n)
Register Input A Used with synchronous adder/subtractor configurations to
register port A. When checked, also allows clock enable and
reset to be configured (the corresponding file parameter is
PORTA_PIPELINE_STAGE=0 or 1)
Clock Enable for Specifies the enable for port A register

Register A
Reset for Register A Specifies the reset for port A register
Constant Value Input Specifies port B as a constant input when checked and
allows you to enter a constant value in the Constant Value/Port
B Width field (the corresponding file parameter is
CONSTANT_PORT =0)
Enable Port B Specifies port B as an input when checked and allows you to
enter a port B width in the Constant Value/Port B Width field
(the corresponding file parameter is CONSTANT_PORT =1)
Constant Value/Port B Specifies either a constant value or port B width depending
Width on Constant Value Input and Enable Port B selection (the
corresponding file parameters are CONSTANT_VALUE=n or
PORT_B_WIDTH=n)
Register Input B Used with synchronous adder/subtractor configurations to

register port B. When checked, also allows clock enable and
reset to be configured (the corresponding file parameter is
PORTB_PIPELINE_STAGE=0 or 1)
Clock Enable for Specifies the enable for the port B register
Register B
Reset for Register B Specifies the reset for the port B register
Output port Width Specifies the width of the output port (the corresponding file
parameter is PORT_OUT_WIDTH=n)
Register output Used with synchronous adder/subtractor configurations to
PortOut register the output port. When checked, also allows clock
enable and reset to be configured (the corresponding file
parameter is PORTOUT_PIPELINE_STAGE=0 or 1
Clock Enable for Specifies the enable for the output port register
Register PortOut LO

172 September 2016
Reset for Register Specifies the reset for the output port register
PortOut
Synchronous Reset Sets the type of reset to synchronous (the corresponding file
parameter is RESET_TYPE=0)
Asynchronous Reset Sets the type of reset to asynchronous (the corresponding
file parameter is RESET_TYPE=1)
SYNCore Counter Wizard

The following describe the parameters you can set in the ROM wizard, which
opens when you select counter_model:
SYNCore Counter Parameters Page 1, on page 173
SYNCore Counter Parameters Page 2, on page 175
SYNCore Counter Parameters Page 1

September 2016 173
Component Name Specifies a name for the counter. This is the name that you
instantiate in your design file to create an instance of the
SYNCore counter in your design. Do not use spaces.
stored. Do not use spaces. The following files are created:
syncore_counter.v Verilog library file required to generate
counter model
testbench.v Verilog testbench file for testing the counter
model
instantiation_file.vin describes how to instantiate the
wrapper file
component.v counter model wrapper file generated by
SYNCore
Note that running the wizard in the same directory
overwrites any existing files.
description of the generated counter. Do not use spaces.
Width of Counter Determines the counter width (the corresponding file
parameter is COUNT_WIDTH=n).
Counter Step Value Determines the counter step value (the corresponding file
parameter is STEP=n).
Up Counter Specifies an up counter (the default) configuration (the
corresponding file parameter is MODE=Up).
Down Counter Specifies an down counter configuration (the corresponding
file parameter is MODE=Down).
UpDown Counter Specifies a dynamic up/down counter configuration (the
corresponding file parameter is MODE=Dynamic).
LO

174 September 2016
SYNCore Counter Parameters Page 2
Enable Load option Enables the load options
Load Constant Value Load the constant value specified in the Load Value for constant
load option field; (the corresponding file parameter is LOAD=1).
Load Value for The constant value to be loaded.

constant load option
Use the port Loads variable value from PortLoadValue (the corresponding
PortLoadValue to load file parameter is LOAD=2).
Value
Synchronous Reset Specifies a synchronous (the default) reset input (the
corresponding file parameter is MODE=0).
Asynchronous Reset Specifies an asynchronous reset input (the corresponding
file parameter is MODE=1).

September 2016 175
Chapter 3: User Interface Commands Analysis Menu
Analysis Menu
When you synthesize a design with Synplify Premier, a default timing report
is automatically written to the log file (projectName.srr), located in the results
directory. This report provides a clock summary, I/O timing summary, and
detailed critical path information for the design. However, you can also
generate a custom timing report that provides more information than the
default report (specific paths or more than five paths) or one that provides
timing based on additional analysis constraint files without rerunning
synthesis.
Use the Analysis->Timing Analyst menu to generate custom timing reports. For
more information about using the Timing Analyst feature, see
Chapter 22, Analyzing Timing in the User Guide.
Command Description
Timing Analyst Displays the Timing Report Generation dialog box to specify
parameters for a stand-alone report. See Timing Report
Generation Parameters, on page 177 for information on
setting these options.
If you click OK in the dialog box, the specified parameters
are saved to a file. To run the report, click Generate. The
report is created using your specified parameters.
Generate Timing Generates and displays a report using the timing option
parameters specified above. SeeTiming Report Generation
Parameters, on page 177 for information on setting
parameters for the report. This includes information on
filtering and options for running backannotation data and
power consumption reports.
LO

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Analysis Menu Chapter 3: User Interface Commands
Timing Report Generation Parameters

You can use the Analysis->Timing Analyst command to specify parameters for a
stand-alone timing report. See Timing Reports, on page 254 for information
on the file contents.

September 2016 177
The following table provides brief descriptions of the parameters for running a
stand-alone timing report.
Timing Report Option Description

From or Specifies the starting (From) or ending (To) point of the path
To for one or more objects. It must be a timing start point
(From) or end (To) point for each object. Use this option in
combination with the others in the Filters section of the
dialog box. See Combining Path Filters for the Timing
Analyzer, on page 181 for examples of using filters.
Through Reports all paths through the specified point or list of
objects. See for more information on using this filter. Use
this option in combination with the others in the Filters
section of the dialog box. See the following for additional
information:
Timing Analyzer Through Points, on page 179
Combining Path Filters for the Timing Analyzer, on
page 181.
Generate Generates a report for paths that cross between clock
Asynchronous Clock groups. Generally paths in different clock groups are
Report automatically handled as false paths. This option provides
a file that contains information on each of the paths and
can be viewed in a spreadsheet. This file is in the results
directory (projectName_async_clk.rpt.csv). For details on the
report, see Asynchronous Clock Report, on page 259.
Async Clock Report File Displays the name of the clock report file when Generate
Asynchronous Clock Report is enabled.
Limit Number of Critical Specifies the maximum number of start/end paths to

Start/End points display for critical paths in the design. The default is 5. Use
this option in combination with the others in the Filters
section of the dialog box.
Limit Number of Paths Specifies the maximum number of paths to report. The
to default is 5. If you leave this field blank, all paths in the
design are reported. Use this option in combination with
the others in the Filters section of the dialog box.
Enable Slack Margin Limits the report to paths within the specified distance of
(ns) the critical path. Use this option in combination with the
others in the Filters section of the dialog box.
LO
Open Report When enabled, clicking the Generate button opens the Text
Editor on the generated custom timing report specified in
the timing report file (ta).

178 September 2016
Timing Report Option Description

Open Schematic When enabled, clicking the Generate button opens a view
showing the top-level netlist specified in the timing report
netlist file (srm).
Perform System Level Enables system-level timing analysis of the individual
Timing Analysis FPGAs synthesized by Synplify Premier. The Post Partition
Netlist File field points to the srp file.
Output Files Displays the name of the generated report:

Timing Analyzer Result File is the standard timing report file,
located in the Implementation Results directory. The file
is also listed in the Project view. Default filename is
projectName.ta.
SRM File updates the top-level view so that you can
display the results of the timing updates in the HDL tool.
The file is also listed in the Project view. The SRM file
selection is disabled when Generate Asynchronous Clock
Report is enabled.
For more details on any of these reports, see Timing
Reports, on page 254.
Constraint Files Enables analysis design constraint files (adc) to be used for
stand-alone timing analysis only. See Input Files, on
page 244 for information on this file.
Generate Clicking this button generates the specified timing report
file and timing view netlist file (srm) if requested, saves the
current dialog box entries for subsequent use, then closes
the dialog box.
Timing Analyzer Through Points

You can specify through points for nets (n:), hierarchical ports (t:), or instanti-
ated cell pins (t:). You can specify the through points in two ways:

September 2016 179
OR Enter the points as a space-separated list. The points are treated as an OR

list list and paths are reported if they crosses any of the points in the list. For
example, when you type the following, the tool reports paths that pass
through points b or c:
{n:b n:c}
See Filtering Points: OR List of Through Points, on page 180.
AND Enter the points in a product of sums (POS) format. The tool treats them as
list an AND list, and only reports the path if it passes through all the points in
the list. The POS format for the timing report is the same as for timing
constraints. The POS format is as follows:
{n:b n:c},{n:d n:e}
This constraint translates as follows:
b AND d
OR b AND e
OR c AND d
OR c AND e
See Filtering Points: AND List of Through Points, on page 181.
See Defining From/To/Through Points for Timing Exceptions, on page 666 for
more information about specifying through points.
Filtering Points: OR List of Through Points

This example reports the five worst paths through port bdpol or net aluout. You
can enter the through points as a space-separated list (enclosing the list in
braces is optional.)
LO

180 September 2016
Filtering Points: AND List of Through Points

This example reports the five worst paths passing through port bdpol and net
aluout. Enclose each list in braces { } and separate the lists with a comma.
Combining Path Filters for the Timing Analyzer

This section describes how to use a combination of path filters to specify what
you need and how to specify start and end points for path filtering.
Number and Slack Path Filters

The Limit Number of Paths To option specifies the maximum number of paths to
report and the Enable Slack Margin option limits the report to output only paths
that have a slack value that is within the specified value. When you use these

September 2016 181
two options together, the tighter constraint applies, so that the actual
number of paths reported is the minimum of the option with the smallest
value. For example, if you set the number of paths to report to 10 and the
slack margin for 1 ns, if the design has only five paths within 1 ns of critical,
then only five paths are reported (not the 10 worst paths). But if, for example,
the design has 15 paths within a 1 ns of critical, only the first 10 are
reported.
From/To/Through Filters
You can specify the from/to points for a path. You can also specify just a from
point or just a to point. The from and to points are one or more hierarchical
names that specify a port, register, pin on a register, or clock as object (clock
alias). Ports and instances can have the same names, so prefix the name with
p: for top-level port, i: for instance, or t: for hierarchical port or instance pin.
However, the c: prefix for clocks is required for paths to be reported.
The timing analyst searches for the from/to objects in the following order:
clock, port, bit port, cell (instance), net, and pin. Always use the prefix quali-
fier to ensure that all expected paths are reported. Remember that the timing
analyst stops at the first occurrence of an object match. For buses, all
possible paths from the specified start to end points are considered.
You can specify through points for nets, cell pins, or hierarchical ports.
You can simply type in from/to or through points. You can also cut-and-paste or
drag-and-drop valid objects from the RTL view into the appropriate fields on
the Timing Report Generation dialog box.
LO

182 September 2016
This following examples show how to specify start, end or through point
combinations for path filtering.
Filtering Points: Single Register to Single Register
Filtering Points: Clock Object to Single Register
Filtering Points: Single Bit of a Bus to Single Register

September 2016 183
Filtering Points: Single Bit of a Bus to Single Bit of a Bus
Filtering Points: Multiple Bits of a Bus to Multiple Bits of a Bus
Filtering Points: With Hierarchy

This example reports the five worst paths for the net foo:
LO

184 September 2016
Filtering Points: Through Point for a Net
Filtering Points: Through Point for a Hierarchical Port

This example reports the five worst paths for the hierarchical port bdpol:
Examples Using Wildcards

You can use the question mark (?) or asterisk (*) wildcard characters for
object searching and name substitution. These characters work the same
way in the Certify environment as in the Linux environment.

September 2016 185
The ? Wildcard
The ? matches single characters. If a design has buses op_a[7:0], op_b[7:0], and
op_c[7:0], and you want to filter the paths starting at each of these buses,
specify the start points as op_?[7:0]. See Example: ? Wildcard in the Name, on
page 186 for another example.
The * Wildcard
The * matches a string of characters. In a design with buses op_a2[7:0],
op_b2[7:0], and op_c2[7:0], where you want to filter the paths starting at each of
these objects, specify the start points as op_*[*]. The report shows all paths
beginning at each of these buses and for all of the bits of each bus. See
Example: * Wildcard in the Name (With Hierarchy), on page 187 and
Example: * Wildcard in the Bus Index, on page 187 for more examples.
Example: ? Wildcard in the Name

The ? is not supported in bus indices.
LO

186 September 2016
Example: * Wildcard in the Name (With Hierarchy)

This example reports the five worst paths, starting at block rxu_fifo and ending
at block rxu_channel within module nac_core. Each register in the design has
the characters reg in the name.
Example: * Wildcard in the Bus Index

This example reports the five worst paths, starting at op_b, and ending at
d_out, taking into account all bits on these buses.

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Chapter 3: User Interface Commands HDL Analyst Menu
HDL Analyst Menu

In the Project View, the HDL Analyst menu contains commands that provide
project analysis in the RTL view. The table below describes the HDL Analyst
menu commands for this view. Commands may be disabled (grayed out),
depending on the current context. Generally, the commands enabled in any
context reflect those available in the corresponding popup menus. The
descriptions in the table indicate when commands are context-dependent.
For explanations about the terms used in the table, like filtered and unfil-
tered, transparent and opaque, see Filtered and Unfiltered Schematic Views,
on page 348 and Transparent and Opaque Display of Hierarchical Instances,
on page 353. For procedures on using the HDL Analyst tool, see Analyzing
Logic in HDL Analyst, on page 305 in the User Guide.
For ease of use, the commands have been divided into sections that corre-
spond to the divisions in the HDL Analyst menu.
HDL Analyst Menu->RTL View Submenus, on page 188
HDL Analyst Menu: Hierarchical and Current Level Submenus, on
page 189
HDL Analyst Menu: Filtering and Flattening Commands, on page 191
HDL Analyst Menu: Analysis Commands, on page 193
HDL Analyst Menu: Selection Commands, on page 196
HDL Analyst Menu: FSM Commands, on page 196
HDL Analyst Menu->RTL View Submenus

This table describes the commands that appear on the HDL Analyst->RTL
submenu. For procedures on using these commands, see Analyzing Logic in
HDL Analyst, on page 305 in the User Guide.
HDL Analyst Command Description

RTL->Hierarchical View Opens a new, hierarchical RTL view. The
schematic is unfiltered.
RTL->Flattened View LO Opens a new RTL view of your entire design,
with a flattened, unfiltered schematic at the
level of generic logic cells. See Usage Notes for
Flattening, on page 192 for some usage tips.

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HDL Analyst Menu Chapter 3: User Interface Commands

RTL->Partitioned RTL View Opens a schematic view of your partitioned
logic assignments.
RTL->Implementation SRP View Opens a schematic view of the SRP file
HDL Analyst Menu: Hierarchical and Current Level Submenus

This table describes the commands on the HDL Analyst->Hierarchical and HDL
Analyst->Current Level submenus when the RTL view is active. For procedures
on using these commands, see Analyzing Logic in HDL Analyst, on page 305
in the User Guide.

Hierarchical->Expand Expands paths from selected pins and/or ports up to
the nearest objects on any hierarchical level, according
to pin/port directions. The result is a filtered
schematic. Operates hierarchically, on lower schematic
levels as well as the current level.
Successive Expand commands expand the paths further,
based on the new current selection.
Hierarchical->Expand to Expands paths from selected pins and/or ports, in the
Register/Ports port/pin direction, up to the next register, port, or black
box. The result is a filtered schematic. Operates
hierarchically, on lower schematic levels as well as the
current level.
Hierarchical->Expand Paths Shows all logic, on any hierarchical level, between two
or more selected instances, pins, or ports. The result is
a filtered schematic. Operates hierarchically, on lower
schematic levels as well as the current level.
Hierarchical->Expand Expands within the hierarchy of an instance, from the
Inwards lower-level ports that correspond to the selected pins, to
the nearest objects and no further. The result is a
filtered schematic. Operates hierarchically, on lower
Hierarchical->Goto Net Displays the unfiltered schematic sheet that contains
Driver the net driver for the selected net. Operates
hierarchically, on lower schematic levels as well as the
current level.

September 2016 189

Hierarchical->Select Net Selects the driver for the selected net. The result is a
Driver filtered schematic. Operates hierarchically, on lower
Hierarchical->Select Net Selects instances connected to the selected net. The
Instances result is a filtered schematic. Operates hierarchically,
on lower schematic levels as well as the current level.
Current Level->Expand Expands paths from selected pins and/or ports up to
the nearest objects on the current level, according to
pin/port directions. The result is a filtered schematic.
Limited to all sheets on the current schematic level.
This command is only available if a HDL Analyst view is
open.
Successive Expand commands expand the paths further,
based on the new current selection.
Current Level->Expand to Expands paths from selected pins and/or ports,
Register/Port according to the pin/port direction, up to the next
register, ports, or black box on the current level. The
result is a filtered schematic. Limited to all sheets on
the current schematic level.
Current Level->Expand Shows all logic on the current level between two or more
Paths selected instances, pins, or ports. The result is a filtered
schematic. Limited to the current schematic level (all
sheets).
Current Level->Goto Net Displays the unfiltered schematic sheet that contains
Driver the net driver for the selected net. Limited to all sheets
on the current schematic level.
Current Level->Select Net Selects the driver for the selected net. The result is a
Driver filtered schematic. Limited to all sheets on the current
schematic level.
Current Level->Select Net Selects instances on the current level that are
Instances connected to the selected net. The result is a filtered
schematic. Limited to all sheets on the current
schematic level.
LO

190 September 2016
HDL Analyst Menu: Filtering and Flattening Commands

This table describes the filtering and flattening commands on the HDL Analyst
menu when the RTL view is active. For procedures on filtering and flattening,
see Analyzing Logic in HDL Analyst, on page 305 in the User Guide.

Filter Schematic Filters your entire design to show only the selected
objects. The result is a filtered schematic. For more
information about using this command, see Filtering
Schematics, on page 347 of the User Guide.
This command is only available with an open HDL
Analyst view.
Hide Selected Instances Removes the selected instances from the current view.
Flatten Schematic In an unfiltered schematic, the command flattens the

(Unfiltered Schematic) current schematic, at the current level and all levels
below. See the next table entry for information about
flattening a filtered schematic.
This command does not do the following:
Flatten your entire design (unless the current level is
the top level)
Open a new view window
Take into account the number of Dissolve Levels defined
in the Schematic Options dialog box.
See Usage Notes for Flattening, on page 192 for tips.

September 2016 191

Flatten Schematic In a filtered schematic, flattening is a two-step process:
(Filtered Schematic) Only unhidden transparent instances (including nested
ones) are flattened in place, in the context of the entire
design.Opaque and hidden hierarchical instances
remain hierarchical. The effect of this command is that
all hollow boxes with pale yellow borders are removed
from the schematic, leaving only what was displayed
inside them.
The original filtering is restored.
This command does not do the following:
Flatten everything inside a transparent instance. It only
flattens transparent instances and any nested
transparent instances they contain.
Open a new view window
Take into account the number of Dissolve Levels defined
in the Schematic Options dialog box.
See Usage Notes for Flattening, on page 192 for usage
tips.
Unflatten Schematic Undoes any flattening operations and returns you to the
original schematic, as it was before flattening and any
filtering.
This command is available only if you have explicitly
flattened a hierarchical schematic using HDL
Analyst->Flatten Current Schematic, for example. It is not
available for flattened schematics created directly with
the RTL submenu of the HDL Analyst menu.
Usage Notes for Flattening

It is usually more memory-efficient to flatten only parts of your design, as
needed. The following are a few tips for flattening designs with different
commands. For detailed procedures, see Flattening Schematic Hierarchy, on
LO

192 September 2016
RTL->Flattened View Commands

Use Flatten Schematic to flatten only the current hierarchical level and below.
Flatten selected hierarchical instances with Dissolve Instances (followed by Flatten
Schematic, if the schematic is filtered).
To make hierarchical instances transparent without flattening them, use Dissolve
Instances in a filtered schematic. This shows their details nested inside the
instances.
Flatten Schematic Command (Unfiltered View)
Flatten selected hierarchical instances with Dissolve Instances.
To see the lower-level logic inside a hierarchical instance, push into it instead of
flattening.
Selectively flatten your design by hiding the instances you do not need, flattening,
and then unhiding the instances.
Flattening erases the history of displayed sheets for the current view. You can no
longer use View->Back. You can, however, use UnFlatten Schematic to get an
unflattened view of the design.
Flatten Schematic Command (Filtered View)
Flatten selected hierarchical instances with Dissolve Instances, followed by Flatten
Schematic.
Selectively flatten your design by hiding the instances you do not need, flattening,
and then unhiding the instances.
Flattening erases the history of displayed sheets for the current view. You can no
longer use View->Back. You can do the following:
Use View->Back for a view of the transparent instance flattened in the context of
the entire design. This is the view generated after step 1 of the two-step flattening
process described above. Use UnFlatten Schematic to get an unflattened view of the
design.
HDL Analyst Menu: Analysis Commands

This table describes the analysis commands on the HDL Analyst menu when
the RTL view is active. For procedures on using the analysis commands, see
Analyzing Logic in HDL Analyst, on page 305 in the User Guide.

September 2016 193

Isolate Paths Filters the current schematic to display only paths
associated with all the pins of the selected instances.
The paths follow the pin direction (from output to input
pins), up to the next register, black box, port, or
hierarchical instance.
If the selected objects include ports and/or pins on
unselected instances, the result also includes paths
associated with those selected objects.
The range of the operation is all sheets of a filtered
schematic or just the current sheet of an unfiltered
schematic. The result is always a filtered schematic.
In contrast to the Expand operations, which add to what
you see, Isolate Paths can only remove objects from the
display. While Isolate Paths is similar to Expand to
Register/Port, Isolate Paths reduces the display while
Expand to Register/Port augments it.
Show Context Shows the original, unfiltered schematic sheet that

contains the selected instance. Available only in a
filtered schematic.
Hide Instances Hides the logic inside the selected hierarchical
(non-primitive) instances. This affects only the active
HDL Analyst view; the instances are not hidden in other
HDL Analyst views.
The logic inside hidden instances is not loaded (saving
dynamic memory), and it is unrecognized by searching,
dissolving, flattening, expansion, and push/pop
operations. (Crossprobing does recognize logic inside
hidden instances, however.) See Usage Notes for Hiding
Instances, on page 195 for tips.
Unhide Instances Undoes the effect of Hide Instances: the selected hidden
hierarchical instances become visible (susceptible to
loading, searching, dissolving, flattening, expansion,
and push/pop operations). This affects only the current
HDL Analyst view; the instances are not hidden in other
HDL Analyst views.
LO

194 September 2016

Show All Hier Pins Shows all pins on the selected transparent,
non-primitive instances. Available only in a filtered
schematic. Normally, transparent instance pins that are
connected to logic that has been filtered out are not
displayed. This command lets you display these pins
that connected to logic that has been filtered out. Pins
on primitives are always shown.
Dissolve Instances Shows the lower-level details of the selected non-hidden
hierarchical instances. The number of levels dissolved
is determined by the Dissolve Levels value in the HDL
Analyst Options dialog box (HDL Analyst Options
Command, on page 206). For usage tips, see Usage
Notes for Dissolving Instances, on page 195.
Usage Notes for Hiding Instances

The following are a few tips for hiding instances. For detailed procedures, see
Flattening Schematic Hierarchy, on page 356 of the User Guide.
Hiding hierarchical instances soon after startup can often save memory.
After the interior of an instance has been examined (by searching or
displaying), it is too late for this savings.
You can save memory by creating small, temporary working files:
File->Save As srs or srm files does not save the hidden logic (hidden
instances are saved as black boxes). Restarting the synthesis tool and
loading such a saved file can often result in significant memory savings.
You can selectively flatten instances by temporarily hiding all the others,
flattening, then unhiding.
You can limit the range of Edit->Find (see Find Command (HDL Analyst),
on page 88) to prevent it looking inside given instances, by temporarily
hiding them.
Usage Notes for Dissolving Instances

Dissolving an instance one level redraws the current sheet, replacing the
hierarchical dissolved instance with the logic you would see if you pushed
into it using Push/pop mode. Unselected objects or selected hidden instances
are not dissolved. For additional information about dissolving instances, see
Flattening Schematic Hierarchy, on page 356 of the User Guide.

September 2016 195
The type (filtered or unfiltered) of the resulting schematic is unchanged from

that of the current schematic. However, the effect of the command is different
in filtered and unfiltered schematics:
In an unfiltered schematic, this command flattens the selected
instances. This means the history of displayed sheets is removed.
In a filtered schematic, this command makes the selected instances
transparent, displaying their internal, lower-level logic inside hollow
boxes. History is retained. You can use Flatten Schematic to flatten the
transparent instances, if necessary. This command is only available if
an HDL Analyst view is open.
HDL Analyst Menu: Selection Commands

This table describes the selection commands on the HDL Analyst menu.

Select All Schematic Selects all Instances or Ports, respectively, on all sheets of
->Instances the current schematic. All other objects are unselected.
This does not select objects on other schematics.
->Ports
Select All Sheet Selects all Instances or Ports, respectively, on the current
->Instances schematic sheet. All other objects are unselected.
->Ports
Unselect All Unselects all objects in all HDL Analyst views.
HDL Analyst Menu: FSM Commands

This table describes the FSM commands on the HDL Analyst menu.

View FSM Displays the selected finite state machine in the FSM
Viewer. Available only in an RTL view.
View FSM Info File Displays information about the selected finite state
machine
LO module, including the number of states, the
number of inputs, and a table of the states and
transitions. Available only in an RTL view.

196 September 2016
Options Menu Chapter 3: User Interface Commands
Options Menu
Use the Options menu to configure the VHDL and Verilog compilers, customize
toolbars, and set options for the Project view, Text Editor, and HDL Analyst
schematics. Additional menu commands let you run technology-vendor
software from this menu.
The following table describes the Options menu commands.
Command Description
Basic Options Menu Commands for all Views
Configure Synplify Launch Opens the Setup Synplify dialog box where you enter the
path to the Synplify Premier executable. You can also
set the maximum number of parallel jobs from the
dialog box when multiple licenses are available.
Configure VHDL Compiler... Opens the Implementation Options dialog box where
you can set the top-level entity and the encoding
method for enumerated types. State-machine encoding
is automatically determined by the FSM compiler or
FSM explorer, or you can specify it explicitly using the
syn_encoding attribute. See Implementation Options
Command, on page 114 for details.
Configure Verilog Compiler... Opens the Implementation Options dialog box where
you can specify the top-level module and the include
search path. See Implementation Options Command,
on page 114.
Toolbars... Lets you control your toolbar display. See Toolbar
Project View Options... Sets options for organizing files in the Project view. See
Project View Options Command, on page 199.
Editor Options... Sets your Text Editor syntax coloring, font, and tabs.
See Editor Options Command, on page 203.
HDL Analyst Options... Sets display preferences for HDL Analyst schematics.
See HDL Analyst Options Command, on page 206.

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Chapter 3: User Interface Commands Options Menu
Command Description
P&R Environment Options Displays the environmental variable options set for the
place-and-route tool. See P&R Environment Options
Configure External Programs Lets you set browser and Acrobat Reader options on
Linux platforms. See Configure External Programs
Certify Preferences Sets Certify-specific display controls for
windows/views and assignments.
Configure Synplify Launch Command

Select Options->Configure Synplify Launch to display the Setup Synplify dialog box
where you specify the path to the Synplify Premier installation.
The Maximum number of parallel jobs setting is used when multiple Synplify
Premier licenses are available and you want to perform tasks such as synthe-
sizing multiple SLP projects in parallel. This option can also be set with a
set_option max_parallel_jobs Tcl command.
LO

198 September 2016
Project View Options Command

Select Options->Project View Options to display the Project View Options dialog box,
where you define how projects appear and are organized in the Project view.
The following table describes the Project View Options dialog box features.

September 2016 199
Show Project File Library When enabled, displays the corresponding VHDL
library next to each source VHDL filename, in the
Project Tree view of the Project view. For example,
with library dune, file pc.vhd is listed as [dune] pc.vhd
if this option is enabled, and as pc.vhd if it is
disabled.
(See also Set VHDL Library Command, on
page 105, for how to change the library of a file.)
Beep when a job completes When enabled, sounds an audible signal whenever
a project finishes running.
View Project Files in Type When enabled, organizes project files into separate
Folders folders by file type. See View Project Files in Type
Folders Option, on page 201 and the add_file
command in the Certify Command Reference.
View Project Files in Custom When enabled, organizes project files into
Folders user-defined custom logical folders created for the
project. See View Project Files in Custom Folders
Option, on page 201.
Order files alphabetically When enabled, orders the files within folders
alphabetically instead of in project order. You can
also use the Sort Files option in the Project view.
Auto-load projects from Enable/Disable automatically loading projects from
previous session the previous session. Otherwise, projects will not be
loaded automatically. This option is enabled by
default. See Loading Projects With the Run
Auto-save project on Run Enable/Disable automatically saving projects when
the Run button is selected. See Automatically Save
Project on Run, on page 202.
Open Log file following Run Enable/Disable automatically opening and
displaying log file after a synthesis run.
Show all files in results directory When enabled, shows all files in the
Implementation Results view. When disabled, the
results directory shows only files generated by the
synthesis tool itself.
LO
Allow multiple projects to be When enabled, multiple projects are displayed at
opened the same time. See Allow Multiple Projects to be
Opened Option, on page 202.

200 September 2016
View log file in HTML Enable/Disable viewing of log file report in HTML
format versus text format. See Log File, on
page 250.
Display project view file From the drop-down menu, select one the following
pathnames ways to display project files:
File name only
Relative file path
Full file path
Use links in SRR log file to Determines if individual job logs use links in the
individual job logs srr log file. You can select:
off appends individual job logs to the srr log file.
on always link to individual job logs.
if_up_to_date only link to individual job logs if the
module is up-to-date.
View Project Files in Type Folders Option
View project files in type folders disabled
View project files in type folders enabled
View Project Files in Custom Folders Option

Selecting this option enables you to view user-defined logical folders that
contain a predefined subset of project files in various hierarchy groupings or
organizational structures. Custom folders are distinguished by their blue
color. For information on creating custom folders, see Creating Custom
Folders, on page 78 in the User Guide.

September 2016 201
Custom
Folders
Allow Multiple Projects to be Opened Option
Project 1
Project 2
Loading Projects With the Run Command

When you load a project that includes the project -run command, a dialog box
appears in the Project view with the following message:
Project run command encountered during project load. Are you sure
you want to run?
You can reply with either yes or no.
Automatically Save Project on Run

LO
If you have modified your project on the disk directory since being loaded into
the Project view and you run your design, a message is generated that infers
the UI is out-of-date.

202 September 2016
The following dialog box appears with a message to which you must reply.
You can specify one of the following:

Yes The Auto-save project on Run switch on the Project View Options dialog
box is automatically enabled, and then your design is run.
No The Auto-save project on Run switch on the Project View Options dialog
box is not enabled, but your design is run.
Cancel Closes this message dialog box and does not run your design.
Editor Options Command

Select Options->Editor Options to display the Editor Options dialog box, where you
select either the internal text editor or an external text editor.

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The following table describes the Editor Options dialog box features.
Feature Description
Select Editor Select an internal or external editor.
Synplicity Editor Sets the Synplicity text editor as the default text
editor.
External Editor Uses the specified external text editor program to view
text files from within the Synopsys FPGA tool. The
executable specified must open its own window for text
editing. See Using an External Text Editor, on page 48
of the User Guide for a procedure.
Note: Files opened with an external editor cannot be
crossprobed.
Options Set text editing preferences for the Synplicity text
editor.
File Type You can define text editor preferences for the following
file types: project files, HDL files, log files, constraint
files, and default files.
Font Lets you define fonts to use with the text editor.
Font Size Lets you define font size to use with the text editor.
Keep Tabs Lets you define whether to use tab settings with the
Tab Size text editor.
Syntax Coloring Lets you define foreground and background syntax

coloring to use with the text editor. See Color Options,
on page 204.
Color Options
Click in the Foreground or Background field for the corresponding object in the
Syntax Coloring field to display the color palette.
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You can set syntax colors for some common syntax options listed in the
following table.
Syntax Description
Comment Comment strings contained in all file types.
Error Error messages contained in the log file.
Gates Gates contained in HDL source files.
Info Informational messages contained in the log file.
Keywords Generic keywords contained in project, HDL source, constraint,

and log files.
Line Comment Line comments contained in HDL source, C, C++, and log files.
Note Notes contained in the log file.
SDCKeyword Constraint-specific keywords contained in the sdc file.
Strength Strength values contained in HDL source files.

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Syntax Description
String DQ String values within double quotes contained in project, HDL
source, constraint, C, C++, and log files.
String SQ String values within single quotes contained in project, HDL
source, constraint, C, C++, and log files.
SVKeyword System Verilog keywords contained in the Verilog file.
Types Type values contained in HDL source files.
Warning Warning messages contained in the log file.
HDL Analyst Options Command

Select Options->HDL Analyst Options to display the HDL Analyst Options dialog box,
where you define preferences for the HDL Analyst schematic view. Some
preferences take effect immediately; others only take effect in the next view
that you open. For details, see Setting Schematic View Preferences, on
For information about the options, see the following, which correspond to the
tabs on the dialog box:
Text Panel, on page 207
General Panel, on page 208
Sheet Size Panel, on page 210
Visual Properties Panel, on page 212
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Text Panel
The following options are in the Text panel.
Show text Enables the selective display of schematic labels.
Which labels are displayed is governed by the other
Show * features and Instance name, described below.
Show port name When enabled, port names are displayed.
Show symbol name When enabled, symbol names are displayed.
Show pin name When enabled, pin names are displayed.
Show bus width When enabled, connectivity bit ranges are displayed
near pins (in square brackets: []), indicating the bits
used for each bus connection.
Instance name Determines how to display instance names:
Show instance name
Show short instance name
No instance name
Set Defaults Set the dialog box to display the default values.

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General Panel
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208 September 2016
The following options are in the General panel.
Incremental Quick Load By default, the HDL Analyst reads the single SRS
netlist. When Incremental Quick Load is enabled, the
HDL Analyst reads the multi-file SRS netlist database.
The Certify tool uses this feature to dynamically load
only the affected design hierarchy to improve run time.
As a result, the hierarchy browser only expands the
lower-level design hierarchy. When disabled (the
default), the entire netlist is loaded into the HDL
Analyst.
Show hierarchy browser When enabled, a hierarchy browser is present as the
left pane of RTL view.
Show tooltip in schematic When enabled, displays tooltips that hover objects as
you move over them in the RTL schematic views.
Compact symbols When enabled, symbols are displayed in a slightly
more compact manner, to save space in schematics.
When this is enabled, Show cell interior is disabled.
Show sheet connector index When enabled, sheet connectors show connecting
sheet numbers see Sheet Connectors, on page 351.
Compress buses When enabled, buses having the same source and
destination instances are displayed as bundles, to
reduce clutter. A single bundle can connect to more
than one pin on a given instance. The display of a
bundle of buses is similar to that of a single bus.
Dissolve levels The number of levels to dissolve, during HDL
Analyst->Dissolve Instances.
Instances added for The maximum number of instances to add during any
expansion operation (such as HDL Analyst->Hierarchical->Expand)
that results in a filtered schematic. When this limit is
reached, you are prompted to continue adding more
instances.

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Sheet Size Panel
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210 September 2016
The following options are in the Sheet Size panel.
Maximum instances Defines the maximum number of instances to display

on a single sheet of an unfiltered schematic. If a given
hierarchical level has more than this number of
instances, then it will be partitioned into multiple
sheets. See Multiple-sheet Schematics, on page 364.
Maximum filtered instances Defines the maximum number of instances to display
on a filtered schematic sheet, at any visible
hierarchical level. This limit is applied recursively, at
each visible level, when
the sheet itself is a level, and
each transparent instance is a level (even if inside
another transparent instance).
Whenever a given level has more child instances inside
it than the value of Filtered Instances, it is divided into
multiple sheets.
(Only children are counted, not grandchildren or
below. Instance A is a child of instance B if it is inside
no other instance that is inside B.)
In fact, at each level except the sheet itself, an
additional margin of allowable child instances is added
to the Maximum filtered instances value, increasing its
effective value. This means that you can see more
child instances than Maximum filtered instances itself
implies.
The Maximum filtered instances value must be at least the
Maximum instances value. See Multiple-sheet
Schematics, on page 364.
Maximum instance ports Defines the maximum number of instance pins to
display on a schematic sheet.
Flow partition Uses the normal cone of logic flow from an instance to
a port, or else, input to a register, black box, or
hierarchical instance, when determining how to
partition the schematic into multiple sheets.
Connectivity partition Uses the number of connections between instances,
from most to least connections, when determining how
to partition the schematic into multiple sheets.

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Visual Properties Panel

Controls the display of the selected property in open HDL Analyst views. The
properties are displayed as colored boxes on the relevant objects. To display
these properties, the View->Visual Properties command must also be enabled.
For more information about properties, see Viewing Object Properties, on
The following options are in the Visual Properties panel.
Show Toggles the property name and value is displayed in a

color-coded box on the object.
Property Sets the properties to display.
RTL Enables or disables the display of visual properties in

the RTL view.
Value Only Displays only the value of an item and not its property
name.
Configure External Programs Command

This command is for Linux platforms only. It lets you specify the web browser
and PDF reader for accessing the Synopsys SolvNet web site (see Web Menu,
on page 221 for details) and LO
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212 September 2016
Web Browser Specify your web browser as an absolute path. You can use the
Browse button to locate the browser you need. The default is
netscape. If your browser requires additional environment
settings, you must do so outside the synthesis tool.
Acrobat Reader Specify your PDF reader as an absolute path. You can use the
Browse button to locate the reader you need. The default is
acroread.
P&R Environment Options Command

The P&R Environment Options command displays the environmental variable
options set for the place-and-route tool.

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Certify Preferences Command

The Certify dialog box is available using Options->Certify Preferences. The dialog
box includes the following panels:
Certify Dialog Box General Panel, on page 214
Certify Dialog Box Assignments Panel, on page 215
Certify Dialog Box General Panel

You use the General panel of the Certify dialog box to set the window/view
displays.
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214 September 2016
Feature Description
Partition View Undo You set the undo depth for Partition view
assignments by entering a value in the Maximum
undo depth field.
Tile Partition Management View When enabled, a tiled RTL view appears whenever
with Analyst when opening the Partition view is opened.
Show warning when closing the When enabled, any related warning messages are
Partition Manager View displayed on exiting the Partition view
Certify Dialog Box Assignments Panel

The Assignments panel sets the display controls.
Feature Description
Warnings If Show partition assignment warnings is enabled,
partitioning warnings are displayed.
Drag/Drop If Show fly lines when dragging is enabled, the
fly-line interconnect is shown when dragging
modules from the RTL view to a device in the
Partition view.

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Chapter 3: User Interface Commands Tech-Support Menu
Tech-Support Menu
The Tech-Support menu contains information the actions you can take when
you encounter problems running your designs or working with Synopsys
FPGA products.
Command Description
Submit Support Request Opens the Technical Support wizard to allow you
to submit online support requests via SolvNet.
The wizard includes provisions for attaching a
test case.
See Submit Support Request Command, on
page 216 for more information.
Web Support Opens the Synopsys support website from where
you can:
Log on to SolvNet to request Synopsys
technical support.
Access the Synopsys Documentation, Downloads,
and Literature pages that have links to product
information.
See Web Support Command, on page 219 for
more information.
Submit Support Request Command

To open a request for Synopsys Technical Support, select Submit Support
Request from the Tech-Support menu. This command brings up the web-based
technical support wizard that helps you prepare the information required to
provide technical support for your request through SolvNet.
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Tech-Support Menu Chapter 3: User Interface Commands
Command Description
Archive Brings up the Archive Utility to create an archive of
your design. Note that designs are limited to 10
MBytes.
Testcase name The name of the test case or file to be transferred. To
transfer multiple files, use the Archive utility to
create a single sar file for the transfer.
Upload Displays the FTP Archive File form to initiate the
transfer of the test case to the FTP file server. See
FTP Archive File Form, on page 218.
SolvNet Opens the Technical Support wizard to allow you to
submit online support requests via SolvNet. Use this
button when there is no accompanying test case.

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FTP Archive File Form

The FTP Archive File form is displayed when transferring a testcase or file to an
FTP file server as a result of clicking the Upload button in the Tech Support
Wizard dialog box.
Command Description
E-Mail Address The user e-mail address. The address entered is
combined with the Filename entry to form a unique
sar file name and is also automatically entered as
the password for the anonymous user name.
FTP Destination Identifies the FTP site destination. Clicking the
Synopsys, Inc. radio button enables the adjacent
drop-down menu to allow selection of one of the four
Synopsys world-wide FTP sites (North America, Europe,
Asia, or India); selecting the Other radio button
enables FTP Site field entry to allow an alternate FTP
site to be entered.
FTP Site The selected FTP site. The field is read-only when a
Synopsys world-wide site is selected from the
drop-down or accepts an FTP site entry when the
Other FTP Destination radio button is enabled.
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Username The user name. The default name of anonymous is
used when any of Synopsys world-wide FTP sites is
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Tech-Support Menu Chapter 3: User Interface Commands
Command Description
Password The user password. The default password for the
world-wide FTP sites is the address entered in the
E-Mail Address field.
Status Reports the status of the transfer.
Transfer Initiates the FTP file transfer; the results of the

transfer are displayed in the Status field.
Web Support Command

Through the Synopsys SolvNet Support page, you can access Products,
Downloads, Training, and Documentation pages on the Synopsys website as well
as submit requests for technical support through SolvNet. To use SolvNet,
you must have a user account. You are prompted for your SolvNet account
when you select Tech-Support->Web Support from the main menu or when you
click the SolvNet button on the Tech Support Wizard dialog box (see Submit
Support Request Command, on page 216).

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Once you logon, the SolvNet Support page is displayed.
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Web Menu Chapter 3: User Interface Commands
Web Menu
This menu contains commands that access up-to-date information from
Synopsys Support.
Command Description
Go to SolvNet Opens the home page for the Synopsys SolvNet
Search support. This website contains links to
useful technical information. You can search for
new or updated articles or documentation, such
as application notes, white papers, release notes,
and other user-oriented documentation.
Go to Training Center Opens the Synopsys training web page for
Synopsys products. Synopsys offers both online
web-based training courses, as well as classroom
training courses taught by Synopsys personnel.
Select the FPGA Implementation courses from
the drop-down menu.
Synopsys Home Opens the Synopsys home web page for
Synopsys products.
FPGA Implementation Tools Opens the Synopsys FPGA design solution web
page for Synopsys FPGA products. You can find
information about the full line of Synopsys FPGA
Implementation products here.

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Chapter 3: User Interface Commands Help Menu
Help Menu
There are four help systems accessible from the Help menu:
Help on the Certify synthesis tool (Help->Help)
Help on standard Tcl commands (Help->TCL)
Help on error messages (Help->Error Messages)
Help on using online help (Help->How to Use Help)
The following table describes the Help menu commands. Some commands are
only available in certain views.
Command Description
Help Displays hyperlinked online help for the product.
Additional Products Displays the Synopsys FPGA family of products and a brief
description.
How to Use Help Displays help on how to use Synopsys online help.
Online Documents Displays an Open dialog box with hyperlinked PDF

documentation on the product including release notes,
user guide, reference manual, and licensing configuration
and setup. You need Adobe Acrobat Reader to view the
PDF files.
Error Messages Displays the error message documentation.
TCL Displays help for Tcl commands.
Tutorial Opens Tutorial I, Partitioning Basics, for the Certify

Multi-FPGA Prototyping tool.
Mouse Stroke Tutor Displays the Mouse Stroke Tutor dialog box, providing
information on the available mouse strokes see Using
Mouse Strokes, on page 53.
License Agreement Displays the Synopsys FPGA software license agreement.
Floating License Usage Specifies the number of floating licenses currently being
used and their users.
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Help Menu Chapter 3: User Interface Commands
Command Description
Preferred License Displays the floating licenses that are available for your
Selection selection. See Preferred License Selection Command, on
page 223.
Tip of the Day... Displays a daily tip on how to use the Synopsys FPGA
synthesis tools better. See Tip of the Day Command, on
page 224.
About this program... Displays the About dialog box, showing the synthesis tool
product name, license expiration date, customer
identification number, version number, and copyright. The
dialog box also provides links to the Synopsys web site.
Clicking the Versions button in the About dialog box displays
the Version Information dialog box, listing the installation
directory and the versions of all the synthesis tool compiler
and mapper programs.
the online help sidebar has three tabs (Contents, Index, and Bookmarks) with
the Contents tab active.
Preferred License Selection Command

Select Help->Preferred License to display the Select Preferred License dialog box,
listing the available licenses for you to choose from. Select a license from the
License Type column and click Save. Close and restart the Certify synthesis
tool. The new session uses the preferred license you selected.

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Chapter 3: User Interface Commands Help Menu
Tip of the Day Command

Select Help->Tip of the Day to display the Tip of the Day dialog box, with a daily tip
on how to best use the Certify synthesis tool. This dialog box also displays
automatically when you first start the tool. To prevent it from redisplaying at
product startup, deselect Show Tips at Startup.
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Popup Menus Chapter 3: User Interface Commands
Popup Menus
Popup menus, available by clicking the right mouse button, offer quick ways
to access commonly used menu commands that are specific to the view
where you click. Commands shown grayed out (dimmed) are currently
inaccessible. Popup menu commands generally duplicate commands avail-
able from the regular menus, but sometimes have commands that are only
available from the popup menu. The following table lists the popup menus:
Popup Menu Description

Project view See Project View Popup Menu, on page 226 for details
SCOPE window Contains commonly used commands from the Edit menu.
Tcl window Contains commands from the Edit menu. For details, see Edit
Menu Commands for the Text Editor, on page 85.
Text Editor window See Text Editor Popup Menu, on page 232 for more
information.
RTL view See RTL View Popup Menus, on page 235.
FSM viewer See FSM Viewer Popup Menu, on page 241.
Log File See Log File Popup Menu, on page 233
Popup menus in the following views are documented in the User Guide:
For information on. . . See . . .

Partition view popup menu Chapter 4, Partitioning a Design
Impact Analysis popup menu Chapter 4, Partitioning a Design, section Impact
Analysis
Trace Assignments popup Chapter 5, Trace Assignments
menu

September 2016 225
Chapter 3: User Interface Commands Popup Menus
Project View Popup Menu

The popup menu commands available in the Project view are context-sensi-
tive, depending on what is currently selected and where in the view you open
the popup menu. Most commands duplicate commands from the File, Project,
Run, and Options menus. The following table describes the Project view popup
menu commands that are not described in other menus.
Command Description
Project Window
Open Project Displays the Open Project Dialog. See Open Project
New Project Creates a new empty project in the Project Window.
Refresh Refreshes the display.
Find Locates files in projects. Opens the project/file directory if

necessary and highlights the first occurrence of the filename
string. Select Find Next to find the next occurrence.
Project View Options Displays the Project View Options dialog. See Project View
Options Command, on page 199.
Project Selected
Project Options... Displays project properties such as name and location. See
Project Options Popup Menu Command, on page 231.
Open as Text Opens the selected file in the Text Editor.
Add Source File Displays the Add Files to Project dialog. See Add Source File
Add Folder Creates a folder with the new name you specified and adds it
to the Project view. See Creating Custom Folders, on
Add Implementation Displays the Implementation Options dialog box. See
Implementation Options Command, on page 114
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226 September 2016
Command Description
Constraint Check Checks the syntax and applicability of the timing
constraints in the sdc file for your project and generates a
report (projectName_cck.rpt). The report contains information
on the constraints that can be applied, cannot be applied
because objects do not exist, and wildcard expansion on the
constraints.
See Constraint Checking Report, on page 260.
Generate Clock Generates a report (project_clk.rpt) identifying all of the clocks
Report in the design.
Run Preparation Runs design preparation on the selected project.
Arrange VHDL Files Reorders the VHDL source files.
Constraint File Selected

File Options... Displays the File Options dialog box. See File Options
Open Opens the SCOPE window.
Copy File... Displays the Copy File dialog box, where you copy the
selected file and add it to the current project. You specify a
new name for the file. See Copy File Command, on
page 230.
Remove File From Removes the file from the project.
Project
File Selected
File Options Displays the File Options dialog box. See File Options
Open Opens the selected file according to the file type; for
example, sdc files are opened in the SCOPE window.
Syntax Check Runs a syntax check on your design code. Reports errors,
warnings, or notes in the Tcl Window.

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Command Description
Synthesis Check Runs a synthesis check on your design code. This includes a
syntax check and a check to see if the synthesis tool could
map the design to the hardware. No optimizations are
performed. Reports errors, warnings, or notes in the Tcl
Window.
Run Tcl Script Runs the selected Tcl script file.
Copy File Displays the Copy File dialog box, where you copy the
selected file and add it to the current project. You specify a
new name for the file. See Copy File Command, on
page 230.
Change File Opens the Source File dialog box where you choose a new file
to replace the selected file. See Change File Command, on
page 105
Remove File From Removes the selected file from the project.
Project
Remove From Folder Removes the selected file from a user-specified folder. The
file is returned to its original folder.
Place in Folder Places the selected file in a user-specified folder. You are
prompted to name a new folder or to select an existing
user-specified folder.
Launch Tools Brings up a Vendor Tool Invocation dialog box specific to the
target technology.
Implementation Selected
Change Displays the Implementation Name dialog box, where you
Implementation rename the selected implementation. (See Change
Name... Implementation Name/Copy Implementation Command,
on page 231.)
Copy Implementation Copies the selected implementation and adds it to the
current project with the name you specify in the dialog box.
(See Change Implementation Name/Copy Implementation
Command, on page 231.)
Remove Removes the selected implementation from the project.
Implementation
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228 September 2016
Command Description
Run Preparation Runs the preparation phase on the design by compiling the
design and board files and optimizing the design.
Synthesize All SLP Calls the Synplify Premier synthesize tool to synthesize the
Projects defined SLP projects.
Synthesize All SLP Calls the Synplify Premier synthesize tool to synthesize the
Projects (Parallel) defined SLP projects; projects can be synthesized in parallel
when additional licenses are available and the maximum
number of parallel jobs setting is greater than 1.
File Options Command

To display the File Options dialog box, right-click on a file in the project view
and select File Options from the popup menu. Specify the File type and the path
type to use when listing the file in the project file (prj).
File Path Path to the file.
Modified Date the file was last modified
Library Name of the compile library which must be compatible with VHDL
Names simulators. For VHDL files, the dialog box is the same as that
accessed by Project->Set VHDL Library see Set VHDL Library
Command, on page 105
File Type The type of file selected.
Note that you can select a different file type from the list of file types.
Changing the file type does not change the file extension it simply
places the file in the corresponding Project view folder. For example,
if you change the file type of a file from VHDL (foo.vhd) to Verilog
(foo.v), the Verilog extension is retained, and the file is moved from
the VHDL folder to the Verilog folder.
Verilog Selects the Verilog type from the drop-down menu: Use Project Default,
Standard Verilog 95, Verilog 2001, or SystemVerilog.
Save file The format for the path type: choose either Relative to Project or with
an Absolute Path.
The following is the dialog box for a Verilog file:

September 2016 229
Path to file
Modified date
Library
File Type
Verilog Standard
Save File
The following is the dialog box for a VHDL file:
Path to file
Modified date
Library
File Type
Save File
Copy File Command

With a file selected, select the Copy File popup menu command to copy the
selected file and add it to the current project. This displays the Copy File dialog
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230 September 2016
File to copy
New file (the copy)
Change Implementation Name/Copy Implementation Command

With an implementation selected, right-click and select the Change Implementa-
tion Name or Copy Implementation popup menu commands to display a dialog
box where you specify the new name.
Command Description
Change The implementation name you specify is the new name for
Implementation Name the implementation
Copy Implementation The currently selected implementation is copied and saved
to the project with the new implementation name you
specify.
New implementation name
Project Options Popup Menu Command

With a project selected, select the Project Options popup menu command to
display the Project Properties dialog box. To enable 64-bit mapping, click the
Enable 64-bit mapping (if available) check box at the bottom of the dialog box.

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Note: If 64-bit operation is requested on a 32-bit machine, a warning is

issued and the request is ignored.
Tcl Window Popup Menu

The Tcl window popup menu contains the Copy, Paste, and Find commands
from the Edit menu, as well as the Clear command, which empties the Tcl
window. For information on the Edit menu commands available in the Tcl
window, see Edit Menu Commands for the Text Editor, on page 85.
Text Editor Popup Menu

The popup menu in the Text Editor window contains the following commonly
used text-editing commands from the Edit menu: Undo, Redo, Cut, Copy, Paste,
and Toggle Bookmark. In addition, HDL Analyst specific commands appear
when both an HDL Analyst view and its corresponding HDL source file are
open. For details of these commands, see Edit Menu Commands for the Text
Editor, on page 85 and HDL Analyst Menu, on page 188.
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232 September 2016
Command Description
Filter in Filters your design to show only the currently selected objects from
Analyst the HDL text file. This is the same as HDL Analyst->Filter Schematic.
Log File Popup Menu

The popup menu in the log file contains commands that control operations in
the log file. The popup menu differs when the log file is opened in the HTML
mode or in the ASCII text mode.
Log File Filter Dialog Box

The Log File Filter dialog box is available by selecting Log File Message Filter from
the log file popup menu when the log file is opened in the HDML mode. The
dialog box allows messages in the current session to be promoted or demoted
in severity or suppressed from the log files for subsequent sessions. For
additional information on using this dialog box, see Log File Message
Controls, on page 845 of the User Guide.

September 2016 233
The following table describes the dialog box functions.
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234 September 2016
Function Description
Log File Displays the message ID and text and the default message type
Messages of messages generated during the current session.
window
Suppress Suppresses the selected note, warning, or advisory message. The
Message button selected message is removed from the upper Log File Messages
column indicating suppress status. Note that error messages
cannot be suppressed.
Make Error button Promotes the status of the selected warning (or note) to an error.
The selected message is removed from the upper Log File
Messages window and displayed in the lower window with the
Override column indicating error status.
Make Warning Promotes the status of the selected note to a warning. The
button selected message is removed from the upper Log File Messages
column indicating warning status.
Make Note button Demotes the status of the selected warning to a note. The
selected message is removed from the upper Log File Messages
column indicating note status.
Remove Override Removes the override status on the selected message in the lower
button window and returns the message to the upper Log File Messages
window.
lower window Lists the status of all messages that have been promoted,
demoted, or suppressed.
OK button Updates the status of any changed messages in the pfl file. Note
that you must recompile/resynthesize the design before any
message status changes become effective.
RTL View Popup Menus

Some commands are only available from the popup menus in the RTL view,
but most of the commands are duplicates of commands from the HDL Analyst,
Edit, and View menus.
This section describes the following popup menu commands:

Hierarchy Browser Popup Menu Commands, on page 236

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RTL View Popup Menu Commands, on page 236
Hierarchy Browser Popup Menu Commands

The following commands become available when you right-click in the
Hierarchy Browser of an RTL view. The Filter, Hide Instances, and Unhide
Instances commands are the same as the corresponding commands in the HDL
Analyst menu. The following commands are unique to this popup menu.
Command Description
Collapse All Collapses all trees in the Hierarchy Browser.
Filter Schematic Highlights and filters objects such as ports, instances, and
primitives in the HDL analyst window.
Hide Selected Removes the selected instances from the RTL view.
Instances
Reload Refreshes the Hierarchy Browser. Use this if the Hierarchy
Browser and schematic view do not match.
Hide/Unhide Hides or unhides selected instances in the HDL analyst window.
Instances For more information on hidden instances, see Hidden
Hierarchical Instances, on page 354.
RTL View Popup Menu Commands

The commands on the popup menu are context-sensitive, and vary
depending on the object selected, the kind of view, and where you click. In
general, if you have a selected object and you right-click in the background,
the menu includes global commands as well as selection-specific commands
for the objects.
Most of the commands duplicate commands available on the HDL Analyst

menu (see HDL Analyst Menu, on page 188). The following table lists the
unique commands.
Common Commands
Command See...
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Timing Analyst... HDL Analyst Menu, on page 188
Find Find Command (HDL Analyst), on page 88

236 September 2016
Filter Schematic HDL Analyst Menu: Filtering and Flattening

Commands, on page 191
Push/Pop Hierarchy HDL Analyst Menu->RTL View Submenus, on page 188
Select All Schematic HDL Analyst Menu: Selection Commands, on page 196
Select All Sheet HDL Analyst Menu: Selection Commands, on page 196
Unselect All HDL Analyst Menu: Selection Commands, on page 196
Flatten Schematic HDL Analyst Menu: Filtering and Flattening

Unflatten Schematic HDL Analyst Menu: Filtering and Flattening
HDL Analyst Options HDL Analyst Options Command, on page 206
Analyst Connectivity View View Menu: RTL View Commands, on page 97
SCOPE->Edit Attributes Opens a new or existing constraint file in SCOPE (see

SCOPE->Edit Attributes Command, on page 239).
Instance Selected
Command See...
Assign To Assigns selected instance or instances to FPGA or black
box.
Perform Impact Analysis Opens the impact analysis view for the selected device or
devices.
Isolate Paths Isolate Paths, on page 194
Show Context Show Context, on page 194
Hide Instance Hide Instances, on page 194
Unhide Instance Unhide Instances, on page 194
Show All Hier Pins Show All Hier Pins, on page 195
Dissolve Instance Dissolve Instances, on page 195
Properties Displays Visual Properties dialog box for selected instance.

September 2016 237
Port Selected
Command See...
Expand to Register/Port Hierarchical->Expand to Register/Ports, on page 189
Expand Inwards Hierarchical->Expand Inwards, on page 189
Current Level->Expand Current Level->Expand, on page 190
Current Level->Expand to Current Level->Expand to Register/Port, on page 190
Register/Port
Current Level->Expand Current Level->Expand Paths, on page 190
Paths
Properties Properties Popup Menu Command, on page 240
Net Selected
Command See...
Goto Net Driver Hierarchical->Goto Net Driver, on page 189
Select Net Driver Hierarchical->Select Net Driver, on page 190
Select Net Instances Hierarchical->Select Net Instances, on page 190
Current Level->Goto Net Current Level->Goto Net Driver, on page 190
Driver
Current Level->Select Net Current Level->Select Net Driver, on page 190
Driver
Current Level->Select Net Current Level->Select Net Instances, on page 190
Instances
Set Net Color Sets the color of the selected net from a color pallet.
Set Net Color Command

The set net color command sets the color of the selected net in the HDL Analyst
for the current session. To use the command, select the desired net or nets in
the RTL view and select set net color from the popup menu to display the dialog
box.
LO

238 September 2016
Double click on the corresponding color in the Color column to display the
color pallet and then double click the desired color and click OK. Nets can be
grouped and assigned to the same color by selecting the same group number
in the Group Number column.
SCOPE->Edit Attributes Command

You use the Select Constraint File dialog box to choose or create a constraint file.
You can open the constraint file and edit it.
For more information about creating constraint files, see Specifying SCOPE
Constraints, on page 655 of the User Guide.

September 2016 239
Properties Popup Menu Command

The software displays property information about the selected object when
you right-click on a net, instance, pin, or port in an HDL Analyst view. See
Viewing Object Properties, on page 307 of the User Guide for more information
about viewing object properties.
Lists pins, if the selected object is an instance or net.

Lists bits, if the selected object is a port.
Partition View Popup Menu

The Partition view popup menu includes several unique commands related to
the Partition view in addition to the standard view commands.
Command Description
Impact Analysis View Toggles the impact analysis view on and off.
Partition Connectivity Toggles the partition connectivity view on and off.

View
Show fly lines When Shows interconnect lines among devices when manually
dragging partitioning objects from the RTL view.
Properties Brings up the Properties dialog box (see Properties

Command, on page 241).
LO

240 September 2016
Properties Command
The Properties command brings up the Properties dialog box which lists the
properties of the selected object in the Object Properties panel. If the selected
object is a device with assignments, an additional panel, Assignments, appears
to allow you to unassign selected modules from the device. Before exiting the
dialog box, you can reassign any modules that you mistakenly unassigned.
FSM Viewer Popup Menu

The popup menu in the FSM Viewer contains commands that determine what
is shown in the FSM Viewer. The following table lists the popup commands in
the FSM Viewer.
Command Description
Properties Displays the Object Properties dialog box and view properties of
a selected state or transition. Information about a selected
transition includes the conditions enabling the transition and
the identities of its origin and destination states. Information
about a selected state includes its name, RTL encoding, and
mapped encoding.
Filter See View Menu: FSM Viewer Commands, on page 97
Unfilter See View Menu: FSM Viewer Commands, on page 97
FSM Properties Displays the Object Properties dialog box indicating the FSM
identity and location, encoding style, reset state, and the
number of states and transitions.

September 2016 241
FSM Properties
State properties Transition properties

(state selected) (transition selected)
LO

242 September 2016
CHAPTER 4
Input and Result Files
This chapter describes the input and output files used by the Certify tool.
Input Files, on page 244
Libraries, on page 246
Output Files, on page 248
Log File, on page 250
Timing Reports, on page 254
Constraint Checking Report, on page 260
Certify-Specific Reports, on page 268

September 2016 243
Chapter 4: Input and Result Files Input Files
Input Files
The following table describes the input files used by the Certify tool.
Extension File Description

.fdc Synopsys Contains the timing constraints (clock parameters,
FPGA Design I/O delays, and timing exceptions) in Synopsys
Constraint standard Tcl format. You can either create this file
manually or generate it using the SCOPE window. For
more information about creating fdc files, see
Specifying SCOPE Constraints, on page 655.
.ini Configuration Governs the behavior of the synthesis tool. You
and normally do not need to edit this file; use the
Initialization Schematic Options dialog box, instead, to customize
behavior. See HDL Analyst Options Command, on
page 206.
On the Windows 7 platforms, the ini file is in the
C:\Users\userName\AppData\Roaming\Synplicity
directory, and on the Windows XP platforms, the ini
file is in the C:\Documents and
Settings\userName\Application Data\Synplicity directory.
On Linux workstations, it is in the windows
subdirectory of your home directory (~/.synplicity,
where ~ is your home directory, which can be set with
the environment variable $HOME).
.prj Project Contains all the information required to complete a
design. It is in Tcl format, and contains references to
source files, compilation, mapping, and optimization
switches, specifications for target technology and
other runtime options.
.sdc Constraint Contains the timing constraints (clock parameters,
I/O delays, and timing exceptions) in Tcl format. For
more information about sdc files, see Specifying
SCOPE Constraints, on page 655.
.vhd Source files Design source files in VHDL format. See VHDL, on
(VHDL) page 245.
.v Source files Design source files in Verilog format. For more
(Verilog) information about the Verilog language, and the
LO
synthesis commands and attributes you can include,
see Verilog, on page 246.

244 September 2016
Input Files Chapter 4: Input and Result Files
HDL Source Files

The HDL source files for a project can be in either VHDL (vhd) or Verilog (v)
format.
The Certify tool contains built-in macro libraries for vendor macros like gates,
counters, flip-flops, and I/Os. If you use the built-in macro libraries, you can
easily instantiate vendor macros directly into the VHDL designs, and
forward-annotate them to the output netlist. Refer to the appropriate
vendor-support documentation for more information.
VHDL
The Certify tool supports a synthesizable subset of VHDL93 (IEEE 1076), and
the following IEEE library packages:
numeric_bit
numeric_std
std_logic_1164
The synthesis tool also supports the following industry standards in the IEEE
libraries:
std_logic_arith
std_logic_signed
std_logic_unsigned
The Certify tool library contains an attributes package (installationDirec-
tory/lib/vhd/synattr.vhd) of built-in attributes and timing constraints that you
can use with VHDL designs. The package includes declarations for timing
constraints (including black-box timing constraints), vendor-specific attri-
butes, and synthesis attributes. To access these built-in attributes, add the
following two lines to the beginning of each of the VHDL design units that
uses them:
library synplify;
use synplify.attributes.all;
For more information about the VHDL language, and the synthesis
commands and attributes you can include, see VHDL Synthesis Guidelines, on
page 246.

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Chapter 4: Input and Result Files Libraries
Verilog
The Certify tool supports a synthesizable subset of Verilog 2001 and Verilog
95 (IEEE 1364) and SystemVerilog extensions. For more information about
the Verilog language, and the synthesis commands and attributes you can
include, see Verilog Synthesis Guidelines, on page 61 and SystemVerilog
Feature Summary, on page 112.
The Certify tool contains built-in macro libraries for vendor macros like gates,
counters, flip-flops, and I/Os. If you use the built-in macro libraries, you can
instantiate vendor macros directly into Verilog designs and forward-annotate
them to the output netlist. Refer to the User Guide for more information.
Libraries
You can instantiate components from a library, which can be either in Verilog
or VHDL. For example, you might have technology-specific or custom IP
components in a library, or you might have generic library components. The
installDirectory/lib directory included with the software contains some compo-
nent libraries you can use for instantiation.
There are two kinds of libraries you can use:

Technology-specific libraries that contain I/O pad, macro, or other
component descriptions. The lib directory lists these kinds of libraries
under vendor sub-directories. The libraries are named for the technology
family, and in some cases also include a version number for the version
of the place-and-route tool with which they are intended to be used.
For information about using vendor-specific libraries to instantiate

LPMs, PLLs, macros, I/O pads, and other components, refer to the
appropriate sections in Chapter 19, Optimizing for Specific Targets in the
User Guide.
Technology-independent libraries that contain common components.
You can have your own library or use the one Synopsys provides. The
Synopsys FPGA library is a Verilog library of common logic elements,
much like the GTECH component library. See The Synopsys FPGA
LO
Generic Technology Library, on page 247 for a description of this library.

246 September 2016
Libraries Chapter 4: Input and Result Files
The Synopsys FPGA Generic Technology Library

The Certify software includes this Verilog library for generic components
under the installDirectory/lib/generic_technology directory. Currently, the library
is only available in Verilog format. The library consists of technology-indepen-
dent common logic elements, which help the designer to develop
technology-independent parts. The library models extract the functionality of
the component, but not its implementation. During synthesis, the mappers
implement these generic components in implementations that are appro-
priate to the technology being used.
To use components from this directory, add the library to the project by doing
either of the following:
Add add_file -verilog "$LIB/generic_technology/gtech.v to your prj file or type it
in the Tcl window.
In the tool window, click the Add file button, navigate to the
install_dir/lib/generic_technology directory and select the gtech.v file.
When you synthesize the design, the tool uses components from this library.
You cannot use the Synopsys FPGA generic technology library together with
other generic libraries, as this could result in a conflict. If you have your own
GTECH library that you intend to use, do not use the Synopsys FPGA generic
technology library.

September 2016 247
Chapter 4: Input and Result Files Output Files
Output Files
The Certify tool generates reports about its operations and files that you pass
to other tools for simulation or placement and routing. The following table
describes the output files, categorizing them as either result and report files,
or output files generated as input for other tools.

_cck.rpt Constraint Checker Checks the syntax and applicability of the
Report timing constraints in the sdc file for your
project and generates a report
(project_name_cck.rpt). See Constraint
Checking Report, on page 260 for more
information.
.est Module area Contains an area estimate for each design
estimation file module.
_est.srr Area estimation log Logs area estimate information. This is
the file displayed by View->View Estimation
Log.
.info Design component Design-dependent. Contains detailed

files information about design components like
state machines or ROMs.
.fse FSM information file Design-dependent. Contains information
about state machine encodings.
.pfl Message Filter Output file created after filtering messages
criteria in the Messages window. See Updating the
projectName.pfl file, on page 848 in the
User Guide.
.sap Synplify Annotated This file is generated after the Annotated
Properties Properties for Analyst option is selected in the
Device panel of the Implementation Options
dialog box. After the compile stage, the tool
annotates the design with properties like
clock pins. You can find objects based on
these annotated properties using Tcl Find. For
more information, see the command
description in the Certify Command
LO Reference and Using the Tcl Find Command
to Define Collections, on page 679 in the
User Guide.

248 September 2016
Output Files Chapter 4: Input and Result Files

.sar Archive file Output of the Synopsys FPGA Archive utility
in which design project files are stored into a
single archive file. Archive files use Synopsys
Proprietary Format. See Archive Project
Command, on page 107 for details on
archiving, unarchiving and copying projects.
.srd Intermediate Contain mapping information from Synplify
mapping file Premier synthesis runs. The information in
these files in added to the project for
system-level timing analysis.
.srr Log file Provides information on the run preparation
stage. See Log File, on page 250, for more
information.
.srs Compiler output file Output file available after the compile (Run
Preparation) stage. The file contains an
RTL-level representation of a design. This is
the representation that appears graphically
in an RTL view.

September 2016 249
Chapter 4: Input and Result Files Log File

.ta Customized Timing Contains the custom timing information
Report that you specify through Analysis->Timing
Options. See Analysis Menu, on page 176,
for more information.
.tap Timing Annotated This file is generated after the Annotated
Properties Properties for Analyst option is selected in the
Device panel of the Implementation Options
dialog box. After the compile stage, the tool
annotates the design with timing properties
and the information can be analyzed in the
RTL view. You can also find objects based on
these annotated properties using Tcl Find. For
more information, see the command
description in the Certify Command
Reference and Using the Tcl Find Command
to Define Collections, on page 679 in the
User Guide.
vendor Constraints file for Contains synthesis constraints to be
constraint forward annotation forward-annotated to the place-and-route
file tool. The constraint file type varies with the
vendor and the technology. Refer to the
vendor chapter for specific information
about the constraints you can
forward-annotate. Check the Implementation
Results dialog (Implementation Options) for
supported files. See Implementation
Results Panel, on page 117.
Log File
The log file report, located in the implementation directory, is written out in
two file formats: text (projectName.srr), and HTML with an interactive table of
contents (projectName.htm and projectName_srr.htm) where projectName is the
name of your project. Select View Log File in HTML in the Options->Project View
Options dialog box to enable viewing the log file in HTML. Select the View Log
button in the Project view (Buttons
LO and Options, on page 73) to see the log file
report.

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Log File Chapter 4: Input and Result Files
The log file is written each time you compile the design and contains only
compiler information. As a precaution, a backup copy of the log file (srr) is
written to the backup sub-directory in the Implementation Results directory.
Only one backup log file is updated for subsequent synthesis runs.
The log file contains detailed reports on the compiler information for your
design including:
Project information: names of the source files, and the top-level module.
Design information: HDL syntax and synthesis checks, black box
instantiations, FSM extractions and inferred RAMs/ROMs. It also
includes informational or warning messages about unused ports,
removal of redundant logic, and latch inference. See Errors, Warnings,
Notes, and Messages, on page 251 for details about the kinds of
messages.
Errors, warnings, and notes appear in both the log file and in the Messages
window.
Errors, Warnings, Notes, and Messages

Throughout the log file, interactive error, note, warning, and informational
messages appear.
Error messages begin with @E.
Warning messages begin with @W.
Notes begin with @N.
Informational messages begin with @I.
Colors distinguish different types of messages:
Color Message Type Example

Blue Information (@I) @I:"D:\t\alu.v"
Notes (@N) @N: CL201 "D:\t\p.v":58:0:58:5|Trying to
extract state machine for ...
Brown Warnings (@W) @W: CG146 "D:\t\e.v":53:9:53:12|Creating
black_box for empty module ...
Red Errors(@E) @E: CS106 "D:\t\e.v":53:9:53:12|Reference
to undefined module ...

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Chapter 4: Input and Result Files Log File
The errors, warnings, and notes are also displayed in the Messages window.
To get help on a message, you can single click on the numeric ID at the begin-
ning of the message in the log file or Messages window. To crossprobe to the
corresponding HDL source code, single click on the source file name.
Clock Buffering Report

This section of the log file reports any clocks that were buffered. For example:
Clock Buffers:
Inserting Clock buffer for port clock0, TNM=clock0
Net Buffering Report

Net buffering reports are generated for most all of the supported FPGAs and
CPLDs. This information is written in the log file, and includes the following
information:
The nets that were buffered or had their source replicated
The number of segments created for that net
The total number of buffers added during buffering
The number of registers and look-up tables (or other cells) added during
replication
Example: Net Buffering Report

Net buffering Report:
Badd_c[2] - loads: 24, segments 2, buffering source
Badd_c[1] - loads: 32, segments 2, buffering source
Badd_c[0] - loads: 48, segments 3w, buffering source
Aadd_c[0] - loads: 32, segments 3, buffering source
Added 10 Buffers
Added 0 Registers via replication
Added 0 LUTs via replication
LO

252 September 2016
Log File Chapter 4: Input and Result Files
Gated Clock Conversion Report

When using the gated clocks option, elements that could not be converted are
reported, and the reason why the conversion did not occur is stated (see
Analyzing the Clock Conversion Report, on page 621 in the User Guide.

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Chapter 4: Input and Result Files Timing Reports
Timing Reports
Timing results from system-level timing analysis are written to the ta file.
This file contains timing information based on the parameters you specify in
the stand-alone Timing Analyst (Analysis->Timing Analyst).
The individual timing reports in the ta file include:

Timing Report Header, on page 254
Performance Summary, on page 255
Clock Relationships, on page 255
Interface Information, on page 256
Detailed Clock Report, on page 257
Asynchronous Clock Report, on page 259
Timing Report Header

The timing report header lists the date and time, the name of the top-level
module, the number of paths requested for the timing report, and the
constraint files used.
You can control the size of the timing report by choosing Project -> Implementa-
tion Options, clicking the Timing Report tab of the panel, and specifying the
number of start/end points and the number of critical paths to report. See
Timing Report Panel, on page 138, for details.
LO

254 September 2016
Timing Reports Chapter 4: Input and Result Files
Performance Summary
The Performance Summary section of the timing report reports estimated and
requested frequencies for the clocks, with the clocks sorted by negative slack.
The timing report has a different section for detailed clock information (see
Detailed Clock Report, on page 257). The Performance Summary lists the
following information for each clock in the design:
Performance Summary Description

Column
Starting Clock Clock at the start point of the path.
If the clock name is system, the clock is a collection

of clocks with an undefined clock event. Rising and
falling edge clocks are reported as one clock
domain.
Requested/Estimated Target frequency goal /estimated value after
Frequency synthesis.
Requested/Estimated Period Target clock period/estimated value after
synthesis.
Slack Difference between estimated and requested
period.
Clock Type The type of clock: inferred, declared, derived or system.
The system clock is the delay for the combinatorial
path.
Clock Group Name of the clock group that a clock belongs.
The synthesis tool does not report inferred clocks that have an unreasonable
slack time. Also, a real clock might have a negative period. For example,
suppose you have a clock going to a single flip-flop, which has a single path
going to an output. If you specify an output delay of 1000 on this output,
then the synthesis tool cannot calculate the clock frequency. It reports a
negative period and no clock.
Clock Relationships
For each pair of clocks in the design, the Clock Relationships section of the
timing report lists both the required time (constraint) and the worst slack time
for each of the intervals rise to rise, fall to fall, rise to fall, and fall to rise.

September 2016 255
This information is provided for the paths between related clocks (that is,
clocks in the same clock group). If there is no path at all between two clocks,
then that pair is not reported. If there is no path for a given pair of edges
between two clocks, then an entry of No paths appears.
For information about how these relationships are calculated, see Clock
Groups, on page 333. For tips on using clock groups, see Defining Other Clock
Requirements, on page 699 of the User Guide.
Interface Information
The interface section of the timing report contains information on arrival
times, required times, and slack for the top-level ports. It is divided into two
subsections, one each for Input Ports and Output Ports. Bidirectional ports are
listed under both. For each port, the interface report contains the following
information.
Port parameter Description

Port Name Port name.
Starting Reference Clock The reference clock.

User Constraint The input/output delay. If a port has multiple delay
records, the report contains the values for the record with
the worst slack. The reference clock corresponds to the
worst slack delay record.
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256 September 2016
Port parameter Description

Arrival Time Input ports: define_input_delay, or default value of 0.
Output ports: path delay (including clock-to-out delay of
source register).
For purely combinational paths, the propagation delay is
calculated from the driving input port.
Required Time Input ports: clock period (path delay + setup time of
receiving register + define_reg_input_delay value).
Output ports: clock period define_output_delay. Default
value of define_output_delay is 0.
Slack Required Time Arrival Time
Detailed Clock Report

Each clock reported in the performance summary also has a detailed clock
report section in the timing report. The clock reports are listed in order of
negative slack.
General Critical Path Information

This section contains general information about the most critical paths in the
design.
Clock Information Description

N most critical start points Start points can be input ports or registers. If the
start point is a register, you see the starting pin in the
report. To change the number of start points reported,
choose Project->Implementation Options, and set the
number on the Timing Report panel.
N most critical end points End points can be output ports or registers. If the end
point is a register, you see the ending pin in the
report. To change the number of end points reported,
select Project->Implementation Options, and set the
number on the Timing Report panel.

September 2016 257
Clock Information Description

N worst path information Starting with the most critical path, the worst path
(see the next table for Information sections contain details of the worst
details) paths in the design. Paths from clock A to clock B are
reported as critical paths in the section for clock A.
You can change the number of critical paths on the
Timing Report panel of the Implementation Options dialog
box.
Worst Path Information

For each critical path, the timing report has a detailed description. It starts
with a summary of the information and is followed by a detailed pin-by-pin
report. The summary reports information like requested period, actual
period, start and end points, and logic levels. Note that the requested period
here is period -route delay, while the requested period in the Performance
Summary (Performance Summary, on page 255) is just the clock period.
The detailed path report uses this format: Output pin Net Input pin Output pin
Net Input pin. The following table describes the critical path information
reported:
Critical path information Description

Instance/Net Name Technology view names for the instances and nets in
the critical path
Type Type of cell
Pin Name Name of the pin
Pin Dir Pin direction
Delay The delay value.
Arrival Time Clock delay at the source + the propagation delay

through the path
Fan Out Number of fanouts for the point in the path
LO

258 September 2016
Asynchronous Clock Report

You can generate a report for paths that cross between clock groups using
the stand-alone Timing Analyst (Analysis->Timing Analyst, Generate Asynchronous
Clock Report check box). Generally, paths in different clock groups are
automatically handled as false paths. This option provides a file that contains
information on each of the paths and can be viewed in a spreadsheet tool. To
display the CSV-format report:
1. Locate the file in your results directory projectName_async_clk.rpt.csv.
2. Open the file in your spreadsheet tool.
Column Description
Index Path number.
Path Delay Delay value as reported in standard timing (ta) file.
Logic Levels Number of logic levels in the path (such as LUTs,

cells, and so on) that are between the start and end
points.
Types Cell types, such as LUT, logic cell, and so on.
Route Delay As reported for each path in ta
Source Clock Start clock.
Destination Clock End clock.
Data Start Pin Sequential device output pin at start of path.
Data End Pin Setup check pin at destination.

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Chapter 4: Input and Result Files Constraint Checking Report
Constraint Checking Report

The projectName_cck.rpt file is generated when you check your constraint
syntax with Run->Constraint Check. For details about running the constraint
checker, see Using the Synopsys Design Constraints Editor, on page 62 in the
User Guide. This section describes the following:
Reporting Details, on page 260
Inapplicable Constraints, on page 261
Applicable Constraints With Issues, on page 262
Sample Report, on page 263
Reporting Details
This constraint checking file reports the following:
Constraints that are not applied
Constraints that are valid and applicable to the design
Wildcard expansion on the constraints
Constraints on objects that do not exist
It contains the following sections:
Summary Statement which summarizes the total number of issues

defined as an error or warning (x) out of the total number of
constraints with issues (y) for the total number of constraints
(z) in the sdc file.
Found <x> issues in <y> out of <z> constraints
Clock Relationship Standard timing report clock table, without slack.
Unconstrained Lists I/O ports that are missing input/output delays.

Start/End Points
LO

260 September 2016
Constraint Checking Report Chapter 4: Input and Result Files
Unapplied Constraints that cannot be applied because objects do not

constraints exist or the object type check is not valid. See Inapplicable
Constraints, on page 261 for more information.
Applicable Constraints will be applied either fully or partially, but there
constraints with might be issues that generate warnings which should be
issues investigated, such as some objects/collections not existing.
Also, whenever at least one object in a list of objects is not
specified with a valid object type a warning is displayed. See
Applicable Constraints With Issues, on page 262 for more
information.
Constraints with Lists constraints or collections using wildcard expressions up
matching wildcard to the first 1000, respectively.
expressions
Inapplicable Constraints
Refer to the following table for constraints that were not applied because
objects do not exist or the object type check was not valid:
For these constraints... Objects must be...

Attributes Valid definitions
define_clock Ports
Nets
Pins
Registers
Instantiated buffers
define_clock_delay Clocks
define_compile_point Region
View
define_current_design v:view

September 2016 261

define_false_path For -to or -from objects:
define_multicycle_path i:sequential instances
define_path_delay p:ports
i:black boxes
For -through objects
n:nets
t:hierarchical ports
t:pins
define_multicycle_path Specified as a positive integer
define_input_delay Input ports
bidir ports
define_output_delay Output ports
Bidir ports
define_reg_input_delay Sequential instances
define_reg_output_delay
Applicable Constraints With Issues

The following table lists reasons for warnings in the report file:

define_clock Ports
Nets
Pins
Registers
Instantiated buffers
define_clock_delay A single object. Multiple objects are
not supported.
define_compile_point A single object. Multiple objects are
not supported.
define_current_design LO v:view

262 September 2016

define_false_path For -to or -from objects:
define_multicycle_path i:sequential instances
define_path_delay p:ports
i:black boxes
For -through objects:
n:nets
t:hierarchical ports
t:pins
define_input_delay A single object. Multiple objects are
not supported.
define_output_delay A single object. Multiple objects are
not supported.
define_reg_input_delay A single object. Multiple objects are
define_reg_output_delay not supported.
Sample Report
The following is a sample report generated by constraint checking:
# Synplicity Constraint Checker, version 9.0.0, Build 260R, built Sep 11 2006
# Copyright (C) 2003-2006, Synplicity Inc. All Rights Reserved
# Written on Tue Sep 12 16:37:45 2006
##### DESIGN INFO #######################################################
Top View: "decode_top"

Constraint File(s): "C:\timing_88\FPGA_decode_top.sdc"
##### SUMMARY ############################################################
Found 3 issues in 2 out of 27 constraints

September 2016 263
##### DETAILS ############################################################
Clock Relationships
*******************
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
------------------------------------------------------------------------------------
clk2x clk2x | 24.000 | 24.000 | 12.000 | 12.000
------------------------------------------------------------------------------------
clk2x clk | 24.000 | No paths | No paths | 12.000
clk clk2x | 24.000 | No paths | 12.000 | No paths
clk clk | 48.000 | No paths | No paths | No paths
====================================================================================
Note:
'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in
different clock groups
Unconstrained Start/End Points

******************************
p:test_mode
Inapplicable constraints
************************
define_false_path -from p:next_synd -through i:core.tab1.ram_loader

@E:|object "i:core.tab1.ram_loader" does not exist
@E:|object "i:core.tab1.ram_loader" is incorrect type; "-through" objects must be of
type net (n:), or pin (t:)
Applicable constraints with issues

**********************************
define_false_path -from {core.decoder.root_mult*.root_prod_pre[*]} -to

{i:core.decoder.omega_inst.omega_tmp_d_lch[7:0]}
@W:|object "core.decoder.root_mult*.root_prod_pre[*]" is missing qualifier which may
result in undesired results; "-from" objects must be of type clock (c:), inst (i:), port
(p:), or pin (t:)
Constraints with matching wildcard expressions

**********************************************
define_false_path -from {core.decoder.root_mult*.root_prod_pre[*]} -to

{i:core.decoder.omega_inst.omega_tmp_d_lch[7:0]}
@N:|expression "core.decoder.root_mult*.root_prod_pre[*]" applies to objects:
core.decoder.root_mult1.root_prod_pre[14:0]
core.decoder.root_mult.root_prod_pre[14:0]
LO

264 September 2016
define_false_path -from {i:core.decoder.*.root_prod_pre[*]} -to

{i:core.decoder.t_*_[*]}
@N:|expression "core.decoder.*.root_prod_pre[*]" applies to objects:
@N:|expression "core.decoder.t_*_[*]" applies to objects:
core.decoder.t_20_[7:0]
define_false_path -from {i:core.decoder.root_mult*.root_prod_pre[*]} -to

{i:core.decoder.err[7:0]}
N:|expression "core.decoder.root_mult*.root_prod_pre[*]" applies to objects:

{i:core.decoder.omega_inst.deg_omega[4:0]}

{i:core.decoder.omega_inst.omega_tmp[0:7]}

{i:core.decoder.root[7:0]}

September 2016 265

{i:core.decoder.root_inst.count[3:0]}
N:|expression "core.decoder.root_mult*.root_prod_pre[*]" applies to objects:

{i:core.decoder.root_inst.q_reg[7:0]}

{i:core.decoder.root_inst.q_reg_d_lch[7:0]}
define_false_path -from {i:core.decoder.root_mult.root_prod_pre[*]} -to

{i:core.decoder.error_inst.den[7:0]}
@N:|expression "core.decoder.root_mult.root_prod_pre[*]" applies to objects:
define_false_path -from {i:core.decoder.root_mult1.root_prod_pre[*]} -to

{i:core.decoder.error_inst.num1[7:0]}
@N:|expression "core.decoder.root_mult1.root_prod_pre[*]" applies to objects:
define_false_path -from {i:core.decoder.synd_reg_*_[7:0]} -to

{i:core.decoder.b_*_[7:0]}
@N:|expression "core.decoder.synd_reg_*_[7:0]" applies to objects:
core.decoder.un1_synd_reg_0_[7:0]
core.decoder.synd_reg_20_[7:0]
LO

266 September 2016
@N:|expression "core.decoder.b_*_[7:0]" applies to objects:
core.decoder.un1_b_0_[7:0]
core.decoder.b_calc.un1_lambda_0_[7:0]
core.decoder.b_20_[7:0]
core.decoder.b_0_[7:0
Library Report
**************
# End of Constraint Checker Report

September 2016 267
Chapter 4: Input and Result Files Certify-Specific Reports
Certify-Specific Reports
The Certify tool includes a set of partitioning, CPM, and board information
reports available through specific report commands entered at the Tcl
prompt. The report output defaults to the display, but can be written or
appended to a file. For a list of the available report commands and their
syntax, see Report Commands, on page 206 in the Command Reference.
LO

268 September 2016
CHAPTER 5
Constraints
Constraints are used in the FPGA synthesis environment to achieve optimal

design results. Timing constraints set performance goals, non-timing
constraints (design constraints) guide the tool through optimizations that
further enhance performance and physical constraints define regions and
locations for placement-aware synthesis.
This chapter provides an overview of how constraints are handled in the

FPGA synthesis environment.
Constraint Types, on page 270
Constraint Files, on page 271
Timing Constraints, on page 273
FDC Constraints, on page 276
Methods for Creating Constraints, on page 277
Constraint Translation, on page 280
Constraint Checking, on page 280
Database Object Search, on page 282
Forward Annotation, on page 283

September 2016 269
Chapter 5: Constraints Constraint Types
Constraint Types
One way to ensure the FPGA synthesis tools achieve the best quality of
results for your design is to define proper constraints. In the FPGA environ-
ment, constraints can be categorized by the following types:
Type Description
Timing Performance constraints that guide the synthesis tools to achieve optimal
results. Examples: clocks (create_clock), clock groups (set_clock_groups),
and timing exceptions like multicycle and false paths (set_multicycle_path...)
See Timing Constraints, on page 273 for information on defining these
constraints.
Design Additional design goals that enhance or guide tool optimizations.
Examples: Attributes and directives (define_attribute, define_global_attribute),
I/O standards (define_io_standard), and compile points (define_compile_point).
Physical Constraints that drive physical synthesis.
Examples: Region constraints for floorplanning (create_region).
The easiest way to specify constraints is through the SCOPE interface. The
tool saves timing and design constraints to an FDC file that you add to your
project.
See Also
Constraint Files, on page 271 for an overview of the types of constraint
files that are passed to the tool.
Timing Constraints, on page 273 for an overview of defining timing
constraints and generating FDC files.
SCOPE Constraints Editor, on page 285 for details on how to automati-
cally create timing and design constraints.
Chapter 10, Timing Constraint Syntax for timing constraint syntax.
Chapter 11, FPGA Design Constraint Syntax for design constraint
syntax.
LO

270 September 2016
Constraint Files Chapter 5: Constraints
Constraint Files
The figure below shows the files used for specifying various types of
constraints. The FDC file is the most important one and is the primary file for
both timing and non-timing design constraints. The other constraint files are
used for specific features or as input files to generate the FDC file, as
described in Timing Constraints, on page 273. The figure also indicates the
specific processes controlled by attributes and directives.
TIMING
DESIGN Legacy Synplify Timing
Constraints
Directives PHYSICAL
Attributes Synopsys Standard
Timing Constraints
Xilinx Timing & Physical
Other Design Constraints Constraints
Legacy SDC
Standard SDC
CDC ADC PDC
FDC
Static
Timing Physical
Compiler Mapper Synthesis
Analyzer
Timing constraints
Design constraints
Controlling constraint & module
Physical constraint
Constraint files

September 2016 271
Chapter 5: Constraints Constraint Files
The table summarizes constraint files.
File Type Common Commands Comments

FDC Timing create_clock, Used for synthesis. Includes
constraints set_multicycle_delay timing constraints that
follow the Synopsys
Design define_attribute, standard format as well as
constraints define_io_standard design constraints.
ADC Timing create_clock, Used with the stand-alone
constraints set_multicycle_delay timing analyzer.
for timing
analysis
CDC Design define_attribute Directives read in during
constraints define_global_attribute the compilation phase of
synthesis.
PDC Translated create_clock, Used in projects for
Xilinx define_attribute syn_loc Physical Plus.
timing and
physical
constraints
SDC FPGA timing create_clock, Use sdc2fdc to convert
(Synopsys constraints set_clock_latency, constraints to an FDC file so
Standard) set_false_path that they can be passed to
the synthesis tools.
SDC Legacy define_clock, Use sdc2fdc to convert the
(Legacy) timing define_false_path constraints to an FDC file so
constraints define_attribute, that they can be passed to
and define_collection the synthesis tools.
non-timing
(or design)
constraints
LO

272 September 2016
Timing Constraints Chapter 5: Constraints
Timing Constraints
Releases prior to G-2012.09 had two types of constraint files that could be
used in a design project:
Legacy Synplify-style timing constraints (define_clock, define_false_path...)
saved to an sdc file. The same file also included non-timing design
constraints, like attributes and compile points.
Synopsys standard timing constraints (create_clock, set_false_path...).
These constraints were also saved to an sdc file, which only contained
timing constraints. Non-timing constraints were in a separate sdc file.
The tool used the two files together, drawing timing constraints from one
and non-timing constraints from the other.
Starting with the G-2012.09 release, Synopsys standard timing constraint

format has replaced the legacy-style constraint format, and a new FDC (FPGA
design constraint) file consolidates both timing and design formats..
As a result of these updates, there are some changes in the use model:
Timing constraints in the legacy format are converted and included in
an FDC file, which includes both timing and non-timing constraints. The
file uses the Synopsys standard syntax for timing constraints (create_-
clock, set_multicycle_path...). The syntax for non-timing design constraints
is unchanged (define_attribute, define_io_standard...).
The SCOPE editor has been enhanced to support the timing constraint
changes, so that new constraints can be entered correctly.
For older designs, use the sdc2fdc command to do a one-time conversion.
If you are are targeting Xilinx 7-series technologies and Vivado,
legacy-style timing constraints are not supported. You must use the
sdc2fdc command to convert any existing legacy-style constraint files.

September 2016 273
Chapter 5: Constraints Timing Constraints
FDC File Generation

The following figure is a simplified summary of constraint-file handling and
the generation of fdc.
It is not required that you convert Synopsys standard sdc constraints as the
figure implies, because they are already in the correct format. You could have
a design with mixed constraints, with separate Synopsys standard sdc and fdc
files. The disadvantage to keeping them in the standard sdc format is that you
cannot view or edit the constraints through the SCOPE interface.
LO

274 September 2016
Timing Constraints Chapter 5: Constraints
Timing Constraint Precedence in Mixed Constraint Designs

Your design could include timing constraints in a Synopsys standard sdc file
and others in an fdc file. With mixed timing constraints in the same design,
this order of precedence applies:
The tool ignores the file order listed in the project file, and first reads in
all Synopsys standard sdc files and applies those constraints. If you have
multiple standard sdc files, the files are read in the order listed in the
project file.
After all the standard sdc files are read, the tool reads in all fdc files. If
you have multiple fdc files, the tool honors project file order.
The implication is that a conflicting constraint in an fdc file overwrites a

preceding sdc constraint. If a period of 10 ns was defined for a clock port in
the sdc file, and the fdc defines a clock on the same port with a period of 12 ns
(without using the -add argument), then the second constraint from the fdc file
applies.
Precedence does not affect legacy timing constraints. With these constraints,
it is strongly recommended that you convert them to the fdc format, but even
if you retain the old format in an existing design, they must be used alone
and cannot be mixed in the same design as fdc or Synopsys standard timing
sdc constraints.

September 2016 275
Chapter 5: Constraints FDC Constraints
FDC Constraints
The FPGA design constraints (FDC) file contains constraints that the tool uses
during synthesis. This FDC file includes both timing constraints and
non-timing constraints in a single file.
Timing constraints define performance targets to achieve optimal
results. The constraints follow the Synopsys standard format, such as
create_clock, set_input_delay, and set_false_path.
Non-timing (or design constraints) define additional goals that help the
tool optimize results. These constraints are unique to the FPGA
synthesis tools and include constraints such as define_attribute, define_io_-
standard, and define_compile_point.
The recommended method to define constraints is to enter them in the

SCOPE editor, and the tool automatically generates the appropriate syntax. If
you define constraints manually, use the appropriate syntax for each type of
constraint (timing or non-timing), as described above. See Methods for
Creating Constraints, on page 277 for details on generating constraint files.
Prior to release G-2012.09, designs used timing constraints in either legacy

Synplify-style format or Synopsys standard format. You must do a one-time
conversion on any existing SDC files to convert them to FDC files using the
following command:
% sdc2fdc
sdc2fdc converts constraints as follows:
For legacy Synplify-style Converts timing constraints to Synopsys standard

timing constraints format and saves them to an FDC file.
For Synopsys standard Preserves Synopsys standard format timing
timing constraints constraints and saves them to an FDC file.
For non-timing or design Preserves the syntax for these constraints and
constraints saves them to an FDC file.
Once defined, the FDC file can be added to your project. Double-click this file
from the Project view to launch the SCOPE editor to view and/or modify your
constraints. See Converting LO
SDC to FDC, on page 686 for details on how to
run sdc2fdc.

276 September 2016
Methods for Creating Constraints Chapter 5: Constraints
Methods for Creating Constraints

Constraints are passed to the synthesis environment in FDC files using Tcl
command syntax.
New Designs
For new designs, you can specify constraints using any of the following
methods:
Definition Method Description

SCOPE Editor Use this method to specify constraints wherever possible.
(fdc file)Recommended The SCOPE editor automatically generates fdc constraints
with the right syntax. You can use it for most constraints.
See Chapter 6, SCOPE Constraints Editor, for
information how to use SCOPE to automatically generate
constraint syntax.
Access: File->New->FPGA Design Constraints
Manually-Entered Text You can manually enter constraints in a text file. Make
Editor sure to use the correct syntax for the timing and design
(fdc File, all other commands.
constraint files) The SCOPE GUI includes a TCL View with an advanced
text editor, where you can manually generate the
constraint syntax. For a description of this view, see TCL
View, on page 306.
You can also open any constraint file in a text editor to
modify it.

September 2016 277
Chapter 5: Constraints Methods for Creating Constraints
Definition Method Description

Source Code Directives must be entered in the source code because
Attributes/Directives they affect the compiler. Do not include any other
(HDL files, cdc file) constraints in the source code, as this makes the source
code less portable. In addition, you must recompile the
design for the constraints to take effect.
You can specify some compiler directives in a cdc file with
the New-> Compiler Directives command.
Attributes can be entered through the SCOPE interface,
as they affect the mapper, not the compiler
Automatic First Pass Enable the Auto Constrain checkbox on the Constraints
tab to have the synthesis tool automatically generate
constraints based on inferred clocks. See the Synplify
Premier documentation for details.
Use this method as a quick first pass to get an idea of
what constraints can be set.
If there are multiple timing exception constraints on the same object, the
software uses the guidelines described in Conflict Resolution for Timing
Exceptions, on page 325 to determine the constraint that takes precedence.
See Also
To specify the correct syntax for the timing and design commands, see:
Chapter 10, Timing Constraint Syntax
Chapter 11, FPGA Design Constraint Syntax
Chapter 1, Synthesis Attributes and Directives
LO

278 September 2016
Methods for Creating Constraints Chapter 5: Constraints
Existing Designs
The SCOPE editor in this release does not save constraints to SDC files. For
designs prior to G-2012.09, it is recommended that you migrate your timing
constraints to FDC format to take advantage of the tools enhanced handling
of these types of constraints. To migrate constraints, use the sdc2fdc
command (see Converting SDC to FDC, on page 686l) on your sdc files.
Note: If you need to edit an SDC file, either use a text editor, or
double-click the file to open the legacy SCOPE editor. For infor-
mation on editing older SDC files, see SCOPE User Interface
(Legacy), on page 329 or Synplify-Style Timing Constraints
(Legacy), on page 513.
See Also
To use the current SCOPE editor, see:
Chapter 6, SCOPE Constraints Editor
Chapter 18, Specifying Constraints

September 2016 279
Chapter 5: Constraints Constraint Translation
Constraint Translation
The synthesis tools include a number of scripts for converting constraints to
the correct format. The sdc2fdc script translates sdc files to fdc files. For
constraints from vendor tools, you must first use the appropriate utility to
translate the constraints to sdc, and then migrate them to fdc with the sdc2fdc
script. For information on using the sdc2fdc Tcl script command, see
Converting SDC to FDC, on page 686; for information on the vendor transla-
tors, see the Synplify Premier documentation.
Constraint Checking
The synthesis tools include several features to help you debug and analyze
design constraints. Use the constraint checker to check the syntax and appli-
cability of the timing constraints in the project. The synthesis log file includes
a timing report as well as detailed reports on the compiler, mapper, and
resource usage information for the design. A stand-alone timing analyzer
(STA) generates a customized timing report when you need more details
about specific paths or want to modify constraints and analyze, without
resynthesizing the design. The following sections provide more information
about these features.
Constraint Checker
Check syntax and other pertinent information on your constraint files using
Run->Constraint Check or the Check Constraints button in the SCOPE editor. This
command generates a report that checks the syntax and applicability of the
timing constraints that includes the following information:
Constraints that are not applied
Constraints that are valid and applicable to the design
Wildcard expansion on the constraints
Constraints on objects that do not exist
LO
See Constraint Checking Report, on page 260 for details.

280 September 2016
Constraint Checking Chapter 5: Constraints
Timing Constraint Report Files

The results of running constraint checking, synthesis, and stand-alone
timing analysis are provided in reports that help you analyze constraints.
Use these files for additional timing constraint analysis:
File Description
_cck.rpt Lists the results of running the constraint checker (see Constraint
Checking Report, on page 260).
.ta Reports timing analysis results (see the Synplify Premier
documentation).
.srr or Reports post-synthesis timing results as part of the text or HTML log file
.htm (see the Synplify Premier documentation).

September 2016 281
Chapter 5: Constraints Database Object Search
Database Object Search

To apply constraints, you have to search the database to find the appropriate
objects. Sometimes you might want to search for and apply the same
constraint to multiple objects. The FPGA tools provide some Tcl commands to
facilitate the search for database objects:
Commands Common Commands Description

Find Tcl Find, open_design... Lets you search for design objects to
form collections that can apply
constraints to the group. See Using
Collections, on page 672 and find, on
page 108 in the Certify Command
Reference.
Collections define_collection, Create, copy, evaluate, traverse, and
c_union... filter collections. See Using Collections,
on page 672 for more information.
LO

282 September 2016
Forward Annotation Chapter 5: Constraints
Forward Annotation
The tool can automatically generate vendor-specific constraint files for
forward annotation to the place-and-route tools when you enable the Write
Vendor Constraints switch (on the Implementation Results tab) or use the -write_apr_-
constraint option of the set_option command.
Vendor File Extension

Altera ACF
SCF
TCL
Xilinx NCD
NCF
UCF
XDC
For information about how forward annotation is handled for your target
technology, refer to the appropriate vendor chapter.

September 2016 283
Chapter 5: Constraints Forward Annotation
LO

284 September 2016
CHAPTER 6
SCOPE Constraints Editor
The SCOPE (Synthesis Constraints OPtimization Environment) editor

automatically generates syntax for synthesis constraints. Enter information
in the SCOPE tabs, panels, columns, and pull-downs to define constraints
and parameter values. You can also drag-and-drop objects from the HDL
Analyst UI to populate values in the constraint fields.
This interface creates Tcl-format Synopsys Standard timing constraints and

Synplify-style design constraints and saves the syntax to an FPGA design
constraints (FDC) file that can automatically be added to your synthesis
project. See Constraint Types, on page 270 for definitions of synthesis
constraints.
Topics in this section include:

SCOPE User Interface, on page 286
SCOPE Tabs, on page 287
Industry I/O Standards, on page 308
Delay Path Timing Exceptions, on page 312
Specifying From, To, and Through Points, on page 318
Conflict Resolution for Timing Exceptions, on page 325
SCOPE User Interface (Legacy), on page 329

September 2016 285
Chapter 6: SCOPE Constraints Editor SCOPE User Interface
SCOPE User Interface

The SCOPE editor contains a number of panels for creating and managing
timing constraints and design attributes. This GUI offers the easiest way to
create constraint files for your project. The syntax is saved to a file using an
FDC extension and can be included in your design project.
From this editor, you specify timing constraints for clocks, ports, and nets as
well as design constraints such as attributes, collections, and compile points.
However, you cannot set black-box constraints from the SCOPE window.
To bring up the editor, use one of the following methods from the Project view:
For a new file (the project file is open and the design is compiled):
Choose File->New-> FPGA Design Constraints; select FPGA Constraint File
(SCOPE).
Click the SCOPE icon in the toolbar; select FPGA Constraint File (SCOPE).
You can also open the editor using an existing constraint file.
Double-click on the constraint file (FDC), or use File->Open, specifying
the file type as FPGA Design Constraints File (*.fdc).
See Also:
Using the SCOPE Editor, on page 650 in the User Guide.
SCOPE User Interface (Legacy), on page 329
LO

286 September 2016
SCOPE Tabs Chapter 6: SCOPE Constraints Editor
SCOPE Tabs
Here is a summary of the constraints created through the SCOPE editor:
SCOPE Panel See...

Clocks Clocks, on page 287
Generated Clocks Generated Clocks, on page 293
Collections Collections, on page 295
Inputs/Outputs Inputs/Outputs, on page 297
Registers Registers, on page 299
Delay Paths Delay Paths, on page 300
Attributes Attributes, on page 303
I/O Standards I/O Standards, on page 304
TCL View TCL View, on page 306
If you choose an object from a SCOPE pull-down menu, it has the appropriate
prefix appended automatically. If you drag and drop an object from an RTL
view, for example, make sure to add the prefix appropriate to the language
used for the module. See Verilog Naming Syntax, on page 535 and VHDL
Naming Syntax, on page 536 for details.
Clocks
You use the Clocks panel of the SCOPE spreadsheet to define a signal as a
clock.
The Clocks panel includes the following options:

September 2016 287
Chapter 6: SCOPE Constraints Editor SCOPE Tabs
Field Description
Name Specifies the clock object name.
Clocks can be defined on the following objects:
Pins
Ports
Nets
For virtual clocks, the field must contain a unique name not
associated with any port, pin, or net in the design.
Period Specifies the clock period in nanoseconds. This is the
minimum time over which the clock waveform repeats. The
period must be greater than zero.
Waveform Specifies the rise and fall edge times for the clock waveforms of
the clock in nanoseconds, over an entire clock period. The first
time in the list is a rising transition, typically the first rising
transition after time zero. There must be two edges, and they
are assumed to be rise and then fall. The edges must be
monotonically increasing. If you do not specify this option, a
default waveform is assumed, which has a rise edge of 0.0 and
a fall edge of period/2.
Add Specifies whether to add this clock to the existing clock or to
overwrite it. Use this option when multiple clocks must be
specified on the same source for simultaneous analysis with
different clock waveforms. When you use this option, you
must also specify the clock and the clocks with the same
source must have different names.
Clock Group Assigns clocks to asynchronous clock groupings. The clock
grouping is inclusionary (for example, clk2 and clk3 can each be
related to clk1 without being related to each other).
Latency Specifies the clock latency applied to clock ports and clock
aliases. Applying the latency constraint on a port can be used
to model the off-chip clock delays in a multi-chip environment.
Clock latency can only:
Apply to clocks defined on input ports.
Be used for source latency.
Apply to port clock objects.
Uncertainty Specifies the LO
clock uncertainty (skew characteristics) of the
specified clock networks. You can only apply latency to clock
objects.

288 September 2016
Clock Groups
With this version of the software, clock grouping is associative-based; two
clocks can be asynchronous to each other but both can be synchronous with
a third clock.
The SCOPE GUI prompts you for a clock group for each clock that you define,
and, by default, assigns all clocks to the default clock group. When you add a
name to the clock group that differs from the default clock group name, the
clock is assigned its own clock group and is asynchronous to the default
clock group as well as all other named clock groups.
This section presents scenarios for defining clocks and includes the following
examples:
Example 1 SCOPE Definition
Example 2 Equivalent Tcl Syntax
Example 3 Establish Clock Relationships
Example 4 Using a Single Group Option
Example 5 UCF Forward Annotation
Example 6 Legacy Clock Grouping
Example 1 SCOPE Definition

A design has three clocks: clk1, clk2, clk3 and you want clk1 and clk2 to be in the
same clock groups synchronous to each other but asynchronous to clk3.
You can do this by adding a name in the Clock Group column in the Clocks tab
of as shown below.

September 2016 289
This specification assigns clk1 and clk2 to clock group group1, synchronous to
each other and asynchronous to clk3. The equivalent command appears in the
text editor window as:
set_clock_groups -derive -asynchronous -name {group1}

-group { {c:clk1} {c:clk2} }
Example 2 Equivalent Tcl Syntax

A design has three clocks: clk1, clk2, clk3. You can use the following commands
to set clk2 synchronous to clk3, but asynchronous to clk1:
set_clock_groups asynchronous group [get_clocks {clk3 clk2}]

set_clock_groups asynchronous -group [get_clocks {clk1}]
Example 3 Establish Clock Relationships

A design has the following clocks defined:
create_clock -name {clka} {p:clka} -period 10 -waveform {0 5.0}

create_clock -name {clkb} {p:clkb} -period 20 -waveform {0 10.0}
create_clock -name {my_sys} {p:sys_clk} -period 200 -waveform
{0 100.0}
The desired clock relationships are:
1. clka and clkb are asynchronous to each other
2. clka and clkb are synchronous to my_sys
For the tool to establish these relationships, multiple -group options are
needed in a single set_clock_groups command. Clocks defined by the first -group
option are asynchronous to clocks in the subsequent -group option. Therefore,
you would use the following syntax to establish the relationships described
above:
set_clock_groups -asynchronous -group [get_clocks {clka}]

-group [get_clocks {clkb}]
LO

290 September 2016
Example 4 Using a Single Group Option

set_clock_groups has a unique behavior when a single -group option is specified
in the command. For example, in the following constraint specification:
set_clock_groups -asynchronous -name {default_clkgroup_0}

-group [get_clocks {clka my_sys}]
set_clock_groups -asynchronous -name {default_clkgroup_1}
-group [get_clocks {clkb my_sys}]
The first statement assigns clka AND my_sys as asynchronous to clkb, and the
second statement assigns clkb AND my_sys as asynchronous to clka. Therefore,
with this specification, all three clocks are established as asynchronous to
each other.
Example 5 UCF Forward Annotation

To forward annotate clock groups to a Xilinx technology UCF for the Xilinx
ISE place and route tool, each clock must belong to only one clock group.
Clock relationships in UCF must be represented in synthesis using the single
group option method for one or more set_clock_groups constraints, but any
given clock may be present in only one of the constraints. This is due to the
linear nature of clock groups in UCF in that, if two clocks in a design are
defined asynchronous to each other, a third clock in the design can only be
defined as synchronous to one of the first two clocks, or asynchronous to
both. The third clock can never be synchronous to both of the first two
clocks.
The SCOPE method of defining clock groups as show in Example 1 SCOPE

Definition, is specifically designed to make this linear type grouping the
default and avoid issues with clock groups when going from the Synopsys
SDC Standard clock grouping to Xilinx UCF clock grouping. The Synplify
Xilinx mappers detect when the target forward annotation is UCF for Xilinx
designs and issues an error if clock grouping in synthesis is not compatible
with UCF. It is recommended that you use SCOPE to define your clocks and
establish clock relationships when targeting Xilinx technologies for ISE place
and route.

September 2016 291
An example of the SCOPE generated SDC Standard syntax for clock grouping
for a design with three clocks clka, clkb, and my_sys is shown below:
set_clock_groups -asynchronous -group [get_clocks {clka my_sys}]

set_clock_groups -asynchronous -group [get_clocks {clkb}]
OR
set_clock_groups -asynchronous -group [get_clocks {clkb my_sys}]

set_clock_groups -asynchronous -group [get_clocks {clka}]
Example 6 Legacy Clock Grouping

This section shows how the legacy clock group definitions (Synplify-style
timing constraints) are converted to the Synopsys standard timing syntax
(FDC). Legacy clock grouping can be represented through Synopsys standard
constraints, but the multi-grouping in the Synopsys standard constraints
cannot be represented in legacy constraints. For example, the following
legacy clock definitions:
define_clock -name{clka} {p:clka}-period 10

-clockgroup default_clkgroup_0
define_clock -name {clkb} {p:clkb} -freq 150
define_clock -name {clkc} {p:clkc} -freq 200
... become these FDC clock definitions:
###==== BEGIN Clocks - (Populated from SCOPE tab, do not edit)

create_clock -name {clka} {p:clka} -period 10 -waveform {0 5.0}
create_clock -name {clkb} {p:clkb} -period 6.667
-waveform {0 3.3335}
create_clock -name {clkc} {p:clkc} -period 5.0 -waveform {0 2.5}
set_clock_groups -derive -name default_clkgroup_0 -asynchronous
-group {c:clka}
set_clock_groups -derive -name default_clkgroup_1 -asynchronous
-group {c:clkb c:clkc}
###==== END Clocks LO

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The create_generated_clock constraints used in legacy SDC are preserved in

FDC. The -derive option directs the create_generated_clock command to inherit
the -source clock group. This behavior is unique to FDC and is an extension of
the Synopsys SDC standard functionality.
See Also
For equivalent Tcl syntax, see:
create_clock, on page 475
set_clock_groups, on page 483
set_clock_latency, on page 486
set_clock_uncertainty, on page 489
For information about all SCOPE panels, see SCOPE Tabs, on page 287.
Generated Clocks
Use the Generated Clocks panel of the SCOPE spreadsheet to define a signal as
a generated clock. The equivalent Tcl constraint is create_generated_clock; its
syntax is described in create_generated_clock, on page 478.

September 2016 293
The Generated Clocks panel includes the following options:
Field Description
Name Specifies the name of the generated clock.
If this option is not used, the clock gets the name of the first
clock source specified in the source.
Source Specifies the master clock source (a clock source pin in the
design), from which the clock waveform is derived. The
actual delays (latency) for the generated clock are computed
using its own source pins and not the master pin.
Object Generated clocks can be defined on the following objects:
Pins
Ports
Nets
Instances where instances have only one output (for
example, BUFGs)
Master Clock Specifies the master clock to be used for this generated
clock, when multiple clocks fan into the master pin.
Generate Type Specifies any of the following:
edges Specifies a list of integers that represents edges from
the source clock that are to form the edges of the generated
clock. The edges are interpreted as alternating rising and
falling edges and each edge must not be less than its
previous edge. The number of edges must be an odd number
and not less than 3 to make one full clock cycle of the
generated clock waveform. For example, 1 represents the
first source edge, 2 represents the second source edge, and
so on.
divide_by Specifies the frequency division factor. If the
divide factor value is 2, the generated clock period is twice
as long as the master clock period.
multiply_by Specifies the frequency multiplication factor. If
the multiply factor value is 3, the generated clock period is
one-third as long as the master clock period.
Generate Parameters Specifies integers that define the type of generated clock.
Generate Modifier Defines LO

the secondary characteristics of the generated
clock.

294 September 2016
Field Description
Modify Parameters Defines modifier values of the generated clock.
Invert Specifies whether to use invert Inverts the generated clock

signal (in the case of frequency multiplication and division).
Add Either add this clock to the existing clock or overwrite it.
Use this option when multiple generated clocks must be
specified on the same source, because multiple clocks fan
into the master pin. Ideally, one generated clock must be
specified for each clock that fans into the master pin. If you
specify this option, you must also specify the clock and
master clock. The clocks with the same source must have
different names.
For more information about other SCOPE options, see SCOPE Tabs, on
page 287.
Collections
The Collections tab allows you to set constraints for a group of objects you
have defined as a collection with the Tcl command. For details, see Creating
and Using Collections (SCOPE Window), on page 673 of the User Guide.
Field Description
Collection Name Enter the collection name.
Command Select a collection creation command from the drop-down

menu. See Collection Commands, on page 296 for
descriptions of the commands.
Command Specify the Tcl syntax for the constraint you want to apply to
Arguments the collection.
Comment Enter comments that are included in the constraints file.

September 2016 295
You can crossprobe the collection results to an HDL Analyst view. To do this,
right-click in the SCOPE cell and select the option Select in Analyst.
Collection Commands
You can use the collection commands on collections or Tcl lists. Tcl lists can be
just a single element long.
To... Use this command...

Create a collection set modules
To create and save a collection, assign it to a variable.
You can also use this command to create a collection
from any combination of single elements, TCL lists and
collections:
set modules [define_collection {v:top} {v:cpu} $mycoll $mylist]
Once you have created a collection, you can assign
constraints to it in the SCOPE interface.
Copy a collection set modules_copy $modules
This copies the collection, so that any change to $modules
does not affect $modules_copy.
Evaluate a collection c_print
This command returns all objects in a column format.
Use this for visual inspection.
c_list
This command returns a Tcl list of objects. Use this to
convert a collection to a list. You can manipulate a Tcl
list with standard Tcl list commands.
Concatenate a list to a c_union
collection
Identify differences c_diff
between lists or Identifies differences between a list and a collection or
collections between two or more collections. Use the -print option to
display the results.
LO

296 September 2016
To... Use this command...

Identify objects c_intersect
common to a list and a Use the -print option to display the results.
collection
Identify objects c_sub
common to two or more Use the -print option to display the results.
collections
Identify objects that c_symdiff
belong exclusively to Use this to identify unique objects in a list and a
only one list or collection, or two or more collections. Use the -print
collection option to display the results.
Inputs/Outputs
The Inputs/Outputs panel models the interface of the FPGA with the outside
environment. You use it to specify delays outside the device.
The Inputs/Outputs panel includes the following options:
Field Description
Delay Type Specifies whether the delay is an input or output delay.
Port Specifies the name of the port.
Rise Specifies that the delay is relative to the rising transition on

specified port.
Fall Specifies that the delay is relative to the falling transition on
specified port
Max Specifies that the delay value is relative to the longest path.

September 2016 297
Field Description
Min Specifies that the delay value is relative to the shortest path.
Clock Specifies the name of a clock for which the specified delay is
applied. If you specify the clock fall, you must also specify the
name of the clock.
Clock Fall Specifies that the delay relative to the falling edge of the clock.
For examples, see Input Delays, on page 298 and Output
Delays, on page 299.
Add Delay Specifies whether to add delay information to the existing
input delay or overwrite the input delay. For examples, see
Input Delays, on page 298 and Output Delays, on page 299.
Value Specifies the delay path value.
Input Delays
Here is how this constraint applies for input delays:
Clock Fall The default is the rising edge or rising transition of a reference
pin. If you specify clock fall, you must also specify the name of the clock.
Add Delay Use this option to capture information about multiple paths
leading to an input port relative to different clocks or clock edges.
For example, set_input_delay 5.0 -max -rise -clock phi1 {A} removes all
maximum rise input delay from A, because the -add_delay option is not
specified. Other input delays with different clocks or with -clock_fall are
removed.
In this example, the -add_delay option is specified as set_input_delay 5.0

-max -rise -clock phi1 -add_delay {A}. If there is an input maximum rise delay
for A relative to clock phi1 rising edge, the larger value is used. The
smaller value does not result in critical timing for maximum delay. For
minimum delay, the smaller value is used. If there is maximum rise
input delay relative to a different clock or different edge of the same
clock, it remains with the new delay.
LO

298 September 2016
Output Delays
Here is how this constraint applies for output delays:
Clock Fall If you specify clock fall, you must also specify the name of the
clock.
Add Delay By using this option, you can capture information about
multiple paths leading from an output port relative to different clocks or
clock edges.
For example, the set_output_delay 5.0 -max -rise -clock phi1 {OUT1} command
removes all maximum rise output delays from OUT1, because the
-add_delay option is not specified. Other output delays with a different
clock or with the -clock_fall option are removed.
In this example, the -add_delay option is specified: set_output_delay 5.0 -max

-rise -clock phi1 -add_delay {Z}. If there is an output maximum rise delay for
Z relative to the clock phi1 rising edge, the larger value is used. The
smaller value does not result in critical timing for maximum delay. For
minimum delay, the smaller value is used. If there is a maximum rise
output delay relative to a different clock or different edge of the same
clock, it remains with the new delay.
See Also

set_input_delay, on page 497
set_output_delay, on page 506
Registers
The Registers panel lets the advanced user add delays to paths feeding
into/out of registers, in order to further constrain critical paths. You use this
constraint to speed up the paths feeding a register. See set_reg_input_delay,
on page 509 and set_reg_output_delay, on page 510 for the equivalent Tcl
commands.

September 2016 299
The Registers SCOPE panel includes the following fields:
Field Description
Enabled (Required) Turn this on to enable the constraint.
Delay Type (Required) Specifies whether the delay is an input or output

delay.
Register (Required) Specifies the name of the register. If you have
initialized a compiled design, you can choose from the
pull-down list.
Route (Required) Improves the speed of the paths to or from the
register by the given number of nanoseconds. The value shrinks
the effective period for the constrained registers without
affecting the clock period that is forward-annotated to the
place-and-route tool.
Comment Lets you enter comments that are included in the constraints
file.
Delay Paths
Use the Delay Paths panel to define the timing exceptions.
LO

300 September 2016
The Path Delay panel includes the following options:
Field Description
Delay Type Specifies the type of delay path you want the synthesis tool to
analyze. Choose one of the following types:
Multicycle
False
Max Delay
Reset Path
Datapath Only
From Starting point for the path. From points define timing start
points and can be defined for clocks (c:), registers (i:), top-level
input or bi-directional ports (p:), or black box output pins (i:).
For details, see the following:
Defining From/To/Through Points for Timing Exceptions
Object Naming Syntax, on page 535
Through Specifies the intermediate points for the timing exception.
Intermediate points can be combinational nets (n:),
hierarchical ports (t:), or instantiated cell pins (t:). If you click
the arrow in a column cell, you open the Product of Sums (POS)
interface where you can set through constraints. For details, see
the following:
Product of Sums Interface
To Ending point of the path. To points must be timing end points
and can be defined for clocks (c:), registers (i:), top-level output
or bi-directional ports (p:), or black box input pins (i:). For
details, see the following:
Max Delay Specifies the maximum delay value for the specified path in
nanoseconds.

September 2016 301
Field Description
Setup Specifies the setup (maximum delay) calculations used for
specified path.
Start/End Used for multicycle paths with different start and end clocks.
This option determines the clock period to use for the
multiplicand in the calculation for clock distance. If you do not
specify a start or end clock, the end clock is the default.
Cycles Specifies the number of cycles required for the multicycle
path.
See Also
set_multicycle_path, on page 502
set_false_path, on page 494
set_max_delay, on page 499
reset_path, on page 481
set_datapathonly_delay, on page 534
For more information on timing exception constraints and how the tool
resolves conflicts, see:
Delay Path Timing Exceptions, on page 312
Conflict Resolution for Timing Exceptions, on page 325
LO

302 September 2016
Attributes
You can assign attributes directly in the editor.
Here are descriptions for the Attributes columns:
Column Description
Object Type Specifies the type of object to which the attribute is assigned.
Choose from the pull-down list, to filter the available choices
in the Object field.
Object (Required) Specifies the object to which the attribute is
attached. This field is synchronized with the Attribute field, so
selecting an object here filters the available choices in the
Attribute field.
Attribute (Required) Specifies the attribute name. You can choose from
a pull-down list that includes all available attributes for the
specified technology. This field is synchronized with the Object
field. If you select an object first, the attribute list is filtered. If
you select an attribute first, the Synopsys FPGA synthesis
tool filters the available choices in the Object field. You must
select an attribute before entering a value.
If a valid attribute does not appear in the pull-down list,
simply type it in this field and then apply appropriate values.
Value (Required) Specifies the attribute value. You must specify the
attribute first. Clicking in the column displays the default
value; a drop-down arrow lists available values where
appropriate.

September 2016 303
Val Type Specifies the kind of value for the attribute. For example,
string or boolean.
Description Contains a one-line description of the attribute.
Comment Lets you enter comments about the attributes.
Enter the appropriate attributes and their values, by clicking in a cell and
choosing from the pull-down menu.
To specify an object to which you want to assign an attribute, you may also
drag-and-drop it from the RTL or Technology view into a cell in the Object
column. After you have entered the attributes, save the constraint file and
add it to your project.
See Also
For more information on specifying attributes, see How Attributes and
Directives are Specified, on page 10.
I/O Standards
You can specify a standard I/O pad type to use in the design. Define an I/O
standard for any port appearing in the I/O Standards panel.
LO

304 September 2016
Field Description
Enabled (Required) Turn this on to enable the constraint, or off to
disable a previous constraint.
Port (Required) Specifies the name of the port. If you have
initialized a compiled design, you can select a port name from
the pull-down list. The first two entries let you specify global
input and output delays, which you can then override with
additional constraints on individual ports.
Type (Required) Specifies whether the delay is an input or output
delay.
I/O Standard Supported I/O standards by Synopsys FPGA products. See
Industry I/O Standards, on page 308 for a description of the
standards.
DCI (Xilinx) The values for these parameters are based on the selected
DV2 (Xilinx) I/O standard.
Slew Rate
Drive Strength
Termination
Power
Schmitt
Description Describes the selected I/O Standard.
Comment Enter comments about an I/O standard.
See Also
The Tcl equivalent of this constraint is define_io_standard.

September 2016 305
TCL View
The TCL View is an advanced text file editor for defining FPGA timing and
design constraints.
Click on Hide Syntax Help

to close this browser
This text editor provides the following capabilities:

Uses dynamic keyword expansion and tool tips for commands that
Automatically completes the command from a popup list
Displays complete command syntax as a tool tip
Displays parameter options for the command from a popup list
Includes a keyword command
LO syntax help

306 September 2016
Checks command syntax and uses color indicators that

Validate commands and command syntax
Identifies FPGA design constraints and SCOPE legacy constraints
Allows for standard editor commands, such as copy, paste,
comment/un-comment a group of lines, and highlighting of keywords
For information on how to use this Tcl text editor, see Using the TCL View of
SCOPE GUI, on page 661.
See Also
For Tcl timing constraint syntax, see FPGA Timing Constraints, on
page 474.
For Tcl design constraint syntax, see Chapter 11, FPGA Design
Constraint Syntax.
You can also use the SCOPE editor to set attributes. See How Attributes
and Directives are Specified, on page 10 for details.

September 2016 307
Chapter 6: SCOPE Constraints Editor Industry I/O Standards
Industry I/O Standards

The synthesis tool lets you specify a standard I/O pad type to use in your
design. You can define an I/O standard for any port supported from the
industry standard and proprietary I/O standards.
For industry I/O standards, see Industry I/O Standards, on page 309.
For vendor-specific I/O standards, see:

Altera I/O Standards, on page 602
Xilinx I/O Standards, on page 649
LO

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Industry I/O Standards Chapter 6: SCOPE Constraints Editor
Industry I/O Standards

The following table lists industry I/O standards.
I/O Standard Description

AGP1X Intel Corporation Accelerated Graphics Port
AGP2X Intel Corporation Accelerated Graphics Port
BLVDS_25 Bus Differential Transceiver
CTT Center Tap Terminated - EIA/JEDEC Standard JESD8-4
DIFF_HSTL_15_Class_I 1.5 volt - Differential High Speed Transceiver Logic
- EIA/JEDEC Standard JESD8-6
DIFF_HSTL_15_Class_II 1.5 volt - Differential High Speed Transceiver Logic
DIFF_HSTL_18_Class_I 1.8 volt - Differential High Speed Transceiver Logic
- EIA/JEDEC Standard JESD8-9A
DIFF_HSTL_18_Class_II 1.8 volt - Differential High Speed Transceiver Logic
- EIA/JEDEC Standard JESD8-9A
DIFF_SSTL_18_Class_II 1.8 volt - Differential Stub Series Terminated Logic
DIFF_SSTL_2_Class_I 2.5 volt - Pseudo Differential Stub Series
Terminated Logic - EIA/JEDEC Standard JESD8-9A
DIFF_SSTL_2_Class_II 2.5 volt - Pseudo Differential Stub Series
Terminated Logic - EIA/JEDEC Standard JESD8-9A
GTL Gunning Transceiver Logic
GTL+ Gunning Transceiver Logic Plus
GTL25 Gunning Transceiver Logic
GTL+25 Gunning Transceiver Logic Plus
GTL33 Gunning Transceiver Logic
GTL+33 Gunning Transceiver Logic Plus

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Chapter 6: SCOPE Constraints Editor Industry I/O Standards

HSTL_12 1.2 volt - High Speed Transceiver Logic
HSTL_15_Class_II 1.5 volt - High Speed Transceiver Logic
HSTL_18_Class_I 1.8 volt - High Speed Transceiver Logic
HSTL_18_Class_II 1.8 volt - High Speed Transceiver Logic
HSTL_18_Class_III 1.8 volt - High Speed Transceiver Logic
HSTL_18_Class_IV 1.8 volt - High Speed Transceiver Logic
HSTL_Class_I 1.5 volt - High Speed Transceiver Logic
HSTL_Class_II 1.5 volt - High Speed Transceiver Logic
HSTL_Class_III 1.5 volt - High Speed Transceiver Logic
HSTL_Class_IV 1.5 volt - High Speed Transceiver Logic
HyperTransport 2.5 volt - Hypertransport - HyperTransport Consortium
LO

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Industry I/O Standards Chapter 6: SCOPE Constraints Editor

LVCMOS_12 1.2 volt - EIA/JEDEC Standard JESD8-16
LVCMOS_33 3.3 volt CMOS - EIA/JEDEC Standard JESD8-B
LVCMOS_5 5.0 volt CMOS
LVDS Differential Transceiver - ANSI/TIA/EIA-644-95
LVDSEXT_25 Differential Transceiver
LVPECL Differential Transceiver - EIA/JEDEC Standard JESD8-2
LVTTL 3.3 volt TTL - EIA/JEDEC Standard JESD8-B
MINI_LVDS Mini Differential Transceiver
PCI33 3.3 volt PCI 33MHz - PCI Local Bus Spec. Rev. 3.0
(PCI Special Interest Group)
PCI66 3.3 volt PCI 66MHz - PCI Local Bus Spec. Rev. 3.0
PCI-X_133 3.3 volt PCI-X - PCI Local Bus Spec. Rev. 3.0
PCML 3.3 volt - PCML
PCML_12 1.2 volt - PCML
RSDS Reduced Swing Differential Signalling
SSTL_18_Class_I 1.8 volt - Stub Series Terminated Logic
SSTL_18_Class_II 1.8 volt - Stub Series Terminated Logic
- EIA/JEDEC Standard JESD8-9B
- EIA/JEDEC Standard JESD8-9B
ULVDS_25 Differential Transceiver

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Chapter 6: SCOPE Constraints Editor Delay Path Timing Exceptions
Delay Path Timing Exceptions

For details about the following path types, see:
Multicycle Paths, on page 312
False Paths, on page 315
Multicycle Paths
Multicycle paths lets you specify paths with multiple clock cycles. The
following table defines the parameters for this constraint. For the equivalent
Tcl constraints, see set_multicycle_path, on page 502. This section describes
the following:
Multi-cycle Path with Different Start and End Clocks, on page 312
Multicycle Path Examples, on page 313
Multi-cycle Path with Different Start and End Clocks

The start/end option determines the clock period to use for the multiplicand in
the calculation for required time. The following table describes the behavior of
the multi-cycle path constraint using different start and end clocks. In all
equations, n is number of clock cycles, and clock_distance is the default,
single-cycle relationship between clocks that is calculated by the tool.
Basic required time for a multi-cycle path clock_distance + [(n-1) * end_clock_period]

Required time with no end clock defined clock_distance + [(n-1) * global_period]
Required time with -start option defined clock_distance + [(n-1) * start_clock_period]
Required time with no start clock defined clock_distance + [(n-1) * global_period]
LO

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Delay Path Timing Exceptions Chapter 6: SCOPE Constraints Editor
If you do not specify a start or end option, by default the end clock is used for
the constraint. Here is an example:
Multicycle Path Examples
Multicycle Path Example 1

If you apply a multicycle path constraint from D1 to D2, the allowed time is
#cycles x normal time between D1 and D2. In the following figure, CLK1 has a
period of 10 ns. The data in this path has only one clock cycle before it must
reach D2. To allow more time for the signal to complete this path, add a
multiple-cycle constraint that specifies two clock cycles (10 x 2 or 20 ns) for
the data to reach D2.
required time required time

10 ns 20 ns
D1 Q1 D2 Q2 D1 Q1 D2 Q2
CLK1 CLK1
without constraint with multiple-cycle path=2
CLK1
0 10 20 30
Q1
D2
(without constraint)
D2
(multiple-cycle path=2)

September 2016 313
Multicycle Path Example 2

The design has a multiplier that multiplies signal_a with signal_b and puts the
result into signal_c. Assume that signal_a and signal_b are outputs of registers
register_a and register_b, respectively. The RTL view for this example is shown
below. On clock cycle 1, a state machine enables an input enable signal to
load signal_a into register_a and signal_b into register_b. At the beginning of clock
cycle 2, the multiply begins. After two clock cycles, the state machine enables
an output_enable signal on clock cycle 3 to load the result of the multiplication
(signal_c) into an output register (register_c).
The design frequency goal is 50 MHz (20 ns) and the multiply function takes
35 ns, but it is given 2 clock cycles. After optimization, this 35 ns path is
normally reported as a timing violation because it is more than the 20 ns
clock-cycle timing goal. To avoid reporting the paths as timing violations, use
the SCOPE window to set 2-cycle constraints (From column) on register_a and
register_b, or include the following in the timing constraint file:
# Paths from register_a use 2 clock cycles

set_multicycle_path -from register_a 2
# Paths from register_b use 2 clock cycles
set_multicycle_path -from register_b 2
Alternatively, you can specify a 2-cycle SCOPE constraint (To column) on

register_c, or add the following to the constraint file:
# Paths to register_cLO
use 2 clock cycles
set_multicycle_path -to register_c 2

314 September 2016
False Paths
You use the Delay Paths constraint to specify clock paths that you want the
synthesis tool to ignore during timing analysis and assign low (or no) priority
during optimization. The equivalent Tcl constraint is described in set_false_-
path, on page 494.
This section describes the following:

Types of False Paths, on page 315
Priority of False Path Constraints, on page 316
Types of False Paths

A false path is a path that is not important for timing analysis. There are two
types of false paths:
Architectural false paths
These are false paths that the designer is aware of, like an external reset
signal that feeds internal registers but which is synchronized with the
clock. The following example shows an architectural false path where
the primary input x is always 1, but which is not optimized because the
software does not optimize away primary inputs.
0 d 0
a 1 1
b + x + z
c 1
x x
Code-introduced false paths

These are false paths that you identify after analyzing the schematic.

September 2016 315
Priority of False Path Constraints

False path constraints can be either explicit or implicit, and the priority of the
constraint depends on the type of constraint it is.
An explicit false path constraint is one that you apply to a path using
the Delay Paths pane of the SCOPE GUI, or the following Tcl syntax:
set_false_path {-from point} | {-to point} | {-through point}
This type of false path constraint has the highest priority of any of the
types of constraints you can place on a path. Any path containing an
explicit false path constraint is ignored by the software, even if you place
a different type of constraint on the same path.
Lower-priority false path constraints are those that the software

automatically applies as a result of any of the following actions:
You assign clocks to different groups (Clocks pane of SCOPE GUI).
You assign an implicit false path (by selecting the false option in the
Delay (ns) column of the SCOPE Clock to Clock panel). (This condition
applies for legacy timing constraints.)
You disable the Use clock period for unconstrained IO option (Project ->
Implementation Options->Constraints).
Implicit false path constraints are overridden by any subsequent

constraints you place on a path. For example, if you assign two clocks to
different clock groups, then place a maximum delay constraint on a
path that goes through both clocks, the delay constraint has priority.
False Path Constraint Examples

In this example, the design frequency goal is 50 MHz (20ns) and the path
from register_a to register_c is a false path with a large delay of 35 ns. After
optimization, this 35 ns path is normally reported as a timing violation
because it is more than the 20 ns clock-cycle timing goal. To lower the
priority of this path during optimization, define it as a false path. You can do
this in many ways:
If all paths from register_a to any register or output pins are not
LOa false path constraint to register_a in the
timing-critical, then add
SCOPE interface (From), or put the following line in the timing constraint
file:

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#Paths from register_a are ignored

set_false_path -from {i:register_a}
If all paths to register_c are not timing-critical, then add a false path
constraint to register_c in the SCOPE interface (To), or include the
following line in the timing constraint file:
#Paths to register_c are ignored

set_false_path -to {i:register_c}
If only the paths between register_a and register_c are not timing-critical,
add a From/To constraint to the registers in the SCOPE interface (From
and To), or include the following line in the timing constraint file:
#Paths to register_c are ignored

set_false_path -from {i:register_a} -to {i:register_c}

September 2016 317
Chapter 6: SCOPE Constraints Editor Specifying From, To, and Through Points
Specifying From, To, and Through Points

The following section describes from, to, and through points for timing excep-
tions specified by the multicycle paths, false paths, and max delay paths
constraints.
Timing Exceptions Object Types, on page 318

From/To Points, on page 318
Through Points, on page 320
Product of Sums Interface, on page 321
Clocks as From/To Points, on page 323
Timing Exceptions Object Types

Timing exceptions must contain the type of object in the constraint specifica-
tion. You must explicitly specify an object type, n: for a net, or i: for an
instance, in the instance name parameter of all timing exceptions. For
example:
set_multicycle_path -from {i:inst2.lowreg_output[7]}

-to {i:inst1.DATA0[7]} 2
If you use the SCOPE GUI to specify timing exceptions, it automatically

attaches the object type qualifier to the object name.
From/To Points
From specifies the starting point for the timing exception. To specifies the
ending point for the timing exception. When you specify an object, use the
appropriate prefix (see syn_black_box, on page 37) to avoid confusion. The
following table lists the objects that can serve as starting and ending points:
From Points To Points

Clocks. See Clocks as From/To Points, Clocks. See Clocks as From/To Points,
LO on page 323 for more information.
Registers Registers

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From Points To Points

Top-level input or bi-directional ports Top-level output or bi-directional ports
Instantiated library primitive cells (gate Instantiated library primitive cells (gate
cells) cells)
Black box outputs Black box inputs
You can specify multiple from points in a single exception. This is most
common when specifying exceptions that apply to all the bits of a bus. For
example, you can specify constraints From A[0:15] to B in this case, there is an
exception, starting at any of the bits of A and ending on B.
Similarly, you can specify multiple to points in a single exception. If you

specify both multiple starting points and multiple ending points such as From
A[0:15] to B[0:15], there is actually an exception from any start point to any end
point. In this case, the exception applies to all 16 * 16 = 256 combinations of
start/end points.

September 2016 319
Through Points
Through points are limited to nets, hierarchical ports, and pins of instanti-
ated cells. There are many ways to specify these constraints.
Single Point
Single List of Points
Multiple Through Points
Multiple Through Lists
You define these constraints in the appropriate SCOPE panels, or in the POS
GUI (see Product of Sums Interface, on page 321). When a port and net have
the same name, preface the name of the through point with n: for nets, or t: for
hierarchical ports. For example n:regs_mem[2] or t:dmux.bdpol. The n: prefix
must be specified to identify nets; otherwise, the associated timing constraint
will not be applied for valid nets.
Single Point
You can specify a single through point. In this case, the constraint is applied to
any path that passes through net regs_mem[2]:
set_false_path -through n:regs_mem[2]

set_false_path -through [get_nets {regs_mem[2]}]
Single List of Points

If you specify a list of through points, the through option behaves as an OR
function and applies to any path that passes through any of the points in the
list. In the following example, the constraint is applied to any path through
regs_mem[2] OR prgcntr.pc[7] OR dmux.alub[0] with a maximum delay value of 5
ns (-max 5):
set_max_delay
-through {t:regs_mem[2] t:prgcntr.pc[7] t:dmux.alub[0]} 5
LO

320 September 2016
Multiple Through Points

You can specify multiple points for the same constraint by preceding each
point with the -through option. In the following example, the constraint
operates as an AND function and applies to paths through regs_mem[2] AND
prgcntr.pc[7] AND dmux.alub[0]:
set_max_delay
-through t:regs_mem[2]
-through t:prgcntr.pc[7]
-through t:dmux.alub[0] 5
Multiple Through Lists

If you specify multiple -through lists, the constraint is applied as an AND/OR
function and is applied to the paths through all points in the lists. The
following constraint applies to all paths that pass through nets {A1 or A2
or...An} AND nets {B1 or B2 or B3}:
set_false_path through {n:A1 n:A2...n:An} through {n:B1 n:B2 n:B3}
In this example,
set_multicycle_path
-through {n:net1 n:net2}
-through {n:net3 n:net4} 2
all paths that pass through the following nets are constrained at 2 clock
cycles:
net1 AND net3

OR net1 AND net4
OR net2 AND net3
OR net2 AND net4
Product of Sums Interface

You can use the SCOPE GUI to format -through points for nets with multicycle
path, false path, and max delay path constraints in the Product of Sums (POS)
interface of the SCOPE editor. You can also manually specify constraints that
use the -through option. For more information, see Defining From/To/Through
Points for Timing Exceptions, on page 666 in the User Guide.

September 2016 321
The POS interface is accessible by clicking the arrow in a Through column cell
in the following SCOPE panels:
Multi-Cycle Paths
False Paths
Delay Paths
Field Description
Prod 1, 2, etc. Type the first net name in a cell in a Prod row, or drag the
net from a HDL Analyst view into the cell. Repeat this
step along the same row, adding other nets in the Sum
columns. The nets in each row form an OR list.
Sum 1, 2, etc. Type the first net name in the first cell in a Sum column,
or drag the net from a HDL Analyst view into the cell.
Repeat this step down the same Sum column. The nets in
each column form an AND list.
Drag and Drop Goes Along Row - places objects in multiple Sum columns,
utilizing only one Prod row.
Down Column - places objects in multiple Prod rows, utilizing
only one Sum column.
Drag and Drop Inserts New Cells - New cells are created when dragging and
dropping nets.
Overwrites Cells - Existing cells are overwritten when
dragging LO
and dropping nets.
Save/Cancel Saves or cancels your session.

322 September 2016
Clocks as From/To Points

You can specify clocks as from/to points in your timing exception constraints.
Here is the syntax:
set_timing_exception -from | -to { c:clock_name [:edge] }
where
timing_exception is one of the following constraint types: multicycle path,
false path, or max delay
c:clock_name:edge is the name of the clock and clock edge (r or f). If you do
not specify a clock edge, by default both edges are used.
See the following sections for details and examples on each timing exception.
Multicycle Path Clock Points

When you specify a clock as a from or to point, the multicycle path constraint
applies to all registers clocked by the specified clock.
The following constraint allows two clock periods for all paths from the rising
edge of the flip-flops clocked by clk1:
set_multicycle_path -from {c:clk1:r} 2
You cannot specify a clock as a through point. However, you can set a
constraint from or to a clock and through an object (net, pin, or hierarchical
port). The following constraint allows two clock periods for all paths to the
falling edge of the flip-flops clocked by clk1 and through bit 9 of the hierar-
chical net:
set_multicycle_path -to {c:clk1:f} -through (n:MYINST.mybus2[9]} 2

September 2016 323
False Path Clock Points

When you specify a clock as a from or to point, the false path constraint is set
on all registers clocked by the specified clock. False paths are ignored by the
timing analyzer. The following constraint disables all paths from the rising
edge of the flip-flops clocked by clk1:
set_false_path -from {c:clk1:r}
You cannot specify a clock as a through point. However, you can set a
constraint from or to a clock and through an object (net, pin, or hierarchical
port). The following constraint disables all paths to the falling edge of the
flip-flops clocked by clk1 and through bit 9 of the hierarchical net.
set_false_path -to {c:clk1:f} -through (n:MYINST.mybus2[9]}
Path Delay Clock Points

When you specify a clock as a from or to point for the path delay constraint,
the constraint is set on all paths of the registers clocked by the specified
clock. This constraint sets a max delay of 2 ns on all paths to the falling edge
of the flip-flops clocked by clk1:
set_max_delay -to {c:clk1:f} 2
You cannot specify a clock as a through point, but you can set a constraint
from or to a clock and through an object (net, pin, or hierarchical port). The
next constraint sets a max delay of 0.2 ns on all paths from the rising edge of
the flip-flops clocked by clk1 and through bit 9 of the hierarchical net:
set_max_delay -from {c:clk1:r} -through (n:MYINST.mybus2[9]} .2
LO

324 September 2016
Conflict Resolution for Timing Exceptions Chapter 6: SCOPE Constraints Editor
Conflict Resolution for Timing Exceptions

The term timing exceptions refers to the false path, max path delay, and multi-
cycle path timing constraints. When the tool encounters conflicts in the way
timing exceptions are specified through the constraint file, the software uses
a set priority to resolve these conflicts. Conflict resolution is categorized into
four levels, meaning that there are four different tiers at which conflicting
constraints can occur, with one being the highest. The table below summa-
rizes conflict resolution for constraints. The sections following the table
provide more details on how conflicts can occur and examples of how they are
resolved.
Conflict Constraint Conflict Priority For Details, see ..

Level
1 Different timing 1 False Path Conflicting Timing
exceptions set on the 2 Path Delay Exceptions, on
same object. page 326.
3 Multi-cycle Path
2 Timing exceptions of 1 From Same Constraint
the same constraint 2 To Type with Different
type, using different Semantics, on
semantics 3 Through page 327.
(from/to/through).
3 Timing exceptions of 1 Ports/Instances/Pins Same Constraint
the same constraint 2 Clocks and Semantics with
type using the same Different Objects,
semantic, but set on on page 328.
different objects.
4 Identical timing Tightest, or most Identical
constraints, except constricting constraint. Constraints with
constraint values differ. Different Values, on
page 328.
In addition to the four levels of conflict resolution for timing exceptions, there
are priorities for the way the tool handles multiple I/O delays set on the same
port and implicit and explicit false path constraints. For information on
resolving these types of conflicts, see Priority of Multiple I/O Constraints, on
page 342 and Priority of False Path Constraints, on page 316.

September 2016 325
Chapter 6: SCOPE Constraints Editor Conflict Resolution for Timing Exceptions
Conflicting Timing Exceptions

The first (and highest) level of resolution occurs when timing exceptions
false paths, max path delay, or multicycle path constraints conflict with
each other. The tool follows this priority for applying timing exceptions:
1. False Path
2. Path Delay
3. Multicycle Path
For example:
B
R2 C1=3 ns
A
C1
set_false_path -from {c:C1:r}

set_max_delay -from {i:A} -to {i:B} 10
set_multicycle_path -from {i:A} -to {i:B} 2
These constraints are conflicting because the path from A to B has three
different constraints set on it. When the tool encounters this type of conflict,
the false path constraint is honored. Because it has the highest priority of all
timing exceptions, set_false_path is applied and the other timing exceptions are
ignored.
LO

326 September 2016
Conflict Resolution for Timing Exceptions Chapter 6: SCOPE Constraints Editor
Same Constraint Type with Different Semantics

The second level of resolution occurs when conflicts between timing excep-
tions that are of the same constraint type, use different semantics
(from/to/through). The priority for these constraints is as follows:
1. From
2. To
3. Through
If there are two multicycle constraints set on the same path, one specifying a
from point and the other specifying a to point, the constraint using -from takes
precedence, as in the following example.
B
R2 C1=3 ns
A
C1
set_multicycle_path -from {i:A} 3

set_multicycle_path -to {i:B} 2
In this case, the tool uses:
set_multicycle_path -from {i:A} 3
The other constraint is ignored even though it sets a tighter constraint.

September 2016 327
Chapter 6: SCOPE Constraints Editor Conflict Resolution for Timing Exceptions
Same Constraint and Semantics with Different Objects

The third level resolves timing exceptions of the same constraint type that use
the same semantic, but are set on different objects. The priority for design
objects is as follows:
1. Ports/Instances/Pins
2. Clocks
If the same constraints are set on different objects, the tool ignores the
constraint set on the clock for that path.
set_multicycle_path -from {i:mac1.datax[0]} -start 4

set_multicycle_path -from {c:clk1:r} 2
In the example above, the tool uses the first constraint set on the instance
and ignores the constraint set on the clock from i:mac1.datax[0], even though
the clock constraint is tighter.
For details on how the tool prioritizes multiple I/O delays set on the same
port or implicit and explicit false path constraints, see Priority of False Path
Constraints, on page 316 and Priority of Multiple I/O Constraints, on
page 342.
Identical Constraints with Different Values

Where timing constraints are identical except for the constraint value, the
tightest or most constricting constraint takes precedence. In the following
example, the tool uses the constraint specifying two clock cycles:
set_multicycle_path -from {i:special_regs.trisa[7:0]} 2

set_multicycle_path -from {i:special_regs.trisa[7:0]} 3
LO

328 September 2016
SCOPE User Interface (Legacy) Chapter 6: SCOPE Constraints Editor
SCOPE User Interface (Legacy)

You can use the Legacy SCOPE editor for the SDC constraint files created
before release version G-2012.09. However, it is recommended that you
translate your SDC files to FDC files to enable the latest version of the SCOPE
editor and to utilize the enhanced timing constraint handling in the tool. The
latest version of the SCOPE editor automatically formats timing constraints
using Synopsys standard syntax (such as create_clock, and set_multicycle_path).
To do this, add your SDC constraint files to your project and run the following
at the command line:
% sdc2fdc
This feature translates all SDC files in your project.
If you want to edit an existing SDC file using the legacy SCOPE editor,
double-click on the constraint file in the Project view.
For the Tcl command syntax created by the Legacy SCOPE editor, see:
Synplify-Style Timing Constraints (Legacy), on page 513
FPGA Design Constraint Syntax, on page 539
How Attributes and Directives are Specified, on page 10

September 2016 329
Chapter 6: SCOPE Constraints Editor SCOPE User Interface (Legacy)
SCOPE Tabs (Legacy)

This section contains a description of the constraint panels in the SCOPE
interface, and details about the constraints you can enter that are saved to
an SDC file. SCOPE timing and design constraints include:
SCOPE Panel See...

Clocks Clocks (Legacy), on page 331
Clock to Clock Clock to Clock (Legacy), on

page 337
Collections Collections, on page 295
Inputs/Outputs Inputs/Outputs (Legacy), on

page 339
Registers Registers (Legacy), on page 343
Delay Paths Delay Paths (Legacy), on

page 344
Attributes Attributes, on page 303
I/O Standards I/O Standards, on page 304
Other Other (Legacy), on page 346
See Also:
For the Tcl constraint syntax, see Timing Constraint Summary (Legacy),
on page 331
For design constraints, see Chapter 11, FPGA Design Constraint Syntax.
LO

330 September 2016
Timing Constraint Summary (Legacy)

The following table shows the correlation between each SCOPE panel and the
Tcl constraint syntax it creates:
SCOPE Panel/GUI Tcl .sdc File

Clocks (Legacy) define_clock
Clock to Clock (Legacy) define_clock_delay
Delay Paths (Legacy) define_false_path
Delay Paths (Legacy) define_multicycle_path
Delay Paths (Legacy) define_path_delay
Inputs/Outputs (Legacy) define_input_delay
Inputs/Outputs (Legacy) define_output_delay
Registers (Legacy) define_reg_input_delay
Registers (Legacy) define_reg_output_delay
Frequency in the Project view set_option -frequency
Implementation Options -> Constraints Panel
Clocks (Legacy)
You use the Clocks panel of the SCOPE spreadsheet to define a signal as a
clock. The equivalent Tcl constraint is define_clock; its syntax is described in
define_clock, on page 514. For more information on using the Clocks panel,
see Defining Clocks, on page 694 of the User Guide.

September 2016 331
Clocks Panel Description

The Clocks panel includes the following fields:
SCOPE Cell Description

Enabled Turn this on to enable the constraint. Turn it off to disable
an existing constraint.
Clock Object (Required) Specifies the clock object name.
Clocks can be defined on the following objects:
Top-level input ports
Nets
Output pins of instantiated cells
Clocks cannot be defined on the following objects:
Top-level output ports
Input pins of instantiated gates
Pins of inferred instances
You can also assign a clock alias name to be used in the
timing reports. See the Clock Alias option, below.
For virtual clocks, the field must contain a unique name not
associated with any port or instance in the design.
Clock Alias Specifies a name for the clock if you want to use a name
other than the object name. This alias name is used in the
timing reports for the clock.
Frequency (MHz) (Required) Specifies the clock frequency in MHz. If you fill in
this field and click in the Period field, the Period value is filled
in automatically. For frequencies other than that implied by
the clock pin, refer to syn_reference_clock, on page 209.
Period (ns) (Required) Specifies the clock period in nanoseconds. If you
fill in this field and click in the Frequency field, the frequency
is filled in automatically.
Clock Group Assigns a clock to a clock group. Clocks in the same clock
group are related.
By default, the software assigns each clock to a group
called default_clkgroup_n, where n is a sequential number.
The Synplify synthesis tool calculates the relationship
between clocks in the same clock group and analyzes all
pathsLObetween them. Paths between clocks in different
groups are ignored (considered false paths).
See Clock Groups, on page 333 for more information.

332 September 2016

Rise At (ns) Specifies non-default rising and falling edges for clocks.By
Fall At (ns) default, the tool assumes that the clock is a 50% duty cycle
clock, with rising edge at 0 and falling edge at Period/2. See
Rise and Fall Constraints, on page 335 for details. Setting
rise/fall calculates the duty cycle automatically.
Duty Cycle (%) Specifies the clock duty cycle as a percentage of the clock
period. If you have a duty cycle that is not 50% (the default),
specify the rising and falling edge values (Rise At/Fall At)
instead of Duty Cycle, and the duty cycle value is calculated
automatically. There is no corresponding Tcl command
option.
Route (ns) Improves the path delays of registers controlled by the clock.
The value shrinks the effective period for synthesis, without
place-and-route tool. This is an advanced user option.
Before you use this option, evaluate the path delays on
individual registers in the optimization timing report and try
to improve the delays only on the registers that need them
(Registers panel).
See Route Option, on page 336 for a detailed explanation of
this option.
Virtual Clock Designates the specified clock as a virtual clock. It lets you
specify arrival and required times on top level ports that are
enabled by clocks external to the chip (or block) that you are
synthesizing. The clock name can be a unique name not
associated with any port or instance in the synthesized
design.
Comment Lets you enter comments that are included in the
constraints file.
Clock Groups
The timing engine uses clock groups to analyze and optimize the design. It
assumes that clocks in the same clock group are synchronized with each
other and treats them as related clocks. Typically, clocks in a clock group are
derived from the same base clock. The timing analyzer automatically calcu-
lates the relationships between the related clocks in a clock group and
analyzes all paths between them. For paths between clocks of the same
group, the timing engine calculates the time available based on the period of
the two clocks. If you want to override the calculation, set a clock delay on the
Clock to Clock tab (define_clock_delay).

September 2016 333
The waveforms in the following figure show how the synthesis tool determines
the worst posedge-to-posedge timing between clocks CLK1 and CLK2. All paths
that begin at CLK1 rising and end at CLK2 rising are constrained at 10 ns.
10ns 20ns 30ns
CLK1
0 15 30 45 60 75 90 105 120 135
CLK2
0 20 40 60 80 100 120 140
The following figure shows how the timing analyzer calculates worst case
edge-to-edge timing between all possible transitions of the two related clocks.
In this example, CLK1 has a period of 5 ns and CLK2 has a period of 10 ns.
Period = 5 ns
CLK1
r-r r-f f-r f-f
Period = 10 ns
CLK2
Conversely, clocks in different clock groups are considered unrelated or

asynchronous. Paths between clocks from different groups are automatically
marked as false paths and ignored during timing analysis and optimization.
By default, all clocks in a design are assigned to separate clock groups. For
most accurate results, re-assign clocks explicitly so that related clocks are in
the same group, using the Clock Group field in the SCOPE spreadsheet.
For example, if your design has three clocks (clk1, clk2, and clk3), by default
they are each assigned to different clock groups. If clk1 and clk3 are related,
assign them to the same clock group so that paths between the two clocks
are analyzed and optimized. For timing optimization, the software treats them
LO
as related clocks. Keep clk2 in a separate group, as it is unrelated to the other

334 September 2016
two clocks. The timing analyzer now only analyzes the relationship between
clk1 and clk3. Paths between clk1 and clk2, and paths between clk3 and clk2, are
considered false paths and are ignored.
Rise and Fall Constraints

The synthesis tool assumes an ideal clock network. By default, the
constraints assume a 50% duty cycle clock with the rising edge at 0 and the
falling edge at Period/2.
The synthesis tool computes relationships between the source clock and
destination clock on a path by using the Rise At and Fall At numbers. When
you enter or change these values, the Duty Cycle is calculated or recalculated
automatically. The timing engine can calculate the rise/fall values from the
Duty Cycle, but entering the rise/fall values directly is more accurate.
To understand how the relationships between source and destination clocks

are computed using the Rise At and Fall At values, consider the following
example.

September 2016 335
In this example:
CLK1 is a clock with a period of 10 ns (100 MHz) in clock group default_-
clkgroup_2. Since none of the other fields are specified, this is a 50% duty
cycle clock rising at 0 and falling at 5.
T= 0 5 10 15
CLK3 is a clock with a period of 20 ns (50 MHz) in clkgroup_2. This means

all paths between CLK3 and CLK1 are automatically treated as false
paths. In addition, CLK3 has a Rise At value of 0 and a Fall At value of 12,
which means it has a 60% duty cycle.
T= 0 12 20
CLK4 is a virtual clock. This means that there can be no port or instance
named CLK4 in this design. However, there may be top-level ports on the
chip which are clocked by CLK4 outside the chip. Input arrival times and
output required times for such ports can be specified relative to CLK4.
Check the Performance Summary for warnings about inferred clocks; an inferred
clock in the summary may mean a declared clock is missing. The Performance
Summary can also identify the alias names of derived clocks, for which timing
exceptions (false path, multicycle path, or path delay) that target the derived
clocks are needed.
Route Option
Use the Route (-route) option if you do not meet timing goals because the
routing delay after placement and routing exceeds the delay predicted by the
synthesis tool. The delay reported on an instance along a path from an input
port is the amount of time by which the clock frequency goal is exceeded
(positive slack), or not met (negative slack) because of the input delay. You
can view slack times in the timing
LO report section of the log file, or with the
HDL Analyst tool.

336 September 2016
Rerun synthesis with this option to include the actual route delay (from
place-and-route results) so that the tool can meet the required clock
frequency. Using the Route option is equivalent to putting a register delay
(define_reg_input_delay) on all registers controlled by that clock.
Assume the frequency goal is 50 MHz (clock period goal of 20.0 ns). If the
synthesis timing reports show the frequency goal is met, but the detailed
timing report from placement and routing shows that the actual clock period
is 21.8 ns because of paths through input_a, you can either tighten the
constraints in the place-and-route tool, or you can rerun synthesis with a
-route 1.8 option added to the define_input_delay constraint.
# In this example, input_a has a 10.0 ns input delay.

# Rerun synthesis with an added 1.8 ns constraint, to
# improve accuracy and match post-place-and-route results.
define_input_delay {input_a} 10.0 -route 1.8
Using this option adds 1.8 ns to the route calculations for paths to input_a and
improves timing by 1.8 ns.
Clock to Clock (Legacy)

Defines the time available from data signals on all paths between the speci-
fied clock edges; only specified clock edge combinations are affected. For
example, if you specify a new relationship for the rise-to-rise clock edge, other
relationships are not affected. By default, the software automatically calcu-
lates clock delay based on the clock parameters defined in the Clock pane of
the SCOPE UI. If you define a clock-to-clock constraint, this delay value
overrides any automatic calculations made by the software and is reflected in
the values shown in the Clock Relationships section of the timing report.
For the equivalent Tcl syntax, see define_clock_delay, on page 517.

September 2016 337
Note: Maintenance for the define_clock_delay command is limited. It is

recommended that you use the define_false_path and
define_path_delay commands instead, since these commands
support clock aliases.
This table provides brief descriptions of the fields shown above.
Delay Parameter Description

From Clock Edge Clock edge that triggers the event of the starting point:
clock_name, followed by a colon and the edge: (r for rising,
f for falling). For example, CLK1:r.
To Clock Edge Clock edge that triggers the event of the ending point:
clock_name:r or f (rise or fall). For example, CLK3:f
Delay (ns) Path delay in nanoseconds.

Alternatively, you can use the keyword false. When you use
the false keyword, the timing engine disables the delay field
and places an implicit false path constraint on the path. See
Defining False Paths, on page 671 in the User Guide for
details.
False Path You can enable the False Path checkbox to specify false
paths for all paths between two clock edges. Clocks that
you have assigned to different clock groups are unrelated,
which means the software treats any paths between them
as implicit false paths. You can use the constraint to
override the implicit false path for paths between clocks in
different clock groups.
LO

338 September 2016
The following is an example where a 5 ns delay constraint is placed on CLK4

rising to CLK3 rising, and an implicit false path constraint is placed on CLK3
rising to CLK2 falling.
clock delay
5 ns
D1 Q1 D2 Q2 D3 Q3
o
CLK4
CLK3
CLK2
CLK4
CLK3
0 10 20
Inputs/Outputs (Legacy)
This panel models the interface of the FPGA with the outside environment.
You use it to specify delays outside the device. The equivalent Tcl constraints
are define_input_delay, on page 521 and define_output_delay, on page 527.
The default delay outside an FPGA is 0.0 ns.
You can specify multiple constraints on the same I/O port. See Priority of
Multiple I/O Constraints, on page 342 for details.

September 2016 339
The SCOPE Inputs/Outputs fields are shown in the following table:
Field Description
Enabled (Required) Turn this on to enable the constraint, or off to
disable a previous constraint.
Port (Required) Specifies the name of the port. If you have
initialized a compiled design, you can select a port name from
the pull-down list. The first two entries let you specify global
input and output delays, which you can then override with
additional constraints on individual ports.
delay.
Clock Edge (Recommended) The rising or falling edge that controls the
event. The syntax for this field is the clock name, followed by a
colon and the edge: r for rising, f for falling. For example,
CLK1:r.
Value (Required) Specifies the delay value. You do not need this
value if you supply a Route value.
Route Improves the delay of the paths to and from the port. The
value shrinks the effective synthesis constraint without
affecting the constraint that is forward-annotated to the
place-and-route tool. This is an advanced user option. See
Route Option, on page 340 for details.
file.
Route Option
Use this option if you do not meet timing goals because the routing delay
after placement and routing exceeds the delay predicted by the Synopsys
FPGA synthesis tool. The delay reported on an instance along a path from an
input port is the amount of time by which the clock frequency goal is
exceeded (positive slack), or not met (negative slack) because of the input
delay. You can view slack times in the timing report section of the log file, or
using the HDL Analyst tool.
Rerun synthesis using this option, which includes the actual route delay
LO
(from place-and-route results) so that the tool can meet the required clock
frequency. Using the Route option is equivalent to putting a register delay
(define_reg_input_delay) on all registers controlled by that clock.

340 September 2016
Assume the frequency goal is 50 MHz (clock period goal of 20.0 ns). If the
synthesis timing reports show the frequency goal is met, but the detailed
timing report from placement and routing shows that the actual clock period
is 21.8 ns because of paths through input_a, you can either tighten the
constraints in the place-and-route tool, or you can rerun optimization after
entering 1.8 in the SCOPE Route column or adding the following define_in-
put_delay -route constraint to the constraint file:
# In this example, input_a has a 10.0 ns input delay.

# Rerun synthesis with an added 1.8 ns constraint, to
# improve accuracy and match post-place-and-route results.
define_input_delay {input_a} 10.0 -route 1.8
Using this option adds 1.8 ns to the route calculations for paths to input_a and
improves timing by 1.8 ns.

September 2016 341
Priority of Multiple I/O Constraints

You can specify multiple input and output delays (define_input_delay and
define_output_delay) constraints for the same I/O port. This is useful for cases
where a port is driven by or feeds multiple clocks. The priority of a constraint
and its use in your design is determined by a few factors:
The software applies the tightest constraint for a given clock edge, and
ignores all others. All applicable constraints are reported in the timing
report.
You can apply I/O constraints on three levels, with the most specific
overriding the more global:
Global (top-level netlist), for all inputs and outputs
Port-level, for the whole bus
Bit-level, for single bits
If there are two bit constraints and two port constraints, the two bit
constraints override the two port constraints for that bit. The other bits
get the two port constraints. For example, take the following constraints:
a[3:0]3 clk1:r
a[3:0]3 clk2:r
a[0]2 clk1:r
In this case, port a[0] only gets one constraint of 2 ns. Ports a[1], a[2], and
a[3] get two constraints of 3 ns each.
If at any given level (bit, port, global) there is a constraint with a refer-
ence clock specified, then any constraint without a reference clock is
ignored. In this example, the 1 ns constraint on port a[0] is ignored.
a[0]2 clk1:r
a[0]1
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342 September 2016
Registers (Legacy)
This panel lets the advanced user add delays to paths feeding into/out of
registers, in order to further constrain critical paths. You use this constraint
to speed up the paths feeding a register. See define_reg_input_delay, on
page 532, and define_reg_output_delay, on page 533 for the equivalent Tcl
commands.
The Registers SCOPE panel includes the following fields:
Field Description
Register (Required) Specifies the name of the register. If you have

initialized a compiled design, you can choose from the
pull-down list.
delay.
Route (Required) Improves the speed of the paths to or from the
register by the given number of nanoseconds. The value shrinks
the effective period for the constrained registers without
place-and-route tool. For an explanation of this advanced user
option, see Route Option, on page 340.
file.

September 2016 343
Delay Paths (Legacy)

Use the Delay Paths panel to specify the following timing exceptions:
Multicycle Paths Paths with multiple clock cycles.
False Paths Clock paths that you want the synthesis tool to ignore
during timing analysis and assign low (or no) priority during optimiza-
tion.
Max Delay Paths Point-to-point delay constraints for paths.
For more details on specifying these constraints, see Delay Path Timing
Exceptions, on page 312.
This table provides brief descriptions of the fields in the Delay Paths panel. You
can use any combination of from, to, and through points: fromthrough, from, from
throughto, and so on.

Delay Type Specify the type of delay path you want the synthesis tool to analyze.
Choose one of the following types:
Multicycle
False
Max Delay
From Starting point for the path. From points define timing start points and
can be clocks (c:), registers (i:), top-level input or bi-directional ports
(p:), or black box outputs (i:). For details, see the following:
syn_black_box, on page 37
LO
Defining From/To/Through Points for Timing Exceptions, on
page 666 in the User Guide

344 September 2016

To Ending point of the path. To points must be timing end points and
can be: clocks (c:), registers (i:), top-level output or bi-directional
ports (p:), or black box inputs (i:). For details, see the following:
Through Specifies the intermediate points for the timing exception.
Intermediate points can be combinational nets (n:), hierarchical ports
(t:), or instantiated cell pins (t:). If you click the arrow in a column cell,
you open the Product of Sums (POS) interface where you can set through
constraints. For details, see the following:
Product of Sums Interface, on page 321
Start/End Used for multi-cycle paths with different start and end clocks. This
option determines the clock period to use for the multiplicand in the
calculation for clock distance. If you do not specify a start or end
clock, the end clock is the default.
For further details, see Multi-cycle Path with Different Start and
End Clocks, on page 312 and Defining Multi-cycle Paths, on
Cycles Number of cycles for the required time calculated for the multi-cycle
path.
Max Delay Maximum delay value in nanoseconds.
(ns)
Comment Lets you enter comments that are included in the constraints file.

September 2016 345
Other (Legacy)
The Other panel is intended for advanced users to enter newly-supported
constraints. This panel contains the following fields
Field Description
Command (Required) Specifies a command that you want to pass to

the place-and-route tool.
Arguments (Required) Specifies arguments to the command.
Comment Lets you enter a comment about the commands that you
are passing to the place-and-route tool.
See Entering and Editing SCOPE Constraints (Legacy), on page 690 in the User
Guide for information.
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346 September 2016
CHAPTER 7
HDL Analyst Tool
The HDL Analyst tool helps you examine your design and synthesis results,
and analyze how you can improve design performance and area.
This chapter describes the HDL Analyst tool and the operations you can
perform with it.
HDL Analyst Views and Commands, on page 348
Schematic Objects and Their Display, on page 350
Basic Operations on Schematic Objects, on page 359
Multiple-sheet Schematics, on page 364
Exploring Design Hierarchy, on page 367
Filtering and Flattening Schematics, on page 374
For additional information, see descriptions of the HDL Analyst commands in
Chapter 3, User Interface Commands.

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Chapter 7: HDL Analyst Tool HDL Analyst Views and Commands
HDL Analyst Views and Commands

The HDL Analyst tool graphically displays information in the RTL schematic
view (see RTL View, on page 42 for information). The graphic representation is
useful for analyzing and debugging your design, because you can visualize
where coding changes or timing constraints might reduce area or increase
performance.
This section gives you information about the following:

Filtered and Unfiltered Schematic Views, on page 348
Accessing HDL Analyst Commands, on page 349
Filtered and Unfiltered Schematic Views

HDL Analyst views (RTL View, on page 42) consist of schematics that let you
analyze your design graphically. The schematics can be filtered or unfiltered.
The distinction is important because the kind of view determines how objects
are displayed for certain commands.
Unfiltered schematics display all the objects in your design, at appro-
priate hierarchical levels.
Filtered schematics show only a subset of the objects in your design,
because the other objects have been filtered out by some operation. The
Hierarchy Browser in the filtered view always list all the objects in the
design, not just the filtered objects. Some commands, such as HDL
Analyst->Show Context, are only available in filtered schematics. Views with
a filtered schematic have the word Filtered in the title bar.
Indicates a filtered schematic
Filtering commands affect only the displayed schematic, not the under-
LO description of filtering, see Filtering and
lying design. For a detailed
Flattening Schematics, on page 374. For procedures on using filtering,
see Filtering Schematics, on page 347 in the User Guide.

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HDL Analyst Views and Commands Chapter 7: HDL Analyst Tool
Accessing HDL Analyst Commands

You can access HDL Analyst commands in many ways, depending on the
active view, the currently selected objects, and other design context factors.
The software offers these alternatives to access the commands:
HDL Analyst and View menus
HDL Analyst popup menus appear when you right-click in an HDL
Analyst view. The popup menu is context-sensitive, and includes
commonly used commands from the HDL Analyst and View menus, as well
as some additional commands.
HDL Analyst toolbar icons provide shortcuts to commonly used
commands
For brevity, this document primarily refers to the menu method of accessing
the commands and does not list alternative access methods.
See also:
RTL View Popup Menus, on page 235
Project Toolbar, on page 59

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Chapter 7: HDL Analyst Tool Schematic Objects and Their Display
Schematic Objects and Their Display

Schematic objects are the objects that you manipulate in an HDL Analyst
schematic: instances, ports, and nets. Instances can be categorized in
different ways, depending on the operation: hidden/unhidden, trans-
parent/opaque, or primitive/hierarchical. The following topics describe
schematic objects and the display of associated information in more detail:
Object Information, on page 350
Sheet Connectors, on page 351
Primitive and Hierarchical Instances, on page 352
Hidden Hierarchical Instances, on page 354
Transparent and Opaque Display of Hierarchical Instances, on page 353
Schematic Display, on page 355
For most objects, you select them to perform operations. For some objects
like sheet connectors, you do not select them but right-click on them and
select from the popup menu commands.
Object Information
To obtain information about specific objects, you can view object properties
with the Properties command from the right-click popup menu, or place the
pointer over the object and view the object information displayed. With the
latter method, information about the object displays in these two places until
you move the pointer away:
The status bar at the bottom of the synthesis window displays the name
of the instance, net, port, or sheet connector and other relevant informa-
tion. Here is an example of the status bar information for a net:
Net clock (local net clock) Fanout=4

You can enable and disable the display of status bar information by
toggling the command View->Status Bar.
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350 September 2016
Schematic Objects and Their Display Chapter 7: HDL Analyst Tool
In a tooltip at the mouse pointer

Displays the name of the object and any attached attributes. The
following figure shows tooltip information for a state machine:
Mouse pointer
Tooltip
To disable tooltip display, select View -> Toolbars and disable the Show
Tooltips option. Do this if you want to reduce clutter.
See also
Pin and Pin Name Display for Opaque Objects, on page 356
HDL Analyst Options Command, on page 206
Sheet Connectors
Whenever the HDL Analyst tool divides a schematic into multiple sheets,
sheet connector symbols indicate how sheets are related. A sheet connector
differs from a port symbol by having an empty diamond or a hexagon with
sheet numbers at one end.
Ports
Diamond indicates sheet connector
If you enable the Show Sheet Connector Index option in the (Options->HDL Analyst
Options), the empty diamond becomes a hexagon with a list of the connected
sheets. You go to a connecting sheet by right-clicking a sheet connector and
choosing the sheet number from the popup menu. The menu has as many
sheet numbers as there are sheets connected to the net at that point.
Show Sheet Connector Index disabled Show Sheet Connector Index enabled

September 2016 351
See also
Primitive and Hierarchical Instances

HDL Analyst instances are either primitive or hierarchical, and sorted into
these categories in the Hierarchy Browser. Under Instances, the browser first
lists hierarchical instances, and then lists primitive instances under
Instances->Primitives.
Primitive Instances
Although some primitive objects have hierarchy, the term is used here to
distinguish these objects from user-defined hierarchies. Primitive instances
include the following:
Logic primitives, such as XOR gates
Technology-specific primitives, such as LUTs
Inferred ROMs, RAMs, and state machines
Black boxes
In a schematic, logic gate primitives are represented with standard schematic
symbols, and technology-specific primitives with various symbols (see
Hierarchy Browser Symbols, on page 45). You can push into primitives like
technology-specific primitives, inferred ROMs, and inferred state machines to
view internal details. You cannot push into logic primitives.
Hierarchical Instances
Hierarchical instances are user-defined hierarchies; all other instances are
considered primitive. Hierarchical instances correspond to Verilog modules
and VHDL entities.
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352 September 2016
The Hierarchy Browser lists hierarchical instances under Instances, and uses
this symbol: . In a schematic, the display of hierarchical instances
depends on the combination of the following:
Whether the instance is transparent or opaque. Transparent instances
show their internal details nested inside them; opaque instances do not.
You cannot directly control whether an object is transparent or opaque;
the views are automatically generated by certain commands. See Trans-
parent and Opaque Display of Hierarchical Instances, on page 353 for
details.
Whether the instance is hidden or not. This is user-controlled, and you
can hide instances so that they are ignored by certain commands. See
Hidden Hierarchical Instances, on page 354 for more information.
Transparent and Opaque Display of Hierarchical Instances

A hierarchical instance can be displayed transparently or opaquely. You
cannot directly control the display; certain commands cause instances to be
transparent. The distinction between transparent and opaque is important
because some commands operate differently on transparent and opaque
instances. For example, in a filtered schematic Flatten Current Schematic flattens
only transparent hierarchical instances.
Opaque instances are pale yellow boxes, and do not display their
internal hierarchy. This is the default display.
No nested logic
Transparent instances display some or all their lower-level hierarchy

nested inside a hollow box with a pale yellow border. Transparent
instances are only displayed in filtered schematics, and are a result of
certain commands. See Looking Inside Hierarchical Instances, on
page 372 for information about commands that generate transparent
instances.

September 2016 353
A transparent instance can contain other opaque or transparent

instances nested inside. The details inside a transparent instance are
independent schematic objects and you can operate on them
independently: select, push into, hide, and so on. Performing an opera-
tion on a transparent object does not automatically perform it on any of
the objects nested inside it, and conversely.
Nested opaque instance

Nested transparent instance
Transparent instance
See also
Looking Inside Hierarchical Instances, on page 372
Multiple Sheets for Transparent Instance Details, on page 366
Hidden Hierarchical Instances

Certain commands do not operate on the lower-level hierarchy of hidden
instances, so you can hide instances to focus the operation of a command
and improve performance. You hide opaque or transparent hierarchical
instances with the Hide Instances command (described in RTL View Popup
Menus, on page 235). Hiding and unhiding only affects the current HDL
Analyst view, and does not affect the Hierarchy Browser. You can hide and
unhide instances as needed. The hierarchical logic of a hidden instance is not
removed from the design; it is only excluded from certain operations.
The schematics indicate hidden hierarchical instances with a small H in the

lower left corner. When the mouse pointer is over a hidden instance, the
status bar and the tooltip indicate that the instance is hidden.
LO

354 September 2016
H indicates a
hidden Tooltip mentions
instance is hidden
Schematic Display
The HDL Analyst Options dialog box controls general properties for all HDL
Analyst views, and can determine the display of schematic object informa-
tion. Setting a display option affects all objects of the given type in all views.
Some schematic options only take effect in schematic windows opened after
the setting change; others affect existing schematic windows as well.
The following are some commonly used settings that affect the display of
schematic objects. See HDL Analyst Options Command, on page 206 for a
complete list of display options.
Option Controls the display of...

Show Cell Interior Internal logic of technology-specific primitives
Compress Buses Buses as bundles
Dissolve Levels Hierarchical levels in a view flattened with HDL Analyst

-> Dissolve Instances or Dissolve to Gates, by setting the
number of levels to dissolve.

September 2016 355
Option Controls the display of...

Instances Instances on a schematic by setting limits to the
Filtered Instances number of instances displayed
Instances added for
expansion
Instance Name Object labels
Show Conn Name
Show Symbol Name
Show Port Name
Show Pin Name Pin names. See Pin and Pin Name Display for
HDL Analyst->Show All Hier Opaque Objects, on page 356 and Pin and Pin
Pins Name Display for Transparent Objects, on
Pin and Pin Name Display for Opaque Objects

Although it always displays the pins, the software does not automatically
display pin names for opaque hierarchical instances, technology-specific
primitives, RAMS, ROMs, and state machines. To display pin names for these
objects, enable Options-> HDL Analyst Options->Text->Show Pin Name. The following
figures illustrate this display. The first figure shows pins and pin names of an
opaque hierarchical instance, and the second figure shows the pins of a
technology-specific primitive with its cell contents not displayed.
Tooltip with
Mouse pointer pin
Pins Pin
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356 September 2016
Pins and names
Mouse pointer
(pin symbol)
Pin and Pin Name Display for Transparent Objects

This section discusses pin name display for transparent hierarchical
instances in filtered views and technology-specific primitives.
Transparent Hierarchical Instances

In a filtered schematic, some of the pins on a transparent hierarchical
instance might not be displayed because of filtering. To display all the pins,
select the instance and select HDL Analyst -> Show All Hier Pins.
To display pin names for the instance, enable Options->HDL Analyst Options->Text
->Show Pin Name. The software temporarily displays the pin name when you
move the cursor over a pin. To keep the pin name displayed even after you
move the cursor away, select the pin. The name remains until you select
something else.
Primitives
To display pin names for technology primitives in the Technology view, enable
Options-> HDL Analyst Options->Text->Show Pin Name. The software displays the pin
names until the option is disabled. If Show Pin Name is enabled when Options->
HDL Analyst Options->General->Show Cell Interior is also enabled, the primitive is
treated like a transparent hierarchical instance, and primitive pin names are
only displayed when the cursor moves over the pins. To keep a pin name
displayed even after you move the cursor away, select the pin. The name
remains until you select something else.

September 2016 357
Pin selected,
showing name
See also:
Controlling the Amount of Logic on a Sheet, on page 364
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Basic Operations on Schematic Objects Chapter 7: HDL Analyst Tool
Basic Operations on Schematic Objects

Basic operations on schematic objects include the following:
Finding Schematic Objects, on page 359
Selecting and Unselecting Schematic Objects, on page 360
Crossprobing Objects, on page 361
For information about other operations on schematics and schematic objects,
see the following:
Exploring Design Hierarchy, on page 367
Finding Schematic Objects

You can use a Hierarchy Browser to browse and find schematic objects. This
can be a quick way to locate an object by name if you are familiar with the
design hierarchy.
You can also locate objects using the Edit->Find command, described in Find
Command (HDL Analyst), on page 88. For detailed procedures, see Finding
Objects, on page 327 in the User Guide. The Find command displays the Object
Query dialog box, which lists schematic objects by type (Instances, Symbols,
Nets, or Ports) and lets you use wildcards to find objects by name. You can
fine-tune your search by setting a range:
Entire Design (all levels at once)
Current Level & Below
Current Level Only

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Chapter 7: HDL Analyst Tool Basic Operations on Schematic Objects
All found objects are selected, whether or not they are displayed in the
current schematic. Although you can search for hidden instances, you
cannot find objects that are inside hidden instances at a lower level. Tempo-
rarily hiding an instance thus further refines the search range by excluding
the internals of a a given instance. This can be very useful when working with
transparent instances, because the lower-level details appear at the current
level, and cannot be excluded by choosing Current Level Only.
Edit->Find enhances filtering. Use Find to select by name and hierarchical level,
and then filter the design to limit the display to the current selection.
Unselected objects are removed. Because Find only adds to the current selec-
tion (it never deselects anything already selected), you can use successive
searches to build up exactly the selection you need, before filtering.
Conversely, filtering helps your search:

Filtering helps you to fine-tune the range of a search. You can search for
objects just within a filtered schematic (by limiting the search range to
the Current Level Only).
Filtering adds to the expressive power of displaying search results. You
can find objects on different sheets and filter them to see them all
together at once. Filtering collapses the hierarchy visually, showing
lower-level details nested inside transparent higher-level instances. The
resulting display combines the advantage of a high-level, abstract view
with detail-rich information from lower levels.
See Filtering and Flattening Schematics, on page 374 for further information.
Selecting and Unselecting Schematic Objects

Whenever an object is selected in one place it is selected and highlighted
everywhere else in the synthesis tool, including all Hierarchy Browsers, all
schematics, and the Text Editor. Many commands operate on the currently
selected objects, whether or not those objects are visible.
The following briefly list selection methods; for a concise table of selection
procedures, see Selecting Objects in the RTL View, on page 311in the User
Guide.
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360 September 2016
Using the Mouse to Select a Range of Schematic Objects

In a Hierarchy Browser, you can select a range of schematic objects by
clicking the name of an object at one end of the range, then holding the Shift
key while clicking the name of an object at the other end of the range.To use
the mouse for selecting and unselecting objects in a schematic, the
cross-hairs symbol ( ) must appear as the mouse pointer. If this is not
currently the case, right-click the schematic background.
Using Commands to Select Schematic Objects

You can select and deselect schematic objects using the commands in the
HDL Analyst menu, or use Edit->Find to find and select objects by name.
The HDL Analyst menu commands that affect selection include the following:
Expansion commands like Expand, Expand to Register/Port, Expand Paths,
and Expand Inwards select the objects that result from the expansion. This
means that (except for Expand to Register/Port) you can perform successive
expansions and expand the set of objects selected.
The Select All Schematic and Select All Sheet commands select all instances
or ports on the current schematic or sheet, respectively.
The Select Net Driver and Select Net Instances commands select the appro-
priate objects according to the hierarchical level you have chosen.
Deselect All deselects all objects in all HDL Analyst views.
See also
Finding Schematic Objects, on page 359
Crossprobing Objects
Crossprobing helps you diagnose where coding changes or timing constraints
might reduce area or increase performance. When you crossprobe, you select
an object in one place and it or its equivalent is automatically selected and
highlighted in other places. For example, selecting text in the Text Editor
automatically selects the corresponding logic in all HDL Analyst views.
Whenever a net is selected, it is highlighted through all the hierarchical
instances it traverses, at all schematic levels.

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Chapter 7: HDL Analyst Tool Basic Operations on Schematic Objects
Crossprobing Between Different Views

You can crossprobe objects (including logic inside hidden instances) between
RTL views, Technology views, the FSM Viewer, HDL source code files, and
other text files. Some RTL and source code objects are optimized away during
synthesis, so they cannot be crossprobed to certain views.
The following table summarizes crossprobing to and from HDL Analyst (RTL
and Technology) views. For information about crossprobing procedures, see
Cross Probing, on page 335 in the User Guide.
From . . . To . . . Do this . . .
Log file (Text HDL source Double-click a log file note, error, or warning. The
Editor) file (Text corresponding HDL source code appears in the
Editor) Text Editor.
Text Editor Analyst view The RTL view or Technology view must be open.
Select the code in the Text Editor that corresponds
FSM Viewer to the objects you want to crossprobe. You can
select a column of objects by pressing and holding
the Alt key while dragging through the objects. On
some platforms you need to use the key to which
the Alt functionality is mapped, such as Meta.
The object corresponding to the selected code is
automatically selected in the target view, if an
HDL source file is in the Text Editor. Otherwise,
choose Select in Analyst from the Text Editor popup
menu (available by right-clicking). (The Enhanced
Text Crossprobing option must be enabled to
crossprobe from text other than source code see
HDL Analyst Options Command, on page 206.)
FSM Viewer Analyst view The target view must be open. The state machine
must be encoded with the onehot style to
crossprobe from the transition table.
Select a state anywhere in the FSM Viewer (bubble
diagram or transition table). The corresponding
object is automatically selected in the HDL
Analyst view.
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362 September 2016
From . . . To . . . Do this . . .
Analyst view Text Editor Double-click an object. The source code
corresponding to the object is automatically
FSM Viewer selected in the Text Editor, which is opened to
show the selection.
If you just select an object, without
double-clicking it, the corresponding source code
is still selected and displayed in the editor
(provided it is open), but the editor window is not
raised to the front.
Analyst view another open Select an object in an HDL Analyst view. The
view object is automatically selected in all open views.
If the target view is the FSM Viewer, then the state
machine must be encoded as onehot.
Tcl window Text Editor Double-click an error or warning message
(available in the Tcl Messages window). The
corresponding source code is automatically
selected in the Text Editor, which is opened to
show the selection.

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Chapter 7: HDL Analyst Tool Multiple-sheet Schematics
Multiple-sheet Schematics
When there is too much logic to display on a single sheet, the HDL Analyst
tool uses additional schematic sheets. Large designs can take several sheets.
In a hierarchical schematic, each module consists of one or more sheets.
Sheet connector symbols (Sheet Connectors, on page 351) mark logic connec-
tions from one sheet to the next.
For more information, see

Navigating Among Schematic Sheets, on page 364
Multiple Sheets for Transparent Instance Details, on page 366
Controlling the Amount of Logic on a Sheet

You can control the amount of logic on a schematic sheet using the options in
Options->HDL Analyst Options->Sheet Size. The Maximum Instances option sets the
maximum number of instances on an unfiltered schematic sheet. The
Maximum Filtered Instances option sets the maximum number of instances
displayed at any given hierarchical level on a filtered schematic sheet.
See also:
Setting Schematic View Preferences, on page 315 of the User Guide.
Navigating Among Schematic Sheets

This section describes how to navigate among the sheets in a given
schematic. The window title bar lets you know where you are at any time.
Multisheet Orientation in the Title Bar

The window title bar of an RTL view or Technology view indicates the current
context. For example, uc_alu (of module alu) in the title indicates that the
LO
current schematic level displays the instance uc_alu (which is of module alu).
The objects shown are those comprising that instance.

364 September 2016
Multiple-sheet Schematics Chapter 7: HDL Analyst Tool
The title bar also indicates, for the current schematic, the number of the
displayed sheet, and the total number of sheets for example, sheet 2 of 4. A
schematic initially opens to its first sheet.
Sheet # of total # Context (level) of current sheet: instance name and module
Navigating Among Sheets

You can navigate among different sheets of a schematic in these ways:
Follow a sheet connector, by right-clicking it and choosing a connecting
sheet from the popup menu
Use the sheet navigation commands of the View menu: Next Sheet,
Previous Sheet, and View Sheets, or their keyboard shortcut or icon equiva-
lents
Use the history navigation commands of the View menu (Back and
Forward), or their keyboard shortcuts or icon equivalents to navigate to
sheets stored in the display history
For details, see Working with Multi-sheet Schematics, on page 313 in the User
Guide.
You can navigate among different design levels by pushing and popping the
design hierarchy. Doing so adds to the display history of the View menu, so
you can retrace your push/pop steps using View->Back and View->Forward.
After pushing down, you can either pop back up or use View->Back.

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Chapter 7: HDL Analyst Tool Multiple-sheet Schematics
See also:
Pushing and Popping Hierarchical Levels, on page 367
Multiple Sheets for Transparent Instance Details

The details of a transparent instance in a filtered view are drawn in two ways:
Generally, these interior details are spread out over multiple sheets at
the same schematic level (module) as the instance that contains them.
You navigate these sheets as usual, using the methods described in
Navigating Among Schematic Sheets, on page 364.
If the number of nested contents exceeds the limit set with the Filtered
Instances option (Options->HDL Analyst Options), the nested contents are
drawn on separate sheets. The parent hierarchical instance is empty,
with a notation (for example, Go to sheets 4-16) inside it, indicating which
sheets contain its lower-level details. You access the sheets containing
the lower-level details using the sheet navigation commands of the View
menu, such as Next Sheet.
See also:
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Exploring Design Hierarchy Chapter 7: HDL Analyst Tool
Exploring Design Hierarchy

The hierarchy in your design can be explored in different ways. The following
sections explain how to move between hierarchical levels:
Navigating With a Hierarchy Browser, on page 370
Looking Inside Hierarchical Instances, on page 372
Pushing and Popping Hierarchical Levels

You can navigate your design hierarchy by pushing down into a high-level
schematic object or popping back up. Pushing down into an object takes you
to a lower-level schematic that shows the internal logic of the object. Popping
up from a lower level brings you back to the parent higher-level object.
Pushing and popping is best suited for traversing the hierarchy of a specific
object. If you want a more general view of your design hierarchy, use the
Hierarchy Browser instead. See Navigating With a Hierarchy Browser, on
page 370 and Looking Inside Hierarchical Instances, on page 372 for other
ways of viewing design hierarchy.
Pushable Schematic Objects

To push into an instance, it must have hierarchy. You can push into the
object regardless of its position in the design hierarchy; for example, you can
push into the object if it is shown nested inside a transparent instance. You
can push down into the following kinds of schematic objects:
Non-hidden hierarchical instances. To push into a hidden instance,
unhide it first.
Technology-specific primitives (not logic primitives)
Inferred ROMs and state machines in RTL views. Inferred ROMs, RAMs,
and state machines do not appear in Technology views, because they are
resolved into technology-specific primitives.

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When you push/pop, the HDL Analyst window displays the appropriate level
of design hierarchy, except in the following cases:
When you push into an inferred state machine in an RTL view, the FSM
Viewer opens, with graphical information about the FSM. See the FSM
Viewer Window, on page 45, for more information.
When you push into an inferred ROM in an RTL view, the Text Editor
window opens and displays the ROM data table (rom.info file).
You can use the following indicators to determine whether you can push into
an object:
The mouse pointer shape when Push/Pop mode is enabled. See How to
Push and Pop Hierarchical Levels, on page 368 for details.
A small H symbol ( ) in the lower left corner indicates a hidden
instance, and you cannot push into it.
The Hierarchy Browser symbols indicates the type of instance and you
can use that to determine whether you can push into an object. For
example, hierarchical instance ( ), technology-specific primitive
( ), logic primitive such as XOR ( ), or other primitive instance
( ). The browser symbol does not indicate whether or not an instance
is hidden.
The status bar at the bottom of the main synthesis tool window reports
information about the object under the pointer, including whether or not
it is a hidden instance or a primitive.
How to Push and Pop Hierarchical Levels

You push/pop design levels with the HDL Analyst Push/Pop mode. To enable
or disable this mode, toggle View->Push/Pop Hierarchy, use the icon, or use the
appropriate mouse strokes.
LO

368 September 2016
Down (push) or up (pop) Pop

arrow mouse pointer
Push
Once Push/Pop mode is enabled, you push or pop as follows:

To pop, place the pointer in an empty area of the schematic background,
then click or use the appropriate mouse stroke. The background area
inside a transparent instance acts just like the background area outside
the instance.
To push into an object, place the mouse pointer over the object and click
or use the appropriate mouse stroke. To push into a transparent
instance, place the pointer over its pale yellow border, not its hollow
(white) interior. Pushing into an object nested inside a transparent
hierarchical instance descends to a lower level than pushing into the
enclosing transparent instance. In the following figure, pushing into
transparent instance inst2 descends one level; pushing into nested
instance inst2.II_3 descends two levels.
Push into transparent

instance along its border
Pop from background
(interior or exterior),
unless at top level
Push into nested

pushable object
Inside Outside

September 2016 369
The following arrow mouse pointers indicate status in Push/Pop mode. For
other indicators, see Pushable Schematic Objects, on page 367.
A down arrow Indicates that you can push (descend) into the object under
the pointer and view its details at the next lower level.
An up arrow Indicates that there is a hierarchical level above the current
sheet.
A crossed-out Indicates that there is no accessible hierarchy above or below
double arrow the current pointer position. If the pointer is over the
schematic background it indicates that the current level is the
top and you cannot pop higher. If the pointer is over an object,
the object is an object you cannot push into: a
non-hierarchical instance, a hidden hierarchical instance, or a
black box.
See also:
Using Mouse Strokes, on page 53
Navigating With a Hierarchy Browser

Hierarchy Browsers are designed for locating objects by browsing your
design. To move between design levels of a particular object, use Push/Pop
mode (see Pushing and Popping Hierarchical Levels, on page 367 and
Looking Inside Hierarchical Instances, on page 372 for other ways of viewing
design hierarchy).
The browser in the RTL view displays the hierarchy specified in the RTL
design description. The browser in the Technology view displays the
hierarchy of your design after technology mapping.
Selecting an object in the browser displays it in the schematic, because the

two are linked. Use the Hierarchy Browser to traverse your hierarchy and
select ports, nets, components, and submodules. The browser categorizes the
objects, and accompanies eachLO with a symbol that indicates the object type.
The following figure shows crossprobing between a schematic and the
hierarchy browser.

370 September 2016
Selecting an object in the browser causes

the schematic to display it also.
Explore the browser hierarchy by expanding or collapsing the categories in

the browser. You can also use the arrow keys (left, right, up, down) to move
up and down the hierarchy and select objects. To select more than one object,
press Ctrl and select the objects in the browser. To select a range of schematic
objects, click an object at one end of the range, then hold the Shift key while
clicking the name of an object at the other end of the range.
See also:
Crossprobing Objects, on page 361
Hierarchy Browser Popup Menu Commands, on page 236

September 2016 371
Looking Inside Hierarchical Instances

An alternative method of viewing design hierarchy is to examine transparent
hierarchical instances (see Navigating With a Hierarchy Browser, on page 370
and Navigating With a Hierarchy Browser, on page 370 for other ways of
viewing design hierarchy). A transparent instance appears as a hollow box
with a pale yellow border. Inside this border are transparent and opaque
objects from lower design levels.
Transparent instances provide design context. They show the lower-level logic
nested within the transparent instance at the current design level, while
pushing shows the same logic a level down. The following figure compares the
same lower-level logic viewed in a transparent instance and a push operation:
Pushing down to lower-level schematic:

The pushed instance itself is not shown at
the lower level; only its details are shown.
Dissolving:
The dissolved instance is shown transparently,
with its details nested inside it.
Same details
Transparent (dissolved)
instance
LO

372 September 2016
You cannot control the display of transparent instances directly. However,

you can perform the following operations, which result in the display of trans-
parent instances:
Hierarchically expand an object (using the expansion commands in the
HDL Analyst menu).
Dissolve selected hierarchical instances in a filtered schematic (HDL
Analyst -> Dissolve Instances).
Filter a schematic, after selecting multiple objects at more than one
level. See Commands That Result in Filtered Schematics, on page 374
for additional information.
These operations only make non-hidden hierarchical instances transparent.

You cannot dissolve hidden or primitive instances (including
technology-specific primitives). However, you can do the following:
Unhide hidden instances, then dissolve them.
Push down into technology-specific primitives to see their lower-level
details, and you can show the interiors of all technology-specific primi-
tives.
See also:

September 2016 373
Chapter 7: HDL Analyst Tool Filtering and Flattening Schematics
Filtering and Flattening Schematics

This section describes the HDL Analyst commands that result in filtered and
flattened schematics. It describes
Commands That Result in Filtered Schematics, on page 374
Successive Filtering Operations, on page 375
Returning to The Unfiltered Schematic, on page 375
Commands That Flatten Schematics, on page 376
Selective Flattening, on page 377
Filtering Compared to Flattening, on page 379
Commands That Result in Filtered Schematics

A filtered schematic shows a subset of your design. Any command that
results in a filtered schematic is a filtering command. Some commands, like
the Expand commands, increase the amount of logic displayed, but they are
still considered filtering commands because they result in a filtered view of
the design. Other commands like Filter Schematic and Isolate Paths remove
objects from the current display.
Filtering commands include the following:

Filter Schematic, Isolate Paths reduce the displayed logic.
Dissolve Instances (in a filtered schematic) makes selected instances
transparent.
Expand, Expand to Register/Port, Expand Paths, Expand Inwards, Select Net Driver,
Select Net Instances display logic connected to the current selection.
Show Critical Path, Flattened Critical Path, Hierarchical Critical Path show critical
paths.
All the filtering commands, except those that display critical paths, operate
on the currently selected schematic object(s). The critical path commands
operate on your entire design, regardless of what is currently selected.
LO
All the filtering commands except Isolate Paths are accessible from the HDL
Analyst menu; Isolate Paths is in the RTL view and Technology view popup
menus (along with most of the other commands above).

374 September 2016
Filtering and Flattening Schematics Chapter 7: HDL Analyst Tool
For information about filtering procedures, see Filtering Schematics, on

See also:
HDL Analyst Menu, on page 188 and RTL View Popup Menus, on
page 235
Successive Filtering Operations

Filtering operations are designed to be used in combination, successively.
You can, for example, perform a sequence of operations like the following:
1. Filter Schematic filter your design to examine a particular instance.
2. Expand expand from one of the output pins of the instance to add its
immediate successor cells to the display.
3. Select Net Driver add the net driver of a net connected to one of the
successors.
4. Isolate Paths filter to isolate the net driver instance, together with those
of its connecting paths that were already displayed.
Filtering operations add their resulting filtered schematics to the history of

schematic displays, so you can use the View menu Forward and Back
commands to switch between the filtered views. You can also combine
filtering with the search operation. See Finding Schematic Objects, on
Returning to The Unfiltered Schematic

A filtered schematic often loses the design context, as it is removed from the
display by filtering. After a series of multiple or complex filtering operations,
you might want to view the context of a selected object. You can do this by
Selecting a higher level object in the Hierarchy Browser; doing so always
crossprobes to the corresponding object in the original schematic.
Using Show Context to take you directly from a selected instance to the
corresponding context in the original, unfiltered schematic.

September 2016 375
Using Goto Net Driver to go from a selected net to the corresponding

context in the original, unfiltered schematic.
There is no Unfilter command. Use Show Context to see the unfiltered schematic
containing a given instance. Use View->Back to return to the previous, unfil-
tered display after filtering an unfiltered schematic. You can go back and
forth between the original, unfiltered design and the filtered schematics,
using the commands View->Back and Forward.
See also:
Commands That Flatten Schematics

A flattened schematic contains no hierarchical objects. Any command that
results in a flattened schematic is a flattening command. This includes the
following.
Command Unfiltered Schematic Filtered Schematic

Dissolve Instances Flattens selected instances --
Flatten Current Flattens at the current level Flattens only non-hidden

Schematic (Flatten and all lower levels. RTL view: transparent hierarchical
Schematic) flattens to generic logic level instances; opaque and hidden
Technology view: flattens to hierarchical instances are not
technology-cell level flattened.
RTL->Flattened Creates a new, unfiltered RTL schematic of the entire design,
View flattened to the level of generic logic cells.
Technology-> Creates a new, unfiltered Technology schematic of the entire
Flattened View design, flattened to the level of technology cells.
LO

376 September 2016

Technology-> Creates a new, unfiltered Technology schematic of the entire
Flattened to Gates design, flattened to the level of Boolean logic gates.
View
Technology-> Creates a filtered, flattened Technology view schematic that
Flattened Critical shows only the instances with the worst slack times and their
Path path.
Unflatten Schematic Undoes any flattening done by Dissolve Instances and Flatten
Current Schematic at the current schematic level. Returns to the
original schematic, as it was before flattening (and any
filtering).
All the commands are on the HDL Analyst menu except Unflatten Schematic,
which is available in a schematic popup menu.
The most versatile commands, are Dissolve Instances and Flatten Current
Schematic, which you can also use for selective flattening (Selective Flattening,
on page 377).
See also:
Filtering Compared to Flattening, on page 379
Selective Flattening
By default, flattening operations are not very selective. However, you can
selectively flatten particular instances with these commands:
Use Hide Instances to hide instances that you do not want to flatten, then
flatten the others (flattening operations do not recognize hidden
instances). After flattening, you can Unhide Instances that are hidden.
Flatten selected hierarchical instances using one of these commands:
If the current schematic is unfiltered, use Dissolve Instances.
If the schematic is filtered, use Dissolve Instances, followed by Flatten
Current Schematic. In a filtered schematic, Dissolve Instances makes the
selected instances transparent and Flatten Current Schematic flattens
only transparent instances.

September 2016 377
The Dissolve Instances and Flatten Current Schematic (or Flatten Schematic)
commands behave differently in filtered and unfiltered schematics as
outlined in the following table:

Dissolve Instances Flattens selected Provides virtual flattening: makes
instances selected instances transparent,
displaying their lower-level details.
Flatten Current Flattens everything Flattens only the non-hidden,
Schematic at the current level transparent hierarchical instances: does
Flatten Schematic and below not flatten opaque or hidden instances.
See below for details of the process.
In a filtered schematic, flattening with Flatten Current Schematic is actually a

two-step process:
1. The transparent instances of the schematic are flattened in the context

of the entire design. The result of this step is the entire hierarchical
design, with the transparent instances of the filtered schematic replaced
by their internal logic.
2. The original filtering is then restored: the design is refiltered to show

only the logic that was displayed before flattening.
Although the result displayed is that of Step 2, you can view the intermediate
result of Step 1 with View->Back. This is because the display history is erased
before flattening (Step 1), and the result of Step 1 is added to the history as if
you had viewed it.
See also:
LO

378 September 2016
Filtering Compared to Flattening

As a general rule, use filtering to examine your design, and flatten it only if
you really need it. Here are some reasons to use filtering instead of flattening:
Filtering before flattening is a more efficient use of computer time and
memory. Creating a new view where everything is flattened can take
considerable time and memory for a large design. You then filter anyway
to remove the flattened logic you do not need.
Filtering is selective. On the other hand, the default flattening operations
are global: the entire design is flattened from the current level down.
Similarly, the inverse operation (UnFlatten Schematic) unflattens every-
thing on the current schematic level.
Flattening operations eliminate the history for the current view: You can
not use View->Back after flattening. (You can, however, use UnFlatten
Schematic to regenerate the unflattened schematic.).
See also:

September 2016 379
LO

380 September 2016
CHAPTER 8
Utilities
This chapter describes some Synopsys FPGA tools and utilities that help
productivity and smooth out the design process. See the following individual
topics for information:
sdc2fdc Tcl Shell Command, on page 382
Synopsys FPGA Archive Utility, on page 388
Tcl synhooks Utility, on page 389
Altera qsf2sdc Utility, on page 392
Encryption Scripts, on page 396

September 2016 381
Chapter 8: Utilities sdc2fdc Tcl Shell Command
sdc2fdc Tcl Shell Command

The sdc2fdc Tcl shell command translates legacy FPGA timing constraints to
Synopsys FPGA timing constraints. From the Tcl command line in the
synthesis tool, the sdc2fdc command scans the input SDC files and attempts
to convert constraints for the implementation. For details, see:
sdc2fdc Tcl Shell Command, on page 382
Examples of sdc2fdc Translation, on page 382
FPGA Design Constraint (FDC) File, on page 383
Troubleshooting, on page 385
sdc2fdc Tcl Shell Command

From the Tcl command line, type:
sdc2fdc
Examples of sdc2fdc Translation

% sdc2fdc
INFO: Translation successful.
See:"D:/bugs/timing_88/clk_prior/scratch/FDC_constraints/rev_2/top_translated.fdc"
Replace your current *.sdc files with this one.
INFO: Automatically updating your project to reflect the new constraint file(s)
Do "Ctrl+S" to save the new settings.
% sdc2fdc
ERROR: Bad -from list for define_false_path: {my_inst}
Missing qualifier(s) (i: p: n: ...)
ERROR: Translation problems were found.
See:"D:/bugs/timing_88/clk_prior/scratch/FDC_constraints/rev_2/top_translate.log"
for details.
LO
_translate.log
ERROR: Bad -from list for define_false_path {my_inst}
Missing qualifier(s) (i: p: n: ...)

382 September 2016
sdc2fdc Tcl Shell Command Chapter 8: Utilities
"define_false_path -from {my_inst} -to i:abc.def.g_reg -through {n:bar}

Synplicity SDC source file: D:/bugs/timing_88/clk_prior/scratch/top.sdc.
Line number: 79
FPGA Design Constraint (FDC) File

FPGA Design Constraints (FDC) are input constraints for the FPGA synthesis
tool. The file format is migrating from legacy FPGA timing constraints (for
example, define_clock, define_input_delay, and define_false_path) to Synopsys SDC
Standard-compliant timing constraints (for example, create_clock, set_in-
put_delay, and set_false_path). FDC combines the FPGA design constraints (for
example, define_attribute, define_scope_collection, and define_io_standard) with the
Synopsys standard timing constraints.
The FDC constraint file is generated after running sdc2fdc that translates
legacy FPGA design constraints (SDC) to Synopsys FPGA design constraints
(FDC). This file is divided into two sections. The first section contains the
FPGA design constraints that are valid (for example, define_scope_collection and
define_attribute) and the legacy timing constraints that are not translated
because they were specified with -disable. The second section contains the
timing constraints that were translated into Synopsys SDC standard format.
This file also provides the following:
Each source sdc file has its separate subhead.
Each compile point is treated as a top level, so its sdc file has its own
_translated.fdc file.
The translator adds the naming rule, set_rtl_ff_names, so that the
synthesis tool knows these constraints are not from the Synopsys
Design Compiler.
The following example shows the contents of the FDC file.

#############################################################################
####This file contains constraints from Synplicity SDC files that have been
####translated into Synopsys FPGA Design Constraints (FDC.
####Translated FDC output file:
####D:/bugs/timing_88/clk_prior/scratch/FDC_constraints/rev_2/top_translated.fdc
####Source SDC files to the translation:
####D:/bugs/timing_88/clk_prior/scratch/top.sdc
#############################################################################
#############################################################################
####Source SDC file to the translation:
####D:/bugs/timing_88/clk_prior/scratch/top.sdc
#############################################################################

September 2016 383
#Legacy constraint file

#C:\Clean_Demos\Constraints_Training\top.sdc
#Written on Mon May 21 15:58:35 2012
#by Synplify Pro, Synplify Pro Scope Editor
#
#Collections
#
define_scope_collection all_grp {define_collection \
[find -inst {i:FirstStbcPhase}] \
[find -inst {i:NormDenom[6:0]}] \
[find -inst {i:NormNum[7:0]}] \
[find -inst {i:PhaseOut[9:0]}] \
[find -inst {i:PhaseOutOld[9:0]}] \
[find -inst {i:PhaseValidOut}] \
[find -inst {i:ProcessData}] \
[find -inst {i:Quadrant[1:0]}] \
[find -inst {i:State[2:0]}] \
}
#
#Clocks
#define_clock -disable -name {clkc} -virtual -freq 150 -clockgroup default_clkgroup_1
#Clock to Clock
#
#
#Inputs/Outputs
#
define_input_delay -disable {b[7:0]} 2.00 -ref clka:r
define_input_delay -disable {c[7:0]} 0.20 -ref clkb:r
define_input_delay -disable {d[7:0]} 0.30 -ref clkb:r
define_output_delay -disable {x[7:0]} -improve 0.00 -route 0.00
define_output_delay -disable {y[7:0]} -improve 0.00 -route 0.00
#
#Registers
#
#
#Multicycle Path
#
#
#False Path
#
#
define_false_path -disable -from {i:x[1]}
#
#Path Delay
#
#
#Attributes
#
define_io_standard -default_input -delay_type input syn_pad_type {LVCMOS_33}#
#I/O standards
#
#
#Compile Points
#
# LO
#Other Constraints

384 September 2016
#############################################################################
#SDC compliant constraints translated from Legacy Timing Constraints
#############################################################################
#
set_rtl_ff_names {#}
create_clock -name {clka} [get_ports {clka}] -period 10 -waveform {0 5.0}

create_clock -name {clkb} [get_ports {clkb}] -period 6.666666666666667
-waveform {0 3.3333333333333335}
set_input_delay -clock [get_clocks {clka}] -clock_fall -add_delay 0.000 [all_
inputs]
set_output_delay -clock [get_clocks {clka}] -add_delay 0.000 [all_outputs]
set_input_delay -clock [get_clocks {clka}] -add_delay 2.00 [get_ports {a[7:0]
}]
set_input_delay -clock [get_clocks {clka}] -add_delay 0 [get_ports {rst}]
set mcp 4
set_multicycle_path $mcp -start \
-from \
[get_ports \
{a* \
b*} \
] \
-to \
[find -seq -hier {q?[*]} ]
set_multicycle_path 3 -end \
-from \
[find -seq {*y*.q[*]} ]
set_clock_groups -name default_clkgroup_0 -asynchronous \
-group [get_clocks {clka dcm|clk0_derived_clock dcm|
clk2x_derived_clock dcm|clk0fx_derived_clock}]
set_clock_groups -name default_clkgroup_1 -asynchronous \
-group [get_clocks {clkb}]
Troubleshooting
The following table contains common types of error messages you might
encounter when running the sdc2fdc Tcl shell command. The error messages
include descriptions of how you can resolve these problems.
Problem and Solution Examples

Cannot translate a translated Remove/disable
file D:FDC_constraints/rev_FDC/top_translated.fdc
from the current implementation.
No active constraint files Add/enable one or more SDC constraint files.

September 2016 385
Clock not translated Add clock object qualifier (p: n: ...) for:
"define_clock -name {clka {clka} -period 10
-clockgroup {default_clkgroup_0}"
Synplicity_SDC source file:
D:.../clk_prior/scratch/top.sdc. Line number: 32
Specify -name for: "define_clock {p:clkb} -period 20
-clockgroup {default_clkgroup_1}"
Synplicity SDC source file:
Bad -from list for Missing qualifier(s) (i: p: n: ...)
define_multicycle_path {a* b*} "define_multicycle_path 4 -from {a* b*} -to
$fdc_cmd_0 -start" Synplicity SDC source file:
Bad -to list for Mixing of object types not permitted
define_multicycle_path "define_multicycle_path -to {i:*y*.q[*] p:ena} 3"
{i: *y* .q[*] p:ena} Synplicity SDC source file:
Bad -from list for Mixing of object types and missing qualifiers not
define_multicycle_path permitted "define_multicycle_path -from {i:*y*.q[*]
{i:*y* .q[*] p:ena enab} p:ena enab} 3" Synplicity SDC source file:
No period or frequency found Default 1000.
"create_clock -name {clkb} {p:clkb} -period 1000
-waveform {0 500.0}" Synplicity SDC source file:
Must specify both -rise and -fall "create_clock -name {clka} {p:clka} -period 10 -rise 5
or neither -clockgroup {default_clkgroup_0"
Synplicity SDC source file:
In addition to these error messages, make sure that your files have
read/write permissions set properly and there is sufficient disk space. Fix
any issues in the SDC source file and rerun the sdc2fdc command.
LO

386 September 2016
Batch Mode
If you run sdc2fdc -batch, then the following occurs:
The two Clock not translated messages in the table above are not
generated.
When the translation is successful, the SDC file is disabled and the FDC
file is enabled and saved automatically in the Project file.
However, if the -batch option is not used and the translation is successful,
then the SDC file is disabled and the FDC file is enabled but not automati-
cally saved in the Project file. A message is generated that states this condi-
tion in the Tcl shell window.

September 2016 387
Chapter 8: Utilities Synopsys FPGA Archive Utility
Synopsys FPGA Archive Utility

The archive utility provides a way to archive, extract, or copy your design
projects. An archive file is in Synopsys proprietary format developed by
Synplicity and is saved to a file name using the sar extension. You can also
use this utility to submit your design along with a request for technical
support.
The archive utility is available through the Project menu in the GUI or through
the project Tcl command. See the following for details:

Archiving, un-archiving, or Archiving Files and Projects, on page 126 in the
copying projects User Guide
Syntax for the associated Tcl project Tcl command in the Certify Command
commands Reference; -archive, -unarchive, and -copy options.
LO

388 September 2016
Tcl synhooks Utility Chapter 8: Utilities
Tcl synhooks Utility

The Tcl synhooks utility provides an advanced user with callbacks to
customize a design flow or integrate with other products. To enable these
callbacks, set the environment variable SYN_TCL_HOOKS to the location of the
Tcl hooks file(synhooks.tcl), then customize this file to get the desired customi-
zation behavior. For more information on creating scripts using synhooks.tcl,
see Automating Flows with synhooks.tcl, on page 292 in the User Guide.
Tcl Callback Syntax Function

proc syn_on_set_project_template Called when creating a new project.
{projectPath} {your default project settings} projectPath is the path name to the
project being created.
proc syn_on_new_project {projectPath} Called when creating a new project.
{ projectPath is the path name to the
your code project being created.
}
proc syn_on_open_project {projectPath} Called when opening a project.
}
proc syn_on_close_project {projectPath} Called after closing a project.
}
proc syn_on_start_application Called when starting the application.
{applicationName version currentDir} applicationName is the name of the
{ software. For example certify.
your code version is the name of the version of
} the software. For example 201003
currentDir is the name of the software
installation directory. For example
C:\fpga_tools\bin\certify.exe.
proc syn_on_exit_application Called when exiting the application.

{applicationName version} applicationName is the name of the
{ software. For example certify.
your code version is the name of the version of
} the software. For example 201003.

September 2016 389
Chapter 8: Utilities Tcl synhooks Utility
Tcl Callback Syntax Function

proc syn_on_start_run {runName Called when starting a run.
projectPath implementationName} runName is the name of the run. For
{ example compile or synthesis.
your code projectPath is the location of the
} project.
implementationName is the name of the
project implementation. For example,
rev_1.
proc syn_on_end_run {run_name Called at the end of a run.

project_path implementation_name} runName is the name of the run. For
{ example, compile or synthesis.
your code projectPath is the location of the
} project.
implementationName is the name of the
project implementation. For example,
rev_1.
proc syn_on_press_ctrl_F8 {} Called when Ctrl-F8 is pressed. See Tcl

{ Hook Command Example next.
your_code
}
proc syn_on_press_ctrl_F9 {} Called when Ctrl-F9 is pressed.
{
your_code
}
proc syn_on_press_ctrl_F8 {} Called when Ctrl-F11 is pressed.
{
your_code
}
Tcl Hook Command Example

Create a modifier key (ctrl-F8) to get all the selected files from a project browser
and project directory.
LO

390 September 2016
Tcl synhooks Utility Chapter 8: Utilities
set sel_files [get_selected_files]

while {[expr [llength $sel_files] > 0]} {
set file_name [lindex $sel_files 0]
puts $file_name
set sel_files [lrange $sel_files 1 end]
}

September 2016 391
Chapter 8: Utilities Altera qsf2sdc Utility
Altera qsf2sdc Utility

A standard logic synthesis flow requires that timing constraints be applied
during synthesis and any required physical constraints be applied during the
place-and-route stage. However, for a physical synthesis flow, logic synthesis
is combined with place-and-route. Therefore, a unified set of timing and
physical constraints is required.
Synopsys provides the qsf2sdc utility to facilitate the conversion of a Quartus

settings file (qsf) into a Synopsys FPGA sdc constraints file. Run the utility
from any shell window.
See the following for details:

QSF2SDC Syntax, on page 392
Supported QSF Constraints, on page 393
Example of Translated QSF Constraints, on page 394
QSF2SDC Syntax
Here is the syntax:
install_directory/bin/qsf2sdc -iqsf input_qsf_file -osdc output_sdc_file

[-oqsf output_residue_qsf_file] [-all] [-silent]
install_directory Defines the path of the directory containing the

Synplicity software
-iqsf Defines the input Quartus settings file (qsf)
-osdc Defines the output constraint file (sdc)
-oqsf Defines the residual constraints that cannot be

converted and must remain in a Quartus settings file
(qsf). This file is optional.
-all Converts any instances with location assignments. By
default, only pin location assignments and IO standards
are automatically converted.
-silent SuppressesLO all the successfully translated (#Supported)
and unsuccessfully translated (#Unsupported) messages
in the sdc file.

392 September 2016
Altera qsf2sdc Utility Chapter 8: Utilities
Assumptions
Keep in mind the following limitations:
Quartus constraints are specified completely on a single line without
spanning multiple lines.
Currently, only two Quartus constraints are translated by this utility:
See Supported QSF Constraints, on page 393 for more information.
Supported QSF Constraints

This section summarizes the two QSF constraints currently translated by the
qsf2sdc script, pin location and I/O standards.
Pin Location Constraints

The QSF syntax for pin locations is as follows:
set_location_assignment -to pin pin_value
The following examples show QSF pin location syntax and their SDC equiva-
lents. See Example of Translated QSF Constraints, on page 394 for a file
example.
QSF Syntax SDC Syntax

set_location_assignment -to CLK define_attribute {CLK} syn_loc
PIN_P23 {PIN_P23}
set_location_assignment PIN_P23 define_attribute {CLK} syn_loc
-to CLK {PIN_P23}
set_location_assignment PIN_AA11 define_attribute {TXWRADDR[10]}
-to TXWRADDR[10] syn_loc {PIN_AA11}
set_location_assignment -to define_attribute {TXWRADDR[10]}
TXWRADDR[10] PIN_AA11 syn_loc {PIN_AA11}

September 2016 393
Chapter 8: Utilities Altera qsf2sdc Utility
I/O Standard Constraints

This is the QSF syntax for I/O standards:
set_instance_assignment -name IO_STANDARD -to instance_name

IO_STD_value
The following examples show QSF I/O standard constraints and their SDC
equivalents. See Example of Translated QSF Constraints, on page 394 for a
file example.
QSF Syntax SDC Syntax

set_instance_assignment -name define_attribute {CLK} syn_pad_type
IO_STANDARD -to CLK LVTTL {LVTTL}
set_instance_assignment -name define_attribute {CLK} syn_pad_type
IO_STANDARD LVTTL -to CLK {LVTTL}
set_instance_assignment -name define_attribute {TXWRADDR[10]}
IO_STANDARD -to TXWRADDR[10] syn_pad_type {LVTTL}
LVTTL
set_instance_assignment -name define_attribute {TXWRADDR[10]}
IO_STANDARD LVTTL -to syn_pad_type {LVTTL}
TXWRADDR[10]
Example of Translated QSF Constraints

The following example illustrates how the QSF constraints are translated.
Original QSF Constraint File

set_location_assignment -to TXWRADDR[10] PIN_AA11
set_location_assignment PIN_AA11 -to TXWRADDR[10]
set_location_assignment -to CLK PIN_P23
set_location_assignment PIN_P23 -to CLK
set_instance_assignment -name IO_STANDARD LVTTL -to TXWRADDR[10]
set_instance_assignment -name IO_STANDARD LVTTL -to CLK
set_instance_assignment -name IO_STANDARD -to CLK LVTTL
LO

394 September 2016
Altera qsf2sdc Utility Chapter 8: Utilities
Results for SDC Constraints

After you run the qsf2sdc utility, the sdc file contains these constraints:
define_attribute {TXWRADDR[10]} syn_loc {PIN_AA11}

#SUPPORTED# set_location_assignment -to TXWRADDR[10] PIN_AA11
define_attribute {TXWRADDR[10]} syn_loc {PIN_AA11}

#SUPPORTED# set_location_assignment PIN_AA11 -to TXWRADDR[10]
define_attribute {CLK} syn_loc {PIN_P23}

#SUPPORTED# set_location_assignment -to CLK PIN_P23
define_attribute {CLK} syn_loc {PIN_P23}

#SUPPORTED# set_location_assignment PIN_P23 -to CLK
define_attribute {TXWRADDR[10]} syn_pad_type {LVTTL}

#SUPPORTED# set_instance_assignment -name IO_STANDARD LVTTL -to
TXWRADDR[10]
define_attribute {CLK} syn_pad_type {LVTTL}

#SUPPORTED# set_instance_assignment -name IO_STANDARD LVTTL -to
CLK
define_attribute {CLK} syn_pad_type {LVTTL}

#SUPPORTED# set_instance_assignment -name IO_STANDARD -to CLK
LVTTL

September 2016 395
Chapter 8: Utilities Encryption Scripts
Encryption Scripts
Two Synopsys FPGA IP encryption methods are available to Synplify Pro and
Synplify Premier users:
IEEE 1735-2014
OpenIP
With either of these encryption methods, the IP vendor is able to encrypt and
control distribution of their IP from their own website. The synthesis user has
access from the synthesis tool to the IP that the vendor makes available for
download and evaluation within a synthesis design.
The two encryption methods are supported by two scripts:

The encryptP1735 Script, on page 397
The encryptIP Script, on page 402
Encryption and Decryption Methodologies

This section describes common encryption schemes. There are two major
classes of encryption/decryption algorithms: symmetric, and asymmetric.
Symmetric Encryption
With this kind of encryption, a special number is used as a key to
encrypt the files. The same key is used to decrypt the file, so you must
have access to the same key.
Source data Encrypted data
Examples of this kind of algorithm are

Data Encryption Standard (DES)
Triple DES or TDES or TDEA (Triple Data Encryption Algorithm),
LOtimes
which uses DES three
Advanced Encryption Standard (AES)

396 September 2016
Encryption Scripts Chapter 8: Utilities
Asymmetric Encryption
With this encryption scheme, you use different keys to encode and
decode data. The end user generates the keys and makes a public key to
everyone who needs it for encryption. The public key cannot be used for
decryption. The end user uses the private key to decrypt the data.
Examples of asymmetric encryption are DH (Diffie-Hellman) and RSA
(Rivest, Shamir, and Adelman).
Public key
Source data Encrypted data
Private key
The encryptP1735 Script

The encryptP1735 script is one of the Synopsys FPGA IP scripts that is
available to IP vendors who wish to provide evaluation IP to their synthesis
users. The script is a Perl script that allows IP vendors to encrypt modules or
components that can then be downloaded for evaluation or use by a
Synopsys FPGA user.
Syntax for Running encryptP1735

This is the syntax for running the encryptP1735 script:
encryptP1735
-i | input inputFileName
-o | output outputFileName
[-pk | public_keys keyFileName]
[-kv | key_version minKeyVersion]
[-kx | keyx symmetricEncryptionKeyInHexadecimalFormat]
[-om | output_method "{plaintext | blackbox | encrypted}"]
[-tier "{pro | premier}"]
[-sk | showkey]
[-v | verbose 0|1]
[-verilog]
[-vhdl]

September 2016 397
Script Command-Line Arguments

The following table provides additional detail on the encryptP1735 script
command-line arguments.
-i | input Specifies the input file; inputFileName is a non-encrypted HDL file

containing one or more encryption envelopes.
-o | output Specifies the encrypted file; outputFileName is the encrypted HDL
file from running the encryption script.
-pk | public_keys Specifies the public keys repository file. This file contains public
keys for various tools. If the encryption envelope contains a key
block with a particular keyowner and keyname, the public keys
file is searched by the script to find a public key to use during
key-block generation.
-kv | key_version Specifies the minimum encryption version required from the
Synplify software used to run the IP.
-kx | keyx Optional parameter. Specifies the symmetric encryption key in
hexadecimal format. If omitted, keys are randomly generated.
-om | Determines how the IP is treated in the output netlist after
output_method synthesis:
plaintext specifies that the IP is unencrypted in the synthesis
netlist.
blackbox specifies that the IP is treated as a black box (the IP is
not written), and only interface information is present in the
output netlist.
encrypted specifies that the output netlist for the IP will be
encrypted using the same session key as input.
See Output Methods for encryptIP, on page 405 for more
information.
-tier Specifies the minimum tool tier to be used for the encryption.
Acceptable values are pro and premier (a file encrypted with premier
can only be decrypted in Synplify Premier).
-sk | showkey When used, the encryption script displays the session key in use
(useful when random keys are used and the user wants to make a
note of the key being used).
-v | verbose Specifies that the encryption script is to be run in verbose mode
(displays more detailed messages) when set to 1.
LO

398 September 2016
Input Files
The encryptP1735 encryption script reads an HDL file containing one or more
encryption envelopes. Additionally it reads the keys repository file that
contains the public keys for the IP consumer tools.
Public Keys Repository File

The encryptP1735 encryption script requires public keys from the file specified
by the public_keys option. This file includes public keys for each of the tools
that require a key block in the encrypted file. The public keys file includes a
Synopsys synthesis tool public key; the file can be expanded by the user to
include public keys for other tools.
Pragmas Used in the encryptP1735 Script

The header blocks in the encryptP1735 script use the pragmas described in the
following table.
Pragma Keyword Description

begin Opens a new encryption envelope
end Closes an encryption envelope
begin_protected Opens a new decryption envelope
end_protected Closes a decryption envelope
author Identifies the author of an envelope
author_info Specifies additional author information
encoding Specifies the coding scheme for the encrypted data
data_keyowner Identifies the owner of the data encryption key
data_method Identifies the data encryption algorithm
data_keyname Specifies the name of the data encryption key
data_block Begins an encoded block of encrypted data
encrypt_agent Identifies the encryption service
encrypt_agent_info Specifies additional encryption-agent information

September 2016 399
Pragma Keyword Description

key_keyowner Identifies the owner of the key encryption key
key_method Specifies the key encryption algorithm
key_keyname Specifies the name of the key encryption key
key_public_key Specifies the public key for key encryption
key_block Begins an encoded block of key data
version IEEE 1735-2014 encryption version
Adding Multiple Keys

It may become necessary to add multiple keys to the RTL to support how
multiple vendors access to the same RTL. Multiple vendor access is done by
editing the Synopsys synthesis tool public key included in the
install/lib/keys.txt key file shown below:
// Use verilog pragma syntax in this file

`pragma protect version=1
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect key_keyowner="Synopsys", key_keyname="SYNP05_001",
key_method="rsa"
`pragma protect key_public_key
MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAybsQaMidiCHZyh14wbXn
UpP8lK+jJY5oLpGqDfSW5PMXBVp0WFd1d32onXEpRkwxEJLlK4RgS43d0FG2ZQ1l
irdimRKNnUtPxsrJzbMr74MQkwmG/X7SEe/lEqwK9Uk77cMEncLycI5yX4f/K9Q9
WS5nLD+Nh6BL7kwR0vSevfePC1fkOa1uC7b7Mwb1mcqCLBBRP9/eF0wUIoxVRzjA
+pJvORwhYtZEhnwvTblBJsnyneT1LfDi/D5WZoikTP/0KBiP87QHMSuVBydMA7J7
g6sxKB92hx2Dpv1ojds1Y5ywjxFxOAA93nFjmLsJq3i/P0lv5TmtnCYX3Wkryw4B
eQIDAQAB
// Add additional public keys below this line
// Add additional public keys above this line
`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cbc"
LO
// End of file

400 September 2016
The file is expanded to include public keys for other tools. Please add any
other key between the lines:

The following is an example of an expanded public keys file that contains

dummy keys with key_keyname ="DUMMY":
// Use verilog pragma syntax in this file

`pragma protect version=1
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect key_keyowner="Synopsys", key_keyname="SYNP05_001",
key_method="rsa"
MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAybsQaMidiCHZyh14wbXn
UpP8lK+jJY5oLpGqDfSW5PMXBVp0WFd1d32onXEpRkwxEJLlK4RgS43d0FG2ZQ1l
irdimRKNnUtPxsrJzbMr74MQkwmG/X7SEe/lEqwK9Uk77cMEncLycI5yX4f/K9Q9
WS5nLD+Nh6BL7kwR0vSevfePC1fkOa1uC7b7Mwb1mcqCLBBRP9/eF0wUIoxVRzjA
+pJvORwhYtZEhnwvTblBJsnyneT1LfDi/D5WZoikTP/0KBiP87QHMSuVBydMA7J7
g6sxKB92hx2Dpv1ojds1Y5ywjxFxOAA93nFjmLsJq3i/P0lv5TmtnCYX3Wkryw4B
eQIDAQAB
`pragma protect key_keyowner="Synopsys", key_keyname="DUMMY",
key_method="rsa"
AAAAAAAA
`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cbc"
// End of file
If you are using a partial file with all pragmas use model, the keyowner
entries also must be edited:

September 2016 401
`protect key_keyowner="Synopsys", key_keyname="SYNP05_001",

key_method="rsa", key_block
`protect key_keyowner=" Synopsys", key_keyname=" DUMMY",
key_method="rsa", key_block
`protect data_keyowner="ip-vendor-a", data_keyname="fpga-ip",
data_method="des-cbc"
Be sure to include the below and above entries within your RTL to be able to
generate the decryption envelope properly. It is very important that you follow
this process when using the partial file with all pragmas use model. If you are
using the full-file use model or partial file with minimal pragmas use model,
editing the RTL is unnecessary when adding additional keys to the default
public key to create expanded keys.
Note: The expanded key shown is only an example and is not intended
be used with the encryptP1735.pl script; the actual key must be
obtained from a valid EDA vendor and added to the keys.txt file.
Limitations
To use the encryptP1735.pl script on Windows, Perl must be installed. Several
commercial and free versions are available including from
http://www.perl.org/get.html.
However, the script works correctly on a Linux 64-bit platform.
The encryptIP Script

The encryptIP script is a Synopsys FPGA IP script that is provided to IP
vendors who wish to provide evaluation IP to synthesis users. The script is a
Perl script and lets the IP vendor encrypt modules or components that can be
downloaded for evaluation or use by the Synopsys FPGA user. You can
download the encryptIP Perl script from SolvNet. See the article published at:
https://solvnet.synopsys.com/retrieve/032343.html
For details, see the following:

LO
Syntax for Running encryptIP, on page 403
Output Methods for encryptIP, on page 405

402 September 2016
The encryptIP Script Run, on page 407

Pragmas Used in the encryptIP Script, on page 410 in the User Guide
Syntax for Running encryptIP

This is the syntax for running the encryptIP script:
encryptIP
-in | input inputFile
-out | output outputFileName
-c | cipher "{des-cbc | 3des-cbc |aes128-cbc |blowfish-cbc}"
-k | key symmetricEncryptionKeyInTextFormat
-kx | keyx symmetricEncryptionKeyInHexadecimalFormat
-bd | build_date ddmmmyyyy
-om | outputmethod "{plaintext | blackbox | persistent_key}"
-incv | includevendor vendorKeyBlock
-dkn | datakeyname sessionKeyName
-dko | datakeyowner sessionKeyOwner
-a | author dataAuthor
-v | verbose
The following table describes the parameters. You must specify all the param-
eters, except for the ones that are optional.
-in | input Names the input RTL file to be encrypted.
-out | output Names the output file generated after encryption.
-c | cipher Specifies the symmetric encryption cipher. See Encryption and

Decryption Methodologies, on page 396 for details. The key
length must match the algorithm being used, with each character
using 8 bits.
des-cbc specifies the Data Encryption Standard (DES); uses a
64-bit key.
3des-cbc specifies the Triple Data Encryption Standard (Triple
DES); uses a 192-bit key.
aes128-cbc specifies the Advanced Encryption Standard (AES
Rijndael); uses a 128-bit key.
blowfish-cbc specifies the Blowfish standard, and is used for
Lattice designs only.

September 2016 403
-k | key Specifies the symmetric data decryption key used to encode your
RTL data block. The key is in text format, and can be any string
(e.g. ABCDEFG).The exact length of the key depends on the data
method you use. In a future release, this key will be automatically
generated if you do not specify one.
-kx | keyx* Optional parameter. Specifies the symmetric encryption key in
hexadecimal format.
-bd | build_date Specifies a date (ddmmmyyyy). The IP only works in Synplicity
software released after the specified date. It is recommended that
you use a date in January 2008 or later. For example:16FEB2008.
This option lets you force users to use newer Synopsys FPGA
releases that contain more security features. Contact Synplicity if
you need help in deciding what build date to use.
-om | Determines how the IP is treated in the output after synthesis:
outputmethod plaintext specifies that the IP is unencrypted in the synthesis
netlist.
blackbox specifies that the IP is treated as a black box, and only
interface information is in the output.
persistent_key is the default setting. It is used for Lattice designs,
and re-encrypts the output after synthesis in accordance with
the OpenIP standard.
See Output Methods for encryptIP, on page 405 for more
information.
-incv | Optional parameter that specifies a key block for an EDA vendor,
includevendor so that IP can be read by the vendor tools. C
-dkn | Specifies a string that denotes your session key, that was used to
datakeyname encrypt your IP.
-dko | Optional parameter that names the owner of the session key. The
datakeyowner value can be any string.
-a | author Optional parameter that names the author of the session key. The
value can be any string.
-v | verbose Specifies that the script run in verbose mode.
LO

404 September 2016
Output Methods for encryptIP

You can control the level of IP protection in the synthesis output netlist by
specifying an output method when you encrypt your IP by running the
encryptIP script. For example, -om blackbox. The output method is included
in the encrypted key block of your encrypted RTL. The table below shows the
values for -om.
Output Method Description

blackbox With this method, you cannot run gate-level simulation on the
output netlist nor can you run physical synthesis or place and
route the IP. This is because the output netlist contains the IP
interface only and no IP contents. It only includes ports and
connections; there are no nets or instances shown inside the IP.
plaintext With this method, you can synthesize, run gate-level simulation,
place, route, and implement an FPGA on the board that includes
your IP. The output netlist contains your unencrypted IP, which
is completely readable.
persistent_key By default, the output is encrypted using the same session key
and cipher you used to encrypt your IP for the synthesis tools.

September 2016 405
The following figure shows how the synthesis tools work with each of the
three encryptIP output methods:
Blackbox Output Method
Plaintext Output Method Persistent_key Output Method
Effect of Output Method onLO

Viewing IP
In the synthesis tools, the contents of the IP are always shown as black
boxes, and you cannot view the contents. In the Technology view, you cannot
view the initialization values for the LUT.

406 September 2016
Effect of Output Method on Output Constraints

After synthesis, the output constraints generated for the IP are not encrypted,
regardless of the output method. They are always readable.
Effect of Output Method on Output Netlist

The following table summarizes how different output methods affect what is
output:
Method (-om) Output Netlist After Synthesis

blackbox The output netlist contains the IP interface only and no IP
content, and only includes IP ports and connections. The IPs are
treated as black boxes, and there are no nets or instances shown
inside the IP. This content applies to all netlist formats generated
for different vendors, whether it is HDL (vm or vhm), EDIF (edf or
edn), or vqm. For Lattice technologies, the netlist includes one
output EDIF file with IP blocks encrypted with the remainder of
the netlist readable; for Xilinx technologies, the netlist includes a
top-level unencrypted EDIF file plus a hierarchy of EDIF files
where the internals of the IP blocks are empty.
plaintext The output netlist contains your unencrypted IP, which is
completely readable (nothing is encrypted).
persistent_key The output netlist includes encrypted versions of the IP. For
Lattice designs, the tool generates one output netlist (EDIF or
HDL) that includes the encrypted IP blocks. The netlist is
readable, except for the IP block sections, which are encrypted.
For Xilinx designs, the netlist includes a top-level unencrypted
EDIF file plus a hierarchy of EDIF files where the internals of the
IP blocks are empty
In future releases, you will be able to specify IP rights at the time of encryp-
tion, which will determine how your IP can be viewed in the RTL and
Technology views.
The encryptIP Script Run

The following example explains the encryptIP script, in the order in which it
executes. For descriptions of the pragmas used in the encryptIP script, see
Pragmas Used in the encryptIP Script, on page 410.
1. For each RTL file, the script creates a data block using symmetric
algorithm and your own session key.

September 2016 407
You can use any of the CBC encryption modes listed in Syntax for
Running encryptIP, on page 403. The initialization vector is a constant,
and the block is encoded in base 64. The following excerpt uses the data
encryption key ABCDEFG:
%%% protect data_block

UWhcm3CPmGz27DXAWQZF8rY7hSsvLwedXiP59HYZHJfoMIMkJ0W+6H7vmJEXZ/
dTxnAgGB2YJCF7lsaZ6x6kRisdtBtIo8+0Glskcykt7FtpAjpz24cJ9hoSYMu
HCmG70dHDNzTHWjkwBs2fxo5S6559d3pW+SDutrvrsHntyvHYiqxUZPsGce
ZZQJpqQIpqo24uFCVHNSX/URvL47CUBWoKB2XEpyRv5Zgd1F52YjBLIpET
+kBEzutAorF5rD9eZSALSo0kvVb7MPXFxmfCF8wHwTnRtkPthNCMq0t3iCgf9EH
2. The script precedes the data block with a small data block header that
describes the data method:
%%% protect data_method=aes128-cbc

dTxnAgGB2YJCF7lsaZ6x6kRisdtBtIo8+0Glskcykt7FtpAjpz24cJ9hoSYMu
HCmG70dHDNzTHWjkwBs2fxo5S6559d3pW+SDutrvrsHntyvHYiqxUZPsGce
ZZQJpqQIpqo24uFCVHNSX/URvL47CUBWoKB2XEpyRv5Zgd1F52YjBLIpET
+kBEzutAorF5rD9eZSALSo0kvVb7MPXFxmfCF8wHwTnRtkPthNCMq0t3iCgf9EH
3. The script then prepares a key block for Synplify, which contains your
session key and Synplicity-specific directives. Note that the
data_decrypt_key is required.
output_method=blackbox (Your IP will be a black box in the output netlist)

data_decrypt_key=ABCDEFG (Session key you used to encrypt your data block)
See Output Methods for encryptIP, on page 405 for information about
output methods.
4. Use Synplify Public key (Synplicity has an executable that returns this
key) and RSA2048 asymmetric encryption to create a key block. Encode
it in base64.
%%% protect key_block

U9n263KwF7RWb8GSz7C+700tKshqQgTmb8UdRxISekIJDfonqfqzjzEQ+xQ4
wyh65wo6X56Jm+ClaVuZjgQKK0c4y47nyA1iWcuq1Nh6KeuUscxp+nL6yT9Am
+nv+c57jSCMG0QsFbRBAIhdlohQAbYbSIuFxdLFEFxW4znF3+YDAsMHeIs
1tqxKqhQzYQ2fGJdQz0NVRi1hFjx/RpGmoXmzvSTX2xsre+ZNDh3r9qvj37
QGwLH2erPt/iXcUVnlnPCOaV5z8M1YLrKY8ui7KBs/HhyP7L2mAMPQAFY3i
LO
DhycUcJ5sirBgKZycpkhP8jQ02yjTZMb7z9KyYTHrzDdA==

408 September 2016

+700tKshqQgTmb8UdRU9n263KwF7RWb8GSz7Cwo6X56Jm+ClxISekIJDfon
qfqzjzEQ+xQ4wyh657nyA1iWcuq1Nh6KeuUscxp+nL6yT9AaVuZjG0QsFb
RBAIhdlohQAbYbgQKK0c4y4m+nv+c57jSCMxW4znF3+YDAsMHeIs1tqx
KqhQzYQ2fGJdQz0NXmzvSTX2xsre+ZNVRi1hFjSIuFxdLFEFx/RpGmo9qvj
37QGwLH2erPt/iXcUVnlnPCO7KBs/HhyP7L2mAMPQAFY3iDhycUcJaV5z8MD
h3r1YLrKY8ui8jQ02yjTZMb7z9pkhPYTHrzDdAKy5sirBgKZyc==
5. The script adds a small key block header to each key block.
%%% protect key_keyowner=Synplicity

%%% protect key_keyname=SYNP05_001
6. Your final encrypted IP key and data blocks looks like this:
%%% protect protected_file 1.0

<optional unencrypted HDL>
%%% protect begin_protected
%%% protect key_keyowner=Synplicity
%%% protect key_keyname=SYNP05_001
wyh65wo6X56Jm+ClaVuZjgQKK0c4y47nyA1iWcuq1Nh6KeuUscxp+nL6yT9Am
+nv+c57jSCMG0QsFbRBAIhdlohQAbYbSIuFxdLFEFxW4znF3+YDAsMHeIs
1tqxKqhQzYQ2fGJdQz0NVRi1hFjx/RpGmoXmzvSTX2xsre+ZNDh3r9qvj37
QGwLH2erPt/iXcUVnlnPCOaV5z8M1YLrKY8ui7KBs/HhyP7L2mAMPQAFY3i
DhycUcJ5sirBgKZycpkhP8jQ02yjTZMb7z9KyYTHrzDdA==
<other key blocks>
%%% protect data_method=aes128-cbc
dTxnAgGB2YJCF7lsaZ6x6kRisdtBtIo8+0Gls/kcykt7FtpAjpz24cJ9ho
SYMuHCmG70dHDNzTHWjkwBs2fxo5S6559d3pW+SDutrvrsHntyv
HYiqxUZPsGceZZQJpqQIpqo24uFCVHNSX/URvL47CUBWoKB2XEpyRv5Zg

%%% protect end_protected
<optional unencrypted HDL>

September 2016 409
Pragmas Used in the encryptIP Script

The header blocks in the encryptIP script use the pragmas described in the
following tables. Note the following:
The %%% protect directive must be placed at the exact beginning of a line.
Exactly one white-space character must separate the %%% from the
command that follows
The following table describes the general pragmas used:
%%% protect protected_file 1.0 Line 1 of protected file
%%% protect begin_protected Begin protected section
%%% protect end_protected Ends protected section
%%% protect comment comment Single line plain-text comment

%%% protect begin_comment Begin block of plain-text comments
%%% protect end_comment End block of plain-text block comments
The following table describes the data block pragmas:
%%% protect author=string Arbitrary string

%%% protect data_method=string For all supported FPGA vendors, one of the
DES encryption methods described in Syntax
for Running encryptIP, on page 403.
%%% protect data_block Immediately precedes encrypted data block
The following table describes the key block pragmas:
%%% protect key_keyowner=string Arbitrary string

%%% protect key_keyname=string Name recognized by Synplify to select key
block
%%% protect key_method=string Encryption algorithm. Currently we support
rsa
w %%% protect key_block Immediately precedes encrypted data block
LO

410 September 2016

September 2016 411
LO

412 September 2016
CHAPTER 9
RAM and ROM Inference
This chapter provides guidelines and Verilog or VHDL examples for coding
RAMs for synthesis. It covers the following topics:
Guidelines and Support for RAM Inference, on page 414
Block RAM Examples, on page 416
LUTRAM Examples, on page 429
RAM with Control Signals Examples, on page 432
Distributed RAM Examples, on page 438
Asymmetric RAM Examples, on page 440
Byte-Enable RAM Examples, on page 446
Byte-Wide Write Enable RAM Examples, on page 449
Initial Values for RAMs, on page 458
RAM Instantiation with SYNCORE, on page 466
ROM Inference, on page 467

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Chapter 9: RAM and ROM Inference Guidelines and Support for RAM Inference
Guidelines and Support for RAM Inference

There are two methods to handle RAMs: instantiation and inference. Many
FPGA families provide technology-specific RAMs that you can instantiate in
your HDL source code. The software supports instantiation, but you can also
set up your source code so that it infers the RAMs. The following table sums
up the pros and cons of the two approaches.
Inference in Synthesis Instantiation

Advantages Advantages
Portable coding style Most efficient use of the RAM primitives
Automatic timing-driven synthesis of a specific technology
No additional tool dependencies Supports all kinds of RAMs
Limitations Limitations
Glue logic to implement the RAM might Source code is not portable because it is
result in a sub-optimal implementation technology-dependent
Can only infer synchronous RAMs Limited or no access to timing and area
No support for address wrapping data if the RAM is a black box
Pin name limitations means some pins Inter-tool access issues, if the RAM is a
are always active or inactive black box created with another tool
You must structure your source code correctly for the type of RAM you want
to infer. The following table lists the supported technology-specific RAMs that
can be generated by the synthesis tool.
RAM Type Altera Xilinx

Single Port x x
Dual Port x x
True Dual Port x x
Asymmetric x x
Byte Enable x
Byte-Wide Write Enable x x
LO
The following sections contain code examples for the various types of RAM
that you can infer:
2016 Synopsys, Inc. -C

re
tify Reference Manual
Guidelines and Support for RAM Inference Chapter 9: RAM and ROM Inference
Block RAM Examples, on page 416

LUTRAM Examples, on page 429
RAM with Control Signals Examples, on page 432
Distributed RAM Examples, on page 438
Asymmetric RAM Examples, on page 440
Byte-Enable RAM Examples, on page 446

September 2016 415
Chapter 9: RAM and ROM Inference Block RAM Examples
Block RAM Examples

The examples below show you how to define RAM in the RTL code so that the
synthesis tools can infer block RAM. See the following for details:
Block RAM Mode Examples, on page 416
Single-Port Block RAM Examples, on page 420
Dual-Port Block RAM Examples, on page 422
True Dual-Port RAM Examples, on page 425
For details about inferring block RAM, see Inferring RAMs, on page 441 in the
User Guide.
Block RAM Mode Examples

The coding style supports the enable and reset pins of the block RAM primi-
tive. The tool supports different write mode operations for single-port and
dual-port RAM. This section contains examples of how to specify the
supported block RAM output modes:
WRITE_FIRST Mode Example, on page 416
READ_FIRST Mode Example, on page 418
NO_CHANGE Mode Example, on page 419
WRITE_FIRST Mode Example

This example shows the WRITE_FIRST mode operation with active enable.
module v_rams_02a (clk, we, en, addr, di, dou);

input clk;
input we;
input en;
input [5:0] addr;
input [63:0] di;
output [63:0] dou;
reg [63:0] RAM [63:0];
reg [63:0] dou; LO

re
Block RAM Examples Chapter 9: RAM and ROM Inference
always @(posedge clk)

begin
if (en)
begin
if (we)
begin
RAM[addr] <= di;
dou <= di;
end
else
dou <= RAM[addr];
end
end
endmodule
if (en & we) mem[addr] <= data_in;
endmodule
The following figure shows the RTL view of a WRITE_FIRST mode RAM
with output registered. The Technology view shows that the RAM is
mapped to a block RAM.
RTL View

September 2016 417
READ_FIRST Mode Example

The following piece of code is an example of READ_FIRST mode with both
enable and reset, with reset taking precedence:
module ram_test(data_out, data_in, addr, clk, rst, en, we);

output [7:0]data_out;
input [7:0]data_in;
input [6:0]addr;
input clk, en, rst, we;
reg [7:0] mem [127:0] /* synthesis syn_ramstyle = "block_ram" */;
reg [7:0] data_out;
always@(posedge clk)
if(rst == 1)
data_out <= 0;
else begin
if(en) begin
data_out <= mem[addr];
end
end
if (en & we) mem[addr] <= data_in;
endmodule
The following figure shows the RTL view of a READ_FIRST RAM with
inferred enable and reset, with reset taking precedence. The Technology
view shows that the inferred RAM is mapped to a block RAM.
RTL View
LO

re
NO_CHANGE Mode Example

This NO_CHANGE mode example has neither enable nor reset. If you register
the read address and the output address, the software infers block RAM.
module ram_test(data_out, data_in, addr, clk, we);

output [7:0]data_out;
input [7:0]data_in;
input [6:0]addr;
input clk,we;
reg [7:0] mem [127:0] /* synthesis syn_ramstyle = "block_ram" */;
reg [7:0] data_out;
if(we == 1)
data_out <= data_out;
else
data_out <= mem[addr];
if (we) mem[addr] <= data_in;
endmodule
The next figure shows the RTL view of a NO_CHANGE RAM. The Technology
view shows that the RAM is mapped to block RAM.
RTL View

September 2016 419
Single-Port Block RAM Examples

This section describes the coding style required to infer single-port block
RAMs. For single-port RAM, the same address is used to index the write-to
and read-from RAM. See the following examples:
Single-Port Block RAM Examples, on page 420
Single-Port RAM with RAM Output Registered Examples, on page 421
Dual-Port Block RAM Examples, on page 422
Single-Port RAM with Read Address Registered Example

In these examples, the read address is registered, but the write address
(which is the same as the read address) is not registered. There is one clock
for the read address and the RAM.
Verilog Example: Read Address Registered

module ram_test(q, a, d, we, clk);
output [7:0] q;
input [7:0] d;
input [6:0] a;
input clk, we;
reg [6:0] read_add;
/* The array of an array register ("mem") from which the RAM is
inferred*/
reg [7:0] mem [127:0] ;
assign q = mem[read_add];
always @(posedge clk) begin
read_add <= a;
if(we)
/* Register RAM Data */
mem[a] <= d;
end
endmodule
VHDL Example: READ Address

LO Registered
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

re
entity ram_test is
port (d : in std_logic_vector(7 downto 0);
a : in std_logic_vector(6 downto 0);
we : in std_logic;
clk : in std_logic;
q : out std_logic_vector(7 downto 0) );
end ram_test;
architecture rtl of ram_test is
type mem_type is array (127 downto 0) of
std_logic_vector (7 downto 0);
signal mem: mem_type;
signal read_add : std_logic_vector(6 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
if (we = '1') then
mem(conv_integer(a)) <= d;
end if;
read_add <= a;
end if;
end process;
q <= mem(conv_integer(read_add));
end rtl ;
Single-Port RAM with RAM Output Registered Examples

In this example, the RAM output is registered, but the read and write
addresses are unregistered. The write address is the same as the read
address. There is one clock for the RAM and the output.
Verilog Example: Data Output Registered

output [7:0] q;
input [7:0] d;
input [6:0] a;
input clk, we;
/* The array of an array register ("mem") from which the RAM is
inferred */
reg [7:0] mem [127:0] ;
reg [7:0] q;

September 2016 421

q = mem[a];
if(we)
/* Register RAM Data */
mem[a] <= d;
end
endmodule
VHDL Example: Data Output Registered

library ieee;
entity ram_test is
port (d: in std_logic_vector(7 downto 0);
a: in integer range 127 downto 0;
we: in std_logic;
clk: in std_logic;
q: out std_logic_vector(7 downto 0) );
end ram_test;
architecture rtl of ram_test is
type mem_type is array (127 downto 0) of
std_logic_vector (7 downto 0);
signal mem: mem_type;
begin
process(clk)
begin
if (clk'event and clk='1') then
q <= mem(a);
if (we='1') then
mem(a) <= d;
end if;
end if;
end process;
end rtl;
Dual-Port Block RAM Examples

The following example or RTL
LOcode results in simple dual-port block RAMs
being implemented in supported technologies.

re
Verilog Example: Dual-Port RAM

This Verilog example has two read addresses, both of which are registered,
and one address for write (same as a read address), which is unregistered. It
has two outputs for the RAM, which are unregistered. There is one clock for
the RAM and the addresses.
module dualportram ( q1,q2,a1,a2,d,we,clk1) ;

output [7:0]q1,q2;
input [7:0] d;
input [6:0]a1,a2;
input clk1,we;
wire [7:0] q1;
reg [6:0] read_addr1,read_addr2;
reg[7:0] mem [127:0] /* synthesis syn_ramstyle = "no_rw_check" */;
assign q1 = mem [read_addr1];
assign q2 = mem[read_addr2];
always @ ( posedge clk1) begin
read_addr1 <= a1;
read_addr2 <= a2;
if (we)
mem[a2] <= d;
end
endmodule
VHDL Example: Dual-Port RAM

The following VHDL example is of READ_FIRST mode for a dual-port RAM:
Library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
use IEEE.std_logic_unsigned.all ;
entity Dual_Port_ReadFirst is
generic (data_width: integer :=4;
address_width: integer :=10);

September 2016 423
port (write_enable: in std_logic;

write_clk, read_clk: in std_logic;
data_in: in std_logic_vector (data_width-1 downto 0);
data_out: out std_logic_vector (data_width-1 downto 0);
write_address: in std_logic_vector (address_width-1 downto 0);
read_address: in std_logic_vector (address_width-1 downto 0)
);
end Dual_Port_ReadFirst;
architecture behavioral of Dual_Port_ReadFirst is
type memory is array (2**(address_width-1) downto 0) of
std_logic_vector (data_width-1 downto 0);
signal mem : memory;
signal reg_write_address : std_logic_vector (address_width-1 downto 0);
signal reg_write_enable: std_logic;
attribute syn_ramstyle : string;
attribute syn_ramstyle of mem : signal is "block_ram";
begin
register_enable_and_write_address:
process (write_clk,write_enable,write_address,data_in)
begin
if (rising_edge(write_clk)) then
reg_write_address <= write_address;
reg_write_enable <= write_enable;
end if;
end process;
write:
process (read_clk,write_enable,write_address,data_in)
begin
if (rising_edge(write_clk)) then
if (write_enable=1) then
mem(conv_integer(write_address))<=data_in;
end if;
end if;
end process;
read:
process (read_clk,write_enable,read_address,write_address)
begin
if (rising_edge(read_clk)) then
LO
if (reg_write_enable=1) and (read_address =
reg_write_address) then data_out <= "XXXX";

re
else
data_out<=mem(conv_integer(read_address));
end if;
end if;
end process;
end behavioral;
True Dual-Port RAM Examples

You must use a registered read address when you code the RAM or have
writes to one process. If you have writes to multiple processes, you must use
the syn_ramstyle attribute to infer the RAM.
There are two situations which can result in this error message:
"@E:MF216: ram.v(29)|Found NRAM mem_1[7:0] with multiple

processes"
An nram with two clocks and two write addresses has syn_ramstyle set to a
value of registers. The software cannot implement this, because there is a
physical FPGA limitation that does not allow registers with multiple
writes.
You have a registered output for an nram with two clocks and two write
addresses.
Verilog Example: True Dual-Port RAM

The following RTL example shows the recommended coding style for true
dual-port block RAM. It is a Verilog example where the tool infers true dual-
port RAM from a design with multiple writes:
module ram(data0, data1, waddr0, waddr1, we0,we1,

clk0, clk1, q0, q1);
parameter d_width = 8;
parameter addr_width = 8;
parameter mem_depth = 256;
input [d_width-1:0] data0, data1;
input [addr_width-1:0] waddr0, waddr1;
input we0, we1, clk0, clk1;
output [d_width-1:0] q0, q1;

September 2016 425
reg [addr_width-1:0] reg_addr0, reg_addr1;

reg [d_width-1:0] mem [mem_depth-1:0] /* synthesis
syn_ramstyle="no_rw_check" */;
assign q0 = mem[reg_addr0];
assign q1 = mem[reg_addr1];
always @(posedge clk0)
begin
reg_addr0 <= waddr0;
if (we0)
mem[waddr0] <= data0;
end
begin
reg_addr1 <= waddr1;
if (we1)
mem[waddr1] <= data1;
end
endmodule
RTL View
LO

re
VHDL Example: True Dual-Port RAM

The following RTL example shows the recommended coding style for true
dual-port block RAM. It is a VHDL example where the tool infers true dual-
port RAM from a design with multiple writes:
library ieee;
use ieee.numeric_std.all;
entity one is
generic (data_width : integer := 4;
address_width :integer := 5 );
port (data_a:in std_logic_vector(data_width-1 downto 0);
data_b:in std_logic_vector(data_width-1 downto 0);
addr_a:in std_logic_vector(address_width-1 downto 0);
addr_b:in std_logic_vector(address_width-1 downto 0);
wren_a:in std_logic;
wren_b:in std_logic;
clk:in std_logic;
q_a:out std_logic_vector(data_width-1 downto 0);
q_b:out std_logic_vector(data_width-1 downto 0) );
end one;
architecture rtl of one is
type mem_array is array(0 to 2**(address_width) -1) of
std_logic_vector(data_width-1 downto 0);
signal mem : mem_array;
attribute syn_ramstyle of mem : signal is "no_rw_check" ;
signal addr_a_reg : std_logic_vector(address_width-1 downto 0);
signal addr_b_reg : std_logic_vector(address_width-1 downto 0);
begin
WRITE_RAM : process (clk)
begin
if (wren_a = '1') then
mem(to_integer(unsigned(addr_a))) <= data_a;
end if;
if (wren_b='1') then
mem(to_integer(unsigned(addr_b))) <= data_b;
end if;
addr_a_reg <= addr_a;
addr_b_reg <= addr_b;

September 2016 427
end if;
end process WRITE_RAM;
q_a <= mem(to_integer(unsigned(addr_a_reg)));
q_b <= mem(to_integer(unsigned(addr_b_reg)));
end rtl;
Limitations to RAM Inference

RAM inference is only supported for synchronous RAMs.
LO

re
LUTRAM Examples Chapter 9: RAM and ROM Inference
LUTRAM Examples
The Altera technologies have LUTRAM memory components. MLAB (Memory
LAB) resources are configured as LUTRAM. MLABs can be configured as
single-port RAM or ROM, or simple dual-port RAM. LUTRAM writes occur on
the falling edge of the clock and can be configured to have synchronous or
asynchronous read.
The following are Verilog code examples that result in memories being
extracted and mapped to LUTRAM.
Synchronous Read Single-Port RAM, Unregistered Output, on page 429
Asynchronous Read Single-Port RAM, Unregistered Output, on page 430
Simple Synchronous Dual-Port RAM, Unregistered Output, on page 430
Simple Asynchronous Dual-Port RAM, Unregistered Output, on
page 431
See Inferring LUTRAMs, on page 390 in the User Guide for the procedure.
Synchronous Read Single-Port RAM, Unregistered Output

The following code implements a single-port LUTRAM:
//SPRAM, with registered address and unregistered output,

//synchronous read
module test (clk,we,addr,datain,dataout);
parameter data_width = 10;
input clk,we;
input [addr_width - 1 : 0] addr;
input [data_width - 1 : 0] datain;
output [data_width - 1 : 0] dataout;
reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0]
/* synthesis syn_ramstyle = "MLAB"*/;
reg [addr_width - 1 : 0] addr_reg;
always @ (posedge clk)begin
addr_reg <= addr;
if(we) mem[addr] <= datain;
end

September 2016 429
Chapter 9: RAM and ROM Inference LUTRAM Examples
assign dataout = mem[addr_reg];

endmodule
Asynchronous Read Single-Port RAM, Unregistered Output

The following code implements a single-port LUTRAM:
//SPRAM, with registered output, asynchronous read

module test (clk,we,addr,datain,dataout);
input clk,we;
input [addr_width - 1 : 0] addr;
input [data_width - 1 : 0] datain;
output [data_width - 1 : 0] dataout;
reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0]
always @ (posedge clk)
begin
if(we) mem[addr] <= datain;
end
assign dataout = mem[addr];
endmodule
Simple Synchronous Dual-Port RAM, Unregistered Output

The following code implements a simple dual-port LUTRAM:
//SDPRAM, with registered address and unregistered output

//synchronous read
module test(clk,we,wraddr,rdaddr,datain,dataout);
input clk,we;
input [data_width-1:0] datain;
input [addr_width-1: 0] wraddr,rdaddr;
LO dataout;
output [data_width-1:0]
reg [data_width-1:0] mem [(2**addr_width)-1:0]

re
LUTRAM Examples Chapter 9: RAM and ROM Inference
reg [addr_width-1: 0] rdaddr_reg;

initial $readmemb("mem64x10.ini",mem);
begin
if(we) mem[wraddr] <= datain;
end
begin
rdaddr_reg <= rdaddr;
end
assign dataout = mem[rdaddr_reg];
endmodule
Simple Asynchronous Dual-Port RAM, Unregistered Output

The following code implements a simple dual-port LUTRAM:
//SDPRAM, with registered output, asynchronous read

module test(clk,we,wraddr,rdaddr,datain,dataout);
input clk,we;
input [data_width-1:0] datain;
input [addr_width-1: 0] wraddr,rdaddr;
output [data_width-1:0] dataout;
reg [data_width-1:0] mem [(2**addr_width)-1:0]
begin
if(we) mem[wraddr] <= datain;
end
assign dataout = mem[rdaddr];
endmodule

September 2016 431
Chapter 9: RAM and ROM Inference RAM with Control Signals Examples
RAM with Control Signals Examples

Altera RAM blocks provide built-in functionality for control signals with
enable pins. The synthesis tool extracts control signals for single-port and
simple dual-port RAMs with a single common clock, and maps the logic to
dedicated RAM instead of registers. This avoids inferring extra logic, and
improves resource utilization and QOR. The control signals can be read
enables, write enables, and clock enables.
Here are examples that show how RAM with control signals are inferred:
Dual-Port RAM with Read Enable and Clock Enable, on page 432
Single-Port RAM with Clock Enable Controlling Read, on page 434
Dual-Port RAM with Read Enable, Write Enable, and Common Clock
Enable, on page 435
For details about inferring RAM with control signals, see Inferring RAM with
Control Signals, on page 392 in the User Guide.
Dual-Port RAM with Read Enable and Clock Enable

The following example shows code for a simple dual-port RAM in READ_-
FIRST mode with read enable and clock enable, and the altsyncram that is
inferred.
module test (addra,addrb,clka,din1a,out1a,we,re,ena0);

input [8:0] addra, addrb;
input clka;
input we,re,ena0;
input [17:0] din1a;
output reg [17:0] out1a;
reg [17:0] out1a_reg1;
reg [17:0] ram1 [511:0] ;
always @(posedge clka)
if (re)
out1a_reg1 <= ram1[addra[8:0]];
LO

re
RAM with Control Signals Examples Chapter 9: RAM and ROM Inference
//Write code Port A

always@(posedge clka)
begin
if (we)
ram1[addrb[8:0]] <= din1a;
end
begin
if (ena0)
out1a <= out1a_reg1;
end
endmodule

September 2016 433
Single-Port RAM with Clock Enable Controlling Read

The following example shows code for a single-port RAM in WRITE_FIRST
mode with a clock enable controlling the read operation. In this code, the
clock enable signal is mapped to the ena0 pin, and read enable is tied to 1.
module test (addra,clka,din1a,out1a,we,ena);

input [12:0] addra;
input clka;
input we,ena;
input [17:0] din1a;
output reg [17:0] out1a;
reg [12:0] addra_reg;
reg re_reg;
reg [17:0] ram1 [8191:0];
always@(posedge clka )
begin
if (ena)
out1a <= ram1[addra_reg[12:0]];
end
//Write code Port A
begin
if (we)
ram1[addra[12:0]] <= din1a;
end
begin
addra_reg <= addra;
end
endmodule
LO

re
Dual-Port RAM with Read Enable, Write Enable, and Common

Clock Enable
The following example shows code for a simple dual-port RAM with read
enable, write enable, and common clock enable:
module test (addra,addrb,clka,din1a,out1a,we,re,ena0);

parameter mem_depth = 4096;

September 2016 435
input [addr_width - 1:0] addra, addrb;

input clka;
input we,re,ena0;
input [data_width -1 :0] din1a;
output reg [data_width -1 :0] out1a;
reg [addr_width -1 :0] addra_reg;
reg re_reg;
reg [data_width -1:0] ram1 [mem_depth - 1:0] ;
if (re_reg & ena0)
out1a <= ram1[addra_reg[addr_width - 1:0]];
//Write code Port A
begin
if (we & ena0)
ram1[addrb[addr_width - 1:0]] <= din1a;
end
begin
if (ena0)
addra_reg <= addra;
end
begin
if (ena0)
re_reg <= re;
end
endmodule
LO

re

September 2016 437
Chapter 9: RAM and ROM Inference Distributed RAM Examples
Distributed RAM Examples

Here are some examples of distributed RAM with Xilinx technologies:
Single-Port Distributed RAM with Asynchronous Read Port, on page 438
Dual-Port Distributed RAM with One Write and Two Asynchronous
Reads, on page 438
For details about inferring distributed RAM, see Distributed RAM Inference,
on page 394 in the User Guide.
Single-Port Distributed RAM with Asynchronous Read Port

The tool implements a single-port distributed RAM with asynchronous read
port for the following code:

output reg [7:0] q;
input [7:0] d;
input [7:0] a;
input clk, we;
reg [7:0] mem [255:0] ;
if(we)
mem[a] <= d;
end
assign q = mem[a];
endmodule
Dual-Port Distributed RAM with One Write and Two

Asynchronous Reads
For the following code, the tool implements a dual-port distributed RAM with
one write and two asynchronous read ports:
module DP_Ram (ADDRA, ADDRB, data_in1, data_in2, CLK, WEA1,WEA2,

LO
data_out1, data_out2);
output[3:0] data_out1;
output[3:0] data_out2;
input [3:0] ADDRA;

re
Distributed RAM Examples Chapter 9: RAM and ROM Inference
input [3:0] ADDRB;

input [3:0] data_in1;
input [3:0] data_in2;
input CLK, WEA1, WEA2;
reg [3:0] mem [15:0];
always@(posedge CLK)
begin
if(WEA1)
mem[ADDRA] = data_in1;
end
assign data_out1 = mem[ADDRA];
assign data_out2 = mem[ADDRB];
endmodule

September 2016 439
Chapter 9: RAM and ROM Inference Asymmetric RAM Examples
Asymmetric RAM Examples

The synthesis tools provide support for RAM with asymmetric ports.
Asymmetric ports have different data width and address depth; these ports
are not interchangeable. The synthesis tool can infer a block RAM primitive
for the simple dual-port RAM.
Support is limited to specific coding styles of simple dual-port RAM shown in

the following examples:
Example 1 (Read Width > Write Width): Coding Style 1, on page 440
Example 1 (Read Width > Write Width): Coding Style 2, on page 441
Example 2 (Read Width < Write Width): Coding Style 1, on page 442
Example 2 (Read Width < Write Width): Coding Style 2, on page 443
Limitations for Asymmetric RAM Inference, on page 444
For details about inferring asymmetric RAM, see Inferring Asymmetric RAM,
Example 1 (Read Width > Write Width): Coding Style 1

The following Verilog and VHDL examples implement an asymmetric port
RAM where:
Port A is 16384x2-bit write-only
Port B is 8192x4-bit read-only
Write first mode has no control signals on address register with different
clocks. Enable is on the write port, but not the read port.
Example 1: Verilog Asymmetric RAM Coding Style 1
Example 1: VHDL Asymmetric RAM Coding Style 1
LO

re
Asymmetric RAM Examples Chapter 9: RAM and ROM Inference
The following example shows the RTL View for Coding Style 1:
RTL View
Example 1 (Read Width > Write Width): Coding Style 2

RAM where:
clocks. Enable is on the write port, but not the read port.

September 2016 441
RTL View
Example 2 (Read Width < Write Width): Coding Style 1

RAM where:
Port A is 256x8-bit read-only
Port B is 64x32-bit write-only
clocks
LO

re
Example2: VHDL Asymmetric RAM Coding Style 1

RTL View
Example 2 (Read Width < Write Width): Coding Style 2

RAM where:
READ_FIRST mode has enable on the read port with different clocks and
enables

The following VHDL example implements an asymmetric port RAM:
READ_FIRST mode has enable on the read port with different clocks and
enables

September 2016 443

RTL View
Limitations for Asymmetric RAM Inference

Limitations include the following:
Support is limited to simple dual-port RAM type coding style.
Memory accessibility for Read and Write ports must match exactly.
Ratio between Read and Write data widths are a power of two.
Ratio between port depths are a power of two.
Deeper/wider RAM descriptions with random initial values that require
multiple asymmetric RAM inference are not supported.
Altera-specific Limitations
Limitations specific for Altera designs include the following:
When a RAM has two different read write clocks and read and write
occurs from the same location, then the RAM output can be unknown
(x).
The enable signal is supported,
LO but the clear signal and initial values on
a Read address register are not supported.

re
Xilinx-specific Limitations
Limitations specific for Xilinx designs include in the following:
Control signals and initial values on a Read address register are not
supported.
Possible simulation mismatch when the RAM output is not registered in
WRITE_FIRST mode. Currently, the synthesis tool does not insert
bypass glue logic around the RAM to prevent a simulation mismatch
due to a READ_WRITE collision.

September 2016 445
Chapter 9: RAM and ROM Inference Byte-Enable RAM Examples
Byte-Enable RAM Examples

With Xilinx technologies, the synthesis tools infer byte-enable RAM. Instead
of using a single enable bit to write data serially to one location at a time, this
feature uses multiple enable signals to read or write data to multiple
locations in a block RAM simultaneously.
For details about inferring byte-enable RAM, see Inferring Byte-Enable RAM,
Byte-Enable RAM Examples

The following Verilog and VHDL examples automatically infer byte enable
pins and maps it to block RAM, for code that uses an if-else-if (mutually
exclusive) style:
Verilog Example
VHDL Example
Verilog Example
The following Verilog example infers a byte-enable RAM:
module test (clock,wren,rden,address,byteena,data,q);

input clock;
input wren;
input rden;
input [8:0] address;
input [3:0] byteena;
input [31:0] data;
output reg [31:0] q;
reg [31:0] mem [511:0]/* synthesis syn_ramstyle="block_ram"*/;
always @(posedge clock)
begin
if (wren)
begin
if (byteena[3])
mem[address][31:24] <= data[31:24];
else if (byteena[2])
LO

re
Byte-Enable RAM Examples Chapter 9: RAM and ROM Inference

end
end
always @(posedge clock)
begin
if (rden)
q <= mem[address];
end
endmodule
VHDL Example
The following VHDL example infers a byte-enable RAM:
library ieee;
use ieee.std_logic_arith.all;
entity test is
port (clock: in std_logic;
wren: in std_logic;
rden: in std_logic;
address : in std_logic_vector (8 downto 0);
byteena: in std_logic_vector (0 downto 0);
data: in std_logic_vector (7 downto 0);
q: out std_logic_vector (7 downto 0) );
end test;
architecture rtl of test is
type memory is array(0 to 127) of std_logic_vector(7 downto 0);
signal mem : memory := (others => (others => '0'));
attribute syn_ramstyle of mem : signal is "block_ram";
begin
mem_write : process (clock)
begin
if (clock'event and clock = '1') then
if (wren = '1') then
if (byteena(0) = '1') then
mem(conv_integer(address))(7 downto 0) <=

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Chapter 9: RAM and ROM Inference Byte-Enable RAM Examples
data(7 downto 0);

end if;
end if;
end if;
end process mem_write;
mem_read : process (clock)
begin
if (rden = '1') then
q <= mem(conv_integer(address));
end if;
end if;
end process mem_read;
end architecture rtl;
Limitations to RAM Inference

Limited support for byte enable RAM, with one enable per byte, up to a
maximum of four enables. For details, refer to Solvnet article 030578, on
byte enable RAM support.
LO

re
Byte-Wide Write Enable RAM Examples Chapter 9: RAM and ROM Inference
Byte-Wide Write Enable RAM Examples

The synthesis tool can infer byte-wide write enable RAM for single-port and
simple dual-port RAM. The tool maps the byte-wide write enable RAM to
block RAM for improved performance by merging the RAM and reducing its
area.
True dual-port RAMs with byte-wide enables cannot be implemented in block

RAM.
For details about inferring byte-wide write enable RAM, see Inferring Byte-
Wide Write Enable RAM, on page 404 in the User Guide.
See the following code examples:

Limitations, on page 457
Byte-Wide Write Enable RAM Examples

Verilog and VHDL code examples are provided for the following:
Example1: Simple Dual-port RAM, on page 449
Example 2: Simple Dual-port RAM (SystemVerilog Compatible), on
page 453
Example 3: Single-port Write First RAM, on page 453
Example1: Simple Dual-port RAM

A Verilog and VHDL example for simple dual-port RAM are provided:
Example 1A: Simple Dual-port RAM (Verilog)
Example 1B: Simple Dual-port RAM (VHDL)
Example 1A: Simple Dual-port RAM (Verilog)

The Verilog code in this example contains a 2-dimensional RAM with byte-
wide write enable.

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Chapter 9: RAM and ROM Inference Byte-Wide Write Enable RAM Examples
module test (clk,we,waddr,raddr, be,wdata,q);

input clk,we;
input [5:0] waddr,raddr;
input [3:0] be;
input [31:0] wdata;
reg [31:0] mem [63:0]

/* xsynthesis xsyn_ramstyle = "xblock_ram, xno_rw_check" */;
//reg [5:0] waddr_reg;
always @(posedge clk) //write process

begin
//waddr_reg <= waddr;

if (we)
begin
if (be[0])
mem[waddr][7:0] <= wdata[7:0];
if (be[1])
mem[waddr][15:8] <= wdata[15:8];
if (be[2])
mem[waddr][23:16] <= wdata[23:16];
if (be[3])
mem[waddr][31:24] <= wdata[31:24];
end
q[31 : 0] <= mem[raddr];
end
endmodule
Example 1B: Simple Dual-port RAM (VHDL)

The VHDL code in this example contains a 2-dimensional RAM with byte-
wide write enable.
-- Simple Dual-Port RAM with different read/write addresses and

--single read/write clock
-- and with a control for writing single bytes into the memory
--word; byte enable
library ieee;
LO
library work;
entity byte_enabled_simple_dual_port_ram is

re
generic (
ADDR_WIDTH : natural := 10;
BYTE_WIDTH : natural := 8;
BYTES : natural := 4);
port (
we, clk : in std_logic;
be : in std_logic_vector (BYTES - 1 downto 0);
wdata : in std_logic_vector(BYTE_WIDTH - 1 downto 0);
waddr : in integer range 0 to 2 ** ADDR_WIDTH -1 ;
raddr : in integer range 0 to 2 ** ADDR_WIDTH - 1;
q : out std_logic_vector(BYTES*BYTE_WIDTH-1 downto 0));
end byte_enabled_simple_dual_port_ram;
architecture rtl of byte_enabled_simple_dual_port_ram is

--Here is the two dimensional RAM array of a third dimensional
--"BYTE_WIDTH data
-- build up 2D array to hold the memory
type word_t is array (0 to BYTES-1) of
std_logic_vector(BYTE_WIDTH-1 downto 0);
type ram_t is array (0 to 2 ** ADDR_WIDTH - 1) of word_t;
-- delcare the RAM
signal ram : ram_t;
signal q_local : word_t;
begin -- rtl
-- Re-organize the read data from the RAM to match the output
unpack: for i in 0 to BYTES - 1 generate
q(BYTE_WIDTH*(i+1) - 1 downto BYTE_WIDTH*i) <= q_local(i);
end generate unpack;
process(clk)
begin
if(rising_edge(clk)) then
if(we = '1') then
if(be(0) = '1') then
ram(waddr)(0) <= wdata;
end if;
if be(1) = '1' then
end if;
if be(2) = '1' then
end if;
if be(3) = '1' then

September 2016 451

end if;
end if;
q_local <= ram(raddr);
end if;
end process;
end rtl;
For the examples above, the following single-port RAM are shown in the HDL
Analyst RTL view.
RTL View
LO

re
Example 2: Simple Dual-port RAM (SystemVerilog Compatible)

The following SystemVerilog code example is equivalent to Example 1 above,
except that it contains a 3-dimensional RAM with byte-wide write enable. For
3-dimensional RAM, make sure to enable the System Verilog switch on the
Verilog tab of the Implementation Options panel.
module ram_infer
(
input we, clk,
input [5:0] waddr, raddr, // address width = 6
input [3:0] be, // 4 bytes per word
input [31:0] wdata, // byte width = 8, 4 bytes per word
output reg [31:0] q // byte width = 8, 4 bytes per word
);
// use a multi-dimensional packed array
// to model individual bytes within the word
reg [3:0][7:0] ram[0:63];// # words = 1 << address width

begin
if(we)
begin
if(be[0]) ram[waddr][0] <= wdata[7:0];
end
q <= ram[raddr];
end
endmodule
Example 3: Single-port Write First RAM

A Verilog and VHDL code example is provided that contains a single-port
write first RAM with the byte enables written in the RTL code, for which the
active byte enables solely determine the read activity of the RAM. For this
type of RAM, you must register the byte enables for read in the RTL code.
Example 3A: Single-port Write First RAM (Verilog)
Example 3B: Single-port Write First RAM (VHDL)

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Example 3A: Single-port Write First RAM (Verilog)

The Verilog code in this example contains a single-port write first RAM with
byte enables.
module test (clk,we,address, be,wdata,q);

input clk,we;
input [8:0] address;
input [3:0] be;
input [31:0] wdata;
reg [31:0] mem [511:0]
/* synthesis syn_ramstyle = "block_ram, no_rw_check" */;
reg [8:0] address_reg;
reg [3:0] be_reg;
always @(posedge clk) //write process
begin
if (we)
begin
if (be[0])
mem[address][7:0] <= wdata[7:0];
if (be[1])
if (be[2])
if (be[3])
end
end
wire [31:0] mem_data_out;
assign mem_data_out = mem[address_reg];
always @(posedge clk) //read process
begin
address_reg <= address;
be_reg <= be;
if (be_reg[0] )
q[7 : 0] <= mem_data_out[7 : 0];
if (be_reg[1] )
q[15 : 8] <= mem_data_out[15 : 8];
if (be_reg[2] )
q[23 : 16] <= mem_data_out[23 : 16];
LO

re
if (be_reg[3] )
q[31 : 24] <= mem_data_out[31 : 24];
end //end of always
endmodule
Example 3B: Single-port Write First RAM (VHDL)

The VHDL code in this example contains a single-port write first RAM with
byte enables.
library ieee;
entity test is
port (
clock : in std_logic;
address : in std_logic_vector (8 downto 0);
byteena : in std_logic_vector (3 downto 0);
data : in std_logic_vector (31 downto 0);
q : out std_logic_vector (31 downto 0)
);
end test;
architecture rtl of test is

type memory is array(512 downto 0) of std_logic_vector
(31 downto 0);
signal mem : memory := (others => (others => '0'));
signal address_reg : std_logic_vector (8 downto 0);
signal byteena_reg : std_logic_vector (3 downto 0);

attribute syn_ramstyle of mem : signal is
"block_ram, no_rw_check";
begin
mem_write : process (clock)
begin
-- Write into memory when byte enabled

mem(conv_integer(address))(7 downto 0)
<= data(7 downto 0);

September 2016 455
end if;
end if;
end if;
end if;
end if;
end process mem_write;
mem_read : process (clock)

begin
--Read output is updated only when byte enable is ON
address_reg <= address;
byteena_reg <= byteena;
if (byteena_reg(0) = '1') then
q(7 downto 0) <= mem(conv_integer(address_reg))
(7 downto 0);
end if;
if (byteena_reg(1) = '1') then
(15 downto 8);
end if;
if (byteena_reg (2) = '1') then
(23 downto 16);
end if;
if (byteena_reg (3) = '1') then
(31 downto 24);
end if;
end if;
end process mem_read;
end architecture rtl;

LO
For the examples above, the following HDL Analyst RTL view shows that the
byte enables for read are registered for the single-port write first RAM.

re
RTL View
Limitations
Simple dual-port RAM can pack up to a maximum of 5 bytes of data.
September 2016 457
Chapter 9: RAM and ROM Inference Initial Values for RAMs
The RTL memory can have any configuration of data size up to a

maximum of 5 bytes; however, read and write data size must be a
multiple of 8-bit bytes. Thus the merged block RAM can only have up to
5 bytes of data width.
Initial Values for RAMs

You can specify initial values for a RAM in a data file and then include the
appropriate task enable statement, $readmemb or $readmemh, in the initial state-
ment of the RTL code for the module. The inferred logic can be different due
to the initial statement. The syntax for these two statements is as follows:
$readmemh ("fileName", memoryName [, startAddress [, stopAddress]]);
$readmemb ("fileName", memoryName [, startAddress [, stopAddress]]);
$readmemb Use this with a binary data file.
$readmemh Use this with a hexadecimal data file.
fileName Name of the data file that contains initial values. See
Initialization Data File, on page 459 for format examples.
memoryName The name of the memory.
startAddress Optional starting address for RAM initialization; if omitted,

defaults to first available memory location.
stopAddress Optional stopping address for RAM initialization;
startAddress must be specified
Also, see the following topics:

RAM Initialization Example, on page 459
Initialization Data File, on page 459
Forward Annotation of Initial Values, on page 462
Initial Values for Asymmetric RAM, on page 463
LO

re
Initial Values for RAMs Chapter 9: RAM and ROM Inference
RAM Initialization Example

This example shows a single-port RAM that is initialized using the $readmemb
binary task enable statement which reads the values specified in the binary
mem.ini file. See Initialization Data File, on page 459 for details of the binary
and hexadecimal file formats.
module ram_inference (data, clk, addr, we, data_out);

input [27:0] data;
input clk, we;
input [10:0] addr;
output [27:0] data_out;
reg [27:0] mem [0:2000] /* synthesis syn_ramstyle = "no_rw_check" */;
reg [10:0] addr_reg;
initial
begin
$readmemb ("mem.ini", mem, 2, 1900) /* Initialize RAM with contents */
/* from locations 2 thru 1900*/;
end
begin
addr_reg <= addr;
end
begin
if(we)
begin
mem[addr] <= data;
end
end
assign data_out = mem[addr_reg];
endmodule
Initialization Data File

The initialization data file, read by the $readmemb and $readmemh system
tasks, contains the initial values to be loaded into the memory array. This
initialization file can reside in the project directory or can be referenced by an
include path relative to the project directory. The system $readmemb or

September 2016 459
$readmemh task first looks in the project directory for the named file and, if
not found, searches for the file in the list of directories on the Verilog tab in
include-path order.
If the initialization data file does not contain initial values for every memory
address, the unaddressed memory locations are initialized to 0. Also, if a
width mismatch exists between an initialization value and the memory width,
loading of the memory array is terminated; any values initialized before the
mismatch is encountered are retained.
Unless an internal address is specified (see Internal Address Format, on

page 461), each value encountered is assigned to a successive word element
of the memory. If no addressing information is specified either with the
$readmem task statement or within the initialization file itself, the default
starting address is the lowest available address in the memory. Consecutive
words are loaded until either the highest address in the memory is reached or
the data file is completely read.
If a start address is specified without a finish address, loading starts at the

specified start address and continues upward toward the highest address in
the memory. In either case, loading continues upward. If both a start address
and a finish address are specified, loading begins at the start address and
continues until the finish address is reached (or until all initialization data is
read).
For example:
initial
begin
//$readmemh ("mem.ini", ram_bank1)
/* Initialize RAM with contents from locations 0 thru 31*/;
//$readmemh ("mem.ini", ram_bank1,0)
$readmemh ("mem.ini", ram_bank1, 0, 31)
The data initialization file can contain the following:

LO
White space (spaces, new lines, tabs, and form-feeds)
Comments (both comment formats are allowed)

re
Binary values for the $readmemb task, or hexadecimal values for the
$readmemh tasks
In addition, the data initialization file can include any number of hexadecimal
addresses (see Internal Address Format, on page 461).
Binary File Format

The binary data file mem.ini that corresponds to the example in RAM Initializa-
tion Example, on page 459 looks like this:
1111111111111111111100110111 /* data for address 0 */

1111111111111111111101100111 /* data for address 1 */
1111111111111111111111000010
1111111111111111111100100001
1111111111111111111101110000
1111111111111111111011100110
... /* continues until Address 1999 */
Hex File Format

If you use $readmemh instead of $readmemb, the hexadecimal data file for the
example in RAM Initialization Example, on page 459 looks like this:
FFFFF37 /* data for address 0 */

FFFFFC2
FFFFF21
.../* continues until Address 1999 */
Internal Address Format

In addition to the binary and hex formats described above, the initialization
file can include embedded hexadecimal addresses. These hexadecimal
addresses must be prefaced with an at sign (@) as shown in the example
below.

@0EA /* memory address 234
FFFFFC2 /* data for address 234*/
FFFFF21 /* data for address 235*/

September 2016 461
...
@0A7 /* memory address 137
FFFFF77 /* data for address 137*/
FFFFF7A /* data for address 138*/
...
Either uppercase or lowercase characters can be used in the address. No

white space is allowed between the @ and the hex address. Any number of
address specifications can be included in the file, and in any order. When the
$readmemb or $readmemh system task encounters an embedded address speci-
fication, it begins loading subsequent data at that memory location.
When addressing information is specified both in the system task and in the
data file, the addresses in the data file must be within the address range
specified by the system task arguments; otherwise, an error message is
issued, and the load operation is terminated.
Forward Annotation of Initial Values

Initial values for RAMs and sequential shift components are forward
annotated to the netlist. The compiler currently generates netlist (srs) files
with seqshift, ram1, ram2, and nram components. If initial values are specified in
the HDL code, the synthesis tool attaches an attribute to the component in
the srs file.
For Altera RAMs, $readmemb or $readmemh passes the initialization data to the
compiler and mapper with statements like the following:
srs File ai .syn_initval "3 00001001 2 00000000 1 00010101 0 00111101 ";

srm File ai .syn_initval "3 00001001 2 00000000 1 00010101 0 00111101 ";
It also creates a hex file with address and data as shown in the following
example. The sixth and seventh digits are the address, and the third and
fourth digits are the corresponding data values.
:0100030009F3
:0100020000FD
:0100010015E9
:010000003DC2 LO
:00000001FF

re
This hex file is associated with the altsyncram in the vqm file as follows:
defparam mem_Z.init_file = "mem.hex";
Initial Values for Asymmetric RAM

Asymmetric RAM, available with Virtex-6 and newer technologies, can be
inferred for simple dual-port RAM with content initial values and asymmetric
ports, where read width is less than write width. For example, the
asymmetric RAM coding style can be specified with the following conditions:
Port A is 512x32 write-only mode (data width 32; address width 9)
Port B is 1024x16 read-only mode (data width 16; address width 10)
Random initial value
For more information, see the topics:
Verilog Example (Read Width < Write Width)
VHDL Example (Read Width < Write Width)
Check Results for the RAM
Limitations
Verilog Example (Read Width < Write Width)

The following Verilog example implements an asymmetric port RAM where:
clocks
Example: Verilog Initial Values for Asymmetric RAM

September 2016 463
VHDL Example (Read Width < Write Width)

The following VHDL example implements an asymmetric port RAM where:
clocks
Example: VHDL Initial Values for Asymmetric RAM
Check Results for the RAM

After synthesizing the RAM, check the log file for startup values on the RAM
as shown below:
Otherwise, you can right-click on the RAM in the Technology view and select
Properties to see the properties for the RAM as shown in the following figure:
LO

re
Limitations
Supports simple dual-port RAM coding styles for read width less that
write width only.
Deeper/wider RAM with random initial values requiring multiple
asymmetric RAM inference is not supported.
See also, Limitations for Asymmetric RAM Inference, on page 444.

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Chapter 9: RAM and ROM Inference RAM Instantiation with SYNCORE
RAM Instantiation with SYNCORE

The SYNCORE Memory Compiler in the IP Wizard helps you generate HDL
code for your specific RAM implementation requirements. For information on
using the SYNCORE Memory Compiler, see Specifying RAMs with SYNCore,
LO

re
ROM Inference Chapter 9: RAM and ROM Inference
ROM Inference
As part of BEST (Behavioral Extraction Synthesis Technology) feature, the
synthesis tool infers ROMs (read-only memories) from your HDL source code,
and generates block components for them in the RTL view.
The data contents of the ROMs are stored in a text file named rom.info. To
quickly view rom.info in read-only mode, synthesize your HDL source code,
open an RTL view, then push down into the ROM component.
Generally, the Synopsys FPGA synthesis tool infers ROMs from HDL source
code that uses case statements, or equivalent if statements, to make 16 or
more signal assignments using constant values (words). The constants must
all be the same width.
Another requirement for ROM inference is that values must be specified for at
least half of the address space. For example, if the ROM has 5 address bits,
then the address space is 32 and at least 16 of the different addresses must
be specified.
Verilog Example
module rom(z,a);
output [3:0] z;
input [4:0] a;
reg [3:0] z;
always @(a) begin
case (a)
5'b00000 : z = 4'b0001;
5'b00001 : z = 4'b0010;
5'b00010 : z = 4'b0110;
5'b00011 : z = 4'b1010;
5'b00100 : z = 4'b1000;
5'b00101 : z = 4'b1001;
5'b00110 : z = 4'b0000;
5'b00111 : z = 4'b1110;
5'b01000 : z = 4'b1111;
5'b01001 : z = 4'b1110;
5'b01010 : z = 4'b0001;
5'b01011 : z = 4'b1000;
5'b01100 : z = 4'b1110;
5'b01101 : z = 4'b0011;
5'b01110 : z = 4'b1111;

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Chapter 9: RAM and ROM Inference ROM Inference
5'b01111 : z = 4'b1100;
5'b10000 : z = 4'b1000;
5'b10001 : z = 4'b0000;
5'b10010 : z = 4'b0011;
default : z = 4'b0111;
endcase
end
endmodule
VHDL Example
library ieee;
entity rom4 is
port (a : in std_logic_vector(4 downto 0);
z : out std_logic_vector(3 downto 0) );
end rom4;
architecture behave of rom4 is
begin
process(a)
begin
if a = "00000" then
z <= "0001";
elsif a = "00001" then
z <= "0010";
z <= "0110";
z <= "1010";
z <= "1000";
z <= "1001";
z <= "0000";
z <= "1110";
z <= "1111";
z <= "1110";LO
z <= "0001";

re
z <= "1000";
z <= "1110";
z <= "0011";
z <= "1111";
z <= "1100";
z <= "1000";
z <= "0000";
z <= "0011";
else
z <= "0111";
end if;
end process;
end behave;

September 2016 469
ROM Table Data (rom.info File)

Note: This data is for viewing only.
ROM work.rom4(behave)-z_1[3:0]
address width: 5
data width: 4
inputs:
0: a[0]
1: a[1]
2: a[2]
3: a[3]
4: a[4]
outputs:
0: z_1[0]
1: z_1[1]
2: z_1[2]
3: z_1[3]
data:
00000 -> 0001
00001 -> 0010
00010 -> 0110
00011 -> 1010
00100 -> 1000
00101 -> 1001
00110 -> 0000
00111 -> 1110
01000 -> 1111
01001 -> 1110
01010 -> 0001
01011 -> 1000
01100 -> 1110
01101 -> 0011
01110 -> 0010
01111 -> 0010
10000 -> 0010
10001 -> 0010
10010 -> 0010
default -> 0111
LO

re
ROM Initialization with Generate Block

The software supports conditional ROM initialization with the generate block,
as shown in the following example:
generate
if (INIT) begin
initial
begin
$readmemb("init.hex",mem);
end
end
endgenerate

September 2016 471
LO

re
CHAPTER 10
Timing Constraint Syntax
The following describe Tcl equivalents for the timing constraints you specify
in the SCOPE editor or manually in a constraint file.
FPGA Timing Constraints, on page 474
Synplify-Style Timing Constraints (Legacy), on page 513

September 2016 473
Chapter 10: Timing Constraint Syntax FPGA Timing Constraints
FPGA Timing Constraints

The FPGA synthesis tools support FPGA timing constraints for a subset of the
clock definition, I/O delay, and timing exception constraints.
For more information about using FPGA timing constraints with your project,
see Using the SCOPE Editor, on page 650 in the User Guide.
The remainder of this section describes the constraint file syntax for the
following FPGA timing constraints in the FPGA synthesis tools. For constraint
file syntax for the legacy timing constraints, see Synplify-Style Timing
Constraints (Legacy), on page 513.
create_clock
create_generated_clock
reset_path
set_clock_groups
set_clock_latency
set_clock_route_delay
set_clock_uncertainty
set_false_path
set_input_delay
set_max_delay
set_multicycle_path
set_output_delay
set_reg_input_delay
set_reg_output_delay
For information on the supported design constraints, see Chapter 11, FPGA
Design Constraint Syntax.
LO

474 September 2016
FPGA Timing Constraints Chapter 10: Timing Constraint Syntax
create_clock
Creates a clock object and defines its waveform in the current design.
Syntax
The supported syntax for the create_clock constraint is:
create_clock
-name clockName [-add] {objectList} |
-name clockName [-add] [{objectList}] |
[-name clockName [-add]] {objectList}
-period value
[-waveform {riseValue fallValue}]
[-disable]
[-comment commentString]
Arguments
-name Specifies the name for the clock being created, enclosed in quotation
clockName marks or curly braces. If this option is not used, the clock gets the
name of the first clock source specified in the objectList option. If you
do not specify the objectList option, you must use the -name option,
which creates a virtual clock not associated with a port, pin, or net.
You can use both the -name and objectList options to give the clock a
more descriptive name than the first source pin, port, or net. If you
specify the -add option, you must use the -name option and the clocks
with the same source must have different names.
-add Specifies whether to add this clock to the existing clock or to
overwrite it. Use this option when multiple clocks must be specified
on the same source for simultaneous analysis with different clock
waveforms. When you specify this option, you must also use the
-name option.
-period value Specifies the clock period in nanoseconds. This is the minimum time
over which the clock waveform repeats. The value type must be
greater than zero.

September 2016 475
-waveform Specifies the rise and fall edge times for the clock waveforms of the
riseValue clock in nanoseconds, over an entire clock period. The first time is a
fallValue rising transition, typically the first rising transition after time zero.
There must be two edges, and they are assumed to be rise followed
by fall. The edges must be monotonically increasing. If you do not
specify this option, a default waveform is assumed, which has a rise
edge of 0.0 and a fall edge of periodValue/2.
objectList Clocks can be defined on the following objects: pins, ports, and nets
The FPGA synthesis tools support nets and instances, where
instances have only one output (for example, BUFGs).
-disable Disables the constraint.
-comment Allows the command to accept a comment string. The tool honors
textString the annotation and preserves it with the object so that the exact
string is written out when the constraint is written out. The
comment remains intact through the synthesis, place-and-route,
and timing-analysis flows.
Examples
Refer to the following examples.
Example 1
A clock named clk_in1 is created for port clk_in1 that uses a period of 10 with
rising edge of 0 and falling edge of 5.
create_clock -name {clk_in1} -period 10 [get_ports {clk_in1}]
Example 2
A clock named clk is created for port clk_in that uses a period of 10.0 with
rising edge of 5.0 and falling edge of 9.5.
create_clock -name {clk} -period 10 -waveform {5.0 9.5}

[get_ports {clk_in}]
Example 3
A virtual clock named CLK is created that uses a period of 12 with a rising
LO6.0.
edge of 0.0 and falling edge of
create_clock -name {CLK} -period 12

476 September 2016

September 2016 477
Creates a generated clock object.
Syntax
The supported syntax for the create_generated_clock constraint is:
-name clockName [-add]] | {clockObject}
-source masterPinName
[-master_clock clockName]
[-divide_by integer | -multiply_by integer [-duty_cycle value]]
[-invert]
[-edges {edgeList}]
[-edge_shift {edgeShiftList}]
[-combinational]
[-disable]
Arguments
-name Specifies the name of the generated clock. If this option is not
clockName used, the clock gets the name of the first clock source specified
in the -source option (clockObject). If you specify the -add option,
you must use the -name option and the clocks with the same
source must have different names.
-add Specifies whether to add this clock to the existing clock or to
overwrite it. Use this option when multiple generated clocks
must be specified on the same source, because multiple clocks
fan into the master pin. Ideally, one generated clock must be
specified for each clock that fans into the master pin. If you
specify this option, you must also use the -name and
-master_clock options.
clockObject The first clock source specified in the -source option in the
absence of clockName. Clocks can be defined on pins, ports, and
nets. The FPGA synthesis tools support nets and instances,
where instances have only one output (for example, BUFGs).
-source Specifies the master clock source (a clock source pin in the
masterPinName LOwhich the clock waveform is derived. The actual
design), from
delays (latency) for the generated clock are computed using its
own source pins and not the masterPin option.

478 September 2016
-master_clock Specifies the master clock to be used for this generated clock,
clockName when multiple clocks fan into the master pin.
-divide_by Specifies the frequency division factor. If the divideFactor value

integer is 2, the generated clock period is twice as long as the master
clock period.
-multiply_by Specifies the frequency multiplication factor. If the
integer multiplyFactor value is 3, the generated clock period is one-third
as long as the master clock period.
-duty_cycle Specifies the duty cycle, as a percentage, if frequency
percent multiplication is used. Duty cycle is the high pulse width.
-invert Inverts the generated clock signal (in the case of frequency
multiplication and division).
-edges edgeList Specifies a list of integers that represents edges from the source
clock that are to form the edges of the generated clock. The
edges are interpreted as alternating rising and falling edges and
each edge must not be less than its previous edge. The number
of edges must be set to 3 to make one full clock cycle of the
generated clock waveform. For example, 1 represents the first
source edge, 2 represents the second source edge, and so on.
-edge_shift Specifies a list of floating point numbers that represents the
edgeShiftList amount of shift, in nanoseconds, that the specified edges are to
undergo to yield the final generated clock waveform. The
number of edge shifts specified must be equal to the number of
edges specified. The values can be positive or negative; positive
indicating a shift later in time, while negative indicates a shift
earlier in time. For example, 1 indicates that the corresponding
edge is to be shifted by one library time unit.
-combinational The source latency paths for this type of generated clock only
includes the logic where the master clock propagates. The
source latency paths do not flow through sequential element
clock pins, transparent latch data pins, or source pins of other
generated clocks.
-comment Allows the command to accept a comment string. The tool

textString honors the annotation and preserves it with the object so that
the exact string is written out when the constraint is written
out. The comment remains intact through the synthesis,
place-and-route, and timing-analysis flows.

September 2016 479
Examples
Example 1
A frequency of -divide_by 2 is used for the generated clock.
create_generated_clock -name {gen_clk} -source

[get_pins {DCM0.CLK0}] [get_pins {BUFGMUX_inst.O}] -divide_by 2
Example 2
A generated clock is created whose edges are 1, 3, and 5 of the master clock
source. If the master clock period is 30 and the master waveform is {24 36},
then the generated clock period becomes 60 with waveform {24 54}.
create_generated_clock -name {genclk} -source

[get_ports {clk_in1}] [get_nets {dut.clk_out2}] -edges {1 3 5}
Example 3
This example shows the generated clock from the previous example with each
derived edge shifted by 1 time unit. If the master clock period is 30 and the
master waveform is {24 36}, then the generated clock period becomes 60 with
waveform {25 55}.
create_generated_clock -name {genclk}

-source [get_ports {clk_in1}] [get_nets {dut.clk_out2}]
-edges {1 3 5} -edge_shift {1 1 1}
Example 4
A generated clock is created, which is 2/5 th of the source clock defined at
port clk_in1.
create_generated_clock -name {genclk}

-source [get_ports {clk_in1}] [get_nets {dut.clk_out2}]
-edges {1 1 2} -edge_shift {0 0.8 -0.4}
LO

480 September 2016
reset_path
Resets the specified paths to single-cycle timing.
Syntax
The supported syntax for the reset_path constraint is:
reset_path [-setup]
[-from {objectList}]
[-through {objectList} [-through {objectList} ...] ]
[-to {objectList}]
[-disable]
Arguments
-setup Specifies that setup checking (maximum delay) is reset to
single-cycle behavior.
-from Specifies the names of objects to use to find path start points.
The -from objectList includes:
Clocks
Registers
Top-level input or bi-directional ports)
Black box outputs
Sequential cell clock pins
When the specified object is a clock, all flip-flops, latches, and
primary inputs related to that clock are used as path start
points

September 2016 481
-through Specifies the intermediate points for the timing exception. The
-through objectList includes:
Combinational nets
Hierarchical ports
Pins on instantiated cells
By default, the through points are treated as an OR list. The
constraint is applied if the path crosses any points in objectList.
If more than one object is included, the objects must be
enclosed either in quotation marks ("") or in braces ({}). If you
specify the -through option multiple times, reset_path applies to
the paths that pass through a member of each objectList. If you
use the -through option in combination with the -from or -to
options, reset_path applies only if the -from or -to and the -through
conditions are satisfied.
-to Specifies the names of objects to use to find path end points.
The -to objectList includes:
Clocks
Registers
Top-level output or bi-directional ports
Black box inputs
If a specified object is a clock, all flip-flops, latches, and primary
outputs related to that clock are used as path end points.

LO

482 September 2016
set_clock_groups
Specifies clock groups that are mutually exclusive or asynchronous with each
other in a design so that the paths between these clocks are not considered
during timing analysis.
Syntax
The supported syntax for the set_clock_groups constraint is:
set_clock_groups
-asynchronous
-group {clockList} [-group {clockList} ]
-derive
[-disable]
Arguments
-asynchronous Specifies that the clock groups are asynchronous to each other
(the FPGA synthesis tools assume all clock groups are
synchronous). Two clocks are asynchronous with respect to
each other if they have no phase relationship at all.
-group clockList Specifies the clocks in a group (clockList). You can use the -group
option more than once in a single command execution.
However, you can include a clock only in one group in a single
command execution. To include a clock in multiple groups, you
must execute the set_clock_groups command multiple times.
By default, a generated clock and its master clock are not in the
same group when the exclusive or asynchronous clock groups
are defined. The -derive option can be used to override this
behavior and allow generated or derived clocks to inherit the
clock group of their parent source clock.
Each -group instance specifies a group of clocks, which are
exclusive or asynchronous with the clocks in all other groups. If
you specify only one group, it means that the clocks in that
group are exclusive or asynchronous with all other clocks in the
design. A default other group is created for this single group.
Whenever a new clock is created, it is automatically included in
this group.
-derive Specifies that generated and derived clocks inherit the clock
group of the parent clock.

September 2016 483

Limitations
Clock grouping in the FPGA synthesis environment is inclusionary or exclu-
sionary (for example, clk2 and clk3 can each be related to clk1 without being
related to each other).
The following set_clock_groups constraint specifies that clk1 and clk2 are
asynchronous, but clk1 and clk2 are synchronous to clk3.
create_clock [get_ports {c1}] -name clk1 -period 10

set_clock_groups -asynchronous -group [get_clocks {clk1}]
-group [get_clocks {clk2}]
This set_clock_groups constraint specifies that clock clk1, clk2, and clk3 are
synchronous to one another, but asynchronous to all other clocks in the
design.
set_clock_groups -asynchronous -group {clk1 clk2 clk3}
This set_clock_groups constraint specifies that clk1 and clk2 are synchronous to
one another, but are asynchronous to clk3 and clk4. However, clk3 and clk4 are
synchronous to each other.
set_clock_groups -asynchronous -group {clk1 clk2}

-group {clk3 clk4}
This set_clock_groups constraint specifies that clk4 is asynchronous to all other

clocks in the design.
set_clock_groups -asynchronous -group {clk4}
Note: The -group option contains

LO a list of clocks that are separated by a
space. Do not add a comma after the clock name.

484 September 2016
For example, if you specify the following:
set_clock_groups -asynchronous -group {clk1, clk2}
The tool generates a warning that clk1 cannot be found, because the comma is
treated as part of the clock name. This is true for all constraints that contain
lists.

September 2016 485
set_clock_latency
Specifies clock network latency.
Syntax
The supported syntax for the set_clock_latency constraint is:
set_clock_latency
-source
[-clock {clockList}]
delayValue
{objectList}
Arguments
-source Indicates that the specified delay is applied to the clock source
latency.
-clock clockList Indicates that the specified delay is applied with respect to the
specified clocks. By default, the specified delay is applied to all
specified objects.
delayValue Specifies the clock latency value.
objectList Specifies the input ports for which clock latency is to be set
Description
In the FPGA synthesis tools, the set_clock_latency constraint accepts both clock
objects and clock aliases. Applying a set_clock_latency constraint on a port can
be used to model the off-chip clock delays in a multi-chip environment. Clock
latency is forward annotated in the top-level constraint file as part of the time
budgeting that takes place in the Certify/HAPS flow. The annotated values
represent the arrival times for clocks on specific ports of any particular FPGA
in a HAPS design.
In the above syntax, objectList references either input ports with defined
clocks or clock aliases defined on the input ports. When more than one clock
is defined for an input port, LO
the -clock option can be used to apply different
latency values to each alias.

486 September 2016
Restrictions
The following limitations are present in the FPGA synthesis environment:
Clock latency can only be applied to clocks defined on input ports.
The set_clock_latency constraint is only used for source latency.
The constraint only applies to port clock objects.
Latency on clocks defined with create_generated_clock is not supported.

September 2016 487
set_clock_route_delay
Translates the -route option for the legacy define_clock constraint.
Syntax
The supported syntax for the set_clock_route_delay constraint is:
set_clock_route_delay {clockAliasList} {delayValue}
Arguments
clockAliasList Lists the clock aliases to include the route delay.
delayValue Specifies the route delay value.
Description
The sdc2fdc translator performs a translation of the -route option for the legacy
define_clock constraint and places a set_clock_route_delay constraint in the
*_translated.fdc file using the following format:
set_clock_route_delay [get_clocks {clk_alias_1 clk_alias_2 ...}]

{delay_in_ns}
LO

488 September 2016
Specifies the uncertainty (skew) of the specified clock networks.
Syntax
The supported syntax for the set_clock_uncertainty constraint is:
{objectList}
-from fromClock |-rise_from riseFromClock | -fall_from fallFromClock
-to toClock |-rise_to riseToClock | -fall_to fallToClock
value
Arguments
objectList Specifies the clocks for simple uncertainty. The uncertainty is
applied to the capturing latches clocked by one of the specified
clocks. You must specify either this argument or a clock pair
with the -from/-rise_from/-fall_from and -to/-rise_to/-fall_to options;
you cannot specify both an object list and a clock pair.
-from fromClock Specifies the source clocks for interclock uncertainty. You can
use only one of the -from, -rise_from, and -fall_from options and you
must specify a destination clock with one of the -to, -rise_to, and
-fall_to options.
-rise_from Specifies that the uncertainty applies only to the rising edge of
riseFromClock the source clock. You can use only one of the -from, -rise_from,
and -fall_from options and you must specify a destination clock
with one of the -to, -rise_to, and -fall_to options.
-fall_from Specifies that the uncertainty applies only to the falling edge of
fallFromClock the source clock. You can use only one of the -from, -rise_from,
and -fall_from options and you must specify a destination clock
with one of the -to, -rise_to, and -fall_to options.
-to toClock Specifies the destination clocks for interclock uncertainty. You
can use only one of the -to, -rise_to, and -fall_to options and you
must specify a source clock with one of the -from, -rise_from, and
-fall_from options.
-rise_to Specifies that the uncertainty applies only to the rising edge of
riseToClock the destination clock. You can use only one of the -to, -rise_to,
and -fall_to options and you must specify a source clock with one
of the -from, -rise_from, and -fall_from options.

September 2016 489
-fall_to fallToClock Specifies that the uncertainty applies only to the falling edge of
the destination clock. You can use only one of the -to, -rise_to,
and -fall_to options and you must specify a source clock with one
of the -from, -rise_from, and -fall_from options.
value Specifies a floating-point number that indicates the uncertainty
value. Typically, clock uncertainty should be positive. Negative
uncertainty values are supported for constraining designs with
complex clock relationships. Setting the uncertainty value to a
negative number could lead to optimistic timing analysis and
should be used with extreme care.
Examples
Example 1
All paths to registers clocked by clk are specified with setup uncertainty of 0.4
in the following example:
set_clock_uncertainty 0.4 -setup [get_clocks clk]
Example 2
For this example, interclock uncertainties are specified between clock clk and
clk2:
set_clock_uncertainty -from [get_clocks clk] -to

[get_clocks clk2] 0.2
set_clock_uncertainty -from [get_clocks clk2] -to
[get_clocks clk] 0.1
Example 3
For this example, interclock uncertainties are specified between clock clk and
clk2 with specific edges:
set_clock_uncertainty -rise_from [get_clocks clk2] -to

set_clock_uncertaintyLO
-rise_from [get_clocks clk2] -rise_to

490 September 2016
set_clock_uncertainty -from [get_clocks clk2] -fall_to


September 2016 491
set_datapathonly_delay
Specifies a point-to-point path delay that excludes any applicable clock
delays at the start and end points.
Syntax
set_datapathonly_delay option {value}
In the above syntax, option is one or more of the following:
-disable
-from {port|inst|clock}
-rise_from clock
-fall_from clock
-to {port|inst|clock}
-rise_to clock
-fall_to clock
-comment textsString
In the above options, the variable clock is a clock alias.
Description
The set_datapathonly_delay constraint specifies a point-to-point path delay that
excludes any applicable I/O delays or clock delays at the start and end
points. The constraint includes clock to out (Tco) and setup time (Tsu) as part
of the data path delay.
Use this constraint in Xilinx designs, as the tool only forward-annotates the
constraint for Xilinx designs. The set_datapathonly_delay constraint appears in
the UCF file as a Xilinx TIMESPEC constraint with the DATAPATHONLY option.
The original sdc command is also forward-annotated as a comment. For
example:
# set_datapathonly_delay -from {p:din[*]} -to {i:int[*]} {4}

...
NET "din[7]" TNM = "from_1005_0";
INST "int[*]" TNM = "to_1005_0"; # int[7:0]
TIMESPEC "TS_1005_0" = FROM "from_1005_0" TO "to_1005_0"
LO
DATAPATHONLY 4.000;

492 September 2016
When you specify this constraint, the tool ignores any clock skew or phase
information. It constrains, analyzes, and forward-annotates just the data
path between the specified points.

September 2016 493
set_false_path
Removes timing constraints from particular paths.
Syntax
The supported syntax for the set_false_path constraint is:
set_false_path
[-setup]
[-to {objectList}]
[-disable]
Arguments
-setup Specifies that setup checking (maximum delay) is reset to
single-cycle behavior.
Clocks
Registers
Top-level input or bi-directional ports
Black box outputs
points.
LO

494 September 2016
Combinational nets
Hierarchical ports
If more than one object is included, the objects must be
enclosed either in quotation marks ("") or in braces ({}). If you
specify the -through option multiple times, set_path applies to the
paths that pass through a member of each objectList. If you use
the -through option in combination with the -from or -to options,
set_false_path applies only if the -from or -to and the -through
conditions are satisfied.
Clocks
Registers
Black box inputs
outputs related to that clock are used as path end points.

Examples
Example 1
All the paths from the sequential cell output pins and clock pins in module
gen_sub\[*\].u_sub with names matching out* (i.e. registers out1 and out2 in
modules gen_sub\[0\].u_sub, gen_sub\[1\].u_sub, and gen_sub\[2\].u_sub) are set as
false paths.
set_false_path -from [get_pins{gen_sub\[*\]\.u_sub.out*.*}] 2

September 2016 495
Note: Only sequential cell clock pins are pins that can be used as valid
start points for a timing path. Note that hierarchical module pins
are not valid as starting points for a timing path.
Example 2
All the paths from the sequential cells in module gen_sub\[*\].u_sub with names
matching out* (i.e. registers out1 and out2 in modules gen_sub\[0\].u_sub,
gen_sub\[1\].u_sub, and gen_sub\[2\].u_sub) are set as false paths.
set_false_path -from [get_cells {gen_sub\[*\]\.u_sub.out*}]
Example 3
All paths from top-level input ports with names in* are set as false paths.
set_false_path -from [get_ports {in*}]
Note: Only top-level ports are valid port based start points for timing
paths. Do not use the get_ports command to reference hierar-
chical module pins.
Example 4
All paths with end points clocked by clock clka are set as false paths.
set_false_path -to [get_clocks {clka}]
LO

496 September 2016
set_input_delay
Sets input delay on pins or input ports relative to a clock signal.
Syntax
The supported syntax for the set_input_delay constraint is:
set_input_delay
[-clock clockName [-clock_fall]]
[-rise|-fall]
[-min|-max]
[-add_delay]
delayValue
{portPinList}
[-disable]
Argument
-clock clockName Specifies the clock to which the specified delay is related. If
-clock_fall is used, -clock clockName must be specified. If -clock is
not specified, the delay is relative to time zero for combinational
designs. For sequential designs, the delay is considered relative
to a new clock with the period determined by considering the
sequential cells in the transitive fanout of each port.
-clock_fall Specifies that the delay is relative to the falling edge of the clock.
The default is the rising edge.
-rise Specifies that delayValue refers to a rising transition on the
specified ports of the current design. If neither -rise nor -fall is
specified, rising and falling delays are assumed to be equal.
Currently, the synthesis tool does not differentiate between the
rising and falling edges for the data transition arcs on the
specified ports. The worst case path delay is used instead.
However, the -rise option is preserved and forward annotated to

September 2016 497
-fall Specifies that delayValue refers to a falling transition on the

specified, rising and falling delays are assumed equal.
However, the -fall option is preserved and forward annotated to
-min Specifies that delayValue refers to the shortest path. If neither
-max nor -min is specified, maximum and minimum input delays
are assumed equal.
Note: The synthesis tool does not optimize for hold time
violations and only reports -min delay values in the
synlog/topLevel_fpga_mapper.srr_Min timing report section
of the log file. The -min delay values are forward annotated to the
-max Specifies that delayValue refers to the longest path. If neither
-max nor -min is specified, maximum and minimum input delays
are assumed equal.
Note: The -max delay values are reported in the top-level log file
and are forward annotated to the place-and-route tool.
-add_delay Specifies if delay information is to be added to the existing input
delay or if is to be overwritten. The -add_delay option enables you
to capture information about multiple paths leading to an input
port that are relative to different clocks or clock edges.

delayValue Specifies the path delay. The delayValue must be in units
consistent with the technology library used during optimization.
The delayValue represents the amount of time the signal is
available after a clock edge. This represents a combinational
path delay from the clock pin of a register.
portPinList Specifies a list of input port names in the current design to
which delayValue is assigned. If more than one object is
LO
specified, the objects are enclosed in quotes ("") or in braces ({}).

498 September 2016
set_max_delay
Specifies a maximum delay target for paths in the current design.
Syntax
The supported syntax for the set_max_delay constraint is:
set_max_delay
[-through{objectList} [-through {objectList} ...] ]
[-to {objectList}]
delayValue
[-disable]
Arguments
Clocks
Registers
Black box outputs
points. All paths from these start points to the end points in the
-from objectList are constrained to delayValue. If a -to objectList is
not specified, all paths from the -from objectList are affected. If
you include more than one object, you must enclose the objects
in quotation marks ("") or braces ({}).

September 2016 499
Combinational nets
Hierarchical ports
The max delay value applies only to paths that pass through
one of the points in the -through objectList. If more than one
object is included, the objects must be enclosed either in
quotation marks ("") or in braces ({}). If you specify the -through
option multiple times, set_max_delay applies to the paths that
pass through a member of each objectList. If you use the -through
option in combination with the -from or -to options, set_max_delay
applies only if the -from or -to and the -through conditions are
satisfied.
Clocks
Registers
Black box inputs
outputs related to that clock are used as path end points. All
paths to the end points in the -to objectList are constrained to
delayValue. If a -from objectList is not specified, all paths to the
-to objectList are affected. If you include more than one object,
you must enclose the objects in quotation marks ("") or braces
({}).

LO

500 September 2016
delayValue Specifies the value of the desired maximum delay for paths
between start and end points. You must express delayValue in
the same units as the technology library used during
optimization. If a path start point is on a sequential device,
clock skew is included in the computed delay. If a path start
point has an input delay specified, that delay value is added to
the path delay. If a path end point is on a sequential device,
clock skew and library setup time are included in the computed
delay. If the end point has an output delay specified, that delay
is added into the path delay.

September 2016 501
set_multicycle_path
Modifies the single-cycle timing relationship of a constrained path.
Syntax
The supported syntax for the set_multicycle_path constraint is:
set_multicycle_path
[-start |-end]
[-to {objectList}]
pathMultiplier
[-disable]
Arguments
-start | -end Specifies if the multi-cycle information is relative to the period of
either the start clock or the end clock. These options are only
needed for multi-frequency designs; otherwise start and end are
equivalent. The start clock is the clock source related to the
register or primary input at the path start point. The end clock
is the clock source related to the register or primary output at
the path endpoint. The default is to move the setup check
relative to the end clock, and the hold check relative to the start
clock. A setup multiplier of 2 with -end moves the relation
forward one cycle of the end clock. A setup multiplier of 2 with
-start moves the relation back one cycle of the start clock. A hold
multiplier of 1 with -start moves the relation forward one cycle of
the start clock. A hold multiplier of 1 with -end moves the
relation back one cycle of the end clock.
LO

502 September 2016
Clocks
Registers
Black box outputs
points. If a -to objectList is not specified, all paths from the -from
objectList are affected. If you include more than one object, you
must enclose the objects in quotation marks ("") or braces ({}).
Combinational nets
Hierarchical ports
The multi-cycle values apply only to paths that pass through
one of the points in the -through objectList. If more than one
object is included, the objects must be enclosed either in double
quotation marks ("") or in braces ({}). If you specify the -through
option multiple times, set_multicycle_delay applies to the paths
that pass through a member of each objectList. If the -through
option is used in combination with the -from or -to options, the
multi-cycle values apply only if the -from or -to conditions and
the -through conditions are satisfied.
Clocks
Registers
Black box inputs
outputs related to that clock are used as path end points. If a
-from objectList is not specified, all paths to the -to objectList are
affected. If you include more than one object, you must enclose
the objects in quotation marks ("") or braces ({})..

September 2016 503

pathMultiplier Specifies the number of cycles that the data path must have for
setup or hold relative to the start point or end point clock before
data is required at the end point. When used with -setup, this
value is applied to setup path calculations. When used with
-hold, this value is applied to hold path calculations. If neither
-hold nor -setup are specified, pathMultiplier is used for setup,
and pathMultiplier -1 is used for hold. Changing the
pathMultiplier for setup also affects the hold check.
Examples
Example 1
All the paths from the sequential cell output pins and clock pins in module
gen_sub\[*\].u_sub with names matching out* (i.e. registers out1 and out2 in
modules gen_sub\[0\].u_sub, gen_sub\[1\].u_sub, and gen_sub\[2\].u_sub) provide 2
timing cycles before the data is required at the end point.
set_multicycle_path -from [get_pins {gen_sub\[*\]\.u_sub.out*.*}]

2
Note: Only sequential cell clock pins are pins that can be used as valid
start points for a timing path. Note that hierarchical module pins
cannot be used as starting points for a timing path.
Example 2
All the paths from the sequential cells in module gen_sub\[*\].u_sub with names
matching out* (i.e. registers out1 and out2 in modules gen_sub\[0\].u_sub,
gen_sub\[1\].u_sub, and gen_sub\[2\].u_sub) support the timing cycle set to 2.
LO
set_multicycle_path -from [get_cells {gen_sub\[*\]\.u_sub.out*}] 2

504 September 2016
Example 3
All paths from top-level input ports with names in* provide 2 timing cycles
before the data is required at the end point.
set_multicycle_path -from [get_ports {in*}] 2
Note: Only top-level ports are valid port based start points for timing
paths. Do not use the get_ports command to reference hierarchical
module pins.
Example 4
All paths with end points clocked by clock clka provide 2 timing cycles before
the data is required at the end point.
set_multicycle_path -to [get_clocks {clka}] 2

September 2016 505
set_output_delay
Sets output delay on pins or output ports relative to a clock signal.
Syntax
The supported syntax for the set_output_delay constraint is:
set_output_delay
[-clock clockName [-clock_fall]]
[-rise|[-fall]
[-min|-max]
[-add_delay]
delayValue
{portPinList}
[-disable]
Arguments
-clock clockName Specifies the clock to which the specified delay is related. If
-clock_fall is used, -clock clockName must be specified. If -clock is
not specified, the delay is relative to time zero for combinational
designs. For sequential designs, the delay is considered relative
to a new clock with the period determined by considering the
sequential cells in the transitive fanout of each port.
-clock_fall Specifies that the delay is relative to the falling edge of the clock.
If -clock is specified, the default is the rising edge.
-rise Specifies that delayValue refers to a rising transition on the
specified, rising and falling delays are assumed to be equal.
However, the -rise option is preserved and forward annotated to
LO

506 September 2016
-fall Specifies that delayValue refers to a falling transition on the

specified, rising and falling delays are assumed equal.
However, the -fall option is preserved and forward annotated to
-min Specifies that delayValue refers to the shortest path. If neither
-max nor -min is specified, maximum and minimum output
delays are assumed equal.
Note: The synthesis tool does not optimize for hold time
violations and only reports -min delay values in the
synlog/topLevel_fpga_mapper.srr_Min timing report section
of the log file. The -min delay values are forward annotated to the
-max Specifies that delayValue refers to the longest path. If neither
-max nor -min is specified, maximum and minimum output
delays are assumed equal.
Note: The -max delay values are reported in the top-level log file
and are forward annotated to the place-and-route tool.
-add_delay Specifies whether to add delay information to the existing
output delay or to overwrite. The -add_delay option enables you
to capture information about multiple paths leading to an
output port that are relative to different clocks or clock edges.

delayValue Specifies the path delay. The delayValue must be in units
consistent with the technology library used during optimization.
The delayValue represents the amount of time that the signal is
required before a clock edge. For maximum output delay, this
usually represents a combinational path delay to a register plus
the library setup time of that register. For minimum output
delay, this value is usually the shortest path delay to a register
minus the library hold time

September 2016 507
portPinList A list of output port names in the current design to which

delayValue is assigned. If more than one object is specified, the
objects are enclosed in double quotation marks ("") or in braces
({}).
LO

508 September 2016
set_reg_input_delay
Speeds up paths feeding a register by a given number of nanoseconds.
Syntax
set_reg_input_delay {registerName} [-route ns] [-disable] [-comment textString]
Arguments
registerName A single bit, an entire bus, or a slice of a bus.
-route Advanced user option that you use to tighten constraints during
resynthesis, when the place-and-route timing report shows the
timing goal is not met because of long paths to the register.
-comment Allows the command to accept a comment string. The tool honors the
annotation and preserves it with the object so that the exact string is
written out when the constraint is written out. The comment remains
intact through the synthesis, place-and-route, and timing-analysis
flows.
Description
The set_reg_input_delay timing constraint speeds up paths feeding a register by
a given number of nanoseconds. The Synopsys FPGA synthesis tool attempts
to meet the global clock frequency goals for a design as well as the individual
clock frequency goals (set with create_clock). Use this constraint to speed up
the paths feeding a register. For information about the equivalent SCOPE
spreadsheet interface, see Registers, on page 299.
Use this constraint instead of the legacy constraint, define_reg_input_delay.

September 2016 509
set_reg_output_delay
Speeds up paths coming from a register by a given number of nanoseconds.
Syntax
set_reg_output_delay {registerName} [-route ns] [-disable] [-comment textString]
Arguments
timing goal is not met because of long paths from the register.
the annotation and preserves it with the object so that the exact
Description
The set_reg_output_delay constraint speeds up paths coming from a register by
a given number of nanoseconds. The synthesis tool attempts to meet the
global clock frequency goals for a design as well as the individual clock
frequency goals (set with create_clock). Use this constraint to speed up the
paths coming from a register. For information about the equivalent SCOPE
spreadsheet interface, see Registers, on page 299.
Use this constraint instead of the legacy constraint, define_reg_output_delay.
LO

510 September 2016
Naming Rule Syntax Commands

The FPGA synthesis environment uses a set of naming conventions for design
objects in the RTL when your project contains constraint files. The following
naming rule commands are added to the constraint file to change the
expected default values. These commands must appear at the beginning of
the constraint file before any other constraints. Similarly, when multiple
constraint files are included in the project, the naming rule commands must
be in the first constraint file read.
set_hierarchy_separator Command
The set_hierarchy_separator command redefines the hierarchy separator
character (the default separator character is the period in the FPGA synthesis
environment). For example, the following command changes the separator
character to a forward slash:
set_hierarchy_separator {/}
set_rtl_ff_names Command
The set_rtl_ff_names command controls the stripping of register suffixes in the
object strings of delay-path constraints (for example, set_false_path, set_multicy-
cle_path). Generally, it is only necessary to change this value from its default
when constraints that target ASIC designs are being imported from the
Design Compiler (in the Design Compiler, inferred registers are given a _reg
suffix during the elaboration phase; constraints targeting these registers
must include this suffix). When importing constraints from the Design
Compiler, include the following command to change the value of this naming
rule to {_reg} to automatically recognize the added suffix.
set_rtl_ff_names {_reg}
For example, using the above value allows the DC exception
set_false_path to [get_cells {register_bus_reg[0]}]
to apply to the following object without having to manually modify the

constraint:
[get_cells {register_bus[0]}]

September 2016 511
bus_naming_style Command
The bus_naming_style command redefines the format for identifying bits of a
bus (by default, individual bits of a bus are identified by the bus name
followed by the bus bit enclosed in square brackets). For example, the
following command changes the bus-bit identification from the default
busName[busBit] format to the busName_busBit format:
bus_naming_style {%s_%d}
bus_dimension_separator_style Command
The bus_dimension_separator_style command redefines the format for identifying
multi-dimensional arrays (by default, multidimensional arrays such as row 2,
bit 3 of array ABC[n x m] are identified as ABC[2][3]). For example, the
following command changes the bus-dimension separator from individual
square bracket sets to an underscore:
bus_dimension_separator_style {_}
The resulting format for the above example is:
ABC[2_3]
read_sdc Command
Reads in a script in Synopsys FPGA constraint format. The supported syntax
for the read_sdc constraint is:
read_sdc fileName
LO

512 September 2016
Synplify-Style Timing Constraints (Legacy) Chapter 10: Timing Constraint Syntax
Synplify-Style Timing Constraints (Legacy)

This section describes the constraint file syntax for the Synplify-style legacy
timing constraints. For tool versions 2012.09 and later, it is recommended
that you use the Synopsys Standard timing constraint format instead of the
Synplify-style legacy format. Use the sdc2fdc command to convert your
constraints. See FPGA Timing Constraints, on page 474 for more information.
The legacy constraints are included in your project through an SDC file. This
section describes the constraint file syntax for the legacy FPGA timing
constraints, which include:
define_clock, on page 514
define_clock_delay, on page 517
define_false_path, on page 518
define_input_delay, on page 521
define_multicycle_path, on page 523
define_output_delay, on page 527
define_path_delay, on page 529
define_reg_input_delay, on page 532
define_reg_output_delay, on page 533
set_datapathonly_delay, on page 534
For information on the supported design constraints, see Chapter 11, FPGA
Design Constraint Syntax.

September 2016 513
Chapter 10: Timing Constraint Syntax Synplify-Style Timing Constraints (Legacy)
define_clock
Defines a clock with a specific duty cycle and frequency or clock period goal.
Syntax
define_clock [-disable] [-virtual] {clockObject}
[-freq MHz |-period ns] [-clockgroup domain]
[-rise value |-fall value] [-route ns]
[-name clockName] [-comment textString]
Arguments
-disable Disables a previous clock constraint.
-virtual Specifies arrival and required times on top level ports that are
enabled by clocks external to the chip (or block) that you are
synthesizing. When specifying -name for the virtual clock, the field
can contain a unique name not associated with any port or instance
in the design.
clockObject A required parameter that specifies the clock object name. Clocks
can be defined on the following objects:
Top-level input ports (p:)
Nets (n:)
Instances (i:)
Output pins of instantiated cells (t:)
Clocks defined on any of the following objects WILL NOT be
honored:
Top-level output ports
Input pins of instantiated gates
Pins of inferred instances
-name Specifies a name for the clock if you want to use a name other than
the clock object name. This alias name is used in the timing reports.
-freq Defines the frequency of the clock in MHz. You can specify either
this or -period, but not both.
-period Specifies the period of the clock in ns. Specify either this or -freq, but
not both. LO

514 September 2016
-clockgroup Allows you to specify clock relationships. You assign related

(synchronized) clocks to the same clock group and unrelated clocks
in different groups.
The synthesis tool calculates the relationship between clocks in the
same clock group, and analyzes all paths between them. Paths
between clocks in different groups are ignored (false paths).
See Clock Groups, on page 333 for more information.
-rise|-fall Specifies a non-default duty cycle. By default, the synthesis tool
assumes that the clock is a 50% duty cycle clock, with the rising
edge at 0 and the falling edge at period/2. If you have another duty
clock cycle, specify the appropriate Rise At and Fall At values. For
more information, see Rise and Fall Constraints, on page 335.
-route An advanced user option that improves the path delays of all
registers controlled by this clock. The value is the difference
between the synthesis timing report path delays and the value in
the place-and-route timing report. The -route constraint applies
globally to the clock domain, and can over constrain registers where
constraints are not needed. For details, see Route Option, on
page 336.
Before you use this option, evaluate the path delays on individual
registers in the optimization timing report and try to improve the
delays by applying the constraints define_reg_input_delay and
define_reg_output_delay only on the registers that need them.
Description
The define_clock timing constraint defines a clock with a specific duty cycle
and frequency or clock period goal. You can have multiple clocks with
different clock frequencies. Set the default frequency for all clocks with the
set_option -frequency Tcl command in the project file. If you do not specify a
global frequency, the timing analyzer uses a default. Use the define_clock
timing constraint to override the default and specify unique clock frequency
goals for specific clock signals. Additionally, you can use the define_clock
timing constraint to set the clock frequency for a clock signal output of clock
divider logic. The clock name is the output signal name for the register
instance. If you are constraining a differential clock, you only need to
constrain the positive input.

September 2016 515
For the equivalent SCOPE spreadsheet interface and descriptions of the

options, see Clocks (Legacy), on page 331 and Clocks Panel Description, on
page 332.
Examples
define_clock Syntax
define_clock {CLK1} -period 10.0 -clockgroup default_clkgroup
define_clock {CLK3} -period 5.0 -clockgroup default_clkgroup
-name INT_REF3
define_clock -virtual {CLK2} -period 20.0 -clockgroup g2
define_clock {CLK4} -period 20.000 -clockgroup g3
-rise 1.000 -fall 11.000 -ref_rise 0.000 -ref_fall 10.000
define_clock Pin-Level Constraint

define_clock {i:myInst1.Q} -period 10.000
-clockgroup default -rise 0.200 fall 5.200 -name myff1
define_clock {i:myInst2.Q} -period 12.000
-clockgroup default -rise 0.400 fall 5.400 -name myff2
In the example above, a clock is defined on the Q pins of instances myInst1 and
myInst2.
LO

516 September 2016
define_clock_delay
Defines the delay between the clocks in the design.
Syntax
define_clock_delay -rise|-fall {clockName1} -rise|-fall {clockName2} delayValue
Arguments
-rise|fall Specifies the clock edge
clockName Specifies the clocks to constrain The clock must be
already defined with define_clock.
delayValue Specifies the delay, in nanoseconds, between the two
clocks. You can also specify a value false which defines
the path as a false path.
Description
The define_clock_delay timing constraint defines the delay between the clocks
in the design. By default, the software automatically calculates clock delay
based on the clock parameters you define through the define_clock command.
However, if you use define_clock_delay, the specified delay value overrides any
calculations made by the software. The results shown in the Clock Relationships
section of the Timing Report are based on calculations made using this
constraint.
Note: Maintenance for the define_clock_delay command is limited. It is

recommended that you use the define_false_path and
define_path_delay commands instead, since these commands
support clock aliases.

September 2016 517
define_false_path
Defines paths to ignore (remove) during timing analysis.
Syntax
define_false_path [-disable] {-from startPoint |-to endPoint |-through throughPoint}
[-comment textString]
Arguments
-from startPoint Specifies the starting point for the false path. The from point
defines a timing start point and can be any of the following:
Clocks (c:) (See Clocks as From/To Points, on page 323.)
Registers (i:)
Top-level input or bi-directional ports (p:)
Black box outputs (i:)
For more information, see the following:
-to endPoint Specifies the ending point for the false path. The to point defines a
timing end point and can be any of the following objects:
Registers (i:)
Top-level output or bi-directional ports (p:)
Black box inputs (i:)
LO

518 September 2016
-through Specifies the intermediate points for the timing exception.

throughPoint Intermediate points can be any of the following objects:
Combinational nets (n:)
Hierarchical ports (t:)
Pins on instantiated cells (t:)
constraint is applied if the path crosses any points in the list. For
more information, see the following:
To keep the signal name intact through synthesis, set the syn_keep
directive (Verilog or VHDL) on the signal.
Description
The define_false_path timing constraint defines paths to ignore (remove) during
timing analysis and gives lower (or no) priority during optimization. The false
paths are also passed on to supported place-and-route tools. For information
about the equivalent SCOPE spreadsheet interface and the options, see False
Paths, on page 315. See False Path Constraint Examples, on page 316, and
Priority of False Path Constraints, on page 316, for additional information.
Example
The following example shows the syntax for setting a define_false_path
constraint between registers:
define_false_path from {i:myInst1_reg} through {n:myInst2_net}

to {i:myInst3_reg}

September 2016 519
The constraint is defined from the output pin of myInst1_reg, through net
myInst2_net, to the input of myInst3_reg. If an instance is instantiated, a
pin-level constraint applies on the pin, as defined. However, if an instance is
inferred, the pin-level constraint is transferred to the instance.
For through points specified on pins, the constraint is transferred to the

connecting net. You cannot define a through point on a pin of an instance that
has multiple outputs. When specifying a pin on a vector of instances, you
cannot refer to more than one bit of that vector.
LO

520 September 2016
define_input_delay
Specifies the external input delays on top-level ports in the design.
Syntax
define_input_delay [-disable] {inputportName | -default ns [-route ns]
[-ref clockName:edge] [-comment textString]
Arguments
inputportName The name of the input port.

-default Sets a default input delay for all inputs. Use this option to set an
input delay for all inputs. You can then set define_input_delay on
individual inputs to override the default constraint. This example
sets a default input delay of 3.0 ns:
define_input_delay -default 3.0
This constraint overrides the default and sets the delay on input_a to
10.0 ns: define_input_delay {input_a} 10.0
-route An advanced option, which includes route delay when the synthesis
tool tries to meet the clock frequency goal. Use the -route option on
an input port when the place-and-route timing report shows that
the timing goal is not met because of long paths through the input
port. See Route Option, on page 340 for an example of its use.
-ref (Recommended.) Clock name and edge that triggers the event. The
value must include either the rising edge or falling edge.
r - rising edge
f - falling edge
For example: define_input_delay {portb[7:0]} 10.00 -ref clock2:f

September 2016 521
Description
The define_input_delay timing constraint specifies the external input delays on
top-level ports in the design. This external delay is the delay outside the chip
before the signal arrives at the input pin. This constraint is used to model the
interface of the inputs of the FPGA with the outside environment. The tool
has no way of knowing what the input delay is unless you specify it in a
timing constraint. For information about the equivalent SCOPE interface, see
Inputs/Outputs (Legacy), on page 339.
Example
Here are some examples of the define_input_delay constraint:
define_input_delay {porta[7:0]} 7.8 -ref clk1:r

define_input_delay -default 8.0
define_input_delay -disable {resetn}
The following example shows how all the bits of the datain input bus are
constrained with a delay of 2 ns, except for bit 16:
define_input_delay {datain[0:15]} 2.00 -ref clk:r

define_input_delay {datain[17:99]} 2.00 -ref clk:r
LO

522 September 2016
define_multicycle_path
Specifies a path that uses multiple clock cycles as a timing exception.
Syntax
define_multicycle_path [-disable] [-start |-end]
{-from startPoint |-to endPoint |-through throughPoint}
clockCycles [-comment textString]
Arguments
-start | -end Specifies the clock cycles to use for paths with different start
and end clocks. This option determines the clock period to use
as the multiplicand in the calculation for clock distance. If you
do not specify a start or end option, the end clock is the default.
See Multi-cycle Path with Different Start and End Clocks, on
-from startPoint Specifies the start point for the multi-cycle timing exception. The
From point in the constraint defines a timing start point and can
be any of the following:
Registers (i:)

September 2016 523
-to endPoint Specifies the end point for the multi-cycle timing exception. The to
point defines a timing end point and can be any of the following
objects:
Registers (i:)
Top-level output or bi-directional ports (p:)
throughPoint Intermediate points can be:
Combinational nets (n:)
Hierarchical ports (t:)
Pins on instantiated cells (t:)
By default, the intermediate points are treated as an OR list, the
exception is applied if the path crosses any points in the list. For
more information, see the following:
You can combine this option with -to or -from to get a specific path.
To keep the signal name intact throughout synthesis when you
use this option, set the syn_keep directive (Verilog or VHDL) on the
signal.
clockCycles The number of clock cycles to use for the path constraint.
LO

524 September 2016
Description
The define_multicycle_path timing constraint specifies a path that uses multiple
clock cycles as a timing exception. This constraint provides extra clock cycles
to the designated paths for timing analysis and optimization. For information
about the equivalent SCOPE interface, see Multicycle Paths, on page 312.
Timing Exceptions Object Types

Timing exception constraints must contain object types in the specification.
Timing exceptions, such as multi-cycle path and false path constraints,
require that you explicitly specify the object type (n: or i:) in the instance
name parameter. For example:
define_multicycle_path -from {i:inst2.lowreg_output[7]}

-to {i:inst1.DATA0[7]} 2
If you use the SCOPE UI to specify timing exceptions, it automatically

attaches object type qualifiers to the object names. For more information, see
Specifying From, To, and Through Points, on page 318.
Example
Here are some examples of the define_multicycle_path constraint syntax:
define_multicycle_path -from{i:regs.addr[4:0]}
-to {i:special_regs.w[7:0]} 2
define_multicycle_path -to {i:special_regs.inst[11:0]} 2
define_multicycle_path -from {p:porta[7:0]}
-through {n:prgmcntr.pc_sel44[0]} -to {p:portc[7:0]} 2
define_multicycle_path -from {i:special_regs.trisc[7:0]}
-through {t:uc_alu.aluz.Q} -through {t:special_net.Q} 2
The following example shows the syntax for setting a multi-cycle path
constraint between registers:
define_multicycle_path from {i:myInst1_reg}

through {n:myInst2_net} to {i:myInst3_reg} 2
The constraint is defined from the output of myInst1_reg, through net

myInst2_net, to the input pin myInst3_reg. If the instance is instantiated, a
pin-level constraint applies on the pin, as defined. However, if the instance is
inferred, the pin-level constraint is transferred to the instance. For through

September 2016 525
points specified on pins, the constraint is transferred to the connecting net.

You cannot define a through point on a pin of an instance that has multiple
outputs. When specifying a pin on a vector of instances, you cannot refer to
more than one bit of that vector.
For additional examples of multi-cycle paths, see Multicycle Path Examples,

on page 313.
LO

526 September 2016
define_output_delay
Specifies the delay of the logic outside the FPGA driven by the top-level
outputs.
Syntax
define_output_delay [-disable] {outputportName} |-default ns [-route ns]
[-ref clockName:edge] [-comment textString]
Arguments
outputportName The name of the output port.
-default Sets a default output delay for all outputs. Use this option to set
a delay for all outputs. You can then set define_output_delay on
individual outputs to override the default constraint. This
example sets a default output delay of 8.0 ns. The delay is
outside the FPGA.
define_output_delay -default 8.0
The following constraint overrides the default and sets the
output delay on output_a to 10.0 ns. This means that output_a
drives 10 ns of combinational logic before the relevant clock
edge.
define_output_delay {output_a} 10.0

September 2016 527
-route An advanced option, which includes route delay when the

synthesis tool tries to meet the clock frequency goal. See Route
Option, on page 340 for an example of its use with an input
register.
-ref Defines the clock name and edge that controls the event. Value
must be one of the following:
r - rising edge
f - falling edge
For example: define_output_delay {portb[7:0]} 10.00 -ref clock2:f
See Output Pad Clock Domain Default, below for more
information on this option.
honors the annotation and preserves it with the object so that
Description
The define_output_delay constraint models the interface of the outputs of the
FPGA with the outside environment. The default delay outside the FPGA is
0.0 ns. Output signals typically drive logic that exists outside the FPGA, but
the tool has no way of knowing the delay for that logic unless you specify it
using a timing constraint. For information about the equivalent SCOPE
spreadsheet interface, see Inputs/Outputs (Legacy), on page 339.
Output Pad Clock Domain Default

By default, define_output_delay constraints with no reference clock are
constrained against the global frequency, instead of the start clock for the
path to the port. The tool assumes the register and pad are not in the same
clock domain. This change affects the timing report and timing driven optimi-
zations on any logic between the register and the pad.
You must specify the clock domain for all output pads on which you have set
output delay constraints. For the pads for which you do not specify a clock,
add the -ref option to the define_output_delay constraint. For example:
LO
define_output_delay {LDCOMP} 0.50
-route 0.25 -ref {CLK1:r}

528 September 2016
define_path_delay
Specifies point-to-point delay for maximum delay constraints.
Syntax
define_path_delay [-disable]
-from {startPoint} | -to {endPoint} | -through {throughPoint}
-max delayValue [-comment textString]
Arguments
-from startPoint Specifies the starting point of the path. The From point defines a
timing start point and can be any of the following objects:
Registers (i:)
-to endPoint Specifies the ending point of the path. The to point in the
constraint must be a timing end point and can be any of the
following objects:
clocks (c:) (See Clocks as From/To Points, on page 323.)
registers (i:)
top-level output or bi-directional ports (p:)
black box inputs (i:)
For more information, see:
You can combine this option with -from or -through to get a specific
path.

September 2016 529

throughPoint Intermediate points can be:
combinational nets (n:)
hierarchical ports (t:)
pins on instantiated cells (t:)
By default, the intermediate points are treated as an OR list, the
exception is applied if the path crosses any points in the list. For
more information, see:
You can combine this option with -to or -from to get a specific
path. To keep the signal name intact throughout synthesis when
you use this option, set the syn_keep directive (Verilog or VHDL)
on the signal.
-max delayValue Sets the maximum allowable delay for the specified path. This is
an absolute value in nanoseconds and is shown as max analysis
in the timing report.
honors the annotation and preserves it with the object so that
the exact string is written out when the constraint is written out.
The comment remains intact through the synthesis,
The define_path_delay timing constraint specifies point-to-point delay, in

nanoseconds, for maximum delay constraints. You can specify the start, end,
or through points using the -from, -to, or -through options or any combination of
these options.
When you specify define_path_delay and you also have input or output delays
defined, the synthesis tool adds the input or output delays to the path delay.
The timing constraint that is forward-annotated includes the I/O delay with
the path delay. This could result in discrepancies with the Xilinx P&R tool,
which ignores the I/O delays and only reports the path delay.
Example
Here are examples of the path delay constraint.
define_path_delay -from
LO {i:dmux.alua[5]}
-to {i:regs.mem_regfile_15[0]} -max 0.800

530 September 2016
The following constraint sets a max delay of 2 ns on all paths to the falling
edge of the flip-flops clocked by clk1.
define_path_delay -to {c:clk1:f} -max 2
Here is an example of setting the path delay constraint on the pins between
registers:
define_path_delay from {i:myInst1_reg} through {t:myInst2_net.Y}

to {i:myInst3_reg} max 0.123
The constraint is defined from the output pin of myInst1, through pin Y of net
myInst2, to the input pin of myInst3. If the instance is instantiated, a pin-level
constraint applies on the pin, as defined. If the instance is inferred, the
pin-level constraint is transferred to the instance.
Limitations
The following limitations are present:

For through points specified on pins, the constraint is transferred to the
connecting net. You cannot define a through point on a pin of an instance
that has multiple outputs.
When specifying a pin on a vector of instances, you cannot refer to more
than one bit of that vector.

September 2016 531
define_reg_input_delay
Speeds up paths feeding a register by a given number of nanoseconds. It is
recommended that you use the FDC equivalent of this legacy command,
which is described in set_reg_input_delay, on page 509.
Syntax
define_reg_input_delay {registerName} [-route ns] [-comment textString]
Arguments
timing goal is not met because of long paths to the register. See
Route Option, on page 340 for an example of its use.
-comment Allows the command to accept a comment string. The tool honors the
annotation and preserves it with the object so that the exact string is
written out when the constraint is written out. The comment remains
intact through the synthesis, place-and-route, and timing-analysis
flows.
Description
The define_reg_input_delay timing constraint speeds up paths feeding a
register by a given number of nanoseconds. The Synopsys FPGA synthesis
tool attempts to meet the global clock frequency goals for a design as well as
the individual clock frequency goals (set with define_clock). Use this constraint
to speed up the paths feeding a register. For information about the equivalent
SCOPE spreadsheet interface, see Registers (Legacy), on page 343.
LO

532 September 2016
define_reg_output_delay
Speeds up paths coming from a register by a given number of nanoseconds. It
is recommended that you use the FDC equivalent of this legacy command,
which is described in set_reg_output_delay, on page 510.
Syntax
define_reg_output_delay {registerName} [-route ns] [-comment textString]
Arguments
timing goal is not met because of long paths from the register. For
an example of its use (on an input register), see Route Option, on
page 340.
The define_reg_output_delay constraint speeds up paths coming from a register

by a given number of nanoseconds. The synthesis tool attempts to meet the
global clock frequency goals for a design as well as the individual clock
frequency goals (set with define_clock). Use this constraint to speed up the
paths coming from a register. For information about the equivalent SCOPE
spreadsheet interface, see Registers (Legacy), on page 343.

September 2016 533
set_datapathonly_delay
Specifies a point-to-point path delay that excludes any applicable I/O delays
or clock delays at the start and end points.
Syntax
set_datapathonly_delay option {value}
In the above syntax, option is one or more of the following:
-disable
-from {port|inst|clock}
-rise_from clock
-fall_from clock
-to {port|inst|clock}
-rise_to clock
-fall_to clock
-comment textsString
In the above options, the variable clock is a clock alias.
Description
The set_datapathonly_delay constraint specifies a point-to-point path delay that
excludes any applicable I/O delays or clock delays at the start and end
points. The constraint includes clock to out (Tco) and setup time (Tsu) as part
of the data path delay.
Use this constraint in Xilinx designs, as the tool only forward-annotates the
constraint for Xilinx designs. The set_datapathonly_delay constraint appears in
the UCF file as a Xilinx TIMESPEC constraint with the DATAPATHONLY option.
The original sdc command is also forward-annotated as a comment. For
example:
# set_datapathonly_delay -from {p:din[*]} -to {i:int[*]} {4}

...
NET "din[7]" TNM = "from_1005_0";
INST "int[*]" TNM = "to_1005_0"; # int[7:0]
TIMESPEC "TS_1005_0" = FROM "from_1005_0" TO "to_1005_0"
LO
DATAPATHONLY 4.000;

534 September 2016
When you specify this constraint, the tool ignores any clock skew or phase
information. It constrains, analyzes, and forward-annotates just the data
path between the specified points.
Object Naming Syntax

This section describes the prefix syntax for identifying objects when different
design objects share the same name. Objects like Verilog modules, VHDL
design units, component instances, ports, and internal nets can have shared
names. The prefix identifiers are used in constraint files to assign timing
constraints and synthesis attributes to the correct object. The syntax varies
slightly, depending on the language used to define the module or component.
The objects in the SCOPE pull-down menus automatically use the correct
prefix, but if you drag and drop an object from an HDL Analyst or other view,
make sure you use the appropriate prefix for the language as described
below:
Verilog Naming Syntax, on page 535
VHDL Naming Syntax, on page 536
Object Naming Examples, on page 537
Verilog Naming Syntax

This section provides syntax for object names in Verilog. No spaces are
allowed in names. You can use the * and ? characters as wildcards in names.
These characters do not match the dot (.) used as a hierarchy separator.
Examples of using wildcards in object names include the following: mybus*,
mybus[??], mybus[*].
Verilog uses the following syntax for module names:
v: cell
v: Identifies a view object
cell The name of the Verilog module
Instance, port, and net names have the following syntax:
cell typespec object_path

September 2016 535
cell The name of the Verilog module
typespec A single letter followed by a colon. The letter can be one of the
following, and is used to determine the kind of object when
objects have the same names:
i: identifies the name of an instance.
p: identifies the name of an entire port (the port itself).
b: identifies the name of a slice of a port (bit-slice of the port).
n: identifies the name of an internal net. This designation is
required for all internal nets.
object_path An instance path with a dot (.) used as a hierarchy separator in
the name. The object path ends with the name of the desired
object.
See Object Naming Examples, on page 537.
VHDL Naming Syntax

This section provides syntax for object names in VHDL. No spaces are allowed
in names. You can use the * and ? characters as wildcards in names. These
characters do not match the dot (.) used as a hierarchy separator. Examples
of using wildcards in object names include the following: mybus*, mybus[??],
mybus[*].
VHDL has the following syntax for design unit names:
v:[lib.]cell [.view]
v: Identifies a view object

lib The name of a library that contains the design unit. The default is the
library containing the top-level design unit.
cell The name of the design unit entity.
view The name of the design unit architecture. The use of view with VHDL
designs is optional; it is required only when the design unit has more
than one architecture.
LO

536 September 2016
Instance, port, and net names have the following syntax:
[ [lib.] cell [ .view] ] | [typespec] objpath
lib The name of a library that contains the design unit. The default
is the library containing the top-level design unit.
cell The name of the VHDL entity.
view The name of the design unit architecture. The use of view with
VHDL designs is optional; it is required only when the design
unit has more than one architecture.
typespec A single letter followed by a colon that is used (if needed) to
resolve the ambiguity of two or more objects in the design that
have the same name. typespec can have the following values:
i: identifies the name of an instance.
p: identifies the name of an entire port (the port itself).
b: identifies the name of a slice of a port (bit-slice of the port).
n: identifies the name of an internal net. This designation is
required for all internal nets.
objpath An instance path using dot (.) as a hierarchy separator. The
object path ends with the name of the desired object.
See Object Naming Examples, on page 537.
Object Naming Examples

To identify all bits of instance statereg in module statemod:
statemod|i:statereg[*]
To identify instances one level of hierarchy from the top with names that
begin with state:
i:*.state*
To identify port mybus[19:0] instead of a driving register that also has the name
mybus[19:0]:
p:mybus[19:0]
To identify top-level port mybus bit 1 instead of a driving register that also has
the name mybus[1]:
b:mybus[1]

September 2016 537
The following shows the constraint file entries that correspond to the previous
source code examples:
define_attribute {statemod|i:statereg[*]} syn_encoding sequential

define_multicycle_path -to {*.*slowreg[*]} 2
LO

538 September 2016
C H A P T E R 11
FPGA Design Constraint Syntax
The following describe the Tcl syntax for the design (non-timing) constraints
specified with a SCOPE editor or entered manually into a constraint file.
These constraints are common between the two supported constraint file
formats.
The remainder of this section describes the constraint file syntax for the
following FPGA design constraints:
define_compile_point, on page 540
define_current_design, on page 541
define_io_standard, on page 542
For information on timing constraints, see either FPGA Timing Constraints,
on page 474 or Synplify-Style Timing Constraints (Legacy), on page 513.

September 2016 539
define_compile_point
The define_compile_point command, available only for the Synplify Pro and
Synplify Premier tools, defines a compile point in a top-level constraint file.
You use one define_compile_point command for each compile point you define.
This is the syntax:
define_compile_point [-disable ] {moduleName}

-type {black_box|soft|hard|locked|locked, partition} [-comment textString ]
-disable Disables a previous compile point definition.
-type Specifies the type of compile point. This can be black_box, soft, hard,
locked, or locked, partition.
Refer to Object Naming Syntax, on page 535 for details about the syntax and
prefixes for naming objects.
Here is a syntax example:
define_compile_point {v:work.prgm_cntr} -type {locked}
LO

540 September 2016
define_current_design
The define_current_design command, available only for the Synplify Pro and
Synplify Premier tools, specifies the module to which the constraints that
follow it apply. It must be the first command in a block-level or compile-point
constraint file. The specified module becomes the top level for objects defined
in this hierarchy and the constraints applied in the respective block-level or
compile-point constraint file.
This is the syntax:
define_current_design {regionName | libraryName.moduleName }
Refer to Object Naming Syntax, on page 535 for details about the syntax and
prefixes for naming objects.
Here is an example:
define_current_design {lib1.prgm_cntr}
Objects in all constraints that follow this command relate to prgm_cntr.

September 2016 541
define_io_standard
Specifies a standard I/O pad type to use for various Microsemi, Altera, and
Xilinx families. See I/O Standards, on page 304 for details of the SCOPE
equivalent.
define_io_standard [-disable] {p:portName} -delay_type input|output|bidir

syn_pad_type {IO_standard} [parameter {value}...]
In the above syntax:
portName is the name of the input, output, or bidirectional port.
-delay_type identifies the port direction which must be input, output, or bidir.
syn_pad_type is the I/O pad type (I/O standard) to be assigned to

portName.
parameter is one or more of the parameters defined in the following

table. Note that these parameters are device-family dependent.
Parameter Function
syn_io_termination The termination type; typical values are pullup
and pulldown.
syn_io_drive The output drive strength; values include low
and high or numerical values in mA.
syn_io_dv2 Switch to use a 2x impedance value.
syn_io_dci Switch for digitally-controlled impedance (DCI).
syn_io_slew The slew rate for single-ended output buffers;
values include slow and fast or low and high.
Example:
define_io_standard {p:DATA1[7:0]} -delay_type input

syn_pad_type {LVCMOS_33} syn_io_slew {high}
syn_io_drive {12} syn_io_termination {pulldown}
LO

542 September 2016
CHAPTER 12
Tcl Find, Expand, and Collections
The FPGA synthesis software includes powerful search functionality in the

Tcl find and expand commands. Objects located by these commands can be
grouped into collections and manipulated. The following sections describe the
commands and collections in detail:
Tcl find Command, on page 544
Tcl Find -filter Command, on page 554
Tcl expand Command, on page 560
Collection Commands, on page 563
Object Query Commands, on page 572
Synopsys Standard Collection Commands, on page 587

September 2016 543
Chapter 12: Tcl Find, Expand, and Collections Tcl find Command
Tcl find Command

The Tcl find command identifies design objects based on specified criteria. Use
this command to locate multiple objects with a common characteristic. If you
want to locate objects that share connectivity, use the expand command
instead of the find command (Tcl expand Command, on page 560).
You can specify the find command from the SCOPE environment or enter it as
a Tcl command. This command operates on the RTL database.
You can define objects identified by find as a group or collection, and operate
on all the objects in the collection at the same time. To do this, you embed the
find command as part of a collection creation or manipulation command to do
this in a single step. The combination of find and collection commands
provides you with very powerful functionality to operate on and manipulate
multiple design objects simultaneously.
The table summarizes where to find detailed information:
For... See...
Command syntax Tcl Find Syntax, on page 545
Syntax details: object Tcl Find Command Object Types, on page 547
types, expressions, case Regular Expressions, Wildcards, and Special
sensitivity, and special Characters, on page 548
characters
Tcl Find Command Case Sensitivity, on page 550
Examples of find syntax Demos and Examples button, accessible from the tool UI
Tcl Find Syntax Examples, on page 550
Filtering find searches by Tcl Find -filter Command, on page 554
property Find Filter Properties, on page 555 in the User Guide
LO

544 September 2016
Tcl find Command Chapter 12: Tcl Find, Expand, and Collections
Tcl Find Syntax

find [-objectType] [ pattern ]
[-in $collectionName | listName]
[-hier] [-hsc separator]
[-regexp] [-nocase] [-exact]
[-print]
[-namespace techview | netlist]
[-flat]
[-leaf]
[-rtl | -tech
[-filter expression]
If used, the -filter option must be specified as the last argument in the
command. Descriptions of each command option are listed alphabetically in
the following table.
Argument Description
-objectType pattern Specifies the type of object to be found: view, inst, port, pin, net or
seq. The object type must be preceded by the appropriate
prefix, as described in Tcl Find Command Object Types, on
page 547.
pattern specifies the search pattern to be matched, and can
include the * and ? wildcard characters.
-exact Disables simple pattern matching. Use it to search for objects
that contain the * and ? wildcard characters. You cannot use
this argument with -nocase or -regexp. See Regular
Expressions, Wildcards, and Special Characters, on page 548
for additional information.
-filter expression Refines the results of find further, by filtering the results by the
specified object property. For details about the syntax, refer to
Tcl Find -filter Command, on page 554.
If you use the -filter option, it must be specified as the last
argument to the find command.
-flat Allows wildcard * to match the hierarchy separator.

September 2016 545
-hier Searches for the pattern from every level of hierarchy, instead
of just the top level. By default, the search occurs from the
top-level hierarchy for the given pattern; this option allows you
to search for the pattern from every level of hierarchy.
When -hier is not specified, the search is limited to the current
view and wildcards do not match the hierarchy delimiter
character. You can still traverse downward through the
hierarchy by adding the delimiter in the pattern. Thus an
asterisk (*) matches any object at the current level, but *.*
matches any object one level below the current view. For more
about wildcard characters, see Regular Expressions,
Wildcards, and Special Characters, on page 548.
-hsc separator Specifies the hierarchy delimiter character. The default is the
dot (.). The dot can be ambiguous if it is used both as a
delimiter and as a normal character. For example, block1.u1
could mean the instance u1 in block1, or a record named
block1.u1.
Use the -hsc separator option to specify an unambiguous
character as the hierarchy delimiter. For example, find -hsc @
[block1@u1] finds the hierarchical instance in the block, while
find -hsc @ [block1.u1] finds the record.
See Tcl Syntax Guidelines for Constraint Files, on page 58 for
more information.
-in Restricts the search to the specified list or collection.
$collectionName|
listName
-leaf Returns only non-hierarchical instances.
-nocase Ignores case when matching patterns. The default is to take

case into account (-case). You cannot use the -nocase argument
with -exact or -regexp. See Tcl Find Command Case Sensitivity,
-namespace Determines the database to search for the find operation.
techview | netlist techview searches the mapped (srm) database. This is the
default.
netlist searches the output netlist.
This option is not available for an RTL view. To select a
database view
LO (srs, srp, or srm) with find in batch mode, use
open_design.

546 September 2016
-print Prints the first 20 results. For a full list of objects found, use
c_print or c_list.
If you specify this command from an HDL Analyst view, the
results are printed to the Tcl window; if you specify it in the
constraint file, the results are printed to the log file, at the
beginning of the Mapper section.
Reported object names have prefixes that identify the object
type, and double quotes around each name to allow for spaces
in the names. For example:
"i:reg1"
"i:\weird_name[foo$]"
"i:reg2"
<<found 233 objects. Displaying first 20 objects. Use
c_print or c_list for all. >>
-regexp Treats the pattern as a regular expression instead of a simple
wildcard pattern. It also uses the == and != filter operators to
compare regular expressions, rather than simple wildcard
patterns. You cannot use this argument with -nocase or -exact.
If you do not specify -regexp, there are only two special
characters that are used as wildcards: * and ?. See Regular
Expressions, Wildcards, and Special Characters, on page 548
for details about regular expressions.
-rtl | -tech Uses the most recently activated RTL or Technology view. If
none are available, it opens a new view. The RTL view is the
default.
Tcl Find Command Object Types

You can specify the following types of objects:
Object Prefix Example Synopsys

view v: v:work.cpu.rtl is the master cell of the cpu entity, rtl lib_cell
(Design) architecture, compiled in the VHDL work library.
inst i: Default object type. i:core.i_cpu.reg1 points to the cell

(Instance) reg1 instance inside i_cpu.
port p: p:data_in[3] points to bit 3 of the primary data_in port

port.
work.cpu.rt1|p:rst is the hierarchical rst port in the cpu
view. This eventually points to all instances of cpu.

September 2016 547
Object Prefix Example Synopsys

pin t: t:core.i_cpu.rst points to the hierarchical rst pin of pin
instance i_cpu.
net n: n:core.i_cpu.rst points to the rst net driven in i_cpu. net
seq i: i:core.i_cpu.reg[7:0] cell
(Seqential
instance)
Regular Expressions, Wildcards, and Special Characters

The Tcl find command significantly differs from a simple Tcl search. A simple
Tcl search does not treat any character, except for the backslash (\), as a
special character, so * matches everything in a string. The Tcl find command
uses various regular expressions and special characters, as shown in the
following table.
Use curly brackets { } or double quotes to prevent the interpretation of special

characters within a pattern, and the backslash to escape a single character.
Syntax Matches...
Meta Characters: Used to match certain conditions in a string

^ At the beginning of the string
$ At the end of the string. Use curly brackets { } or double quotes to prevent
the interpretation of special characters within a pattern.
. Any character. If you want to use the dot (.) as a hierarchy delimiter, you
must escape it with a backslash (\), because it has a special meaning in
regular expressions.
\k Interprets and matches the specified non-alphanumeric character as an
ordinary, non-reserved character (where k is the non-alphanumeric
character). For example, \$ matches a dollar symbol, not the character in
its reserved sense of matching the end of a string. Similarly \.d in a.b.c\.d.e
indicates that c.d must be interpreted as part of the instance name, not as
a hierarchy separator.
\c The specified non-alphanumeric character (where c is the
LO
non-alphanumeric character) when it is used in an escape sequence.
| Equivalent to an OR.

548 September 2016
Syntax Matches...
Character Class: A list of characters to match

[list] Any single character from the list. For example, [abc] matches a lower-case
a, b, or c. To specify a range of characters in the list, use a dash. For
example, [A-Za-z] matches any alphabetical character. Use curly brackets
{ } or double quotes to prevent the interpretation of special characters
within a pattern.
[^list] Characters not in the list. You can specify a range, as described above.
For example, [^0-9] matches any non-numeric character.
\ Used as a prefix to escape special characters like the following: ^ $ \ . | ( ) [ ]
{}?+*
Escape Sequences: Shortcuts for common character classes

\d A digit between 0 and 9
\D A non-numeric character
\s A white space character
\S A non-white space character
\w A word character; i.e., alphanumeric characters or underscores
\W A non-word character
Quantifiers: Number of times to match the preceding pattern

* A sequence of 0 or more matches
If you do not specify -hier, the search is restricted to the current view only.
To traverse downward through the hierarchy, either use the -hier
argument or specify the hierarchical levels to be searched by adding the
hierarchical delimiter to the pattern. For example, *.* matches objects one
level below the current view.
+ A sequence of 1 or more matches
? A sequence of 0 or 1 matches
{N} A sequence of exactly N matches

Use curly brackets to interpret special characters as ordinary characters
within a pattern.
{N,} A sequence of N or more matches
{N,P} A sequence of N through P matches (P included); N<=P

September 2016 549
Tcl Find Command Case Sensitivity

Case sensitivity depends on the rules of the language used to specify the
object. If the object was generated in VHDL, it is case-insensitive; if it was
generated in Verilog, it is case-sensitive. In mixed-language designs, the
case-sensitivity rules for the parent object prevail, even when another
language is used to define the lower-level object.
Verilog
VHDL
A A
i:A.B.Reg - correct i:A.B.Reg - correct
B i:A.b.Reg - correct B i:A.b.Reg - incorrect
i:a.B.Reg - correct i:a.B.Reg - incorrect
Reg Reg i:a.b.Reg - incorrect
i:a.b.Reg - correct
i:A.B.REG - incorrect i:A.B.REG - correct
i:A.B.reg - incorrect i:A.B.reg - correct
Tcl Find Syntax Examples

The following are examples of find syntax:
Example Description
find {a*} Finds any object in the current view that
starts with a
find {a*} -hier -nocase Finds any object that starts with a or A
find -net {*synp*} -hier Finds any net the contains synp
find -seq * -filter {@clock==myclk} Finds any register in the current view that is
clocked by myclk
find -flat -seq {U1.*} Finds all sequential elements at any
hierarchical level under U1 (* matches
hierarchy separator)
find -hier-seq {*} -filter Finds all registers enabled by the ena signal.
@clock_enable==ena
find -hier-seq {*} -filter @slack <{-0.0}

LO Finds all sequential elements with negative
slack.

550 September 2016
Example Description
find -hier-seq {*} -filter {@clock ==clk1} Finds all sequential elements within the clk1
clock domain
find -hier-net {*} -filter {@fanout >20} Finds high fanout nets that drive more than
20.destinations
find -hier-seq * -in $all_inst_coll Finds sequential elements inside the
all_inst_coll collection
find -net -regexp {[a-b].*} Finds all nets in hierarchy a and b. This
means {n:a.*} and {n:b.*}
Use the {} characters to protect patterns that contain [] from Tcl evaluation.
For example, use the following command to find instance reg[4]:
find -inst {reg[4]}
Find Equivalents for UCF Group Commands

The following table shows UCF commands (simple Tcl) and their equivalent
find commands:
UCF Constraint Using find Command

INST *ctrlfifo*" TNM = FIFO_GRP";_ set FIFOS [find hier -inst {i:*ctrlfifo*}]
INST *ctrlfifo" TNM = FIFO_GRP";_ set FIFOS [find hier -inst {i:*ctrlfifo}]
INST ctrlfifo*" TNM = FIFO_GRP";_ set FIFOS [find hier -inst * -filter
@hier_rtl_name == ctrlfifo*]
INST ctrlfifo*hier_inst" TNM = set FIFOS [find hier -inst * -filter
FIFO_GRP";_ @hier_rtl_name == ctrlfifo*hier_inst]
Example: Custom Report Showing Paths with Negative Slack

Use the following commands:
open_design implementation_a/top.srm
set find_negslack[find -hier seq inst {*} -filter @slack <
{-0.0}]
c_print -prop slack -prop view $find_negslack -file negslack.txt
The result of running these commands is a report called negslack.txt:

September 2016 551
Object Name slack view

{i:CPU_A_SOC.CPU.DATAPATH.GBR[0]} -3.264 "FDE"
Example: Custom Report for Negative Slack FFs in a Clock Domain

The following procedure steps through the commands used to find all
negative slack flip-flops with a given clock domain:
1. Create a collection that contains all sequential elements with negative

slack:
set negFF [find -tech -hier -seq {*} -filter @slack < {-0.0}]
2. Create a collection of all sequential elements within the clk clock domain
set clk1FF find -hier -seq * -filter {@clock==clk1}
3. Isolate the common elements in the two collections:
set clk1Slack [c_intersect $negFF $clk1FF]
4. Generate a report using the c_print command:
c_print [find -hier -net * -filter @fanout>=2]

{n:ack1_tmp}
{n:ack2_tmp}
...
{n:blk_xfer_cntrl_inst.lfsr_data[20:14]}
{n:blk_xfer_cntrl_inst.lfsr_inst.blk_size[6:0]}
{n:blk_xfer_cntrl_inst.lfsr_inst.clk_c}
...
Custom Fanout Report Example

The following command generates a fanout report:
% c_print -prop fanout [find -hier -net * -filter @fanout>=2]
This is an example of the report generated by the command:
LO

552 September 2016
Object Name fanout

{n:ack1_tmp} 3
{n:ack2_tmp} 4
...
{n:blk_xfer_cntrl_inst.lfsr_data[14]} 3
...
You can add additional information to the report, by specifying more proper-
ties. For example:
% c_print -prop fanout [find -hier -net * -filter @fanout>=2] -prop

pins
This command generates a report like the one shown below:
Object Name Fanout Pins

{n:ack1_tmp} 3 "t:word_xfer_cntrl_inst.ack1_tmp
t:word_xfer_inst.ack1_tmp"
{n:ack2_tmp} 4 "t:blk_xfer_cntrl_inst.ack2_tmp
t:blk_xfer_inst.ack2_tmp"
{n:adr_o_axb_1} 2 "t:blk_xfer_inst.adr_o_axb_1
t:adr_o_cry_1_0.S t:adr_o_s_1.LI"
...
To save the report as a file, use a command like this one:
c_print -prop fanout [find -hier -net * -filter @fanout>=2]

-prop pins file prop.txt

September 2016 553
Chapter 12: Tcl Find, Expand, and Collections Tcl Find -filter Command
Tcl Find -filter Command

The Tcl find command includes the optional -filter option, which provides a
powerful way to further refine the results of the find command and filter
objects based on properties. See the following for details about the find -filter
command:
Find -filter Syntax, on page 554
Find Filter Properties, on page 555
Find Filter Examples, on page 558
For the Tcl find command syntax, see
Find -filter Syntax

find pattern other_args -filter [!]{@property_name operator value}
! Optional character to specify the negative. Include the !

character if you are checking for the absence of a property;
leave it out if you are checking for the presence of a
property.
@property_name Property name to use for filtering. The name must be
prefixed with the @ character. For example, if clock is the
property name, specify {@clock==myclk}.
operator Evaluates and determines the property value used for the
filter expression. You can use the following operators:
Relational operators: =, <, >, ==, >=, <=
Logical operators: &&, ||, !
value Property value for the property in the filter expression, when
the property has a value. The value can either be an object
name such as myclk in {@clock==myclk}, or a value, such as
60 in {@fanout>=60}.
When specified, the -filter option must be the last option specified for the find
command.
LO

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Tcl Find -filter Command Chapter 12: Tcl Find, Expand, and Collections
Find Filter Properties

The object properties are based on the design or constraint, and are used to
qualify searches and build collections. To generate these properties, open
Project->Implementation Options->Device and enable the Annotated Properties for
Analyst check box. The properties display in the Tcl window when the RTL or
Technology view is active. Some properties are only available in a certain
view. The tool creates .sap and .tap files (design and timing properties,
respectively) in the project folder.
The table below lists the common filter object properties. It does not include
some vendor-specific properties. Use the table as a guide to filter the proper-
ties you want. Here is how to read the columns:
Property Name Property Value HDL View Comment
Common Properties
type view|port|net|instance| All
pin]
View Properties
compile_point locked Tech
is_black_box 1 All
is_verilog 0|1 All
is_vhdl 0|1 All
syn_hier remove|flatten|soft|firm Tech

|hard
Port Properties
direction input|output|inout All
fanout value All Total fanout (integer)
side bottom | top| left | right Tech Xilinx only
Instance Properties
area area_value Tech

September 2016 555

arrival_time value Tech Corresponds to worst
slack
async_reset n:netName All
async_set n:netName All
clock clockName All Could be a list if there

are multiple clocks
clock_edge rise|fall| All Could be a list if there
high|low are multiple clocks
clock_enable n:netName All Highest branch name in
the hierarchy, and
closest to the driver
compile_point locked Tech Automatically inherited
from its view
hier_rtl_name hierInstanceName All
inout_pin_count value All
input_pin_count value All

inst_of viewName All
is_black_box 1 (Property added) All Automatically inherited
from its view
is_hierarchical 1 (Property added) All
is_sequential 1 (Property added) All
is_combinational 1 (Property added) All
is_pad 1 (Property added) All
is_tristate 1 (Property added) All
is_keepbuf 1 (Property added) All
is_clock_gating 1 (Property added) All
is_vhdl 0|1 All Automatically inherited

LO from its view
is_verilog 0|1 All Automatically inherited
from its view

556 September 2016

kind primitive All Tech view contains
For example: inv | and |dff | vendor-specific
mux | statemachine | ...) primitives
location (x, y) Tech Format can differ
name instanceName All
orientation N|S|E|W Tech
output_pin_count value All
pin_count value All
placement_type unplaced | placed All
rtl_name nonhierInstanceName All
slack value Tech Worst slack of all arcs
slow 1 Tech
sync_reset n:netName All
sync_set n:netName All
syn_hier remove|flatten| Tech Automatically inherited

soft|firm|hard from its view
view viewName All
Pin Properties
arrival_time timingValue Tech

are multiple clocks
clock_edge rise|fall| All Could be a list if there
high|low are multiple clocks
direction input|output| All
inout
is_clock 0|1 All

September 2016 557

is_gated_clock 0|1 All Set in addition to
is_clock
slack value Tech
Net Properties
are multiple clocks
is_clock 0|1 All
is_gated_clock 0|1 All Set in addition to

is_clock
Find Filter Examples

The following examples show how find -filter is used to check for the presence
or absence of a property, with the ! character indicating a negative check:
c_print [find -hier -view{ *} -filter Finds all objects that are black
(@is_black_box)] boxes.
c_print [find -hier -view {*} -filter Finds all objects that are not black
(!@is_black_box)] boxes
The following are additional positive check examples:
find * -filter @fanout>8

(Finds all ports, pins, and nets from the top level with a fanout greater than 8)
find * -hier -filter @view!=andv || @view!=orv
(Finds all instances other than andv and orv in the design)
find -hier -inst * -filter @inst_of==statemachine
(Finds all instances of statemachine throughout the hierarchy)
find -hier -inst * -filter @kind==statemachine
(Finds all instances of statemachine throughout the hierarchy)
LO
find -hier -inst {*reg*} -filter @clock==CLK
(Finds all instances throughout the hierarchy with the name reg and that are
clocked by CLK)

558 September 2016
find -hier -net {*} -filter (@fanout > 4)

(Finds all nets throughout the hierarchy that have a fanout greater than 4)
This is another example of a negative check:
find -inst *big* -filter (!@is_black_box && @pin_count > 10

(Finds all instances from the top level that have the name big, are not black boxes,
and have more than 10 pins)
You can also specify Boolean expressions on multiple properties:
find * -filter @pin_count>8 && @slack<0

(Finds all instances from the top level that have more than 8 pins and with
negative slack)

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Chapter 12: Tcl Find, Expand, and Collections Tcl expand Command
Tcl expand Command

The expand command identifies objects based on their connectivity, by
expanding forward from a given starting point.
Tcl expand Syntax

The syntax for the expand command is as follows:
expand [-objectType] [-from object] [-thru object] [-to object] [-level integer]
[-hier] [-leaf] [-seq] [-print]
-from object Specifies a list or collection of ports, instances, pins, or nets for
expansion forward from all the pins listed. Instances and input
pins are automatically expanded to all output pins of the
instances. Nets are expanded to all output pins connected to the
net.
If you do not specify this argument, backward propagation stops
at all sequential elements.
-hier Modifies the range of any expansion to any level below the
current view. The default for the current view is the top level and
is defined with the define_current_design command as in the
compile-point flow.
-leaf Returns only non-hierarchical instances.
-level integer Limits the expansion to N logic levels of propagation. You cannot
specify more than one -from, -thru, or -to point when using this
option.
-objectType Optionally specifies the type of object to be returned by the
expansion. If you do not specify an objectType, all objects are
returned. The object type is one of the following:
-instance returns all instances between the expansion points.
This is the default.
-pin returns all instance pins between the expansion points.
-net returns all nets between the expansion points.
-port returns all top-level ports between the expansion points.
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Tcl expand Command Chapter 12: Tcl Find, Expand, and Collections
-print Evaluates the expand function and prints the first 20 results. If
you use this command from HDL Analyst, these results are
printed to the Tcl window; for constraint file commands, the
results are printed to the log file at the start of the Mapper
section.
For a full list of objects found, you must use c_print or c_list.
Reported object names have prefixes that identify the object
type. There are double quotes around each name to allow for
spaces in the names. For example:
"i:reg1"
"i:reg2"
"i:\weird_name[foo$]"
"i:reg3"
<<found 233 objects. Displaying first 20 objects. Use
c_print or c_list for all. >>
-seq Modifies the range of any expansion to include only sequential
elements. By default, the expand command returns all object
types. If you want just sequential instances, make sure to define
the object_type with the -inst argument, so that you limit the
command to just instances.
-thru object Specifies a list or collection of instances, pins, or nets for
expansion forward or backward from all listed output pins and
input pins respectively. Instances are automatically expanded to
all input/output pins of the instances. Nets are expanded to all
input/output pins connected to the net. You can have multiple
-thru lists for product of sum (POS) operations.
-to object Specifies a list or collection of ports, instances, pins, or nets for
expansion backward from all the pins listed. Instances and
output pins are automatically expanded to all input pins of the
instances. Nets are expanded to all input pins connected to the
net.
If you do not specify this argument, forward propagation stops at
all sequential elements.

September 2016 561
Chapter 12: Tcl Find, Expand, and Collections Tcl expand Command
Tcl expand Syntax Examples

Example Description
expand -hier -from {i:reg1} -to {i:reg2} Expands the cone of logic between two
registers. Includes hierarchical instances
below the current view.
expand -inst -from {i:reg1} Expands the cone of logic from one register.
Does not include instances below the current
view.
expand -inst -hier -to {i:reg1} Expands the cone of logic to one register.
Includes hierarchical instances below the
current view.
expand -pin -from {t:i_and2.z} -level 1 Finds all pins driven by the specified pin.
Does not include pins below the current
view.
expand -hier -to {t:i_and2.a} -level 1 Finds all instances driving an instance.
Includes hierarchical instances below the
current view.
expand -hier -from {n:cen} Finds all elements in the transitive fanout of
a clock enable net, across hierarchy.
expand -hier -from {n:cen} -level 1 Finds all elements directly connected to a
clock enable net, across hierarchy.
expand -hier -thru {n:cen} Finds all elements in the transitive fanout
and transitive fanin of a clock enable net,
across hierarchy.
LO

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Collection Commands Chapter 12: Tcl Find, Expand, and Collections
Collection Commands
A collection is a group of objects. Grouping objects lets you operate on
multiple group members at once; for example you can apply the same
constraint to all the objects in a collection. You can do this from both the
SCOPE editor (see Collections, on page 295) or in a Tcl file.
The following table lists the commands for creating, copying, evaluating,
traversing, and filtering collections, and subsequent sections describe the
collections, except for find and expand, in alphabetical order. For information
on using collections, see Using Collections, on page 672 in the User Guide.
Command Description
Creation
define_collection Creates a collection from a list
set modules Creates a collection

set modules_copy $modules Copies a collection
Creation from Objects Identified by Embedded Commands
Tcl find Command Does a targeted search and finds objects.
Embedding the find command in a collection creation
command first finds the objects, and then creates a
collection out of the identified group of objects.
Tcl expand Command Identifies related objects by expanding from a
selected point. Embedding the expand command in a
collection creation command first finds the objects,
and then creates a collection out of the identified
group of objects.
Operators for Comparison and Analysis
c_diff Identifies differences between lists or collections
c_intersect Identifies objects common to a list and a collection
c_symdiff Identifies objects that belong exclusively to only one

list or collection
c_union Concatenates a list to a collection

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Chapter 12: Tcl Find, Expand, and Collections Collection Commands
Command Description
Operators for Evaluation and Statistics
c_info Prints statistics for a collection
c_list Converts a collection to a Tcl list for evaluation
c_print Displays collections or properties for evaluation
Tcl Collection Commands that

manipulate two or more collections
c_union
c_diff
c_symdiff
c_intersect
c_diff
Identifies differences by comparing collections, or a list and a collection. For

this command to work, the design must be open in the GUI.
Syntax
c_diff $collection1 $collection2 |list -print
This command also includes a -print option to display the result.
LO

564 September 2016
Examples
The following examples combines the set with the c_diff command to create a
new collection that contains the results of the c_diff command. The first
example compares two collections and puts the results in diffCollection:
set diffCollection [c_diff $collection1 $collection2]
The next example compares collection1 to a Tcl list containing one object, and
puts the results in a collection called diffCollection:
%set collection1 {i:reg1 i:reg2}

%set diffCollection [c_diff $collection1 {i:reg1}]
%c_print $diffCollection
{i:reg2}
c_info
Returns specifics of a collection, including database name, number of objects
per type, and total number of objects. You can save the results to a Tcl
variable (array) using the -array name option.
Syntax
c_info $mycollection [-array name]
c_intersect
Defines common objects that are included in each of the collections or lists
being compared.
Syntax
c_intersect $collection1 $collection2 |list -print

September 2016 565
Example
The following example uses the set command to create a new collection that
contains the results of the c_intersect command. The example compares a list
to a collection (myCollection) and puts the common elements in a new collec-
tion called commonCollection:
%set mycollection {i:reg1 i:reg2}

%set commonCollection [c_intersect $mycollection {i:reg1 i:reg3}]
%c_print $intercollection
{i:reg1}
c_list
Converts a collection to a Tcl list of objects. You can evaluate any collection
with this command. If you assign the collection to a variable, you can then
manipulate the list using standard Tcl list commands like lappend and lsort.
Optionally, you can specify object properties to add to the resulting list with
the -prop option:
(object prop_value ... prop_value)...

(object prop_value ... prop_value)
Syntax
c_list $collection|list [-prop propertyName]*
Example
$set myModules [find -view *]
%c_list $myModules
{v:top}{v:block_a}{v:block_b}
%c_list $myModules prop is_vhdl prop is_verilog

Name is_vhdl is_verilog
{v:top} 0 1
{v:block_a} 1 0
{v:block_b} 1 0
LO

566 September 2016
c_print
Displays collections or properties in column format. Object properties are
printed using one or more prop propertyName options.
Syntax
c_print $collection|list [-prop propertyName]* [-file filename]
To print to a file, use the -file option. The following command in a constraint
file prints the whole collection to a file:
c_print file foo.txt $col
Note that the command prints the file to the current working directory. If you
have multiple projects loaded, check that the file is written to the correct
location. You can use the pwd command in the Tcl window to echo the current
directory and then use cd directoryName to change the directory as needed.
Example
%set modules [find view *]
%c_print $modules
{v:top}
{v:block_a}
{v:block_b}
%c_print prop is_vhdl prop is_verilog $modules

Name is_vhdl is_verilog
{v:top}0 1
{v:block_a}1 0
{v:block_b}1 0
c_symdiff
Compares a collection to another collection or Tcl list and finds the objects
that are unique, not shared between the collections or Tcl lists being
compared. It is the complement of the c_intersect command (c_intersect, on
page 565).

September 2016 567
Syntax
c_symdiff $collection1 $collection2 |list -print
Examples
The following example uses the set command together with the c_symdiff
command to compare two collections and create a new collection (symDiffCol-
lection) that contains the results of the c_symdiff command.
set symDiff_collection [c_symdiff $collection1 $collection2]
The next example is more detailed. It compares a list to a collection (collection1)

and creates a new collection called symDiffCollection from the objects that are
different. In this case, reg1 is excluded from the new collection because it is
common to both the list and collection1.
set collection1 {i:reg1 i:reg2}

set symDiffCollection [c_symdiff $collection1 {i:reg1 i:reg3}]
c_list $symDiffCollection
{"i:reg2" "i:reg3"}
You can also use the command to compare two collections:
c_union
Adds collections, or a list to a collection, and removes any redundant

instances. For this command to work, the design must be open in the GUI.
Syntax
c_union $collection1 $collection2 |list -print
The c_union command automatically removes redundant elements. This

command also includes a -print option to display the result.
LO

568 September 2016
Examples
You can concatenate two collections into a new collection using the c_union
and set commands, as shown in the following example where collection1 and
collection2 are concatenated into combined_collection:
set combined_collection [c_union $collection1 $collection2]
The following example creates a new collection called sumCollection, which is

generated by adding a Tcl list with one object (reg3) to collection1, which
consists of reg1 and reg2. The new collection created by c_union contains reg 1,
reg2, and reg3.
%set collection1 [find instance {reg?} print]

{i:reg1}
{i:reg2}
%set sumcollection [c_union $collection1 {i:reg3}]
%c_list $sumcollection
{i:reg1} {i:reg2} {i:reg3}
If instead you added reg2 and reg3 to collection1 with the c_union command, the
command removes redundant instances (reg2), so that the new collection still
consists of reg1, reg2, and reg3.
%set collection1 {i:reg1 i:reg2}

%set sumcollection [c_union $collection1 {i:reg2 i:reg3}]
%c_list $sumcollection
{i:reg1} {i:reg2} {i:reg3}
get_prop
Returns a single property value for each member of the collection in a Tcl list.
Examples
get_prop -prop clock [find -seq *]
get_prop $listExpandedInst -prop rtl_name LOROM32X1inst
get_prop $listExpandedInst -prop location SLICE_X1y36
get_prop $listExpandedInst -prop bel C6LUT
get_prop $listExpandedInst -prop slack 0.678

September 2016 569
define_collection
Creates a collection from any combination of single elements, Tcl lists, and
collections. You get a warning message about empty collections if you define
a collection with a leading asterisk and then define an attribute for it, as
shown here:
set noretimesh [define_collection [find -hier -seq *uc_alu]]

define_attribute {$noretimesh} {syn_allow_retiming} {0}
To avoid the error message, remove the leading asterisk and change *uc_alu
to uc_alu.
Example
set modules [define_collection {v:top} {v:cpu} $mycoll $mylist]
define_scope_collection
The define_scope_collection command combines set and define_collection to create
a collection and assigns it to a variable.
define_scope_collection my_regs {find -hier -seq *my*}
LO

570 September 2016
set
Copies a collection to create a new collection. This command copies the
collection but not the name, so the two are independent. Changes to the
original collection do not affect the copied collection.
Syntax
set collectionName collectionCriteria
set copyName $collectionName
collectionName The name of the new collection.
collectionCriteria Criteria for defining the elements to be included in the collection.

Use this argument to embed other commands, like Tcl find and
expand, as shown in the examples below, or other collection
commands like define_collection, c_intersect, c_diff, c_union, and
c_symdiff. Refer to the these commands for examples.
copyName The name assigned to the copied collection.
$collectionName Name of an existing collection to copy.
Examples
The following syntax examples illustrate how to use the set command:
Use the set command to copy a collection:
set my_mod_copy $my_module
Use the set command with a variable name and an embedded find
command to create a collection from the find command results:
set my_module [find view *]

Use the set command with define_collection to create a collection:
set my_module [define_collection {v:top} {v:cpu} $col_l $mylist]
For more examples of the set command used with embedded Tcl collec-
tion commands, see the examples in c_diff, on page 564, c_intersect, on
page 565c_symdiff, on page 567, c_union, on page 568, and define_col-
lection, on page 570.

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Chapter 12: Tcl Find, Expand, and Collections Object Query Commands
Object Query Commands

The query commands are Synopsys SDC commands from the Desgin
Compiler tool for creating collections of specific object types. Functionally,
they are equivalent to the Tcl find and expand commands (Tcl find Command,
on page 544 and Tcl expand Command, on page 560).
The Synopsys SDC collection commands are only intended to be used in the
the FDC file to create collections of objects for constraints. This section
describes the syntax for the object query commands supported in the FPGA
synthesis tools. For complete documentation on these commands, refer to the
Design Compiler documentation.
all_clocks
all_inputs
all_outputs
all_registers
get_cells
get_clocks
get_nets
get_pins
get_ports
Object Query Commands and Tcl find and expand Commands

The Synopsys get* commands and all* commands are functionally similar to
the the Tcl find and expand commands. The get* commands and all*
commands are better suited to use with constraints and the fdc file, because
they handle properties like @clock better than the Tcl find and expand
commands. In certain cases, the fdc file does not support the find and expand
commands, although you can still enter them in the Tcl window. See Object
Query Commands and Tcl find and expand Commands, on page 572 for
examples.
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Object Query and Tcl find/expand Examples

The following table lists parallel examples that compare how to use either the
Tcl find/expand or the get/all commands to query design objects and set
constraints.
Return the output pins of top-level registers clocked by clkb (e.g. inst1.inst2.my_reg.Q)
all_registers FDC Constraint:
set_multicycle_path {4} -from [all_registers -no_hierarchy -output_pins -clock
[get_clocks {clkb}]]
set_multicycle_path {4} -from [get_pins -of_objects [get_cells * -filter {@clock ==
clkb}] -filter {@name == Q}]
find Tcl Window:

% define_collection [regsub -all {i:([^\s]+)} [join [c_list [find -inst * -filter @clock ==
clkfx]]] {t:\1.Q}]
Return all registers in the design clocked by the rising edge of clock clkfx
set_multicycle_path {3} -to [all_registers -cells -rise_clock [get_clocks {clkfx}]]
set_multicycle_path {3} -to [get_cells -hier * -filter {@clock == clkfx &&
@clock_edge == rise}]
find Tcl Window:

find -hier -inst * -filter {@clock == clkfx && @clock_edge == rise}
Return clock pins of all registers clocked by the falling edge of cklfx
set_multicycle_path {2} -from [all_registers -clock_pins -fall_clock [get_clocks
{clkfx}]]
set_multicycle_path {2} -from [get_pins -of_objects [get_cells -hier * -filter {@clock
== clkfx && @clock_edge == fall}] -filter {@name == C}]
find Tcl Window:

% find -hier -inst * -filter {@clock == clkfx && @clock_edge == fall}
Return the E pins of all instances of dffre cells (e.g. inst1.inst2.my_reg.E)

get_pins FDC Constraint:
set_multicycle_path -to [get_pins -filter {@name == E} -of_objects [get_cells -hier
* -filter {@inst_of == dffre}]
find Tcl Window and FDC Constraint:

% regsub -all {i:([^\s]+)} [join [c_list [find -hier -inst * -filter @inst_of == dffre]]]
{t:\1.E}]

September 2016 573
all_clocks
Returns a collection of clocks in the current design.
Syntax
This is the supported syntax for the all_clocks command:
all_clocks
This command has no arguments. All clocks must be defined in the design
before using this command. To create clocks, you can use the create_clock
command.
Example
The following constraint sets a multicycle path from all the starting points.
set_multicycle_path 3 -from [all_clocks]
all_inputs
Returns a collection of input or inout ports in the current design.
Syntax
This is the supported syntax for the all_inputs command:
all_inputs
Example
The following constraint sets a default input delay.
set_input_delay 3 [all_inputs]
LO

574 September 2016
all_outputs
Returns a collection of output or inout ports in the current design.
Syntax
This is the supported syntax for the all_outputs command:
all_outputs
Example
The following constraint sets a default output delay.
set_output_delay 2 [all_outputs]
all_registers
Returns a collection of sequential cells or pins in the current design.
Syntax
This is the supported syntax for the all_registers command:
all_registers
Example
The following constraint sets a max delay target for timing paths leading to all
registers.
set_max_delay 10.0 -to [all_registers]

September 2016 575
get_cells
Creates a collection of cells from the current design that is relative to the
current instance.
Syntax
This is the supported syntax for the get_cells command:
get_cells
[-hierarchical]
[-nocase]
[-regexp]
[pattern]
Arguments
-hierarchical Searches each level of hierarchy for cells in the design relative to
the current instance. The object name at a particular level must
match the patterns. For the cell block1/adder, a hierarchical
search uses "adder" to find this cell name.
By default, the search is not hierarchical.
-nocase Ensures that matches are case-insensitive. This applies for both
the patterns argument and the filter operators (== and !=).
-regexp Views the patterns argument as a regular expression rather
than a simple wildcard pattern. The behavior of the filter
operators (== and !=)have also been modified to use regular
expression rather than simple wildcard patterns.
When using the -regexp option, be careful how you quote the
patterns argument and filter expression. Rigidly quoting with
curly braces around regular expressions is recommended.
Regular expressions are always anchored; that is, the
expression assumes matching begins at the beginning of the
object name and ends matching at the end of an object name.
You can expand the search by adding ".*" to the beginning or
end of the expressions, as needed.
-filter expressions Filters the collection with the specified expression.
For each cellLOin the collection, the expression is evaluated based
on the cells attributes. If the expression evaluates to true, the
cell is included in the result.

576 September 2016
pattern Creates a collection of cells whose names match the specified

patterns. Patterns can include the * (asterisk) and ? (question
mark) wildcard characters. Pattern matching is case sensitive
unless you use the -nocase option.
Examples
The following example creates a collection of cells that begin with o and refer-
ence an FD2 library cell.
get_cells "o*" -filter "@ref_name == FD2"
The following example creates a collection of cells connected to a collection of

pins.
set pinsel [get_pins o*/cp]

get_cells -of_objects $pinsel
The following example creates a collection of cells connected to a collection of

nets.
set netsel [get_nets tmp]

get_cells -of_objects $netsel

September 2016 577
get_clocks
Creates a collection of clocks from the current design.
Syntax
This is the supported syntax for the get_clocks command:
get_clocks
[-nocase]
[-regexp ]
[pattern | -of_objects objects]
[-include_generated_clocks]
Arguments
-nocase Ensures that matches are case-insensitive. This applies for
both the patterns argument and the filter operators (== and
!=).
operators (== and !=) have also been modified to use regular
When using the -regexp option, be careful how you quote
the patterns argument and filter expression. Rigidly quoting
with curly braces around regular expressions is
recommended. Regular expressions are always anchored;
that is, the expression assumes matching begins at the
beginning of the object name and ends matching at the end
of an object name. You can expand the search by adding
".*" to the beginning or end of the expressions, as needed.
For each clock in the collection, the expression is evaluated
based on the clocks attributes. If the expression evaluates
to true, the clock is included in the result.
pattern Creates a collection of clocks whose names match the
specified patterns. Patterns can include the * (asterisk) and
? (question mark) wildcard characters. Pattern matching is
LO
case sensitive unless you use the -nocase option.
-of_objects objects Creates a collection of clocks that are defined for the given
net or pin objects.

578 September 2016
-include_generated_ Creates a collection of clocks matching the search criteria

clocks and includes any clocks derived or generated from the
source clocks found.
Examples
The following example creates a collection of clocks that match the wildcard
pattern.
get_clocks {*BUF_1*derived_clock*}
The following example creates a collection of clocks that match the given
regular expression.
get_clocks -regexp {.*derived_clock}
The following example creates a collection that includes clka and any gener-
ated or derived clocks of clka.
get_clocks -include_generated_clocks {clka}

September 2016 579
get_nets
Creates a collection of nets from the current design.
Syntax
This is the supported syntax for the get_nets command:
get_nets
[-hierarchical]
[-nocase]
[-regexp | -exact]
[pattern | -of_objects objects]
Arguments
-hierarchical Searches each level of hierarchy for nets in the design relative
to the current instance. The object name at a particular level
must match the patterns. For the net block1/muxsel a
hierarchical search uses muxsel to find this net name.
-nocase Ensures that matches are case-insensitive. This applies for
both the patterns argument and the filter operators (== and
!=).
For any nets
LO in the collection, the expression is evaluated
based on the nets attributes. If the expression evaluates to
true, the net is included in the result.

580 September 2016
pattern Creates a collection of nets whose names match the specified

The patterns and -of_objects arguments are mutually exclusive;
you can specify only one. If you do not specify any of these
arguments, the command uses * (asterisk) as the default
pattern.
-of_objects objects Creates a collection of nets connected to the specified objects.
Each object can be a pin, port, or cell.
Examples
The following example creates a collection of nets connected to a collection of
pins.
set pinsel [get_pins {o_reg1.Q o_reg2.Q}]

get_nets -of_objects $pinsel
The following example creates a collection of nets connected to the E pin of

any cell in the modulex_inst hierarchy.
get_nets {*.*} -filter {@pins == modulex_inst.*.E}

September 2016 581
get_pins
Creates a collection of pins from the current design that match the specified
criteria.
Syntax
This is the supported syntax for the get_pins command:
get_pins
[-hierarchical]
[-nocase]
[-regexp | -exact]
[pattern |-of_objects objects [-leaf]
Arguments
-hierarchical Searches each level of hierarchy for pins in the design relative to
the current instance. The object name at a particular level must
match the patterns. For the cell block1/adder/D[0], a
hierarchical search uses adder/D[0] to find this pin name.
The -regexp and -exact options are mutually exclusive; use
only one.
LO

582 September 2016
-exact Treats wildcards as plain characters, so the meanings of these

wildcard are not interpreted.
The -regexp and -exact options are mutually exclusive; use
only one.
For each pin in the collection, the expression is evaluated based
on the pins attributes. If the expression evaluates to true, the
cell is included in the result.
pattern Creates a collection of pins whose names match the specified
The patterns and -of_objects arguments are mutually exclusive;
you can specify only one. If you do not specify any of these
arguments, the command uses * (asterisk) as the default
pattern.
-of_objects Creates a collection of pins connected to the specified objects.
objects Each object can be a cell or net.
By default, the command considers only pins connected to the
specified nets at the same hierarchical level. To consider only
pins connected to leaf cells on the specified nets, use the -leaf
option.
You cannot use the -hierarchical option with the
-of_objects option.
-leaf Includes pins that are on leaf cells connected to the nets
specified with the -of_objects option. The tool can cross
hierarchical boundaries to find pins on leaf cells.
Examples
The following example creates a collection for all pins in the design.
get_pins -hier *.*
The following example creates a collection for pins from the top-level
hierarchy that match the regular expression.
get_pins -regexp {.*\.ena}
The following example creates a collection for pins throughout the hierarchy
that match the regular expression.
get_pins -hier - regexp {.*\.ena}

September 2016 583
The following example creates a collection of hierarchical pin names for the
library cell pin DQSFOUND, and for each instantiation of a library cell named
PHASER_IN_PHY.
get_pins -filter {@name == DQSFOUND} -of_objects [get_cells -hier

* -filter {@inst_of == PHASER_IN_PHY}]
LO

584 September 2016
get_ports
Creates a collection of ports from that match the specified criteria.
Syntax
This is the supported syntax for the get_ports command:
get_ports
[-nocase]
[-regexp]
[pattern]
Arguments
For each port in the collection, the expression is evaluated
based on the ports attributes. If the expression evaluates to
true, the port is included in the result.
pattern Creates a collection of ports whose names match the specified
The patterns and -of_objects arguments are mutually exclusive,
so only specify one of them. If you do not specify either
argument, the command uses * (asterisk) as the default pattern.

September 2016 585
Examples
The following example queries all input ports beginning with mode.
get_ports mode* -filter {@direction == input}
LO

586 September 2016
Synopsys Standard Collection Commands Chapter 12: Tcl Find, Expand, and Collections
Synopsys Standard Collection Commands

There are a number of Synopsys standard SDC collection commands that can
be included in the fdc file. These commands are not compatible with the
define_scope_collection command.
The collection commands let you manipulate or operate on multiple design

objects simultaneously by creating, copying, evaluating, iterating, and
filtering collections. This section describes the syntax for the following collec-
tion commands supported in the FPGA synthesis tools; for the complete
syntax for these commands, refer to the Design Compiler documentation.
add_to_collection
append_to_collection
copy_collection
foreach_in_collection
get_object_name
index_collection
remove_from_collection
sizeof_collection
Use these commands in the FDC constraint file to facilitate the shared
scripting of constraint specifications between the FPGA synthesis and Design
Compiler tools.

September 2016 587
Chapter 12: Tcl Find, Expand, and Collections Synopsys Standard Collection Commands
add_to_collection
Adds objects to a collection that results in a new collection. The base collec-
tion remains unchanged. Any duplicate objects in the resulting collection are
automatically removed from the collection.
Syntax
This is the supported syntax for the add_to_collection command:
add_to_collection
[collection1]
[objectSpec]
Arguments
collection1 Specifies the base collection to which objects are to be added. This
collection is copied to a resulting collection, where objects matching
objectSpec are added to this results collection.
objectSpec Specifies a list of named objects or collections to add.
Depending on the base collection type (heterogeneous or
homogeneous), the searches and resulting collection may differ. For
more information, see Heterogeneous Base Collection, on page 588
and Homogeneous Base Collection, on page 589.
Description
The add_to_collection command allows you to add elements to a collection. The
result is a new collection representing the objects added from the objectSpec
list to the base collection. Objects are duplicated in the resulting collection,
unless they are removed using the -unique option. If objectSpec is empty, then
the new collection is a copy of the base collection. Depending on the base
collection type (heterogeneous or homogeneous), the searches and resulting
collection may differ.
Heterogeneous Base Collection

If the base collection is heterogeneous, then only collections are added to the
LO
resulting collection. All implicit elements of the objectSpec list are ignored.

588 September 2016
Homogeneous Base Collection

If the base collection is homogeneous and any elements of objectSpec are not
collections, then the command searches the design using the object class of
the base collection.
When collection1 is an empty collection, special rules apply to objectSpec. If

objectSpec is not empty, at least one homogeneous collection must be in the
objectSpec list (can be any position in the list). The first homogeneous collec-
tion in the objectSpec list becomes the base collection and sets the object
class for the function.
Example
set result [get_cells{u*}]
get_object_name $result
==> {u:u1} {i:u2} {i:u3}
set result_1 [add_to_collection $result {get_cells {i:clkb_IBUFG}]
get_object_name $result_1
==> {i:u1} {i:u2} {i:u3} {i:clkb_IBUFG}
See Also

September 2016 589
Adds objects to the collection specified by a variable, modifying its value.
Objects must be unique, since duplicate objects are not supported.
Syntax
This is the supported syntax for the append_to_collection command:
append_to_collection]
[variableName]
[objectSpec]
Arguments
variableName Specifies a variable name. The objects matching objectSpec
are added to the collection referenced by this variable.
objectSpec Specifies a list of named objects or collections to add to the
resulting collection.
Description
The append_to_collection command allows you to add elements to a collection.
This command treats the variableName option as a collection, and appends
all the elements of objectSpec to that collection. If the variable does not exist,
it creates a collection with elements from the objectSpec as its value. So, a
collection is created that was referenced initially by variableName or
automatically if the variableName was not provided. However, if the variable
exists but does not contain a collection, then an error is generated.
The append_to_collection command can be more efficient than the add_to_collec-

tion command (append_to_collection, on page 590) when you are building a
collection in a loop.
LO

590 September 2016
Example
set result [get_cells{u*}]
==> {u:u1} {i:u2} {i:u3}
append_to_collection result {get_cells {i:clkb_IBUFG}]
==> {i:u1} {i:u2} {i:u3} {i:clkb_IBUFG}
See Also
add_to_collection

September 2016 591
copy_collection
Duplicates the contents of a collection that results a new collection. The base
collection remains unchanged.
Syntax
This is the supported syntax for the copy_collection command:
copy_collection
[collection1]
Arguments
collection1 Specifies the collection to be copied.
Description
The copy_collection command is an efficient mechanism to create a duplicate of
an existing collection. It is sometimes more efficient and usually sufficient to
simply have more than one variable referencing the same collection. However,
whenever you want to copy the collection instead of reference it, use the
copy_collection command.
Be aware that if an empty string is used for the collection1 argument, the
command returns an empty string. This means that a copy of the empty
collection is an empty collection.
Example
set insts [define_collection {u1 u2 u3 u4}]
set result_copy [copy_collection $insts]
get_object_name $result_copy
==> {u1} {u2} {u3} {u4}
LO

592 September 2016
Iterates on the elements of a collection.
Syntax
This is the supported syntax for the foreach_in_collection command:
[iterationVariable]
[collections]
[body]
Arguments
iterationVariable Specifies the name of the iteration variable. It is set to a
collection of one object. Any argument that accepts
collections as an argument can also accept the
iterationVariable, as they are the same data type.
collections Specifies a list of collections on which to iterate.
body Specifies a script to execute for the iteration. If the body of

the iteration is modifying the netlist, all or part of the
collection involved in the iteration can be deleted. The
foreach_in_collection command is safe for such operations. A
message is generated that indicates the iteration ended
prematurely.
Description
The foreach_in_collection command is a Design Compiler and PrimeTime
command used to iterate on each element of a collection. This command
requires the following arguments: an iteration variable (do not specify a list),
the collection on which to iterate, and the script to apply for each iteration.
You can nest this command within other control structures, including
another foreach_in_collection command.
You can include the command in an FDC file, but if you are using the Tcl
window and HDL Analyst, you must use the standard Tcl foreach command
instead of foreach_in_collection.

September 2016 593
Example
The following examples show valid methods to reference a collection for this
command:
set seqs[all_registers]
set port[all_inputs]
foreach_in_collection x [all_registers] {body}
foreach_in_collection x $ports {body}
foreach_in_collection x [list $seqs $ports] {body}
foreach_in_collection x {$seqs} {body}
foreach_in_collection x {$seqs $ports} {body}
LO

594 September 2016
get_object_name
Returns a list of names for objects in a collection.
Syntax
This is the supported syntax for the get_object_name command:
get_object_name
[collection1]
Arguments
collection1 Specifies the name of the collection that contains the
requested objects.
Example
set c1[define_collection {u1 u2}]
get_object_name $c1
==> {u1} {u2}

September 2016 595
index_collection
Creates a new collection that contains only the single object for the index
specified in the base collection. You must provide an index to the collection.
Syntax
This is the supported syntax for the index_collection command:
index_collection
[collection1]
[index]
Arguments
collection1 Specifies the collection to be searched.
index Specifies an index to the collection. Allowed values are

integers from 0 to sizeof_collection -1.
Description
You can use the index_collection command to extract a single object from a
collection. The result is a new collection that contains only this object. The
range of indices can be from 0 to one less than the size of the collection. If the
specified index is outside that range, an error message is generated.
Commands that create a collection of objects do not impose a specific order

on the collection, but they do generate the objects in the same, predictable
order each time. Applications that support the sorting of collections allow you
to impose a specific order on a collection.
If you use an empty string for the collection1 argument, then any index to the
empty collection is not valid. This results in an empty collection and gener-
ates an error message.
Be aware that all collections cannot be indexed.
LO

596 September 2016
Example
set c1[get_cells {u1 u2}]]
get_object_name [index_collection $c1 0]
==> {u1}
See Also
sizeof_collection

September 2016 597
Removes objects from a collection that results in a new collection. The base
collection remains unchanged.
Syntax
This is the supported syntax for the remove_from_collection command:
[-intersect]
[collection1]
[objectSpec]
Arguments
-intersect Removes objects from the base collection that are not found
in objectSpec.
By default, when this option is not specified, objects are
removed from the base collection that are found in the
objectSpec.
collection1 Specifies the base collection that is copied to a resulting
collection, where objects matching objectSpec are removed
from this results collection.
objectSpec Specifies a list of named objects or collections to remove.
The object class for each element in this list must be the
same in the base collection. If the name matches an existing
collection, that collection is used. Otherwise, objects are
searched in the design using the object class for the base
collection.
Description
The remove_from_collection command removes elements from a collection and
creates a new collection.
When the -intersect option is not specified and there are no matches for
objectSpec, the resulting collection is just a copy of the base collection. If
LO
everything in the collection1 option matches the objectSpec, this results in an
empty collection. When using the -intersect option, nothing is removed from
the resulting collection.

598 September 2016
Heterogeneous Base Collection

If the base collection is heterogeneous, then any elements of objectSpec that
are not collections are ignored.
Homogeneous Base Collection

If the base collection is homogeneous and any elements of objectSpec are not
collections, then the command searches the design using the object class of
the base collection.
Examples
set c1[define_collection {u1 u2 u3}]]
set c2[define_collection {u2 u3 u4}]]
get_object_name [remove_from_collection $c1 $c2]
==> {u1}
get_object_name [remove_from_collection $c2 $c1]
==> {u4}
get_object_name [remove_from_collection -intersect $c1 $c2]
==> {u2} {u3}
See Also
add_to_collection

September 2016 599
sizeof_collection
Returns the number of objects in a collection.
Syntax
This is the supported syntax for the sizeof_collection command:
sizeof_collection
[collection1]
Arguments
collection1 Specifies the name of the collection for which the number of
objects is requested.
If no collection argument is specified, then the command
returns 0.
Examples
set c1[define_collection {u1 u2 u3}]
sizeof_collection $c1
==> 3
LO

600 September 2016
APPENDIX A
Designing with Altera
The following topics describe how to design and synthesize with different
Altera technologies:
Basic Support for Altera Designs, on page 602
Input for Altera Designs, on page 608
Altera RAMs and ROMs, on page 614
Altera LPMs, on page 617
Altera Optimizations, on page 624
Forward-annotation to Altera Tools, on page 631
Integration with Altera Tools and Processes, on page 633
Stratix Device Families, on page 636
set_option Command for Altera Architectures, on page 639
project Command for Altera Architectures, on page 642
Altera Attribute and Directive Summary, on page 643

September 2016 601
Appendix A: Designing with Altera Basic Support for Altera Designs
Basic Support for Altera Designs

The following topics briefly describe flows, constraints, and attributes
supported by the synthesis tools for Altera designs:
Altera Device Support, on page 602
Synthesis Constraints and Attributes for Altera Designs, on page 602
Altera I/O Standards, on page 602
For information on support in specific areas, see the other sections in this
chapter.
Altera Device Support

The synthesis tools create technology-specific netlists for various Altera FPGA
technologies. New devices are added on an ongoing basis. For the most
current list of supported devices, check the Device panel of the Implementation
Options dialog box and the release notes.
After synthesis, the tool generates netlists that are used as input to the Altera
place-and-route tool. The accepted netlists are updated periodically, so check
the most current version of the place-and-route tool. The software generates
vqm netlist files as input for the Quartus II place-and-route tool.
Synthesis Constraints and Attributes for Altera Designs

The synthesis tools let you specify timing constraints, general HDL attributes,
and Altera-specific attributes to improve your design. You can manage the
attributes and constraints in the SCOPE interface. Altera has vendor-specific
I/O standard constraints it supports for synthesis. For a list of supported I/O
standards, see Altera I/O Standards, on page 602.
Altera I/O Standards

The following tables show the applicable I/O standards for the supported
Stratix families with their equivalent Quartus I/O standards.
LO

602 September 2016
Basic Support for Altera Designs Appendix A: Designing with Altera
Stratix II and Stratix II GX I/O Standards

Synopsys FPGA Quartus I/O Stratix II Stratix II GX
Synthesis I/O Standard Standard
DIFF_HSTL_15_Class_I Differential 1.5-V X X
HSTL Class I
DIFF_HSTL_15_Class_II Differential 1.5-V X X
HSTL Class II
HSTL Class I
DIFF_HSTL_18_Class_II Differential 1.8-V X
HSTL Class II
DIFF_SSTL_18_Class_I Differential 1.8-V X
SSTL Class I
DIFF_SSTL_18_Class_II Differential 1.8-V X X
SSTL Class II
DIFF_SSTL_2_Class_I Differential 2.5-V X X
SSTL Class I
SSTL Class II
HSTL_15_Class_I 1.5-V HSTL X X
Class I
HSTL_15_Class_II 1.5-V HSTL X X
Class II
Class I
Class II
HyperTransport HyperTransport X
LVCMOS_15 1.5V X X
LVCMOS_18 1.8V X X
LVCMOS_25 2.5V X X
LVCMOS_33 3.0-V LVCMOS X X
LVDS LVDS X X

September 2016 603
Synopsys FPGA Quartus I/O Stratix II Stratix II GX

Synthesis I/O Standard Standard
LVPECL Differential X X
LVPECL
LVTTL 3.0-V LVTTL X
PCI33 3.3-V PCI X X
PCI-X_133 3.3-V PCI-X X X
SSTL_18_Class_I SSTL-18 Class I X X
SSTL_18_Class_II SSTL-18 Class II X X
Stratix III and Stratix IV I/O Standards

Synopsys FPGA Synthesis Quartus I/O Stratix III Stratix IV
I/O Standard Standard
1_2 1.2 V X
1_5 1.5 V X
1_8 1.8 V X
2_5 2.5 V X
DIFF_HSTL_12_I Differential 1.2-V X X

HSTL Class I
DIFF_HSTL_12_II Differential 1.2-V X X
HSTL Class II
DIFF_HSTL_15_I Differential 1.5-V X
HSTL Class I
DIFF_HSTL_15_II Differential 1.5-V X
HSTL Class II
DIFF_HSTL_15_Class_I Differential 1.5-V X
HSTL Class I
LO
DIFF_HSTL_15_Class_II Differential 1.5-V X
HSTL Class II

604 September 2016

HSTL Class I
DIFF_HSTL_18_Class_II Differential 1.8-V X X
HSTL Class II
DIFF_SSTL_15_I Differential 1.5-V X
SSTL Class I
DIFF_SSTL_15_II Differential 1.5-V X
SSTL Class II
DIFF_SSTL_15_Class_I Differential 1.5-V X
SSTL Class I
DIFF_SSTL_15_Class_II Differential 1.5-V X
SSTL Class II
SSTL Class I
SSTL Class II
SSTL Class I
SSTL Class II
HCSL HCSL X
HSTL_12_I 1.2-V HSTL X X

Class I
HSTL_12_II 1.2-V HSTL X X
Class II
Class I
Class II
Class I
Class II

September 2016 605

LVCMOS 3.0-V LVCMOS X
LVCMOS_12 1.2 V X
LVCMOS_15 1.5 V X
LVCMOS_18 1.5 V X
LVCMOS_25 2.5 V X
LVCMOS_33 3.3-V LVCMOSV X
LVDS LVDS X
LVDS_E_1R LVDS_E_R1 X X
LVDS_E_3R LVDS_E_3R X X
LVPECL Differential X
LVPECL
LVTTL 3.0-V LVTTL X
LVTTL_33 3.3-V LVTTL X
MINI_LVDS mini-LVDS X
MINI_LVDS_1R mini-LVDS_1R X X
MINI_LVDS_3R mini-LVDS_3R X X
PCI 3.0-V PCI X X
PCI_X 3.0-V PCI-X X X
PCML_12 1.2-V PCML X
RSDS RSDS X
RSDS_E_1R RSDS_E_1R X X
LO
RSDS_E_3R RSDS_E_3R X X
SSTL_15_I SSTL-15 Class I X X

606 September 2016

SSTL_15_II SSTL-15 Class II X X
See Also:
Industry I/O Standards, on page 308 for a list of industry I/O
standards.
Altera Attribute and Directive Summary, on page 643 for a list of Altera
attributes and directives.

September 2016 607
Appendix A: Designing with Altera Input for Altera Designs
Input for Altera Designs

The following describe how to handle different kinds of input to Altera
designs:
Altera Verilog Libraries, on page 608
Altera VHDL Libraries, on page 608
IP Core Support, on page 608
QSF Constraints, on page 609
Initial Values for Altera RAMs, on page 609
Altera Verilog Libraries

The synthesis tool automatically loads the Altera library files, so you do not
need to add these files to your project file. To automatically load other
common and family-specific Verilog libraries, select the correct Quartus II
place-and-route tool version from the drop-down menu on the Implementation
Results tab of the Implementation Options dialog box. The Altera macro files are in
installDirectory/lib/altera/quartusVersion.
Altera VHDL Libraries

The Altera macro files are in installDirectory/lib/altera/quartusVersion. Unlike Verilog
designs where the appropriate macro files automatically become available
when you select the Quartus version, in VHDL designs you must manually
specify a non-default library by adding a line to the prj file.
The following example shows the syntax to be added to the prj file to link in a
user-instantiated LPM component called compinv.vhd from the Quartus II 9.0
library, when Quartus II 8.1 is the default library for the design:
add_file -vhdl -lib X:/Altera/quartus_II90/quartus/lpm

"./compinv.vhd"
IP Core Support
In a typical design flow, IP is LO
instantiated as black boxes in the VHDL/Verilog
source. EDIF files for these modules are supplied to the place-and-route tool
to complete the design. This design flow has the following limitations:

608 September 2016
Input for Altera Designs Appendix A: Designing with Altera
The Synopsys FPGA software does not have timing models for the black
boxes which limits its capability to perform realistic timing analysis and
optimizations on the remainder of the design. Although you can add
timing models for black boxes, this process is tedious and error prone
even for very small blocks.
The Synopsys FPGA software does not have resource usage summaries
for the black boxes, which limits its capability to correctly report the
resources needed for the complete design. Without this information,
optimizations including RAM/ROM to block RAM mapping and clock
buffer insertion cannot be effectively performed.
The following briefly describe how to work with various kinds of Altera IP:
Stratix The synthesis software can implement megafunctions generated by

Clearbox the Altera Megawizard tool as Clearboxes. It uses the underlying
Megafunctions structural information from the Clearbox model for timing and
resource allocation. For details of this flow, see Implementing
Megafunctions with Clearbox Models, on page 798 of the User
Guide.
Grey Box You can incorporate encrypted IP as grey boxes in your Altera
Megafunctions designs. The synthesis tool uses the grey box netlist information for
timing and resource allocation, but does not include the grey box in
the output. For details of the procedure, see Implementing
Megafunctions with Greybox Models, on page 808 in the User
Guide. You can also import the megafunction as an IP package
(Including Altera MegaCore IP Using an IP Package, on page 814 in
the User Guide), but it is recommended that you use the grey box
netlist method instead.
QSF Constraints
The synthesis tools include functionality to translate Altera QSF constraints
to the SDC format. See Altera qsf2sdc Utility, on page 392 in the User Guide
for details.
Initial Values for Altera RAMs

You can specify startup values for RAMs in Altera designs. See Initializing
RAMs, on page 459 in the User Guide for step-by-step procedures on setting
initial values in Verilog or VHDL code.

September 2016 609
Appendix A: Designing with Altera Altera Components
Altera Components
The following topics describe how the Certify handles various Altera compo-
nents, and show you how to work with or manipulate them during synthesis
to get the results you need:
Altera Macros, on page 610
Altera Black Boxes, on page 611
Altera LPMs, on page 617
Altera Multipliers, on page 611
Special Registers in Altera Designs, on page 611
Altera PLLs, on page 612
Stratix ShiftTaps, on page 612
Altera Pad Cells, on page 612
See Altera RAMs and ROMs, on page 614, Altera LPMs, on page 617, and
DSP Blocks, on page 618 for information about other Altera components.
Altera Macros
You can select macros from the Altera library of predefined macros and
instantiate them as black boxes. You can instantiate global buffers for clocks,
resets, sets, and other heavily loaded signals. Make sure to use the appro-
priate macro library, located in the installDirectory/lib/altera directory. You can
have Verilog or VHDL macros in Altera designs. Refer to the Altera documen-
tation for supported macros.
LO

610 September 2016
Altera Components Appendix A: Designing with Altera
Verilog For Verilog designs, the tool automatically adds the Verilog component
declaration file for the target technology to your project from the
lib/altera/quartusVersion directory. To make sure that the correct version of
the component declaration file is included, select the version of Quartus
that you intend to use from the Implementation Results tab of the
Implementation Options panel.
For example, if you are using Stratix III with Quartus 11.1, select Quartus
II 11.1 from the drop-down menu to use the stratixiii.v file from the
quartus_II111 directory to access the port and parameter definitions for the
primitives.
VHDL For VHDL designs, instantiate Altera VHDL macro library elements as
predefined black boxes into your design. Add the following library and use
clauses to the top of the source files in which you instantiate the macros:
library family ;
use altera.family.all;
In this example, family is the name of the library family such as stratixiigx
(for a list of family names, see the location.map file in the /lib/vhd directory).
Altera Black Boxes

You can create an instance of any externally defined macro, including a
user-defined macro or Altera macro such as an I/O or flip-flop, by instanti-
ating a black box in your Verilog or VHDL source code. These black boxes are
empty Verilog module descriptions and VHDL component declarations. For a
procedure to instantiate black boxes, see Defining Black Boxes for Synthesis,
Altera Multipliers
Use the syn_multstyle attribute if you need to allocate the multiplier resources
in your design. Set it to lpm_mult to infer LPM functions, and block_mult to infer
DSP blocks.
Special Registers in Altera Designs

The compiler can infer additional register primitive types so that the mapper
can implement a better solution, when it targets Altera technologies:

September 2016 611
Appendix A: Designing with Altera Altera Components
Registers with The compiler identifies and extracts clock-enable logic for
clock enables registers. The RTL view displays registers with enables as
special primitives with an extra pin for the enable signal. The
special primitives are dffe, dffre, dffse, dffrse, dffpatre and dffpatrse.
Set syn_direct_enable in the HDL source file (not in the SCOPE
spreadsheet or a constraint file) to direct the compiler to infer
desirable clock enables. For further syntax details see
syn_direct_enable, on page 54. By default, registers without
clock enables will be inferred.
Registers with The compiler identifies and extracts registers with synchronous
synchronous sets and resets, and passes them to the mapper. The special
sets/resets primitives are sdffr, sdffs, sdffrs, sdffpat, sdffre, sdffse and sdffpate.
The compiler does this automatically and does not require a
directive.
Altera PLLs
The synthesis software recognizes Altera PLL components, or altplls. You
generate the component files with the Altera Megawizard tool and then add
constraints before you synthesize. For details of the procedure, see Working
with Altera PLLs, on page 723 of the User Guide.
Stratix ShiftTaps
The synthesis tools can implement shift registers with taps as ShiftTap
megafunctions in Stratix designs. A ShiftTap is a parameterized array of shift
registers with intermediate tap points. This configuration is inferred as the
Stratix megafunction altshift_tap in the vqm or vm file that Quartus maps into
either altsyncram or registers. see Initializing Xilinx Select RAM, on page 468 of
the User Guide for information on implementing these components.
Altera Pad Cells

The synthesis tools automatically insert pad cells when known primitives
(lcell, register, ram_block, mlab, MAC) are connected to top-level ports. However,
the tool does not insert pad cells when the pins of a black box or Quartus
megafunction with unknown contents are connected to top-level ports. If the
black box or Megafunction already contains pad cells, this prevents double
pad cell failures during P&R. LO

612 September 2016
Altera Components Appendix A: Designing with Altera
To override this behavior and insert pad cells on black boxes or megafunc-
tions, include an enable_io_map.txt file in the implementation directory. This
file specifies how you want to handle pad cells, and uses the following syntax
to do so:
To insert all pad cells, use... cellName, any
To insert a pad cell on a specific pin, use... cellName, pinName
To insert pad cells on all inputs, use... cellName, input
To insert pad cells on all outputs, use... cellName, output
For example:
altsyncram, any
test0, in0
test1, input
test2, output

September 2016 613
Appendix A: Designing with Altera Altera RAMs and ROMs
Altera RAMs and ROMs

The following describe how the synthesis tools infer and implement Altera
RAMs and ROMs. For information about other Altera components, see Altera
Components, on page 610.
Instantiating RAMs with SYNCORE, on page 616
Stratix III and Stratix IV RAMs with Control Signals, on page 615
Altera ROMs, on page 615
See Altera Components, on page 610, Altera LPMs, on page 617, and DSP
Blocks, on page 618 for descriptions of other Altera components.
Altera RAMs
From the HDL source code, the synthesis tool automatically infers RAMs and
generates single-port, dual-port, or multi-port RAMS. This section contains
an overview; for details refer to the RAM inference sections in Chapter 9, RAM
and ROM Inference.
Stratix RAMs
This table describes RAM inference for Stratix devices. For Stratix II,
Stratix III, and Stratix IV devices, RAMs are mapped to Stratix II, Stratix III,
or Statix IV RAM blocks (for earlier Stratix families, RTL RAMs are extracted
to the altsyncram mega function).
RAMs with... Mapped to...

Synchronous read and write RAM. The read operation can be synchronized by
registering either the read address or the output of
the RAM.
Asynchronous read or write Logic
Only one address bus RAM (generally in single-port mode)
However, because old data cannot be obtained in
single-port mode, whenever only the output of a RAM
is registered, the RAM is mapped in dual-port mode.
LO

614 September 2016
Altera RAMs and ROMs Appendix A: Designing with Altera
RAMs with... Mapped to...

Two address buses (one RAM (dual-port mode)
each for read and write) Glue logic is created if new data must be obtained in
dual-port mode. You can disable the creation of glue
logic by setting the syn_ramstyle value to no_rw_check.
Two address buses, (one for RAM (in BIDIR mode)
read and write, the other for
read only)
You can also use the syn_ramstyle attribute (syn_ramstyle, on page 199) to
map the RAM to particular resources. For example:
Stratix II, Stratix II GX MRAM, M4K, M512

Stratix III, Stratix IV M144K, M9K
For information on ROM inference for Stratix, see Altera ROMs, on page 615.
Stratix III and Stratix IV RAMs with Control Signals

The enable pins on Altera Stratix III and Stratix IV RAM blocks provide
built-in functionality for control signals. You can set up your Verilog VHDL
code so that the synthesis tool extracts control signals for single-port and
simple dual-port RAMs with a single common clock, and maps the logic to
Stratix III and Stratix IV LutRAMs instead of registers. This avoids inferring
extra logic, and improves resource utilization and QOR. The control signals
can be read enables, write enables and clock enables.
Altera ROMs
ROMs that would normally be implemented as logic can be implemented as
RAMs (or EABs or ESBs). See syn_romstyle (Altera), on page 217 for syntax
details.

September 2016 615
Appendix A: Designing with Altera Altera RAMs and ROMs
The following table shows how ROMs are inferred and implemented in
different Altera technologies.
Technology Synthesis infers... Implementation

Stratix II technology_ram_block RAM. A synchronous ROM can have any
Stratix II GX RAM primitive (for of the following configurations:
Stratix III synchronous ROMs Only read address registered
Stratix IV only).
Only ROM output registered
Both read address and ROM output
registered
Each register can optionally have an
asynchronous clear (aclr) and/or clock
enable (clken) control signal. When the
read address register has an aclr, the aclr
is moved to the output of the ROM,
because in these technologies a RAM core
does not allow an asynchronous reset of
the read address.
When only the ROM output is registered,
the synthesis tool automatically retimes
the output register of the ROM to its
address inputs during the mapping
phase.
Stratix III and MLAB RAM. Asynchronous ROM are mapped to
newer families MLAB resources.
From your HDL source code, the synthesis tool automatically infers ROMs
and maps them to RAM primitives.
Instantiating RAMs with SYNCORE

The SYNCORE Memory Compiler is available under the IP Wizard to help you
generate HDL code for your specific RAM implementation requirements. For
information on using the SYNCORE Memory Compiler, see Specifying RAMs
with SYNCore, on page 507 in the User Guide.
LO

616 September 2016
Altera LPMs Appendix A: Designing with Altera
Altera LPMs
The Altera Library of Parameterized Modules (LPMs) contains
technology-independent logic functions parameterized for scalability and
adaptability. The library is derived from LPM version 2.2.0, which offers
architecture-independent design entry for all Quartus II-supported devices.
For step-by-step procedures, see Working with LPMs, on page 475 in the User
Guide.
There are three methods for instantiating Altera LPMs:

As black boxes (Verilog or VHDL). Start by defining the LPM using the
Altera MegaWizard megafunction coding style. For synthesis, set the
LPM as a black box and instantiate it in your design. Supply the original
LPM megafunction file along with the vqm file as input for the
place-and-route tool. See Instantiating Altera LPMs as Black Boxes, on
page 476 in the User Guide for details.
Using the Verilog LPM library provided. See Instantiating Altera LPMs
Using a Verilog Library, on page 481 in the User Guide for a procedure.
Using the provided VHDL prepared components that are provided (see
Prepared LPM Components Provided by Synopsys (VHDL), on page 617
for a list). Prepared LPM Components use generics instead of attributes
to specify different design parameters. You instantiate the components
and assign (map) the ports and the values for the generics. Refer to the
Altera place-and-route documentation for ports and generics that
require mapping. See Instantiating LPMs Using VHDL Prepared Compo-
nents, on page 479 in the User Guide for a detailed procedure.
Prepared LPM Components Provided by Synopsys (VHDL)

The following VHDL prepared LPM components are provided by Synopsys.
Their VHDL source code definitions are in the installDirectory/lib/vhd/lpm.vhd file.
altcam_syn altcdr_rx altcdr_tx altclklock

altclklock_syn altddio_bidir altddio_out altdpram
altlvds_rx altlvds_tx altqpram csfifo
dcfifo lpm_abs lpm_add_sub lpm_and
lpm_bustri lpm_clshift lpm_compare lpm_components

September 2016 617
Appendix A: Designing with Altera DSP Blocks
lpm_constant lpm_counter lpm_decode lpm_divide

lpm_ff lpm_fifo lpm_fifo_dc lpm_inv
lpm_latch lpm_mult lpm_mux lpm_ram_dp
lpm_ram_dq lpm_ram_io lpm_or lpm_rom
lpm_shiftreg lpm_xor scfifo
DSP Blocks
Altera Stratix devices have dedicated DSP blocks that can be configured as
multipliers, multiplier adders or multiplier accumulators. The DSP blocks are
specified in a vqm netlist file as the Altera mega functions altmult_add,
altmult_accum, and lpm_mult. Structural VHDL and Verilog simulation netlists
also contain these functions.
The synthesis tools automatically recognize and extract these functions, then
pass them to Quartus II, which maps them directly to the dedicated DSP
blocks. This section describes the following:
DSP Block Inference, on page 618
Attributes and Directives for DSP Block Inference, on page 621
Synchronous and Asynchronous Reset Packing for DSP Blocks, on
page 622
Formal Verification with DSP Blocks, on page 623
DSP Block Inference

The following table summarizes when DSP blocks are inferred.
LO

618 September 2016
DSP Blocks Appendix A: Designing with Altera
Configuration The synthesis tool implements...

Multiply-only mode
A standalone signed or unsigned The lpm_mult megafunction
multiplier:
x = a*b;
It can be one of the following:
36x36-bit multiplier (36-bit
inputs, at most)
18x18-bit multiplier (18-bit
inputs, at most)
9x9-bit multiplier (9-bit inputs, at
most)
Multiply-add mode without input shift register
2, 3, or 4 multipliers (all signed or The altmult_add mega function.
all unsigned) feeding an adder. The The multiplier inputs and outputs can be
outputs of the second and/or registered. The output of the final adder can
fourth multipliers can be negated. also be registered. The registers can have an
x = a*b + c*d; asynchronous reset and/or enable. A
x = a*b - c*d; maximum of four clocks (with or without
x = a*b + c*d + e*f; enables) and four asynchronous resets can
x = a*b - c*d + e*f; be used in an altmult_add to control the
x = a*b + c*d - e*f; registers.
x = a*b - c*d - e*f; The width of each multiplier bus is rounded
x = (a*b + c*d) + (e*f + g*h); up to the next highest multiple of 9 bits, and
x = (a*b - c*d) + (e*f + g*h); the larger of the two widths is taken as the
x = (a*b + c*d) + (e*f - g*h); size of the multiplier. Unused most
x = (a*b - c*d) + (e*f - g*h); significant bits (MSBs) are automatically sign
extended.
Multiply-add with non-multiplier
input. For example: Transformed and packed into a multiply-add
DSP block by multiplying the input variable
a*b + c
by 1.
a*b + c*d + e
a*b + c + d a*b + c*1
a + b*c a*b + c*d + e*1
a*b + c + d + e*f a*b + c*1 + d*1
a*1 + b*c
a*b + c*1 + d*1 + e*f

September 2016 619

Multiply-add mode with input shift register
Scan chains are formed in one of The altmult_add mega function when possible.
these ways: It implements the altmult_add megafunction
Plain multiplier input registers for scan chains formed by the input registers
Input registers followed by adder of a multiplier, regardless of whether it is
followed by an adder.
Scan chain formed by the input
register of an accumulator. The tool implements the altmult_accum
megafunction for scan chains formed by the
A DSP block has a scan chain when input registers of an accumulator.
a multiplier register is driven by the
output of the input register of
another multiplier. The start of a
scan chain is an input register
driven by external signals.
The final multiplier input registers
can have scan-outs, which can be
used to drive only another
multiplier input register that can go
into another DSP block.
Multiply-accumulate mode with synchronous load
The altmult_accum mega function whenever
possible.
The accumulator is loaded with the output of
a multiplier without first clearing the
accumulator. The synchronous load data
must come from the same source feeding the
adder. The source must be a non-negated
multiplier; it can be signed or unsigned,
registered or unregistered.
LO

620 September 2016

Multiply-accumulate mode without sload_mux
1 multiplier driving an accumulator The altmult_accum mega function.
x = x + a*b; The multiplier can be signed or unsigned.
x = x - a*b; The multiplier input and outputs can be
registered. The accumulator register can
have an asynchronous reset and/or enable.
The accumulator width can be between 4 and
52; the multiplier width must be between 4
and 18.
The width of each multiplier bus is rounded
up to the next highest multiple of 9 bits, and
the larger of the two widths is taken as the
size of the multiplier. Unused most
significant bits (MSBs) will automatically be
set to zero, sign extended.
Attributes and Directives for DSP Block Inference

DSP block inference is influenced by the following attributes and directives:
syn_useioff Registers with either of these attributes are not packed into MACs.
syn_preserve
syn_keep A syn_keep directive between the adder and the multiplier prevents
inference of multipliers altmult_add and altmult_accum, but not plain
multipliers.
syn_multstyle This attribute is used to choose between an LPM implementation
(Stratix only) and logic. The default implementation uses dedicated multiplier
blocks (MAC); you specify logic or lpm_mult for alternative
implementations. A multiplier with syn_multstyle attribute value of
logic is mapped to logic, not packed into a MAC.

September 2016 621
Synchronous and Asynchronous Reset Packing for DSP Blocks

The software packs asynchronous and synchronous resets into the Altera
DSP block. The following code is an example of packing asynchronous resets.
library ieee;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity rst_sync is
port(
clk,rst : in std_logic;
Port_In : in std_logic_vector(15 downto 0);
Port_In1 : in std_logic_vector(15 downto 0);
Port_Out : out std_logic_vector(31 downto 0) );
end rst_sync;
architecture rtl of rst_sync is
signal dly,dly1,dly2,dly3 : std_logic_vector(15 downto 0);
signal mult1, mult2 : std_logic_vector(31 downto 0);
signal dly_mult1, dly_mult2 : std_logic_vector(31 downto 0);
signal sum : std_logic_vector(31 downto 0);
begin
process(clk)
begin
if (rst='1') then
dly <= (others => '0');
dly1 <= (others => '0');
dly2 <= (others => '0');
dly3 <= (others => '0');
else
dly <= Port_In;
dly1 <= Port_In1;
dly2 <= Port_In2;
dly3 <= Port_In3;
end if;
end if;
end process;
LO
mult1 <= dly * dly1;
mult2 <= dly2 * dly3;

622 September 2016
process(clk)
begin
if (rst='1') then
dly_mult1 <= (others => '0');
dly_mult2 <= (others => '0');
else
dly_mult1 <= mult1;
dly_mult2 <= mult2;
end if;
end if;
end process;
sum <= dly_mult1 + dly_mult2;
process(clk)
begin
if (rst='1') then
Port_Out <= (others => '0');
else
Port_Out <= sum;
end if;
end if;
end process;
end rtl;
Formal Verification with DSP Blocks

When formal verification is enabled, the DSP block maps to LPM_MULT. See
Altera Optimizations, on page 624 for more information.

September 2016 623
Appendix A: Designing with Altera Altera Optimizations
Altera Optimizations
This section describes optimizations that are specific to Altera.
Core Voltage, on page 624
Fanout Limits in Altera Designs, on page 624
I/O Insertion in Altera Designs, on page 626
Pipelining in Altera Designs, on page 626
Retiming in Altera Designs, on page 627
Altera Gated Clocks, on page 627
Altera Generated Clocks, on page 627
Sequential Optimizations in Altera Designs, on page 627
Verification Mode in Altera Designs, on page 628
Core Voltage
You can specify a core voltage value for Stratix III parts. See Specifying Core
Voltage in Stratix III Designs, on page 727 in the User Guide for details.
Fanout Limits in Altera Designs

Large fanouts can cause large delays and routability problems. The synthesis
tool maintains reasonable fanouts automatically, and also allows you to
specify maximum fanouts. There are two ways to specify fanout limits: the
Fanout Guide option and the syn_maxfan attribute (see Fanout Limits in Altera
Designs, on page 624).
The software first reduces fanout by replicating the driver of the high fanout
net and splitting the net into segments. This replication can affect the
number of register bits in your design. If replication is not possible, the
signals are buffered. Buffering increases intrinsic delay and consumes more
resources, and is therefore not used until a slightly higher fanout limit has
been reached than is specified. You might want to instantiate global buffers
for clocks with high fanouts to save resources.
LO
Click View Log to display the net buffering report in the log file. The report
shows how many nets were buffered or had their sources replicated, and the
number of segments created for the net.

624 September 2016
Altera Optimizations Appendix A: Designing with Altera
Fanout Guide Option

To access this option, select Project->Implementation Options->Device. Specify an
integer value for Fanout Guide. During technology mapping, the synthesis tool
tries to keep the fanout to less than the specified fanout guide. However, this
value is only a guideline, not a hard limit. This means that the synthesis tool
might not always respect it, if the limit imposes constraints that interfere
with optimization.
The syn_maxfan attribute for Altera Designs

The syn_maxfan attribute controls the maximum fanout of an instance, net, or
port. The limit specified by this attribute is treated as a hard or soft limit
depending on where you specify it. The following rules determine how the tool
treats the fanout limit
A global fanout limit serves as a soft limit (or guide) and may not be
honored if the limit degrades performance. You set a global fanout limit
either by setting it as an implementation option (Fanout Guide) or by
specifying the syn_maxfan attribute on a top-level module or view.
A syn_maxfan attribute applied on a module or view serves as a soft limit
for the scope of the module. The module fanout limit overrides the global
fanout guide limit for the scope of the module.
When you specify a syn_maxfan attribute on an instance that is not a
primitive as inferred by the compiler, the limit serves as a soft limit and
can be propagated down the hierarchy.
When you specify a syn_maxfan attribute on a port, net, or register (or any
primitive instance), the limit is considered a hard limit. Note that the
syn_maxfan attribute does not prevent the instance from being optimized
away. Note that any design rule violations that result from buffering or
replication are the responsibility of the user.
Buffering vs Replication
The fanout of an instance or a net can be reduced by either replicating the
driver of the net that violates the maxfan limit or by creating a buffer tree.
Replication or buffering depends on where the syn_maxfan attribute is speci-
fied and also on other attributes such as syn_replicate. The set of rules given
below describes when the software replicates or creates a buffer tree.
When a syn_maxfan attribute is set on a port or on a net driven by a port
(or an I/O pad), a buffer tree is always created to honor the maxfan limit.

September 2016 625
When the value of syn_replicate is 0, the software creates a buffer tree.

Note that the syn_replicate attribute must be used in conjunction with the
syn_maxfan attribute; if not, syn_replicate has no meaning. The syn_replicate
attribute is used only to turn off the replication.
When a syn_keep or syn_preserve attribute is specified on a net driver, a
buffer tree is created.
When a net driver is not a primitive gate or register, a buffer tree is
created. (only registers and ATOMs are replicated).
I/O Insertion in Altera Designs

I/O pads are automatically inserted into the design, unless you disable it. If
you manually instantiate I/Os, I/Os are inserted only for the pins that need
them.
If you do not want to insert any I/Os in the design, enable the Disable I/O Inser-
tion check box (Project->Implementation Options->Device). This is useful for
bottom-up compiles, because you can check the area your logic blocks use
before you synthesize the whole design. If you disable I/O insertion, you will
not get any I/Os in the design unless you manually instantiate them.
Register Packing in Altera Designs

When a register drives an output, or an input drives a register, you can pack
the register into the I/O. You can use the syn_useioff attribute to control
register packing. See Packing I/O Cell Registers, on page 725 in the User
Guide for the procedure.
Pipelining in Altera Designs

Pipelining allows designs with multipliers to operate at a faster frequency by
moving registers after a multiplier into the multiplier. If you have suitable
registers, the software can automatically pipeline multipliers.
You enable/disable pipelining with the Pipelining device mapping option

(Project->Implementation Options->Device) or by setting the syn_pipeline attribute
(syn_pipeline, on page 192).
LO

626 September 2016
Altera Optimizations Appendix A: Designing with Altera
Retiming in Altera Designs

Retiming is the process of automatically moving registers (register balancing)
across combinational gates/LUTs to improve timing, while ensuring identical
logic behavior.
You enable/disable global retiming with the Retiming device mapping option
(Project->Implementation Options->Device). You can use the syn_allow_retiming attri-
bute in Synplify Premier to enable or disable retiming for individual flip-flops.
Pipelining is automatically enabled when retiming is enabled. Use the

syn_pipeline attribute (syn_pipeline, on page 192) to control pipelining. See the
Synplify Premier User Guide for a procedure.
Altera Gated Clocks

The Clock Conversion option (Implementation Options->Prototyping Tools) converts
gated clocks by extracting the enable logic from the clock path. Extracting the
enable logic lets clock constraints be applied globally, eliminates broken
paths, and makes use of the dedicated clock networks. It also simplifies ASIC
prototyping. For information on using the gated clocks, see Chapter 17, Clock
Conversion in the User Guide.
Altera Generated Clocks

generated clocks to a circuit with an enable, which helps improve perfor-
mance by reducing clock skew. For more information on generated clocks, see
Chapter 17, Clock Conversion in the User Guide.
Sequential Optimizations in Altera Designs

The Disable Sequential Optimization option determines whether sequential optimi-
zations are performed. By default, sequential optimizations are performed.
Note that unused registers are always removed from the design regardless of
this option setting. Disabling sequential optimizations (checking the Disable
Sequential Optimizations box) can increase delay times and area requirements,
and effectively disables the FSM Compiler. The Tcl equivalent for this option
is -no_sequential_opt 1|0.

September 2016 627
Verification Mode in Altera Designs

Verification mode determines whether optimzations are disabled so that the
output is compatible with verification tools. This option is only supported in
the Synplify Pro and Synplify Premier tools. You control verification mode
with the Verification Mode option in the Device tab of the Implementation Options
dialog box. Or you can use the equivalent Tcl command: set_option -verification_-
mode 1|0.
Note that although they are similar, Verification Mode differs from the Disable
Sequential Optimizations option. The Disable Sequential Optimizations option only
disables sequential optimizations, but Verification Mode disables other FPGA
optimizations as well.
The following describes the effects of setting the Verification Mode option:
Enabled Ensures that synthesis output files are compatible with the verification
tool by disabling various sequential optimizations that cannot be easily
verified. It disables boundary optimizations and sequential optimizations,
like the inference of resettable SRLs.
When you enable Verification Mode, you must also disable the Retiming
and Pipelining options and remove any assigned syn_pipeline and
syn_allow_retiming attributes.
Enabling this mode also enables the Write Verification Interface Format (VIF)
File option, which generates a vif file. This file allows you to formally
verify the equivalence of your input RTL description with the
post-synthesis netlist. Enable this option only when this verification
is needed.
Disabled Might perform additional optimizations that could result in output that is
incompatible with the LEC.
Effect of Verification Mode on Multiplier Mapping

For Altera Stratix designs, the Verification Mode setting affects how multipliers
are mapped. When this option is disabled, the multipliers are mapped to
device-specific components:
LO

628 September 2016
Altera Reports Appendix A: Designing with Altera
Verification Multiplier Mapping

Mode
On All mapped to altmult_add or altmult_accum
Off Stratix II - stratixii_mac_mult and stratixii_mac_out

Stratix II GX - stratixiigx_mac_mult and stratixiigx_mac_out
Stratix III - stratixiii_mac_mult and stratixiii_mac_out
Stratix IV - stratixiv_mac_mult and stratixiv_mac_out
Altera Reports
Synopsys FPGA tools generate resource usage and timing reports. To view
these reports, click the View Log button in the Project view or select View ->View
Log File from the menu. In addition to the standard reports described in this
section, you can generate custom timing reports when using some devices
see Altera Custom Timing Reports, on page 631.
Altera Resource Usage Reports, on page 629
Altera Net Buffering Reports, on page 631
Altera Custom Timing Reports, on page 631
Altera Resource Usage Reports

The log file for Altera designs includes various reports: a resource usage
report, a timing report, and a net buffering report. To view these synthesis
reports, click View Log in the Project view. The resource usage reports include
this information:
Cell usage, including the following:
Carry chains, and flip-flops
LUTs and DSP blocks
Memory cell usage

September 2016 629
Appendix A: Designing with Altera Altera Reports
MRAM Stratix II, Stratix II GX
M4K Stratix II, Stratix II GX,
M512 Stratix II, StratixII GX
M144K Stratix III, Stratix IV
M9K Stratix III, Stratix IV
Number of I/Os
Utilization percentage
See Stratix II GX Resource Usage Report Example, on page 630 for an
example of this report.
Stratix II GX Resource Usage Report Example

##### START OF AREA REPORT #####[</a>
Design view:work.eight_bit_uc(verilog)
Selecting part EP2SGX30CF780C3
Total combinational functions 213
ALUT usage by number of inputs
7 input functions 5
6 input functions 55
[=3 input functions 87
ALUTs by mode
normal mode 188
extended LUT mode 5
arithmetic mode 20
shared arithmetic mode 0
Total registers 180
Total Estimated Packed ALMs 184
I/O pins 26
LO

630 September 2016
Forward-annotation to Altera Tools Appendix A: Designing with Altera
Total user instanciated Altsyncrams: 1

DSP Blocks: 0 (0 nine-bit DSP elements).
DSP Utilization: 0.00% of available 16 blocks (128 nine-bit).
ShiftTap: 0 (0 registers)
MRAM: 0 (0% of 1)
M4Ks: 1 (0% of 144)
M512s: 1 (0% of 202)
Total ESB: 1792 bits
##### END OF AREA REPORT #####]
Altera Net Buffering Reports

number of segments created for the net.
Altera Custom Timing Reports

In addition to the default timing report, you can generate custom timing
reports for some technologies. You must have a Synplify Premier or Synplify
Pro license to generate custom timing reports. The default timing report is
part of the log file (projectName.srr) that is located in the results directory. This
report provides a clock summary, I/O timing summary, and detailed timing
information about paths you specify.
The custom timing report lets you run targeted timing analysis. For example,
you can specify start and end points of paths and generate a report for only
those sections of the design. You generate a custom timing report with the
Analysis->Timing Analyst command. The generated custom timing report is
stored in a text file with a ta extension.
Forward-annotation to Altera Tools

The following describe forward-annotation to the Altera place-and-route tools:
Forward-annotation for Altera Designs, on page 632
Forward-annotation Formats for Stratix II Constraints, on page 632
VQM Filenames for Place-and-route Tools, on page 632

September 2016 631
Appendix A: Designing with Altera Forward-annotation to Altera Tools
Forward-annotation for Altera Designs

The synthesis tools automatically generate constraint files for
forward-annotation that are specific to the P&R tool you are using tcl for
Quartus II. If you want to disable this option, click Implementation Options, go to
the Implementation Results panel, and disable Write Vendor Constraint File.
The tool forward-annotates constraints like delays and clock relationships.

See Forward-annotation to Altera Tools, on page 631 for details.
Forward-annotation Formats for Stratix II Constraints

You have a choice of constraint formats, depending on which timing analyzer
you are targeting in the Quartus tool.
TimeQuest Timing Analyzer scf constraints file

Classic Timing Analyzer tcl constraints file
To specify the correct output format for the constraints to be

forward-annotated, enable or disable the Use TimeQuest Timing Analyzer
option on the Device tab of the Implementation Options dialog box or use the
set_option -timequest 1|0 Tcl command.
VQM Filenames for Place-and-route Tools

Altera requires that the name (without the filetype extension) of a VQM file be
identical to the top-level design name inside the file. Make sure that your
synthesis result file has the same name as your top-level Verilog module or
VHDL entity.
The synthesis result filename defaults to your HDL source filename with the
edf extension, so give the top-level module/entity the same name as the
source file, but without the extension. If you do not have identical names, you
get this error message:
"Can't find top level cell filename"
To keep track of the files generated by Quartus II create a subdirectory for the
EDIF or VQM result files before running the place-and-route tool.
LO

632 September 2016
Integration with Altera Tools and Processes Appendix A: Designing with Altera
Integration with Altera Tools and Processes

The following describe how the synthesis tools support various tools and
flows for Altera designs:
Altera Place-and-route Tools, on page 633
Clearbox Support in Synplify Pro and Synplify Premier, on page 634
Greybox Support in Synplify Pro and Synplify Premier, on page 635
Altera Place-and-route Tools

The synthesis tools support many versions of the Altera place-and-route
tools, and automatically generate the appropriate files for the tool and version
you are using. The vqm format varies slightly from version to version, so you
must specify the Quartus tool version and set the output format on the Imple-
mentation Results panel of the Implementation Options dialog box.
When you set these options, the synthesis tools automatically generate the
appropriate vqm files for the version you are using for placement and routing.
You can set P&R to run automatically after synthesis or launch the P&R UI
from the Options menu. See Working with Quartus II, on page 729of the User
Guide for details.

September 2016 633
Appendix A: Designing with Altera Integration with Altera Tools and Processes
Clearbox Support in Synplify Pro and Synplify Premier

Most Quartus megafunctions do not come with timing information. Without
this information, the synthesis tools cannot do any timing-driven optimiza-
tions at the megafunction boundary. Providing timing information for the
Quartus megafunction library is difficult because most of the relevant
megafunctions are highly parameterized. For several megafunctions, timing
changes dramatically when a single parameter changes.
Typically, the synthesis tools treat megafunctions without timing information

as black boxes. This approach prevents the tool from performing boundary
optimizations. For example, the tool might be able to move registers to
increase the FMAX of a design, but the registers in a pipelined LPM_MULT are
fixed.
Altera Clearbox models provide for the conversion of megafunctions to struc-

tural VHDL or Verilog. Using these models eliminates the need to black box
the Quartus megafunctions. The Clearbox structural content is fully visible
and has known primitives like dffe or latch in addition to the WYSIWYG
Clearbox primitives (see Clearbox WYSIWYG Cells, on page 634). There are no
undefined parameters, except for the ones remaining on the ATOMs. The
synthesis tool uses the timing information from the model to perform
boundary optimizations on the megafunctions.
Clearbox Flow Support

There are two ways in which the synthesis tools can get the Clearbox infor-
mation and optimize timing:
Read the information from a Clearbox netlist added to the design
Automatically generate the timing models from the Quartus Clearbox
information.
The synthesis tools use the Clearbox information for optimization, and then
include the architecture-specific primitives in the output netlist. For proce-
dures on using Clearbox models, see Implementing Megafunctions with
Clearbox Models, on page 798 in the User Guide.
Clearbox WYSIWYG CellsLO

The following WYSIWYG primitives are generated by Clearbox tools. The
synthesis tools obtain the information about the internals of the megafunc-
tions and the timing from each input to output.

634 September 2016
Integration with Altera Tools and Processes Appendix A: Designing with Altera
lcell
mac_mult
mac_out
ram_block
Greybox Support in Synplify Pro and Synplify Premier

The Certify tool supports Altera grey box models. Generally, user-instantiated
Quartus megafunctions do not come with any timing information and are
treated as black boxes, so the synthesis tool cannot optimize timing at the
megafunction boundary.
Instead of using black boxes, you can implement the megafunctions using
Altera grey box timing models. The synthesis tools can use the resource infor-
mation for optimizations, but does not write the underlying logic out to the
output netlist. For details about implementing megafunctions using grey box
timing models, see Implementing Megafunctions with Greybox Models, on

September 2016 635
Appendix A: Designing with Altera Stratix Device Families
Stratix Device Families

This section provides guidelines for using the synthesis tool with Stratix
devices.
Stratix Device Mapping Options, on page 636
Stratix File Format Options, on page 638
Altera Attribute and Directive Summary, on page 643
Stratix Device Mapping Options

You can specify device mapping options in the Implementation Options dialog box
or with the Tcl set_option command.
Device Mapping Options

This table alphabetically lists the options you can set on the Device tab:
Option Description
Altera Models Specifies if Clearbox or Grey Box models are used for
instantiated and inferred Altera megafunctions.
on looks for Clearbox and Greybox timing models. If both are
available, the synthesis tool uses the Clearbox model.
off does not look for Clearbox or Greybox timing models.
clearbox_only looks for Clearbox models only.
See Implementing Megafunctions with Clearbox Models, on
page 798 and Implementing Megafunctions with Greybox
Models, on page 808 in the User Guide for information about
how to use these timing models.
Annotated Properties Annotates the design with properties after the design is
for Analyst compiled. You can view these properties in the schematic view,
and use them to create collections using the Tcl Find
command. See Creating and Using Collections (SCOPE
Window), on page 673 in the User Guide for more
information.
Clock Conversion PerformsLO
gated and generated clock optimization when
enabled. See Chapter 17, Clock Conversion in the User
Guidefor details.

636 September 2016
Stratix Device Families Appendix A: Designing with Altera
Option Description
Core Voltage Stratix III
Lets you specify a core voltage. See Specifying Core Voltage in
Stratix III Designs, on page 727 in the User Guide.
Disable I/O Insertion Enables or disables I/O insertion during synthesis. The
default is false, so I/O ATOMs are inserted. See I/O Insertion
in Altera Designs, on page 626 for details.
Disable Sequential Enables or disables the sequential optimizations for the
Optimizations design. See Sequential Optimizations in Altera Designs, on
page 627.
Fanout Guide Guide for fanout-based optimizations which results in
buffering or replication of the net driver. See Setting Fanout
Limits, on page 589 in the User Guide for more information.
The default is 500.
Resolve Mixed When a net is driven by a VCC or GND and active drivers,
Drivers enable this option to connect the net to the VCC or GND
driver.
Use TimeQuest Stratix II and Stratix II GX
Timing Analyzer Determines which timing analyzer to use. Enable it to use the
Quartus II TimeQuest Timing Analyzer, and disable it to use
the Classic Timing Analyzer. See Forward-annotation
Formats for Stratix II Constraints, on page 632 for additional
information.
Verification Mode Determines whether certain optimizations that cannot be
easily verified are disabled so that the output is compatible
with the Conformal Equivalence Checker. See Verification
Mode in Altera Designs, on page 628.
set_option Command Options

You can use the set_options command to specify the Tcl equivalents of the
options on the Device and Options tabs of the Implementation Options dialog
box. For descriptions of these Tcl options, see set_option Command for Altera
Architectures, on page 639.
set_option Device Options

This is the syntax for setting device options for Stratix devices.

September 2016 637
Appendix A: Designing with Altera Stratix Device Families
set_option -technology keyword -part partName

-speed_grade value-package packageName
-block 1|0 or -disable_io_insertion 1|0
-enable_designware 1|0
-enhanced_optimization 1|0
-fix_gated_and_generated_clocks 0|1
-maxfan value
-no_sequential_opt 1|0
-resolve_multiple_driver 1|0
-run_prop_extract 1|0
-syn_altera_model on|off|clearbox_only
-timequest 1|0
-verification_mode 1|0
-voltage value
set_option Synthesis Options

The following set_option arguments are the equivalents of the options on the
Options tab of the Implementation Options dialog box:
set_option
-fast_synthesis 1|0
-physical_synthesis 1|0
-pipe 1|0
-resource_sharing 1|0
-retiming 1|0
-symbolic_fsm_compiler 1|0 or -autosm 1|0
-use_fsm_explorer 1|0
Stratix File Format Options

Use one of the following methods to set options for result file formats and
design filenames:
User Interface Select Project->Implementation Options to display the Implementation

Options dialog box.
Go to the Implementation Results panel and specify options for results
files.
Tcl LO command to specify the format and file name. See
Use the project Tcl
project Command for Altera Architectures, on page 642 for details
of the arguments.

638 September 2016
set_option Command for Altera Architectures Appendix A: Designing with Altera
set_option Command for Altera

Architectures
The set_option Tcl command offers an alternative way to set options that are
available on the Device and Options tabs on the Implementation Options dialog
box. You can save options set with this command in a file and re-execute
them. For a complete list of all available set_option arguments, see set_option,
on page 221 of the Command Reference, or enter help set_option in a Tcl Script
window
The following table describes the subset of options available for different
Stratix technologies.
OPTION DESCRIPTION
Target Technology Options
-technology keyword Specifies the target technology. See Technology
Keywords, on page 641 for a list of valid keywords.
-part partName Specifies a part for the implementation. Refer to
Project->Implementation Options->Device or to the Altera
documentation for available choices.
-part_companion partName Specifies a companion part package for certain
technologies. Refer to Project -> Implementation
Options->Device for available choices.
-speed_grade value Sets the speed grade. Refer to Project-> Implementation

Options->Device or to the Altera documentation for
available choices.
-package packageName Specifies the package. Refer to Project-> Implementation
Options->Device or to the Altera documentation for
available choices.
Optimization Options
-block 1|0 Enables/disables I/O insertion during synthesis.
-disable_io_insertion 1|0 See I/O Insertion in Altera Designs, on page 626.
Default: 0 (Inserts I/Os)
-enable_designware 1|0 Enables/disables replacement of Synopsys
DesignWare foundation library building blocks in
your design with DesignWare-compatible models.

September 2016 639
Appendix A: Designing with Altera set_option Command for Altera Architectures
OPTION DESCRIPTION
-fast_synthesis 1|0 Enables/disables some mapper optimizations to
improve logic synthesis runtimes. See
Chapter 4, Fast Synthesis of the User Guide for
details.
-fix_gated_and_ Performs gated- and generated-clock optimizations
generated_clocks 1|0 when enabled. See Chapter 17, Clock Conversion
in the User Guidefor details.
-maxfan value Establishes a limit for fanout-based optimizations
See Fanout Limits in Altera Designs, on page 624
-no_sequential_opt 1|0 Enables or disables the sequential optimizations for
the design. See Sequential Optimizations in Altera
Designs, on page 627 for details.
Default: 0 (sequential optimizations enabled)
-physical_synthesis 1|0 Enables/disables physical synthesis, which
includes global placement, placement-aware
optimizations, and graph-based placement.
-pipe 1|0 Runs designs at a faster frequency by moving
registers located outside of a multiplier module back
into the module to create pipeline stages.
-resolve_multiple_driver 1|0 When a net is driven by a VCC or GND and active
drivers, enable this option to connect the net to the
VCC or GND driver.
-resource_sharing 1|0 Enables or disables resource sharing. See Sharing
Resources, on page 593 in the User Guide for
information about using it.
-retiming 1|0 When enabled (1), registers may be moved into
combinational logic to improve performance.
Enabling -retiming also enables -pipe.
Default: 0 (retiming disabled)
-run_prop_extract 1|0 Determines whether the tool extracts properties for
annotation. See Forward-annotation Formats for
Stratix II Constraints, on page 632 in the User
Guide for more information.
LO

640 September 2016
set_option Command for Altera Architectures Appendix A: Designing with Altera
OPTION DESCRIPTION
-symbolic_fsm_compiler Enables or disables the FSM compiler. Controls the
1|0 use of FSM synthesis for state machines. FSM
syntheis is enabled when the value is 1 or true. See
-autosm 1|0 Running the FSM Compiler, on page 599 in the User
Guide for details of its use.
Default: 0 or false (FSM synthesis disabled)
-syn_altera_model Determines whether Clearbox and/or Greybox
on|off|clearbox_only models are used for Altera megafunctions during
synthesis.
See Implementing Megafunctions with Clearbox
Models, on page 798 and Implementing
Megafunctions with Greybox Models, on page 808in
the User Guide for information about how to use
these timing models.
-timequest 1|0 Stratix II and Stratix II GX
Determines whether to use the Altera Quartus II
TimeQuest Timing Analyzer (1) or the Classic Timing
Analyzer (0).
The Quartus II TimeQuest Timing Analyzer is the
default for Stratix IV and Stratix III devices.
-use_fsm_explorer 1|0 Enables or disables the FSM Explorer. See Running
the FSM Explorer, on page 603 in the User Guide
for information about using it.
-verification_mode 1|0 Enables or disables the Verification Mode option. See
Verification Mode in Altera Designs, on page 628.
-voltage value Stratix III
Sets a core voltage for Stratix III devices that
support speed grade 4. See Core Voltage, on
page 624.
Technology Keywords
The following table lists the -technology keywords for the supported Altera
technologies:
Family Valid -technology Keywords

Stratix STRATIXII, STRATIXII-GX, STRATIXIII, STRATIXIV

September 2016 641
Appendix A: Designing with Altera project Command for Altera Architectures
project Command for Altera Architectures

Use the Tcl project command to specify file format options. These options are
the equivalents of the ones you set in the Implementation Options dialog box. The
following table lists the options used to specify file formats for Altera devices.
For a complete list of project command options, see project, on page 180 of the
Command Reference, or type help project in a Tcl Script window:
Option Description
-result_format vqm Specifies the synthesis result file format for the
implementation. The format must be vqm (lower-case
letters).
-result_file filename Specifies the name of the synthesized netlist for the
implementation.
LO

642 September 2016
Altera Attribute and Directive Summary Appendix A: Designing with Altera
Altera Attribute and Directive Summary

The table below summarizes attributes available with Altera technology.
Attribute/Directive Description
black_box_pad_pin (D) Specifies that a pin on a black box is an I/O pad.
It is applied to a component, architecture, or
module, with a value that specifies the set of pins
on the module or entity.
black_box_tri_pins (D) Specifies that a pin on a black box is a tristate
pin. It is applied to a component, architecture, or
module, with a value that specifies the set of pins
on the module or entity.
full_case (D) Specifies that a Verilog case statement has
covered all possible cases.
loop_limit (D) Specifies a loop iteration limit for for loops.
parallel_case (D) Specifies a parallel, multiplexed structure in a

Verilog case statement, rather than a
priority-encoded structure.
syn_black_box (D) Defines a black box for synthesis.
syn_direct_enable (D and A) Identifies the signal to use as the enable input to

an enable flip-flop, when multiple candidates are
possible.
syn_encoding Specifies the encoding style for state machines.
syn_enum_encoding (D) Specifies the encoding style for enumerated types

(VHDL only).
syn_forward_io_constraints Enables I/O constraints to forward-annotate to
syn_force_seq_prim (D) Indicates that the fix gated clocks algorithm can
be applied to the associated primitive.
syn_gatedclk_clock_en (D) Specifies the name of the enable pin within a
black box.
syn_gatedclk_clock_en_polarity Indicates the polarity of the clock enable port on a
(D) black box, so that the software can apply the
algorithm to fix gated clocks.
(D) = directive. (D) and (A) = both directive and attribute. All others are attributes.

September 2016 643
Appendix A: Designing with Altera Altera Attribute and Directive Summary
syn_hier Controls the handling of hierarchy boundaries of
a module or component during optimization and
mapping.
Note that the syn_hier hard and macro options are
available for Altera devices.
syn_isclock (D) Specifies that a black-box input port is a clock,
even if the name does not indicate it is one.
syn_keep (D) Prevents the internal signal from being removed
during synthesis and optimization.
syn_loc Specifies pin locations for I/O pins and cores, and
forward-annotates this information to the
syn_maxfan Overrides the default fanout guide for an
individual input port, net, or register output.
syn_multstyle Determines whether multipliers are implemented
in logic or hardware blocks.
syn_netlist_hierarchy Determines whether VQM output netlist is flat or
hierarchical.
syn_noclockbuf Turns off automatic clock buffers for entire
modules or nets, or just for specific input ports.
syn_noprune (D) Controls the automatic removal of instances with
outputs that are not driven.
syn_pipeline Specifies that registers be moved into multipliers
to improve frequency.
syn_preserve (D) Enables or prevents sequential optimizations,
which eliminate redundant registers and registers
with constant drivers.
syn_ramstyle Determines how RAMs are implemented.
syn_reference_clock Specifies a clock frequency other than that

implied by the signal on the clock pin of the
register.
syn_replicate Controls the replication of registers.
LO

644 September 2016
Altera Attribute and Directive Summary Appendix A: Designing with Altera
syn_resources Specifies the resources available for black boxes.
It is attached to Verilog black-box modules or
VHDL architectures or component definitions.
syn_romstyle (Altera) Determines how ROM architectures are
implemented.
syn_rw_conflict_logic Allows synthesis to NOT automatically infer a
block RAM when unnecessary, and ensures that
the tool does NOT insert bypass logic around the
RAM to prevent a simulation mismatch.
syn_sharing (D) Specifies resource sharing of operators.
syn_srlstyle Specifies register packing for Stratix altshift_tap

mega function.
syn_state_machine (D) Determines if the FSM Compiler extracts a
structure as a state machine.
syn_tco<n> (D) Defines the clock to output delay timing through
a black box. The n indicates a value between 1
and 10.
syn_tpd<n> (D) Specifies timing propagation for combinational
delay through a black box. The n indicates a value
between 1 and 10.
syn_tristate(D) Specifies that a black box pin is a tristate pin.
syn_tsu<n> (D) Specifies the timing setup delay for input pins,
relative to the clock. The n indicates a value
between 1 and 10.
syn_useenables Generates register instances with clock enable
pins.
syn_useioff (Altera) Determines whether flip-flops are packed in the
I/O ring to improve input/output path timing.
translate_off/translate_on (D) Specifies sections of code to exclude from
synthesis, such as simulation-specific code.

September 2016 645
Appendix A: Designing with Altera Altera Attribute and Directive Summary
LO

646 September 2016
APPENDIX B
Designing with Xilinx
This chapter contains guidelines for synthesizing Xilinx-based designs. It

discusses the following topics:
Basic Support for Xilinx Designs, on page 648
Design Considerations, on page 653
Initial Value Support for Xilinx, on page 656
I/Os and Pin Locations, on page 677
Xilinx Optimizations, on page 688
Output Files and Forward-annotation for Xilinx, on page 693
Integration with Xilinx Tools and Flows, on page 697
Virtex and Spartan-3 Technologies, on page 698
Xilinx Attribute and Directive Summary, on page 705

September 2016 647
Appendix B: Designing with Xilinx Basic Support for Xilinx Designs
Basic Support for Xilinx Designs

The following topics briefly describe flows, constraints, and attributes
supported by the synthesis tools for Xilinx designs:
Xilinx Device Support, on page 648
Xilinx I/O Standards, on page 649
Synthesis Constraints and Attributes for Xilinx Designs, on page 652
For information on support in specific areas, see the other sections in this
chapter.
Xilinx Device Support

Following SLP generation, the Synplify Premier tool creates
technology-specific netlists for various Xilinx FPGA technologies. Synopsys is
committed to supporting new Xilinx technologies as they become available.
For a list of supported devices, check the Device panel of the Implementation
Options dialog box. If a new technology is not in your current release, contact
Synopsys to arrange an overlay.
After synthesis, the Synplify Premier tool generates XNF or EDIF netlists that
are used as input to the Xilinx ISE Design Suite. You can use these files to
run the ISE Design Suite.
LO

648 September 2016
Basic Support for Xilinx Designs Appendix B: Designing with Xilinx
Xilinx I/O Standards

The following table shows the applicable I/O standards for the Virtex and
Spartan families and the equivalent ISE I/O standards. For Virtex-6 and
Spartan-6 devices, see Virtex-6 and Spartan-6 I/O Standards, on page 650.
Synopsys FPGA ISE I/O Standard Spartan Virtex-5 Virtex-II

Synthesis I/O Standard Virtex-IIP
Virtex-4
AGP1X AGP1 X X X
AGP2X AGP2 X X X
BLVDS_25 BLVDS_25 X
CTT CTT X X X
DIFF_HSTL_15_Class_II DIFF_HSTL15_II X
DIFF_HSTL_18_Class_II DIFF_HSTL18_II X
DIFF_SSTL_18_Class_II DIFF_SSTL18_II X
DIFF_SSTL_2_Class_II DIFF_SSTL2_II X
GTL GTL X X X
GTL+ GTLP X X X
HSTL_Class_I HSTL_I X X X
HSTL_Class_II HSTL_II X X X
HSTL_Class_III HSTL_III X X X
HSTL_Class_IV HSTL_IV X X X
HSTL_18_Class_I HSTL18_I X X X
HSTL_18_Class_II HSTL18_II X X X
HSTL_18_Class_III HSTL18_III X X X
HSTL_18_Class_IV HSTL18_IV X X X
HyperTransport LDT_25 Virtex-4
LVCMOS_15 LVCMOS15 X X X

September 2016 649
Synopsys FPGA ISE I/O Standard Spartan Virtex-5 Virtex-II

Synthesis I/O Standard Virtex-IIP
Virtex-4
LVDS LVDS_25 X X X
LVDSEXT_25 LVDSEXT_25 X
LVPECL LVPECL X X X
LVTTL LVTTL X X X
PCI33 PCI33_3 X X X
PCI66 PCI66_3 X X X
PCI-X_133 PCIX X X X
SSTL_18_Class_I SSTL18_I X X X
SSTL_18_Class_II SSTL18_II X X X
ULVDS_25 ULVDS_25 X
Virtex-6 and Spartan-6 I/O Standards

The following table shows the applicable I/O standards for the Virtex-6 and
Spartan-6 families and the equivalent ISE I/O standards.
Synopsys FPGA ISE I/O Standard Spartan-6 Virtex-6

Synthesis I/O Standard
12C 12C X
BLVDS BLVDS_25 X
LO
DIFF_HSTL_Class_I DIFF_HSTL_I X X
DIFF_HSTL_Class_II DIFF_HSTL_II X X

650 September 2016
Basic Support for Xilinx Designs Appendix B: Designing with Xilinx

DIFF_HSTL_18_Class_II DIFF_HSTL_II_18 X X
DIFF_SSTL_18_Class_II DIFF_SSTL18_II X X
DIFF_SSTL_2_Class_II DIFF_SSTL2_II X X
DISPLAY_PORT DISPLAY_PORT X
HSTL_Class_I HSTL_I X X
HSTL_Class_I_12 HSTL_I_12 X X
HSTL_Class_II HSTL_II X X
HSTL_Class_III HSTL_III X X
HSTL_Class_I_18 HSTL_I_18 X X
HSTL_Class_II_18 HSTL_II_18 X X
HSTL_Class_III_18 HSTL_III_18 X X
HT_25 HT_25 X
LVCMOS_15 LVCMOS15 X X
LVCMOS_15_JEDEC LVCMOS15_JEDEC X
LVDS LVDS_25 X X
LVDS_33 LVDS_33 X
LVDSEXT_25 LVDSEXT_25 X
LVPECL_25 LVPECL_25 X
LVPECL_33 LVPECL_33 X
MINI_LVDS_25 MINI_LVDS_25 X
MINI_LVDS_33 MINI_LVDS_33 X
MOBILE_DDR MOBILE_DDR X

September 2016 651

PCI33 PCI33_3 X
PCI66 PCI66_3 X
PCI-X_133 PCIX X
RSDS_25 RSDS_25 X
SDIO SDIO X
SMBUS SMBUS X
SSTL_15 SSTL15 X
SSTL_15_class_II SSTL15_II X X
SSTL_18_Class_I SSTL18_I X X
SSTL_18_Class_II SSTL18_II X X
SSTL_2_Class_I SSTL2_I X X
SSTL_2_Class_II SSTL2_II X X
SSTL_3_Class_I SSTL3_I X
SSTL_3_Class_II SSTL3_II X
TMDS_33 TMDS_33 X
Synthesis Constraints and Attributes for Xilinx Designs

The synthesis tools let you specify timing constraints, general HDL attributes,
and Xilinx-specific attributes to improve your design. You can manage the
attributes and constraints in the SCOPE interface. See Xilinx Attribute and
Directive Summary, on page 705 for a list of Xilinx attributes and directives.
LO

652 September 2016
Design Considerations Appendix B: Designing with Xilinx
Design Considerations
This section describes general considerations for using the synthesis tool
with Xilinx devices.
IP Core Support, on page 653
Startup Blocks, on page 655
IOB Packing, on page 655
Initial Value Support for Xilinx, on page 656
IP Core Support
In a typical design flow, IP is instantiated as black boxes in the VHDL/Verilog
source. EDIF files for these modules are supplied to the place and route tool
to complete the design. This design flow has the following limitations:
The Synopsys FPGA software does not have timing models for the black
boxes which limits its capability to perform realistic timing analysis and
optimizations on the remainder of the design. Although you can add
timing models for black boxes, this process is tedious and error prone
even for very small blocks.
The Synopsys FPGA software does not have resource usage summaries
for the black boxes, which limits its capability to correctly report the
resources needed for the complete design. Without this information,
optimizations including RAM/ROM to block RAM mapping and clock
buffer insertion cannot be effectively performed.
The following discuss other ways of working with Xilinx IP:

IP Black Box Cores, on page 653
Xilinx Core Generator Files, on page 654
IP Black Box Cores

The flow IP cores can be divided into a compile phase and a mapping phase.
During the compile phase, the edf, edn, ngo, ngc, and the corresponding
black box files representing the IP cores from the Xilinx Core Generator are

September 2016 653
Appendix B: Designing with Xilinx Design Considerations
added to the synthesis project with the normal Verilog/VHDL source files.
The EDIF files are converted to srs files which are then combined into a
single srs file that is passed to the mapper.
During the mapping phase, the following steps are performed:
1. IP cores are marked as timing models to prevent them from being

optimized by the mapper.
2. Cores are then flattened to allow the resources to be computed for block
RAM, LUT, and global buffer usage.
3. Basic DRC is performed for the instantiated pads and tri-states.
4. A complete srm file is written modules representing black boxes are not
written for vm, vhm, and edf files.
Xilinx Core Generator Files

If you have EDIF core files from the Xilinx Core Generator, the synthesis tool
can read these files. You add the EDIF files from the core generator to the
project file. The resulting srs files include special attributes that allow the
mapper to use the portion of the design represented by these files only for
timing analysis and reporting. The generated srs files are merged into a
single srs file that is passed to mapper.
The core generator creates structural EDIF netlists (Xilinx/EDIF version

2.00) with both ndf and edn filename extensions. An ndf file is a Xilinx binary
file equivalent to an edf file and can only be read by Xilinx software. The
primary difference between an edn file and an ndf file is that the edn file has
complete functionality (used both for logic implementation and for communi-
cating resource and timing information), and the edf file has only LUT
functionality (conveys only resource and timing information). For Xilinx
implementation software, the netlists representing the lower levels of the
hierarchical core are a combination of edn and ndf files.
Most legacy cores still use the edn extension and are in a single, flat EDIF
netlist file. Most new cores are a combination of edn and ndf files. These new
cores are hierarchical with each level specified in a separate netlist file. The
top-level netlist created by the core generator is the IP core name with an edn
extension. LO

654 September 2016
The EDIF files from the core generator (edn and ndf) are placed in the design
project directory where the core is created without any additional directory
structure. These IP cores are treated as black boxes by the tool since their
contents are already defined in the edn and ndf netlist files.
Startup Blocks
The installDirectory/lib/xilinx directory provides Xilinx startup blocks in both
Verilog (unisim.v) and VHDL (unisim.vhd) formats. The following table summa-
rizes the information for different technologies.
Technology Component Usage

Virtex-II, STARTUP_VIRTEX2_GSR Instantiate the components
Virtex-II Pro STARTUP_VIRTEX2_GTS directly. You can use them
STARTUP_VIRTEX2_CLK independently, because the
three blocks are merged to
form a single startup block
in the EDIF result file.
Virtex-4 STARTUP_VIRTEX4 Instantiate the component.
Spartan-3 STARTUP_SPARTAN3 Instantiate the component.
IOB Packing
When a register drives an output, or an input drives a register, you can place
the register in a CLB or in an IOB. Depending on the design requirements,
you may want to pack the registers in the IOB instead of the CLB. Reasons
for this include the following:
The chip interfaces with another chip, and the register-to-output or the
input-to-register delay must be minimized. Packing the register in the
IOB instead of the CLB is more advantageous.
If CLB resources are limited, it may be worth packing the registers in
IOBs to free up CLB resources.
The synthesis tool packs I/Os based on the highest (registers) to lowest
(global) priority.

September 2016 655
Appendix B: Designing with Xilinx Design Considerations
I/O Type syn_useioff Description

Value
Registers 1 Packs registers into the I/O pad cells, regardless of
the ports or global specifications.
0 Does not pack registers into I/O pad cells,
regardless of the ports or the global specification.
Ports 1 Packs registers into the I/O pad cells, regardless of
the global specification.
0 Does not pack registers into I/O pad cells,
regardless of the global specification.
Global 1 Packs registers into the I/O pad cells.
0 Does not pack registers into I/O pad cells.
Initial Value Support for Xilinx

Initial values specified in the RTL for sequential elements and memories can
be mapped to startup values on the FPGA. Xilinx devices support power on
startup values for registers and memories. See Setting Xilinx RAM Initializa-
tion Values, on page 463 and Specifying Xilinx Register INIT Values, on
page 743 in the User Guide for step-by-step procedures.
The tool also supports initial values on asynchronous reset and no-change
output registers that are mapped into RAMs.
The compiler supports both procedural assignments and calls to readmemb()

and readmemh() in Verilog, from within the initial block. When loading data
files with readmemb() and readmemh(), the memory is loaded from the lowest
address to the highest address if the start and finish addresses are not speci-
fied. If both start and finish addresses are specified, then loading begins at
the start address and continues toward the finish address. In cases where the
start address is specified without a finish address, loading starts at the speci-
fied start address and continues upward toward the highest address in
memory.
For example:
LO
reg [7:0] mem [31:0]
$readmemh ("mem.ini", ram_bank1)

656 September 2016
$readmemh ("mem.ini", ram_bank1,0)

Note that this behavior is based on the Verilog 2005 standard.
Sequential elements can be mapped into registers/latches/SRLs, or

select/block RAM. Initial values are supported only on sequential elements
mapped to select/block RAM. If a read-first block RAM has an output register
with an initial value, the tool preserves the INIT value and packs the register
into the RAM.

September 2016 657
Appendix B: Designing with Xilinx Xilinx Components
Xilinx Components
The following topics describe how the synthesis tools handle various Xilinx
components, and show you how to work with or manipulate them during
synthesis to get the results you need:
Macros and Black Boxes, on page 658
Xilinx Registers, on page 661
DDR Registers, on page 662
Dynamic Shift Register Lookup (SRL) Table Inference, on page 664
Latch Mapping, on page 666
DSP Components in Virtex Designs, on page 667
Advanced LUT Combining, on page 667
Wide Adders in Virtex-5 and Virtex-6 Designs, on page 668
Control Sets in Virtex Architectures, on page 668
For information about I/Os, see I/Os and Pin Locations, on page 677.
Macros and Black Boxes

You can create an instance of any externally defined macro, including a
user-defined macro or Xilinx macro such as an I/O or flip-flop, by instanti-
ating a black box in your Verilog or VHDL source code. These black boxes are
empty Verilog module descriptions and VHDL component declarations.
The synthesis tool provides Xilinx macro libraries that you can use to instan-
tiate components such as I/Os, I/O pads, gates, counters, and flip-flops.
Using the macros from these libraries allows you to perform a subsequent
simulation run without changing your code. The Verilog library is located at
install_dir/lib/xilinx/unisim.v. It is automatically compiled when you choose a
Xilinx target device.
To instantiate Xilinx macros such as gates, counters, flip-flops, or I/Os, use

the appropriate library that defines the macros as black boxes. The macro
LO
libraries are located in the install_dir/lib/xilinx directory. For VHDL designs, add
the corresponding library and use clauses to the beginning of the design units
that instantiate the macros.

658 September 2016
Xilinx Components Appendix B: Designing with Xilinx
library unisim;
use unisim.vcomponents.all;
To review the available macros, check the unisim.vhd macro library in the
install_dir/lib/xilinx directory.
Unimacro Library Support

While most designs use generic code, the use of device-specific components is
often required to achieve the desired, end-circuit implementation and results.
Xilinx ISE provides a number of device-specific components that are part of
the Xilinx unimacro library. To use these components in the synthesis tool,
you must set the XILINX environment variable to point to the ISE installation
directory.
Note: If the XILINX environment variable is not set or set incorrectly,

the compiler errors out if a unimacro component is encountered
in the design.
A list of the supported unimacro components can be found at:

$XILINX/verilog/src/unimacro/ (Verilog) or
$XILINX/vhdl/src/unimacro/ (VHDL)
Any component in the unimacro library can be directly instantiated. The
following usage models are supported.
The following example uses Verilog to instantiate an ADDMACC_MACRO

module from the unimacro library.
Example Verilog Unimacro

module ADDMACC_MACRO_WRP ( PRODUCT, CARRYIN, CE, CLK,
MULTIPLIER, LOAD, LOAD_DATA, PREADD1, PREADD2, RST );
// Visible parameters
parameter DEVICE = "VIRTEX6";
parameter LATENCY = 4;
parameter WIDTH_PREADD = 25;
parameter WIDTH_MULTIPLIER = 18;
parameter WIDTH_PRODUCT = 48;
output [WIDTH_PRODUCT-1:0] PRODUCT;
input CARRYIN;

September 2016 659
input CE;
input CLK;
input [WIDTH_MULTIPLIER-1:0] MULTIPLIER;
input LOAD;
input [WIDTH_PRODUCT-1:0] LOAD_DATA;
input [WIDTH_PREADD-1:0] PREADD1;
input [WIDTH_PREADD-1:0] PREADD2;
input RST;
ADDMACC_MACRO
#(.DEVICE("SPARTAN6"))
U (.PRODUCT(PRODUCT),
.CARRYIN(CARRYIN),
.CE(CE),
.CLK(CLK),
.MULTIPLIER(MULTIPLIER),
.LOAD(LOAD),
.LOAD_DATA(LOAD_DATA),
.PREADD1(PREADD1),
.PREADD2(PREADD2),
.RST(RST)
);
endmodule
The following example uses VHDL to instantiate an ADDMACC_MACRO

entity from the unimacro library. When using VHDL, the library UNIMACRO
must be called before instantiating any component from the unimacro library
as noted in the library and use statements at beginning of the example.
Example VHDL Unimacro

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
entity ADDMACC_MACRO_WRP is
generic (DEVICE : string := "VIRTEX6";
LATENCY : integer := 4;
WIDTH_PREADD : integer := 25;
WIDTH_MULTIPLIER : integer := 18;
WIDTH_PRODUCT : integer := 48 );
LO

660 September 2016
port (PRODUCT : out std_logic_vector(WIDTH_PRODUCT-1 downto 0);

CARRYIN : in std_logic;
CE : in std_logic;
CLK : in std_logic;
MULTIPLIER : in std_logic_vector
(WIDTH_MULTIPLIER-1 downto 0);
LOAD : in std_logic;
LOAD_DATA : in std_logic_vector(WIDTH_PRODUCT-1 downto 0);
PREADD1 : in std_logic_vector(WIDTH_PREADD-1 downto 0);
PREADD2 : in std_logic_vector(WIDTH_PREADD-1 downto 0);
RST : in std_logic );
end entity ADDMACC_MACRO_WRP;
architecture ADDMACC_MACRO_arch of ADDMACC_MACRO_WRP is
begin
INST : ADDMACC_MACRO
generic map ( DEVICE => "VIRTEX6" )
port map (PRODUCT => PRODUCT ,
CARRYIN => CARRYIN ,
CE => CE ,
CLK => CLK ,
MULTIPLIER => MULTIPLIER ,
LOAD => LOAD ,
LOAD_DATA => LOAD_DATA ,
PREADD1 => PREADD1 ,
PREADD2 => PREADD2 ,
RST => RST );
end architecture ADDMACC_MACRO_arch;
Xilinx Registers
The compiler can infer additional register primitive types so that the mapper
can implement a better solution when it targets Xilinx technologies:
Registers with clock enables The compiler identifies and extracts
clock-enable logic for registers. The RTL view displays registers with
enables as special primitives with an extra pin for the enable signal. The
special primitives are dffe, dffre, dffse, dffrse, dffpatre, and dffpatrse. Set
syn_direct_enable in the HDL source file (not in the SCOPE spreadsheet or
a constraint file) to direct the compiler to infer the clock enables you
want. For further syntax details see syn_direct_enable, on page 54. By
default, registers without clock enables will be inferred.
Registers with synchronous sets/resets The compiler identifies and
extracts registers with synchronous sets and resets, and passes them to

September 2016 661
the mapper. The special primitives are sdffr, sdffs, sdffrs, sdffpat, sdffre,
sdffse, and sdffpate. Set syn_direct_set and/or syn_direct_reset in the HDL
source file (not in the SCOPE spreadsheet or a constraint file) to direct
the compiler to infer the set/reset you want. For further syntax details
see syn_direct_set, on page 64 and syn_direct_reset, on page 60. The
compiler does this automatically.
DDR Registers
The Virtex-II and later technologies and the Spartan-3 and later technologies
support input DDR registers. Output DDR registers are instantiated by using
Xilinx FDDRRSE/FDDRCPE primitives or ODDR
(Virtex-4/Virtex-5/Virtex-6). Output DDR registers
(FDDRRSE/FDDRCPE/ODDR) are automatically inferred without having to
instantiate them in the HDL. The following example shows the HDL coding
style to infer the output DDR registers.
Example
module fddrrse(d1, d0, clk0, clk1, rst, set, ce, q);
input [0:0]d1;
input [0:0]d0;
input clk0, clk1;
input rst;
input set;
input ce;
output [0:0]q;
reg [0:0]q0;
reg [0:0]q1;
begin
if(rst)
q0 = 1'b0;
else if(set)
q0 = 1'b1;
else if(ce)
q0 = d0;
end
LO

662 September 2016

begin
if(rst)
q1 = 1'b0;
else if(set)
q1 = 1'b1;
else if(ce)
q1 = d1;
end
assign q = clk0 ? q0 : q1;
endmodule
The following schematic represents the above Verilog code. The mapper
checks that clk0 and clk1 are output from a DCM, and that the two clocks have
180 degrees of phase shift. The mapper then replaces the clocks with a DDR
primitive. To infer the output DDR primitive, additional checks are made to
ensure that clk0 and clk1 are 180 degrees out of phase.
clk1
d1[0] D Q 0
rst R q[0]
set S 1
ce E
q[0]
q1[0]
clk0
d0[0] D Q
R
S
E
q0[0]

September 2016 663
Alternate coding styles:
1. Use positive and negative edges to clock the two registers which are then
inferred as DDR flip-flops
2. Use the negative edge of clk0 to trigger q1.
clk0
d1[0] D Q 0
rst R q[0]
set S 1
ce E
q[0]
q1[0]
d0[0] D Q
R
S
E
q0[0]
Dynamic Shift Register Lookup (SRL) Table Inference

The synthesis tools infer dynamic and static sequential shift components in
corresponding Virtex and Spartan architectures. If you do not want to
automatically infer the shift registers, set the syn_srlstyle attribute to registers.
See Initializing Xilinx Select RAM, on page 468 in the User Guide for details.
VHDL SRL Example

This is a VHDL example of a shift register with no resets. It has four 8-bit
wide registers and a 2-bit wide read address. Registers shift when the write
enable is 1.
LO
library IEEE;
use IEEE.std_logic_1164.all;

664 September 2016
entity srltest is
port (inData: std_logic_vector(7 downto 0);
clk, en : in std_logic;
outStage : in integer range 3 downto 0;
outData: out std_logic_vector(7 downto 0) );
end srltest;
architecture rtl of srltest is
type dataAryType is array(3 downto 0) of
std_logic_vector(7 downto 0);
signal regBank : dataAryType;
begin
outData <= regBank(outStage);
process(clk)
begin
if (clk'event and clk = '1') then
if (en='1') then
regBank <= (regBank(2 downto 0) & inData);
end if;
end if;
end process;
end rtl;

September 2016 665
Verilog SRL Example

This is a Verilog example of a shift register with no resets. It has sixteen 4-bit
wide registers and a 4-bit wide read address. Registers shift when the write
enable is 1.
module test_srl(clk, enable, dataIn, result, addr);

input clk, enable;
input [3:0] dataIn;
input [3:0] addr;
output [3:0] result;
reg [3:0] regBank[15:0];
integer i;
if (enable == 1) begin
for (i=15; i>0; i=i-1) begin
regBank[i] <= regBank[i-1];
end
regBank[0] <= dataIn;
end
end
assign result = regBank[addr];
endmodule
Latch Mapping
For architectures that do not support level-sensitive latches (e.g., XC4000),
the latches can be mapped to the latch components LD_1 (level-sensitive
latch), LDC_1 (level-sensitive latch with clear), LDP_1 (level-sensitive latch with
preset), and LDCP_1 (level-sensitive latch with preset and clear) so that you
can supply implementations. Sample XNF files are included containing
implementations you can use when you run the Xilinx ISE Design Suite.
Alternatively, you can change the XNF files for these latches to create your
own implementations before performing placement and routing.
The sample latch XNF files (with extension xnf) are located in the installDirec-
tory/lib/xilinx directory.
LO

666 September 2016
DSP Components in Virtex Designs

For the Virtex-4, Virtex-5, Virtex-6, and Spartan-6 families, the Synopsys
FPGA tool automatically infers DSP structures. Structures can be general or
customized depending on the coding style.
DSPs are used for the most important structures in the design, so they are
not automatically inferred for adders and counters. To control the inference
of DSPs on operators, registers, and module/architectures, use the syn_dsp-
style attribute. The syn_dspstyle attribute value is either logic, which ignores the
DSP, or dsp48, which infers the DSP.
DSP Examples
The following examples show the inference of an adder to a DSP.
VHDL
attribute syn_dspstyle : string;
attribute syn_dspstyle of adder_sig : signal is "dsp48";
Verilog
wire [9:0] adder_sig /* synthesis syn_dspstyle = "dsp48" */;
The following examples show the inference of a multiplier to logic.
VHDL
attribute syn_dspstyle : string;
attribute syn_dspstyle of mult_sig : signal is "logic";
Verilog
wire [9:0] mult_sig /* synthesis syn_dspstyle = "logic" */;
Advanced LUT Combining

The Enable Advanced LUT Combining (Implementation Options->Device) option is used
to prepare the netlist for advanced LUT combining, so that the Xilinx ISE P&R
tool can pack into the LUT6_2 depending on available resources. This option

September 2016 667
is available for Virtex-5 and Spartan-6 or newer devices and supported only
in Xilinx ISE 10.1 (sp1) or later versions. You can also enable this mode using
the equivalent command: set_option -enable_prepacking 1.
Wide Adders in Virtex-5 and Virtex-6 Designs

Virtex-5 and Virtex-6 support a wide adder/subtractor structure by
cascading DSPs using the CARRYCASCOUT pin. The structure supports three,
two, one, or zero pipeline registers with different synchronous control signals.
An adder/subtractor with three pipelined registers gives maximum perfor-
mance. Both the adders and subtractors support two or three
signed/unsigned inputs (with carry/borrow).
The synthesis tools infer a wide adder or subtractor and map it to a DSP if
you set the syn_dspstyle to dsp48 (syn_dspstyle, on page 68).
Control Sets in Virtex Architectures

The Virtex-5 and later architectures optimize area by having all registers that
appear in the same slice share the clock, clock enable, and synchronous
set/reset signals. Each unique combination of these signals is called a
control set.
The Xilinx ISE Design Suite cannot place two flip-flops with different control
sets in the same slice. This restriction can result in placement issues when
there are a large number of unique control sets and there are more than two
registers in a slice as found in the larger Xilinx technologies.
The synthesis software controls slice placement by moving control signals to

the data inputs when the control set is unique. This redefinition of the control
set reduces the number of unique control sets which improves the placement
of registers in the design. An attribute (syn_reduce_controlset_size) is available to
set the minimum size of the control set on which control-set optimizations
can occur. For details on this attribute, see syn_reduce_controlset_size, on
page 205.
LO

668 September 2016
Xilinx RAMs and ROMs Appendix B: Designing with Xilinx
Xilinx RAMs and ROMs
ROM Mapping
You can map ROM to block RAM with the syn_romstyle attribute. See Mapping
Xilinx ROM to Block RAM, on page 458 of the User Guide for details.
Xilinx RAMs
Depending on the technology, you can infer distributed or block RAMs. You
can also disable automatic RAM inference or specify the RAM implementation
with the syn_ramstyle attribute.
Distributed RAM Implementations

The synthesis tool can infer synchronous RAMs from your HDL source code,
and generate single- or dual-port RAMs using the distributed RAM resources
in the CLBs. See Chapter 9, RAM and ROM Inference for information on speci-
fying RAM implementations.
Mapping Byte Enables to Block RAM

The synthesis tool can map byte enable pins to block RAM if they are coded in
the prescribed style. For details, see Chapter 9, RAM and ROM Inference.
Mapping of Byte-Write Enable to Block RAM

The synthesis tool can map byte-write enable for RAMs with mutually exclu-
sive writes to block RAMs. For details, see Chapter 9, RAM and ROM Infer-
ence.
Single-port and Dual-port Block RAM Implementations

Block RAMs support multiple clocks and use enables and resets to control
RAM read and write operations. By default, the tool infers block SelectRAM,
but you can force block RAM inference by specifying the syn_ramstyle attribute
with a value of block_ram or no_rw_check.
Single-port block RAMs

September 2016 669
Appendix B: Designing with Xilinx Xilinx RAMs and ROMs
In single-port block RAMs, the enable signal has the highest priority. See
Chapter 9, RAM and ROM Inference for more information and examples.
Dual-port Block RAMs
Except for additional address collision recovery logic, a dual-port RAM is
essentially two independent single-port RAMs that share a common
memory. Dual-port RAMs have only one write port. See Chapter 9, RAM
and ROM Inference for more information and examples.
Single-port Block RAMs

In single-port block RAMs, the Enable signal has the highest priority. The
following table describes what happens with different Enable and Reset
settings:
Enable Reset Results

Inactive - All read and write operations are disabled.
Active Active Write operations and memory contents are unaffected (data_out
is 0).
Active Inactive If Write Enable is active, data_in goes to data_out and is updated
in memory.
If Write Enable is inactive, data_out reflects the memory
contents
The following Verilog code defines the behavior of a single-port block RAM.
module RAMB4_S4 (data_out, ADDR, data_in, EN, CLK, WE, RST);

output[3:0] data_out;
input [7:0] ADDR;
input [3:0] data_in;
input EN, CLK, WE, RST;
reg [3:0] mem [255:0];
reg [3:0] data_out;
if(EN)
if(RST == 1)
data_out <= 0;
else
LO
begin

670 September 2016
if(WE == 1)
data_out <= data_in;
else
data_out <= mem[ADDR];
end
always @(posedge CLK)
if (EN && WE) mem[ADDR] = data_in;
endmodule
For a code segment to map to a single-port block RAM, there must be a

one-to-one correspondence between the following signals:
Read and write clocks
Read and write addresses
Enable signal
Write enable signal
Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, and Spartan-3 block RAM supports
three write modes: writefirst, readfirst, and nochange. These modes determine
what appears at data_out when Write Enable is active.
.
Writefirst data_in goes to data_out
Readfirst memory goes to data_out

Nochange data_out remains unchanged
For information about implementing single-port RAMs, see Specifying RAM

Implementation Styles, on page 447 and Implementing Xilinx RAMs Automati-
cally, on page 451 in the FPGA Synthesis User Guide.
Dual-port Block RAMs

Except for the addition of address collision recovery logic, a dual-port RAM is
essentially two, independent single-port RAMs sharing a common memory.
The dual-port RAM has only one write port.
The following segment of Verilog code defines the behavior of a Virtex-II,

Virtex-II Pro, Virtex-4, Virtex-5, and Spartan-3 dual-port block RAM (address
collision recovery code is not shown).

September 2016 671
Appendix B: Designing with Xilinx Xilinx RAMs and ROMs
module DP_Block_Ram (ADDRA, ADDRB, data_in, CLK, WEA, data_out);

output[3:0] data_out;
input [9:0] ADDRA;
input [9:0] ADDRB;
input [3:0] data_in;
input CLK, WEA;
reg [3:0] mem [1023:0] /* synthesis syn_ramstyle="block_ram" */;
reg [9:0] ADDRB_reg;
if(WEA)
mem[ADDRA] = data_in;
always @(posedge CLK)

ADDRB_reg <= ADDRB;
assign data_out = mem[ADDRB_reg];

endmodule
For information about implementing dual-port RAMs, see Specifying RAM

Implementation Styles, on page 447 and Implementing Xilinx RAMs Automati-
cally, on page 451 in the FPGA Synthesis User Guide.
LO

672 September 2016
Multi-Port RAM Implementations

The compiler extracts a multi-port RAM called nram, which has one read port
and multiple write ports. Each write port has its own write clock, write
enable, data in, and write address. For syntax and coding information,
Chapter 9, RAM and ROM Inference. For usage, see Basic Guidelines for
Coding RAMs, on page 442, Specifying RAM Implementation Styles, on
page 447, and Implementing Xilinx RAMs Automatically, on page 451 in the
FPGA Synthesis User Guide.
The nram is mapped to true dual-port block RAMs in the following cases:
An inferred RAM with two writes and one read. The read shares an
address with only one of the write ports.
Two inferred RAMs with exactly the same write addresses, clocks, and
enables, but with different read address can be paired together and
mapped.
Parity Bus
When using Virtex-II block RAM, the parity bus is automatically used to infer
RAMs of specific data bus widths. For example, instead of implementing a
memory with a 9-bit data bus as two block RAMs (one 8-bit and one 1-bit),
the software uses a single block RAM with an 8-bit DI/DO data bus, and
implements the 9th bit using the DIP/DOP parity bus.
To utilize the parity bus, treat the RAM as if it is of width 9/18/36 when
calculating and selecting the block RAM aspect ratio. The software creates a
separate memory array for the parity bus. When it assigns bits, the software
assigns the parity bus to the MSBs of the data. For example, if d[8:0] is imple-
mented in RAMB16_S9, d[8] is assigned to DIP[0], and d[7:0] are assigned to
DI[7:0].
Disabling RAM Inference

If your RAM resources are limited, designate additional instances of inferred
RAMs as flip-flops and logic using the syn_ramstyle attribute (Verilog or VHDL)
with a value of registers. This attribute is specified for the signal (VHDL) or reg
port (Verilog) that defines the RAM, or the label of the RAM component
instance. For syntax information, see syn_ramstyle, on page 199.

September 2016 673
Appendix B: Designing with Xilinx Xilinx I/O Support
Xilinx I/O Support

The following topics describe how the synthesis tools handle Xilinx I/O
components, and show you how to work with them during synthesis to get
the results you need:
Xilinx I/O Macros, on page 674
Xilinx I/O Pads, on page 674
Xilinx I/O Insertion, on page 674
IOB Packing, on page 675
Xilinx Differential I/O Buffers, on page 675
Xilinx BUFGMUX, on page 675
Xilinx I/Os and Pin Locations, on page 675
Xilinx Regional Clock Buffers, on page 676
Xilinx I/O Macros

You can create an instance of a Xilinx I/O macro by instantiating a black box
in your source code. These black boxes are empty Verilog module or VHDL
component declarations. To instantiate the Xilinx macros, use the appro-
priate library that defines the macros as black boxes. The macro libraries are
located in the installDirectory/lib/xilinx directory. See Specifying Xilinx Macros,
Xilinx I/O Pads

For all Virtex technologies and all Spartan-II and later technologies, you can
use the Xilinx macro libraries to instantiate I/O pads (Xilinx Select I/O
resources) using different I/O standards. See Specifying Xilinx Macros, on
Xilinx I/O Insertion

I/O pads are automatically inserted into the design. If you manually instan-
tiate I/Os, I/Os are insertedLO
only for the pins that need them.

674 September 2016
Xilinx I/O Support Appendix B: Designing with Xilinx
If you do not want to insert any I/Os in the design, select the Disable I/O Inser-
tion check box in the Implementation Options dialog box. This is useful for
bottom-up compiles, because you can check the area your logic blocks use
before you synthesize the whole design. If you disable I/O insertion, you will
not get any I/Os in the design unless you manually instantiate them.
IOB Packing
When a register drives an output, or an input drives a register, you can place
the register in a CLB or in an IOB. Depending on the design requirements,
you may want to pack the registers in the IOB instead of the CLB. You can
use the syn_useioff attribute to control register packing. See Packing Registers
for I/Os, on page 741 in the User Guide.
Xilinx Differential I/O Buffers

By default, the synthesis tool does not automatically infer differential I/O
buffers. You can direct the tool to infer IBUFDS, IBUFGDS, OBUFDS, OBUFTDS,
and IOBUFDS by setting the syn_diff_io attribute to 1 or true. See Working with
Xilinx Buffers, on page 752 in the User Guide.
Xilinx BUFGMUX
By default, the Xilinx mapper does not infer BUFGMUX/BUFGMUX_1 from
the HDL. You can control inference by setting syn_insert_buffer on the mux
instance. See Working with Xilinx Buffers, on page 752 in the User Guide.
Xilinx I/Os and Pin Locations

By default the synthesis tools automatically insert I/Os for inputs, outputs,
and bidirectionals (such as IBUFs and OBUFs), and the Xilinx ISE Design
Suite chooses the I/O locations. However, you can manually instantiate I/Os
and specify pin locations with the syn_loc attribute. See Inserting Xilinx I/Os
and Specifying Pin Locations, on page 745 in the User Guide.

September 2016 675
Appendix B: Designing with Xilinx Xilinx I/O Support
Xilinx Regional Clock Buffers

The Xilinx regional clock buffer (BUFR) available for Virtex-6, Virtex-5, and
Virtex-4 devices is a special buffer used to connect the clock nets in the same
region and adjacent regions, independent of the global clock tree. The BUFR
can drive the I/O logic and logic resources based on the Virtex architectures
and can be used as a clock divider in low power and low skew operations.
By default, the synthesis tools do not automatically infer the Xilinx BUFR. If
you want the tools to infer Xilinx regional clock buffers, you must use the
syn_insert_buffer attribute. For more information, see Working with Xilinx
Buffers, on page 752.
LO

676 September 2016
I/Os and Pin Locations Appendix B: Designing with Xilinx
I/Os and Pin Locations

This section presents the following topics dealing with I/Os, I/O pads, and
pins.
Using Xilinx Macro Libraries with Verilog and VHDL, on page 677
Instantiating I/O Pads With Different Standards, on page 677
Specifying Pin Locations and Inserting I/Os, on page 680
Specifying Relative Location, on page 686
Using Xilinx Macro Libraries with Verilog and VHDL

The Synopsys FPGA synthesis tool provides Xilinx macro libraries that you
can use to insert I/Os and instantiate I/O pads. Using the macros from these
libraries allows you to perform a subsequent simulation run without
changing your code.
For Verilog designs, add the unisim.v Xilinx macro library file to the top of the
source files list for your project. This file is located in the installDirectory/lib/xilinx
directory. Review the library file for the available macros.
For VHDL designs, add the corresponding library and use clauses to the begin-
ning of the design units that instantiate the macros (adding macro library
files to your projects source files list is not required). The file for the VHDL
macro library is named unisim.vhd and is located in the installDirectory/lib/xilinx
directory. Review the library file for the available macros.
The following is an example of VHDL library and use clauses:
library unisim;
Instantiating I/O Pads With Different Standards

For all Virtex technologies and the Spartan-3 technology, you can use the
Xilinx macro libraries to instantiate I/O pads (Xilinx Select I/O resources)
using different I/O standards. The following I/O pad types can be instanti-
ated:
IBUF

September 2016 677
Appendix B: Designing with Xilinx I/Os and Pin Locations
IBUFG
OBUF
OBUFT
IOBUF
When you instantiate an I/O pad type in your HDL source files, you can use
an IOSTANDARD generic/parameter to specify the I/O standard you want.
Consult the Xilinx documentation for a list of all supported I/O standards. In
addition to IOSTANDARD, you can specify the following properties as
generics/parameters for certain I/O pad types:
SLEW output slew rate
DRIVE output drive strength
The macro libraries are located in the installDirectory/lib/xilinx directory. See
Using Xilinx Macro Libraries with Verilog and VHDL, on page 677, for more
information on using the Xilinx macro libraries.
LO

678 September 2016
The following examples show the declaration of OBUF in macro library files:
VHDL component OBUF

generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
I : in std_logic;
);
end component;
attribute syn_black_box of OBUF : component is
true
Verilog module OBUF(O, I); /* synthesis syn_black_box */
parameter IOSTANDARD="default";
parameter SLEW="SLOW";
parameter DRIVE=12;
output O;
input I;
endmodule
To use the macro libraries to instantiate I/O pad types, define the
generic/parameter values in the Verilog or VHDL source files. The following
examples show how to instantiate OBUF pads with an I/O standard value of
LVCMOS2, an output slew value of FAST, and an output drive strength of 24.
VHDL Data : OBUF

generic map (
IOSTANDARD => "LVCMOS2",
SLEW => "FAST",
DRIVE => 24
)
port map (
O => o1,
I => i1
);
Verilog OBUF Data(.O(o1), .I(i1));
defparam Data.IOSTANDARD = "LVCMOS2";
defparam Data.SLEW = "FAST";
defparam Data.DRIVE = 24;

September 2016 679
The resulting EDIF file contains the following, which corresponds to the
instantiations above:
(instance (
rename dataZ0 "data")
(viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
(property iostandard (string "LVCMOS2"))
(property slew (string "FAST"))
(property drive (integer 24) )
)
Specifying Pin Locations and Inserting I/Os

I/Os for inputs, outputs, and bidirectionals (such as IBUFs and OBUFs), are
automatically inserted, and the Xilinx place-and-route tool chooses the I/O
locations. See Automatically Inserting I/Os and Assigning Locations in
Verilog, on page 681.
You can alternatively instantiate I/Os manually see Manually Inserting

I/Os and Assigning Locations in Verilog, on page 682 and Manually Inserting
I/Os and Assigning Locations in VHDL, on page 685. You can also specify
I/O locations for some or all of your instantiated I/Os. If you do that, I/Os are
inserted by the place-and-route tool only for the pins that need them.
Assigning I/O Locations with the SCOPE Spreadsheet

You can assign I/O locations using the Attributes panel of the SCOPE spread-
sheet. This is a convenient method that also makes it easy to maintain
vendor independence. Here is an example of assigning locations using the
xc_loc attribute.
LO

680 September 2016
Automatically Inserting I/Os and Assigning Locations in Verilog

Create a new top-level module and instantiate your Verilog design. Create
this new top-level module to specify your I/O locations so that your
vendor-specific information is separate from the rest of your design. Once you
have done this, set the xc_loc attribute with the appropriate value for the I/Os
you want to specify the locations for. If you do not specify the xc_loc attribute
for certain I/Os, the Xilinx place-and-route tool will choose the I/O locations
for them.
For example:
1. Starting with the following module declaration:
module cnt4 (cout, out, in, ce, load, clk, rst);

// Counter definition goes here
endmodule
2. Create a new top-level module to place I/Os for Xilinx. This module is
typically in another file, so that your original design remains untouched
and technology-independent.
module cnt4_xilinx (cout, out, in, ce, load, clk, rst);
3. Specify that cout is located at A1.
output cout /* synthesis xc_loc="A1" */;
4. Specify that out is in the top left (TL) of the chip.
output [3:0] out /* synthesis xc_loc="TL" */;
5. Specify that in[3] be at P20, in[2] be at P19, in[1] be at P18, and in[0] be at
P17.
input [3:0] in /* synthesis xc_loc="P20,P19,P18,P17" */;
6. Let Xilinx automatically place the rest of the inputs.
input ce, load, clk, rst;
7. Instantiate your design.
cnt4 my_counter (.cout(cout), .out(out), .in(in),

.ce(ce), .load(load), .clk(clk), .rst(rst));
endmodule

September 2016 681
Manually Inserting I/Os and Assigning Locations in Verilog

Create instances of I/Os by instantiating a black box in your Verilog source
code. These black boxes are empty Verilog module descriptions that are
found in supplied Xilinx macro libraries. Add the unisim.v macro library file to
the top of the source files list for your project. This file is located in the install-
Directory/lib/xilinx directory.
If you instantiate I/Os, the Xilinx place-and-route tool will choose their
locations. Or, you can specify your own I/O locations as follows:
1. Create a new top-level module and instantiate your Verilog design.
2. Manually instantiate the Xilinx I/Os.
3. Add the appropriate Xilinx macro library filename to the top of the
source files list for your project.
4. If you want to specify I/O locations, set the xc_loc attribute for those
I/Os locations. If you do not specify I/O locations for some of your I/Os,
the Xilinx place-and-route tool will choose the locations for them.
LO

682 September 2016
Verilog Example
module cnt4 (cout, out, in, ce, load, clk, rst);
/* Your counter definition goes here, */
endmodule
/* Create a top level to place I/Os specifically
for Xilinx. Any top level pins which do not have
I/Os will be automatically inserted */
module cnt4_xilinx(cout, out, in, ce, load, clk, rst);
output [3:0] out;
output cout;
input [3:0] in;
input ce, load, clk, rst;wire [3:0] out_c, in_c;
wire cout_c;
/* The xc_loc attribute can be added right after the
instance name like that shown below, or right before
the semicolon. */
IBUF i3 /* synthesis xc_loc="P20" */ (.O(in_c[3]), .I(in[3]));
OBUF o3 /* synthesis xc_loc="TL" */ (.O(out[3]), .I(out_c[3]));
OBUF cout_p /* synthesis xc_loc="BL" */ (.O(cout), .I(cout_c));
cnt4 it(.cout(cout_c), .out(out_c), .in(in_c),
.ce(ce), .load(load), .clk(clk), .rst(rst));
endmodule
Automatically Inserting I/Os and Assigning Locations in VHDL

Create a new top-level design unit and instantiate your VHDL design. Use
this new top-level design unit to specify your I/O locations so that your
vendor-specific information is separate from the rest of your design. Specify
the xc_loc attribute with the appropriate value for the locations of the I/Os
you want to specify. If you do not specify the xc_loc attribute for certain I/Os,
the Xilinx place-and-route tool will choose locations for them.

September 2016 683
VHDL Example
library synplify;
entity cnt4 is
port (cout: out bit;
output: out bit_vector (3 downto 0);
input: in bit_vector (3 downto 0);
ce, load, clk, rst: in bit );
end cnt4;
architecture behave of cnt4 is
begin
-- Behavioral description of the counter.
end behave;
-- New top level entity, created specifically
-- to place I/Os for Xilinx. This entity is typically
-- in another file, so that your original
-- design stays untouched and technology independent.
entity cnt4_xilinx is
-- Place a single I/O for cout at location A1.
attribute xc_loc : string;
attribute xc_loc of cout: signal is "A1";
-- Place all bits of "output" in the
-- top-left of the chip.
attribute xc_loc of output: signal is "TL";
-- Place input(3) at P20, input(2) at P19,
-- input(1) at P18, and input(0) at P17
attribute xc_loc of input: signal is "P20, P19, P18, P17";
-- Let Xilinx place the rest of the inputs.
end cnt4_xilinx;
-- New top level architecture instantiates your design.
architecture structural of cnt4_xilinx is
-- Component declaration for your entity.
LO

684 September 2016
component cnt4
end component;
begin
-- Instantiate your VHDL design here:
my_counter: cnt4 port map (cout, output, input,
ce, load, clk, rst);
end structural;
Manually Inserting I/Os and Assigning Locations in VHDL

For VHDL designs, add the corresponding library and use clauses to the begin-
ning of your design units that instantiate the macros.
library unisim;
The Xilinx unisim.vhd macro library is always visible in the synthesis tool, so
do not add this library file to the source files list for your project. To see which
design units are available, use a text editor of your choice to view the file
located in the installDirectory/lib/xilinx directory (do not edit this file in any way).
Steps
1. Create a new top-level module and instantiate your VHDL design.
2. Instantiate the Xilinx I/Os.
3. Add the appropriate library and use clauses (see source code below) to the
beginning of your design unit that instantiates the I/Os.
4. If you wish to specify I/O locations, add the xc_loc attribute to the I/O
instances for which you want to specify the locations, and give the
locations values. If you leave out the xc_loc attribute, the Xilinx
place-and-route tool will choose the locations.

September 2016 685
The following example is a behavioral D flip-flop with instantiated data input

I/O. The other ports will have synthesized I/Os.
VHDL Example
library ieee, synplify;
use synplify.attributes.all;
-- Now the library and use clauses for access
-- to the Xilinx Macro Library.
library unisim;
entity place_example is
port (q: out std_logic;
d, clk: in std_logic );
end place_example;
architecture behave of place_example is
signal dz: std_logic;
attribute xc_loc of I1: label is "P3";
begin
I1: IBUF port map (I=>d,O=>dz);
process (clk) begin
q<=dz;
end if;
end process;
end behave;
Specifying Relative Location

The following three Xilinx-specific attributes specify relative position of
components in your designs.
xc_map
xc_rloc
xc_uset LO

686 September 2016
The general steps are as follows:
1. Create design units (modules) and use the xc_map attribute to specify
them as fmap or hmap, or lut.
2. Instantiate these design units at a higher level.
3. Use the xc_uset attribute to group a number of instances together.
4. Use the xc_rloc attribute to specify the relative locations of all instances
of the same xc_uset value.
5. Create a top-level design unit instantiating your design.
For details on syntax, see:

xc_map, on page 290
xc_rloc, on page 302
xc_uset, on page 309

September 2016 687
Appendix B: Designing with Xilinx Xilinx Optimizations
Xilinx Optimizations
The synthesis tools offer various optimizations for Xilinx designs. The
following describe the optimizations in more detail.
Fanout Limits in Xilinx Designs, on page 688
Pipelining in Xilinx Designs, on page 690
Retiming in Xilinx Designs, on page 690
Xilinx Gated Clocks, on page 690
Xilinx Generated Clocks, on page 691
Sequential Optimizations in Xilinx Designs, on page 691
Verification Mode in Xilinx Designs, on page 691
Fanout Limits in Xilinx Designs

Large fanouts can cause large delays and routability problems. The synthesis
tool maintains reasonable fanouts automatically, and also allows you to
specify maximum fanouts. There are two ways to specify fanout limits: the
Fanout Guide option (Fanout Guide Option, on page 689), and the syn_maxfan
attribute (The syn_maxfan Attribute for Xilinx Designs, on page 689).
The software first reduces fanout by replicating the driver of the high fanout
net and splitting the net into segments. This replication can affect the
number of register bits and LUTs in your design. If replication is not possible,
the signals are buffered. Buffering increases intrinsic delay and consumes
more resources, and is therefore not used until a slightly higher fanout limit
has been reached than is specified. See Controlling Buffering and Replication,
on page 591 in the user guide for more details. For extremely large clock
fanout nets, the software inserts global buffer (BUFG) cells in most cases. For
large non-clock nets, it may be necessary to insert global buffers manually.
Global buffers reduce the delay on large fanout nets and can free up routing
resources for other signals. View the net buffering report for details (see Xilinx
Net Buffering Report, on page 694).
For tips on setting and using fanout limits, see Setting Fanout Limits, on
LO
page 589 and Controlling Buffering and Replication, on page 591 in the User
Guide.

688 September 2016
Xilinx Optimizations Appendix B: Designing with Xilinx
Fanout Guide Option

Select Project->Implementation Options->Device. Specify an integer value for Fanout
Guide. The minimum value you can enter is 8. The default is 100.
During technology mapping, the synthesis tool tries to keep the fanout to less
than the specified fanout guide. However, the fanout guide is only a guideline,
not a hard limit. This means that the synthesis tool takes it into account, but
does not always respect it absolutely. If the limit imposes constraints that
interfere with optimization, the software does not respect the limit.
The syn_maxfan Attribute for Xilinx Designs

The syn_maxfan attribute controls the maximum fanout of an instance, net, or
port. See syn_maxfan, on page 151 for details of the syntax. The limit speci-
fied by this attribute is treated as a hard or soft limit, depending on where it
has been specified. A set of rules that treat the fanout limit as soft or as hard
is described below:
The maximum fanout is specified globally either by setting it as an
implementation option (Fanout Guide) or by specifying the syn_maxfan
attribute on a top-level module or view. A globally specified maximum
fanout limit is considered as a soft limit (or guide) and may not be
honored if the limit degrades performance.
A syn_maxfan attribute can be applied on a module or view. In this case,
the limit specified is treated as a soft limit for the scope of the module.
This limit overrides the global fanout guide limit for the scope of the
module.
When a syn_maxfan attribute is specified on an instance that is not of
primitive type as inferred by the Synopsys FPGA compiler, the limit is
considered a soft limit, which is propagated down the hierarchy.
When a syn_maxfan attribute is specified on a port, net, or register (or any
primitive instance), the limit is considered a hard limit. Note that the
syn_maxfan attribute does not prevent the instance from being optimized
away. Implementing a hard fanout limit gives you the ability to specify
implementations that will violate place and route design rules. The tool
checks for design rule violations and if detected, the fanout limit is not
honored and a warning is generated.
Note that it may not be possible to detect all possible design rule violations
that result from allowing a hard fanout limit. In these cases, you must take
responsibility and adjust the fanout value (or remove the syn_maxfan attribute)

September 2016 689
to produce a valid netlist. Note also that the syn_maxfan attribute is treated as
a guide on clock nets and asynchronous control nets (for example, asynchro-
nous reset).
Pipelining in Xilinx Designs

Pipelining multipliers and ROMs allows your design to operate at a faster
frequency. The Synplify Premier tool moves registers that follow a multiplier
or ROM into the multiplier or ROM, provided that you have registers in your
RTL code.
You can pipeline ROMs in all Xilinx FPGA technologies if the ROM is bigger
than 512 words. You can also pipeline multipliers in all Virtex technologies
and in the Spartan-3 technology. To forward annotate pipelining to Synplify
Premier, enable the Pipelining option on the Options tab of the Implementation
Options dialog box. For more information, see the Synplify Premier documen-
tation set.
Retiming in Xilinx Designs

Retiming is a powerful technique use by Synplify Premier to improve the
timing performance of sequential circuits. The retiming process moves
storage devices (flip-flops) across computational elements with no memory
(gates/LUTs) to improve the performance of the circuit. You can use retiming
with all Virtex technologies and with Spartan-3 technologies. Pipelining is
automatically enabled when retiming is enabled.
To forward annotate pipelining to Synplify Premier, enable the Pipelining option

on the Options tab of the Implementation Options dialog box. For more informa-
tion, see the Synplify Premier documentation set.
Xilinx Gated Clocks

gated clocks by extracting the enable logic from the clock path. Extracting the
enable logic lets clock constraints be applied globally, eliminates broken
paths, and makes use of the dedicated clock networks. It also simplifies ASIC
LO
prototyping. For information on using this option, see Chapter 17, Clock
Conversion in the User Guide.

690 September 2016
Xilinx Optimizations Appendix B: Designing with Xilinx
Xilinx Generated Clocks

generated clocks to a circuit with an enable, which helps improve perfor-
mance by reducing clock skew. For more information on generated clocks,
see Chapter 17, Clock Conversion in the User Guide.
Sequential Optimizations in Xilinx Designs

The Disable Sequential Optimization option determines when sequential optimiza-
tions are performed. Unchecking the checkbox or setting the option to 0 (the
defaults) enables sequential optimizations to be performed. Note that unused
registers are always removed from the design regardless of this option setting.
Disabling sequential optimizations (checking the Disable Sequential Optimizations
checkbox) can increase delay times and area requirements, and effectively
disables the FSM Compiler. The Tcl equivalent for this device option is set_op-
tion -no_sequential_opt 1|0.
Verification Mode in Xilinx Designs

Verification mode disables optimizations so that the output is compatible
with verification tools. You select verification mode with the Verification Mode
option in the Device tab of the Implementation Options dialog box or you can use
the equivalent Tcl command: set_option -verification_mode 1.
Note that although they are similar, Verification Mode differs from the Disable
Sequential Optimizations option. The Disable Sequential Optimizations option only
disables sequential optimizations, but Verification Mode disables other FPGA
optimizations as well.
The following describes the effects of setting the Verification Mode option:
Enabled Ensures that synthesis output files are compatible with the verification
tool by disabling various sequential optimizations that cannot be easily
verified. It disables boundary optimizations and sequential optimizations,
like the inference of resettable SRLs.
When you enable Verification Mode, you must also disable the Retiming and
Pipelining options and remove any assigned syn_pipeline and
syn_allow_retiming attributes.
Disabled May perform additional optimizations that could result in output that is
incompatible with the logic equivalency checker.

September 2016 691
Compile Point Remapping in Xilinx Designs

Compile points are smaller synthesis units that allow you to break up a larger
design into smaller units and perform incremental synthesis. See the Synplify
Premier documentation for information about the flow and compile points.
Compile points are supported for all Virtex technologies and the Spartan-III
technology.
The Update Compile Point Timing Data option determines if changes to a compile
point force the remapping of its parent, taking into account the new timing
model of the child. The term child refers to a compile point that is contained
inside another; the term parent refers to the compile point that contains the
child. These terms are thus not used here in their strict sense of direct,
immediate containment: If a compile point A is nested in B, which is nested
in C, then A and B are both considered children of C, and C is a parent of
both A and B. The top level is considered the parent of all compile points.
The following table describes the settings for the Update Compile Point Timing
Data option:
Disabled (Default). Only compile points that have changed are remapped, and
their remapping does not take into account changes in the timing models
of any of their children. The old (pre-change) timing model of a child is
used to map and optimize its parents.
If the option is disabled and the interface of a locked compile point is
changed, the immediate parent of the compile point must be changed
accordingly. In this case, both are remapped, and the updated timing
model of the child is used when remapping this parent.
Enabled Compile point changes are taken into account by updating the timing
model of the compile point and resynthesizing all of its parents (at all
levels), using the updated model. This includes any compile point
changes that took place prior to enabling this option, and which have not
yet been taken into account because the option was disabled. The timing
model of a compile point is updated when either of the following is true:
The compile point is remapped, and the Update Compile Point Timing Data
option is enabled.
The interface of the compile point is changed.
LO

692 September 2016
Output Files and Forward-annotation for Xilinx Appendix B: Designing with Xilinx
Output Files and Forward-annotation for

Xilinx
After synthesis, the software generates a log file and output files for Xilinx.
The following describe some of the reports with Xilinx-specific information, or
files that forward-annotate information to the Xilinx ISE Design Suite.
Xilinx Resource Usage Reports, on page 693
Xilinx Net Buffering Report, on page 694
Virtex-5 and Virtex-6 Detailed Clock Path Report, on page 695
Custom Timing Reports for Xilinx, on page 695
Forward-annotation of Xilinx Constraints, on page 696
Forward-annotation of Port Names in EDIF, on page 696
Xilinx Resource Usage Reports

The log file for Xilinx designs includes various reports: a resource usage
report, a timing report, and a net buffering report. To view these synthesis
reports, click View Log in the Project view. The Xilinx resource usage reports
include this information:
Cell usage (for example, carry chains, flip-flops)
Total registers
Registers packed in I/Os
Memory cell usage
Number of I/Os
Global buffer usage
LUTs
Percent of utilization
The number of CLBs reported is within a few percentage points of the number
reported by Xilinx after placement and routing.

September 2016 693
Appendix B: Designing with Xilinx Output Files and Forward-annotation for Xilinx
Example: Xilinx Spartan-3 Resource Usage Report

Resource Usage Report for a_cnt_demo
Mapping to part: xc3s50tq144-4
Cell usage:
FD 29 uses
GND 2 uses
MUXCY_L 14 uses
XORCY 16 uses
LUT1 21 uses
LUT2 4 uses
LUT3 2 uses
LUT4 17 uses
I/O ports: 9
I/O primitives: 8
OBUF 8 uses
BUFGP 1 use
I/O Register bits: 0
Register bits not including I/Os: 29 (1%)
Global Clock Buffers: 1 of 8 (12%)
Total load per clock:
a_cnt_demo|osc: 19
repeated_unit|reference_cnt_inferred_clock: 3
Mapping Summary:
Total LUTs: 44 (2%)
Xilinx Net Buffering Report

number of segments created for the net. For an explanation of buffering and
replication, see Controlling Buffering and Replication, on page 591 in the user
guide.
LO

694 September 2016
Output Files and Forward-annotation for Xilinx Appendix B: Designing with Xilinx
Virtex-5 and Virtex-6 Detailed Clock Path Report

For Synplify Premier Virtex-5 and Virtex-6 designs, the log file includes a
Detailed Clock Path section for each Detailed Data Path section. There is a Detailed
Clock Path section for every clock that is not an ideal clock.
In the following example, Derived Clock shows the clock name derived from
clk_r, which is adcm|clk1_derived_clock.
Custom Timing Reports for Xilinx

In addition to the default timing report, you can generate custom timing
reports for some technologies. The default timing report is part of the log file
(projectName.srr), located in the results directory. This report provides a clock
summary, I/O timing summary, and detailed timing information about paths
you specify. The custom timing report lets you run targeted timing analysis.
For example, you can specify start and end points of paths, and generate a
report for only those sections of the design.

September 2016 695
Appendix B: Designing with Xilinx Output Files and Forward-annotation for Xilinx
You generate a custom timing report with the Analysis->Timing Analyst

command.
Forward-annotation of Xilinx Constraints

By default, the tool forward-annotates timing constraints to the P&R tool
through a Xilinx (ucf) file, and placement constraints through a Xilinx ncf
file. If you do not want to forward-annotate the timing constraints and
generate a ucf file, select Project -> Implementation Options, go to the Implementation
Results panel, and disable Write Vendor Constraint File.
Forward-annotation of Port Names in EDIF

You can control how port names are written in the EDIF output files gener-
ated for your designs. This is especially useful for instantiated black-box
components (usually IP components). By default, the character case of port
names is preserved as it appears in the HDL source code.
You use two attributes for this: one for scalar (individual) port names and the
other for bus port names. Specify the attributes on individual components in
your HDL source code, or globally by using constraint files and the SCOPE
spreadsheet. See syn_edif_scalar_format, on page 87 and syn_edif_bit_-
format, on page 81 for syntax details.
Scalar ports Use syn_edif_scalar_format to determines if port names are all

uppercase or all lowercase (for example, AbCd becomes ABCD).
Bus Ports Use the syn_edif_bit_format attribute to determine the following:
If names are all uppercase or all lowercase (AbCd becomes ABCD)
If additional characters are appended to the end of names (qout
becomes qout_IP)
If the bus range is appended to the end of names (qout becomes
qout[31:1])
The format for a range delimiter when a range is appended
(qout<31:0> or qout[31:0])
LO

696 September 2016
Integration with Xilinx Tools and Flows Appendix B: Designing with Xilinx
Integration with Xilinx Tools and Flows

The following describe how the synthesis tools support various tools and
flows for Xilinx designs:
Xilinx ISE Design Suite, on page 697
Xilinx Xflow and Xtclsh, on page 697
Xilinx ISE Design Suite

When you launch the Xilinx ISE Design Suite directly from the synthesis tool,
the tool automatically creates a corresponding Xilinx project. Alternatively
you can set the ISE Design Suite to run automatically after synthesis. For
details about the ISE Design Suite, consult the Xilinx documentation.
Xilinx Xflow and Xtclsh

In earlier releases, the synthesis tool generated an opt file that contained the
P&R options, and then ran ISE by calling the xflow executable. The new
default is for the synthesis tools to generate a Tcl options file (tcl) and call
the xtclsh executable to run the ISE Design Suite. See the Synplify Premier
documentation for information about using a Tcl file.
If you are using the new Tcl flow and the xtclsh executable, note that this flow
names files based on the top-level name, whereas xflow named files based on
the EDIF. If the top level of your design has a different name than the edf
generated by the synthesis tools, the difference could affect scripts that are
looking for specific files.
The following table lists the differences between the output files generated by
the two flows when your synthesis EDIF file is called test.edf and your
top-level design is called design:
xflow test.mrp, test.twr, test.par, ... (Based on the EDIF name)
xtclsh design.mrp, design.twr, design.par, ... (Based on the top-level design name)
If you want to use the old xflow method, enable the Use Xilinx xflow option in
the Device tab of the Implementation Options dialog box. See the Synplify Premier
documentation for more information.

September 2016 697
Appendix B: Designing with Xilinx Virtex and Spartan-3 Technologies
Virtex and Spartan-3 Technologies

This section provides guidelines for using the synthesis tool with devices from
the Virtex family and the Spartan-3 technology. The topics include:
Virtex and Spartan-3 Device Mapping Options, on page 698
Virtex and Spartan-3 set_option Tcl Command, on page 700
Virtex and Spartan-3 project Tcl Command, on page 704
The Virtex family includes these technologies:
Virtex-II Virtex-II Pro Virtex-4 Virtex-5

Virtex-6 Virtex-7
Virtex and Spartan-3 Device Mapping Options

Device mapping options are synthesis algorithms to optimize your design. To
set these options, select Project->Implementation Options and set the options on
the Device tab. You can set other options on other tabs of this dialog box.
The following table lists device mapping options (Device tab) for the Virtex and
Spartan-3 and technologies. Some options might only be available for certain
devices.
Annotated Properties Annotates the design with properties after the design is
for Analyst compiled. You can view these properties in the schematic
view, and use them to create collections using the Tcl Find
command.
Guidefor details.
Disable I/O Insertion When enabled, prevents automatic I/O insertion during
synthesis. By default, this option is disabled (I/Os are
inserted). See I/Os and Pin Locations, on page 677 for
details.
LO

698 September 2016
Virtex and Spartan-3 Technologies Appendix B: Designing with Xilinx

Guidefor details.
The Clock Conversion option is only available with the Synplify
Pro and Synplify Premier products.
Disable Sequential Enables or disables sequential optimizations for the design.
Optimizations See Sequential Optimizations in Xilinx Designs, on
page 691.
Enable Advanced Combines LUTs into LUT6_2 primitives in Virtex-5 and
LUT Combining Virtex-6 designs. LUT6_2 primitives are supported only in
Xilinx ISE 10.1 (sp1) or later versions. See Control Sets in
Virtex Architectures, on page 668 for additional details. You
can also enable this mode using the equivalent command:
set_option -enable_prepacking 1
Error if unassigned When set (the default), results in an error if unassigned pins
pins are found in are present during HSTDM assignment. When clear, HSTDM
HSTDM mode operation proceeds with the place-and-route tool assigning pin
locations.
Estimate Area Effort Sets the effort level for area estimation. The low and medium
values use fast estimation; the default is high (normal
estimation).
Fanout Guide Sets a guideline for the fanout limit. The default is 10000. For
tips on setting and using fanout limits, see Setting Fanout
Limits, on page 589 and Controlling Buffering and
Replication, on page 591 in the User Guide.
Resolve Mixed When a net is driven by a VCC or GND and active drivers,
Drivers enable this option to connect the net to the VCC or GND
driver.
Timing Budget Effort Sets the effort level for estimating timing constraints for the
Level individual FPGAs. This step automatically budgets the
top-level timing constraints for each FPGA and annotates this
information into the individual synthesis constraint
(*_timing.sdc) files.

September 2016 699
Use Xilinx Xflow Determines if the Xilinx xflow or xtclsh flow is used for P&R. For
usage information, see the Synplify Premier documentation.
Use Xilinx XPartition Determines if compile points are used with the Xilinx
Flow XPartition flow, which compares partitions or modules in the
previous and current implementations. Partitions that have
not changed are preserved from the previous implementation.
This feature saves a significant amount of time in that place
and route for the entire design does not need to be rerun. For
details, see the Synplify Premier documentation.
Verification Mode Ensures that your synthesis output files are compatible with
the Verplex Conformal Logic Equivalence Checker (LEC). See
the Synplify Premier documentation for details.
You can also use the corresponding set_option Tcl command to enable/disable
these options. See Virtex and Spartan-3 set_option Tcl Command, on page 700
Virtex and Spartan-3 set_option Tcl Command

Specifies the implementation options for a design. These are the options you
set for synthesis such as the target technology, device architecture and
synthesis styles. The set_option Tcl command lets you specify the same imple-
mentation options as you do through the dialog box displayed in the Project
view with Project->Implementation Options.
This section provides information on some of the specific options for the
Virtex family and the Spartan-3 technology.
The following table lists the options for these families. See set_option, on
page 221 of the Command Reference or enter help set_option in the Tcl Script
window for a full list of syntax and options.
LO

700 September 2016
OPTION DESCRIPTION
Target Technology Options
-technology keyword Sets the target technology for the implementation. See
Virtex and Spartan-3 Technologies, on page 698 for
the list of technology keywords and their
corresponding Xilinx libraries.
-part partName Specifies a part for the implementation. Refer to the
Implementation Options dialog box for available choices
(Implementation Options Command, on page 114).
-speed_grade value Sets the speed grade for the implementation. Refer to
the Implementation Options dialog box for available
choices (Implementation Options Command, on
page 114).
-package packageName Specifies the package for the implementation. Refer to
the Implementation Options dialog box for available
choices (Implementation Options Command, on
page 114).
Optimization Options
-area_effort Sets the area effort.
high | medium | low
-block 1 | 0 Controls I/O insertion during synthesis. The default is
O, where I/Os are inserted automatically. To disable
I/O insertion, set it to 1. See I/Os and Pin Locations,
on page 677 for a description.
-enable_designware 1 | 0 Enables/disables replacement of Synopsys
DesignWare foundation library building blocks in your
design with DesignWare-compatible models.
-enable_prepacking 1 | 0 Determines whether LUTS are combined into LUT6_2
primitives in Virtex-5, Virtex-6, and Spartan-6
designs. The default is on. See Control Sets in Virtex
Architectures, on page 668 for details.
-fast_synthesis 1 | 0 Enables/disables some mapper optimizations to
improve logic synthesis runtimes. See Fast Synthesis,
on page 137 of the User Guide for details.
-fix_gated_and_ Performs gated- and generated-clock optimizations
generated_clocks 1|0 when enabled. See Chapter 17, Clock Conversion in
the User Guidefor details.

September 2016 701
OPTION DESCRIPTION
-hstdm_error_unassigned Determines if unassigned pins following trace
1|0 assignment are reported as errors in HSTDM mode.
maxfan value Sets the fanout limit. Default is 100. See Fanout
Limits in Xilinx Designs, on page 688 for details.
-no_sequential_opt 1 | 0 Enables or disables the sequential optimizations for
the design. Note that unused registers are always
removed from the design regardless of this option
setting. The default value is false or 0; therefore,
sequential optimizations are performed. Values can
be 1 or true, 0 or false.
Disabling sequential optimizations can increase
delay times and area requirements, and effectively
disables the FSM Compiler.
par_use_xflow 1 | 0 Determines whether the old Xilinx xflow is used. This
option is turned off (0) by default. Set it to 1 to use
xflow. See Xilinx Xflow and Xtclsh, on page 697 for
details.
par_use_xpartition 1 | 0 Determines whether to use compile points with the
Xilinx XPartition flow, which compares partitions or
modules in the previous and current implementations.
Partitions that have not changed are preserved from
the previous implementation. This feature saves a
significant amount of time in that place and route for
the entire design does not need to be rerun. The
default is 0.
-physical_synthesis 1 | 0 Forwards setting to Synplify Premier to enable/disable
physical synthesis, which includes global placement,
placement-aware optimizations, and graph-based
placement.
-pipe 1 | 0 Forwards setting to Synplify Premier to determine if
designs are to be run at a faster frequency by moving
registers appearing after the multiplier into the
multiplier itself. The default setting is 0 (registers are
not moved). See Pipelining in the Synplify Premier
documentation for information on how to use it.
-resolve_multiple_driver When a net is driven by a VCC or GND and active
1|0 drivers,
LO enable this option to connect the net to the
VCC or GND driver.

702 September 2016
OPTION DESCRIPTION
-resource_sharing 1 | 0 Enables/disables resource sharing. See Sharing
Resources, on page 593 in the User Guide for
-retiming 1 | 0 Forwards setting to Synplify Premier to determine if
retiming is to be used to optimize your design. When
enabled (1), registers may be moved into combinational
logic to improve performance. The default value is 0
(disabled). You must also enable -pipe. See Pipelining
in the Synplify Premier documentation for information
on how to use it.
-run_prop_extract 1 | 0 Determines whether the tool extracts properties for
annotation.
-symbolic_fsm_compiler Enables/disables the FSM compiler. Controls the use
1|0 of FSM synthesis for state machines. The default is
false (FSM Compiler disabled). Value can be 1 or true, 0
-autosm 1 | 0 or false. See Running the FSM Compiler, on page 599
in the User Guide for details of its use.
-timing_effort high | low Sets the timing budget effort level.
-use_fsm_explorer 1 | 0 Enables/disables the FSM Explorer. See Running the

FSM Explorer, on page 603 in the User Guide for
-verification_mode 1 | 0 Determines if synthesis output files are compatible
with the Verplex Conformal Logic Equivalence Checker
(LEC).
1 Ensures that synthesis output files are compatible
with the Verplex tool.
0 Might perform additional optimizations that could
result in output that is incompatible with the LEC.
Virtex and Spartan Technologies

The following table lists the supported Xilinx and Spartan technologies and
corresponding parameter values for the set_option -technology Tcl command.

September 2016 703
Technology Value Technology Value

Virtex-II virtex2 Virtex-6 virtex6
Virtex-II Pro virtex2p Virtex-7 virtex7
Virtex-4 virtex4 Spartan-3 spartan3
Virtex-5 virtex5
Virtex and Spartan-3 project Tcl Command

You can use the project Tcl command to specify the same result file formats
and filenames as are available from the Implementation Results panel of the
Implementation Options dialog box.
This table lists the options for the project Tcl command for the Virtex and
Spartan-3 technologies. See project, on page 180 for complete syntax and
options for this command, or type help project in the Tcl Script window:
Option Description
-result_file value Specifies the name of the synthesized netlist for the
implementation.
-result_format edif Specifies the synthesis result file format for the
implementation. The format must be edif (lower-case
letters).
LO

704 September 2016
Xilinx Attribute and Directive Summary Appendix B: Designing with Xilinx
Xilinx Attribute and Directive Summary

The following table summarizes the synthesis and Xilinx-specific attributes
and directives available with the Xilinx Technology. Complete descriptions
and examples can be found in Chapter 1, Synthesis Attributes and Directives.
black_box_pad_pin Specifies that a pin on a black box is an I/O pad. It
is applied to a component, architecture, or module,
with a value that specifies the set of pins on the
module or entity.
black_box_tri_pins Specifies that a pin on a black box is a tristate pin. It
is applied to a component, architecture, or module,
with a value that specifies the set of pins on the
module or entity.
full_case Specifies that a Verilog case statement has covered
all possible cases.
loop_limit Specifies a loop iteration limit for for loops.
parallel_case Specifies a parallel multiplexed structure in a

Verilog case statement, rather than a
priority-encoded structure.
syn_black_box Specifies allowed resources for compile points
(applies to all Virtex and Spartan-3 technologies).
The value assigned to a given compile point includes
the resources used by its children (at all levels).
syn_black_box Defines a black box for synthesis.
syn_clean_reset Changes asynchronous reset registers, which

cannot go into DSP48 blocks, into synchronous
reset logic. Xilinx Virtex-4, Virtex-5, and Virtex-6
only.
syn_clock_priority Establishes clock priority between clocks. The
priority is forward-annotated in the UCF file.
syn_diff_io Controls the inference of I/O buffers.
syn_direct_enable Identifies which signal to use as the enable input to

an enable flip-flop when multiple candidates are
possible.

September 2016 705
Appendix B: Designing with Xilinx Xilinx Attribute and Directive Summary
syn_direct_reset Controls the assignment of a net to the dedicated
reset pin of a synchronous storage element
(flip-flop). Using this attribute, you can direct the
mapper to only use a particular net as the reset
when the design has a conditioned reset on multiple
candidates.
syn_direct_set Controls the assignment of a net to the dedicated set
pin of a synchronous storage element (flip-flop).
Using this attribute, you can direct the mapper to
only use a particular net as the set when the design
has a conditioned set on multiple candidates.
syn_dspstyle In Virtex-4, Virtex-5, and Virtex-6 designs,
determines if an operator, register, or
module/architecture is placed in the DSP48
component.
syn_edif_bit_format Controls the character formatting and style of bus
signal names, port names, and vector ranges in the
EDIF output file.
syn_edif_scalar_format Controls the character formatting of scalar signal
and port names in the EDIF output file.
syn_encoding Specifies the encoding style for state machines.
syn_enum_encoding Specifies the encoding style for enumerated types

(VHDL only).
syn_forward_io_constraints Enables forward annotation of I/O constraints to
Xilinx place-and-route tools.
syn_global_buffers Sets the number of global buffers to use in a design.
syn_hier Controls the handling of hierarchy boundaries of a

module or component during optimization and
mapping.
syn_insert_buffer Inserts a clock buffer according to the specified
value.
syn_insert_pad Inserts I/O buffers to either ports or nets.
syn_isclock Specifies that a black-box input port is a clock, even

LO
if the name does not indicate it is one.
syn_keep Prevents the internal signal from being removed
during synthesis and optimization.

706 September 2016
syn_loc Specifies pin locations for I/O pins and cores, and
forward-annotates this information to the
syn_macro Prevents instantiated macros from being merged or
otherwise optimized away.
syn_multstyle Allows the synthesis software to handle registers
with asynchronous set and reset for Virtex-6 and
Spartan-6 devices.
syn_maxfan Overrides the default fanout guide for an individual
input port, net, or register output.
syn_multstyle Determines implementation style for multipliers in
Virtex-II and later, and Spartan-3 designs.
syn_netlist_hierarchy Determines if the EDIF output netlist is flat or
hierarchical.
syn_noarrayports Prevents the ports in the EDIF output netlist from
being grouped into arrays, and leaves them as
individual signals.
syn_noclockbuf Controls the automatic insertion of global clock
buffers.
syn_noprune Controls the automatic removal of instances that
have outputs that are not driven.
syn_pad_type Specifies an I/O buffer standard. (Spartan-3 and
Virtex-II and later).
syn_pipeline Specifies that registers be moved into ROMs or
multipliers to improve frequency. This attribute
applies to all Virtex-II and Spartan-3 and later
technologies.
syn_preserve Prevents sequential optimizations across a flip-flop
boundary during optimization, and preserves the
signal.
syn_ramstyle Determines the way in which RAMs are
implemented.
syn_reduce_controlset_size Controls the minimum size of the unique control-set
on which control-set optimizations can occur.

September 2016 707
syn_reference_clock Specifies a clock frequency other than that implied
by the signal on the clock pin of the register.
syn_replicate Disables replication.
syn_romstyle (Xilinx) Determines how ROM architectures are

implemented.
syn_rw_conflict_logic Allows synthesis to NOT automatically infer a block
RAM when unnecessary, and ensures that the tool
does NOT insert bypass logic around the RAM to
prevent a simulation mismatch.
syn_sharing Specifies resource sharing of operators.
syn_srlstyle Determines how to implement the sequential shift

(seqShift) components. This attribute applies to
Virtex technologies.
syn_state_machine Determines if the FSM Compiler extracts a structure
as a state machine.
syn_tco<n> Defines timing clock to output delay through the
black box. The n indicates a value between 1 and 10.
syn_tpd<n> Specifies timing propagation for combinational delay
through the black box. The n indicates a value
between 1 and 10.
syn_tristate Specifies that a black-box pin is a tristate pin.
syn_tristatetomux Converts tristate drivers that drive nets below a

certain limit to multiplexers. This only applies to the
Virtex technologies.
syn_tsu<n> Specifies the timing setup delay for input pins,
relative to the clock. The n indicates a value between
1 and 10.
syn_useenables Prevents generation of registers with clock enable
pins.
syn_useioff (Xilinx) Packs flip-flops in the I/Os to improve input/output
path timing.
syn_user_instance Prevents user-instantiated instances from being
LO
merged or otherwise optimized away.

708 September 2016
translate_off/translate_on Specifies sections of code to exclude from synthesis,
such as simulation-specific code.
xc_clockbuftype Specifies that a clock port use the Clock Delay
Locked Loop primitive, CLKDLL, in Virtex designs.
xc_fast Speeds up the transition time of the output driver.
xc_fast_auto Controls the instantiation of fast output buffers in

Virtex designs.
xc_global_buffers Controls the number of global buffers to use in a
design.
xc_padtype Specifies an I/O buffer standard in Virtex designs.
xc_pullup/xc_pulldown Specifies that a port is a pullup or pull-down port.
xc_rloc Specifies the relative locations of all instances with

the same xc_uset attribute value.
xc_use_keep_hierarchy Preserves the hierarchy of the marked module for
diagnostics and timing simulation.
xc_use_timespec_for_io Uses the TIMESPEC command to write out I/O
constraints.

September 2016 709
LO

710 September 2016
APPENDIX C
RAM Example Code
This appendix contains the code samples that are referenced by the
corresponding chapter.

September 2016 711
Appendix C:
Example: Verilog Initial Values for Asymmetric RAM

//
// Asymmetric port RAM
// Port A is 256x8-bit read-only
// Port B is 64x32-bit write-only
// Write_First mode with no control signals on Address register.
Different clocks.
//
module v_asymmetric_ram_4 (clkA, clkB, weB, addrA, addrB, doA,

diB);
parameter WIDTHA = 8;
parameter SIZEA = 256;
parameter ADDRWIDTHA = 8;
parameter WIDTHB = 32;
parameter SIZEB = 64;
parameter ADDRWIDTHB = 6;
input clkA;
input clkB;
input weB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
output [WIDTHA-1:0] doA;
input [WIDTHB-1:0]
LO diB;
reg [ADDRWIDTHA-1:0] addrA_reg;

712 September 2016
Appendix C:
`define max(a,b) {(a) > (b) ? (a) : (b)}

`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;

input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);

localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [WIDTHB-1:0] readB;

September 2016 713
Appendix C:
genvar i;
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];

// RAM initialization
initial
$readmemb (mem_init_256x8.dat, RAM);
always @(posedge clkA)

begin
addrA_reg <= addrA;
end
assign doA = RAM[addrA_reg];
generate for (i = 0; i < RATIO; i = i+1)

begin: ramread
localparam [log2RATIO-1:0] lsbaddr = i;
always @(posedge clkB)
begin
if (weB)
RAM[{addrB, lsbaddr}] <= diB[(i+1)*minWIDTH-1:i*minWIDTH];
end
end
endgenerate
LO
endmodule
Back

714 September 2016
Appendix C:
Example: VHDL Initial Values for Asymmetric RAM

library ieee;
entity asymmetric_ram_4 is
generic (
WIDTHA : integer := 8;
SIZEA : integer := 256;
ADDRWIDTHA : integer := 8;
WIDTHB : integer := 32;
SIZEB : integer := 64;
ADDRWIDTHB : integer := 6
);
port (
clkA : in std_logic;
clkB : in std_logic;
reA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTHA-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0);
diB : in std_logic_vector(WIDTHB-1 downto 0);
doA : out std_logic_vector(WIDTHA-1 downto 0)
);

September 2016 715
Appendix C:
end asymmetric_ram_4;
architecture behavioral of asymmetric_ram_4 is
function max(L, R: INTEGER) return INTEGER is

begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is

begin
if L < R then
return L;
else
return R;
end if;
end;
function log2 (val: INTEGER) return natural is

variable res : natural;
begin
LO
for i in 0 to 31 loop
if (val <= (2**i)) then

716 September 2016
Appendix C:
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
constant minWIDTH : integer := min(WIDTHA,WIDTHB);

constant maxWIDTH : integer := max(WIDTHA,WIDTHB);
constant maxSIZE : integer := max(SIZEA,SIZEB);
constant RATIO : integer := maxWIDTH / minWIDTH;
type ramType is array (0 to maxSIZE-1) of

std_logic_vector(minWIDTH-1 downto 0);
shared variable ram : ramType := (others =>11111111);
signal readA : std_logic_vector(WIDTHA-1 downto 0):= (

others => 0);
signal regA : std_logic_vector(WIDTHA-1 downto 0):=
(others => 0);
begin
process (clkA)
begin
if rising_edge(clkA) then
if reA = 1 then

September 2016 717
Appendix C:
doA <= ram(conv_integer(addrA));

end if;
end if;
end process;
process (clkB)
begin
if rising_edge(clkB) then
if weB = 1 then
for i in 0 to RATIO-1 loop
ram(conv_integer(addrB &
conv_std_logic_vector(i,log2(RATIO))))
:= diB((i+1)*minWIDTH-1 downto i*minWIDTH);
end loop;
end if;
end if;
end process;
end behavioral;
Back
LO

718 September 2016
Appendix C:
Example 1: VHDL Asymmetric RAM Coding Sytle 1

library ieee;
entity asymmetric_ram is
generic (
);
port (
weA : in std_logic;
enA : in std_logic;
diA : in std_logic_vector(WIDTHA-1 downto 0);
doB : out std_logic_vector(WIDTHB-1 downto 0)
);
end asymmetric_ram;

September 2016 719
Appendix C:
architecture behavioral of asymmetric_ram is

begin
if L > R then
return L;
else
return R;
end if;
end;

begin
if L < R then
return L;
else
return R;
end if;
end;

begin
LO
res := i;

720 September 2016
Appendix C:
exit;
end if;
end loop;
return res;
end function Log2;


signal ram : ramType := (others => (others => 0));
signal addrB_reg : std_logic_vector(ADDRWIDTHB-1 downto 0);
begin
process (clkA)
begin
if enA = 1 then
if weA = 1 then
ram(conv_integer(addrA)) <= diA;
end if;
end if;
end if;
end process;

September 2016 721
Appendix C:
process (clkB)
begin
doB((i+1)*minWIDTH-1 downto i*minWIDTH) <=
ram(conv_integer(addrB_reg &
conv_std_logic_vector(i,log2(RATIO))));
addrB_reg <= addrB;
end loop;
end if;
end process;
end behavioral;
Back
LO

722 September 2016
Appendix C:
Example 1: Verilog Asymmetric RAM Coding Sytle 1

module asymmetric_ram (clkA, clkB, weA, enA, addrA, addrB, diA,
doB);
input clkA;
input clkB;
input weA;
input enA;
input [WIDTHA-1:0] diA;
output reg [WIDTHB-1:0] doB;


reg [31:0] shifted;
integer res;

September 2016 723
Appendix C:
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
log2 = res;
end
end
endfunction


reg [ADDRWIDTHB-1:0] addrB_reg;
genvar i;

begin
LO
if ( enA & weA)
RAM[addrA] <= diA;

724 September 2016
Appendix C:
end

begin
addrB_reg <= addrB;
end

begin: ramread
begin
doB[(i+1)*minWIDTH-1:i*minWIDTH] <= RAM[
{addrB_reg, lsbaddr}];
end
end
endgenerate
endmodule
Back

September 2016 725
Appendix C:

library ieee;
generic (
);
port (
weA : in std_logic;
enA : in std_logic;
LO
);

726 September 2016
Appendix C:
end asymmetric_ram;

begin
if L > R then
return L;
else
return R;
end if;
end;

begin
if L < R then
return L;
else
return R;
end if;
end;


September 2016 727
Appendix C:

signal ram : ramType := (others => (others => 0));
signal addrB_reg : std_logic_vector(ADDRWIDTHB-1 downto 0);
begin
process (clkA)
begin
if enA = 1 then
if weA = 1 then
ram(conv_integer(addrA)) <= diA;
end if;
end if;
end if;
end process;
process (clkB)
begin
addrB_reg <= addrB;
doB(minWIDTH-1 downto 0) <=
ram(conv_integer(addrB_reg&conv_std_logic_vector(0,2)));
doB(2*minWIDTH-1 downto minWIDTH) <=
LO
doB(3*minWIDTH-1 downto 2*minWIDTH) <=

728 September 2016
Appendix C:
doB(4*minWIDTH-1 downto 3*minWIDTH) <=
end if;
end process;
end behavioral;
Back

September 2016 729
Appendix C:

module asymmetric_ram (clkA, clkB, weA, enA, addrA, addrB, diA,
doB);
input clkA;
input clkB;
input weA;
input enA;
input [WIDTHA-1:0] diA;


LO

730 September 2016
Appendix C:

reg [ADDRWIDTHB-1:0] addrB_reg;

begin
if (weA)
begin
RAM[addrA] <= diA;
end
end

begin
addrB_reg <= addrB;
doB[4*minWIDTH-1:3*minWIDTH] <= RAM[{addrB_reg, 2d3}];
doB[3*minWIDTH-1:2*minWIDTH] <= RAM[{addrB_reg, 2d2}];
doB[2*minWIDTH-1:minWIDTH] <= RAM[{addrB_reg, 2d1}];
doB[minWIDTH-1:0] <= RAM[{addrB_reg, 2d0}];
end
endmodule
Back

September 2016 731
Appendix C:

library ieee;
generic (
ADDRWIDTHB : integer := 6 );
port (clkA : in std_logic;

weB : in std_logic;
diB : in std_logic_vector(WIDTHB-1 downto 0);
doA : out std_logic_vector(WIDTHA-1 downto 0) );
end asymmetric_ram;
LO
begin
if L > R then

732 September 2016
Appendix C:
return L;
else
return R;
end if;
end;
begin
if L < R then
return L;
else
return R;
end if;
end;
begin
res := i;
exit;
end if;
end loop;
return res;
end function Log2;


September 2016 733
Appendix C:

shared variable ram : ramType := (others => (others => 0));
signal addrA_reg : std_logic_vector(ADDRWIDTHA-1 downto 0);
begin
process (clkA)
begin
addrA_reg <= addrA;
end if;
end process;
doA <= ram(conv_integer(addrA_reg));
process (clkB)
begin
if weB = 1 then
ram(conv_integer(
addrB & conv_std_logic_vector(i,log2(RATIO))))
:= diB((i+1)*minWIDTH-1 downto i*minWIDTH);
end loop;
end if;
LO
end if;
end process;

734 September 2016
Appendix C:
end behavioral;
Back

September 2016 735
Appendix C:

module v_asymmetric_ram (clkA, clkB, weB, addrA, addrB, doA, diB);
input clkA;
input clkB;
input weB;
output [WIDTHA-1:0] doA;
input [WIDTHB-1:0] diB;
reg [ADDRWIDTHA-1:0] addrA_reg;

reg [31:0] shifted;
integer res;
LO
begin
if (value < 2)

736 September 2016
Appendix C:
log2 = value;
else
begin
shifted = value-1;
log2 = res;
end
end
endfunction
reg [WIDTHB-1:0] readB;
genvar i;
begin
addrA_reg <= addrA;
end
assign doA = RAM[addrA_reg];

begin: ramread

September 2016 737
Appendix C:

begin
if (weB)
RAM[{addrB, lsbaddr}] <= diB[(i+1)
*minWIDTH-1:i*minWIDTH];
end
end
endgenerate
endmodule
Back
LO

738 September 2016
Appendix C:

library ieee;
generic (
);
port (
rst : in std_logic;
weA : in std_logic;
enA : in std_logic;
enB : in std_logic;

September 2016 739
Appendix C:
);
end asymmetric_ram;

type ramType is array (0 to SIZEA-1)
of std_logic_vector (WIDTHA-1 downto 0);
SHARED VARIABLE ram : ramType;
begin
process (clkA)
begin
if enA = 1 then
if weA = 1 then
ram(conv_integer(addrA)) := diA;
end if;
end if;
end if;
end process;
process (clkB)
variable mux : std_logic_vector(WIDTHA-1 downto 0);
begin
if enB = 1 then
LO
if addrB(0) = 0 then
mux := ram(conv_integer

740 September 2016
Appendix C:
(addrB(ADDRWIDTHB-1 downto 1)));

doB <= mux (WIDTHB-1 downto 0);
else
mux := ram(conv_integer(
addrB(ADDRWIDTHB-1 downto 1)));
doB <= mux(WIDTHA-1 downto WIDTHB);
end if;
end if;
end if;
end process;
end behavioral;
Back

September 2016 741
Appendix C:

module asymmetric_ram (clkA, clkB, enA, enB, weA, addrA,
addrB, diA, doB );
parameter WIDTHB= 16;
input clkA, clkB, enA, enB, weA;

input [WIDTHA-1:0] diA ;
reg [WIDTHA-1:0] mux;
reg [WIDTHA-1:0] RAM [SIZEA-1:0];
begin
if(enA & weA)
RAM[addrA] <= diA;
end

begin
LO
mux = RAM[addrB[ADDRWIDTHB-1:1]];
if(enB)

742 September 2016
Appendix C:
if (addrB[0])
begin
doB <= mux[WIDTHA-1:WIDTHB];
end
else
begin
doB <= mux[WIDTHB-1:0];
end
end
endmodule
Back

September 2016 743
Appendix C:
LO

744 September 2016
Index
Symbols About this program command 223

Add Source File command 101
_est.srr file 248
add_to_collection command 588
_SEARCHFILENAMEONLY_
directive 123 Additional Products command 222
! character, find command 558 Allow Duplicate Modules
Verilog panel 120
? wildcard
Timing Analyzer 186 Alt key
selecting columns (Text Editor) 49
.est file 248
Altera 601
.fse file 248 attributes 643
.info file 248 byte-wide write enable RAM 449
.ini file 244 device support 602
device support. See also Altera
.prj file 24, 244 technologies 602
.sap directives 643
annotated properties for analyst 248 DSP block inference 618
.sar file 249 edif and vqm filenames 632
fanout limits 624
.sdc file 244 gated clocks 627
.srd file 249 generated clocks 627
.srr file 250 grey boxes See grey boxes
See log file IP core support 608
LUTRAMs 429
.srs file 249
macro library, Verilog 608
initial values (Verilog) 462
macro library, VHDL 608
See srs file
macros 610
.synplicity directory (UNIX) 244 pad cell insertion 612
.ta file 250 PLLs 612
See timing report file 179 prepared components method 617
.v file 244, 245 qsf2sdc utility 392
RAM inference 614
.vhd file 244, 245 RAM with control signals 432
.xnf file (Xilinx). See xnf file (Xilinx) register inference 611
reports 629
Numerics ROM inference 615
specifying VHDL library 608
64-bit mapping 231 technology keywods 641
translating PIN file to constraint
file 143
A
Altera black boxes
aborting a synthesis run 143 pad cell insertion (Altera) 612

September 2016 745
Index
Altera Clearbox bind function 120

megafunctions 634 black boxes
Altera device options for predefined macros (Altera) 610
Arria 636 Xilinx 658
Cyclone 636 Xilinx macros 674
Stratix 636 block RAM
Altera megafunctions dual-port RAM examples 422
DSP blocks 618 NO_CHANGE mode example 419
Altera RAMs parity bus (Xilinx) 673
$readmemb/$readmemh RAM with control signals examples 432
initialization 462 READ_FIRST mode example 418
single-port RAM examples 420
Analyst
WRITE_FIRST mode example 416
HDL
See HDL Analyst tool block RAMs
inferring byte enables examples 446
annotated properties for analyst
Xilinx single port and dual-port 669
.sap 248
.timing annotated properties (.tap) 250 blocks
object properties for filtering 555 packing I/O (Xilinx) 655, 675
Xilinx startup 655
append_to_collection command 590
Board Wizard icon 60
archive file (.sar) 249
Browser, Hierarchy 370
archive utility
_SEARCHFILENAMEONLY_ buffering, Altera 625
directive 123 BUFGMUX/BUFGMUX_1 inference 675
area estimation file (.est) 248 Build Project command 78
Arrange VHDL files command 141 bus bundling 209
Arria 636 bus_dimension_separator_style
device options 636 command 512
file format options 638 bus_naming_style command 512
set_option synthesis options 638
buses
arrow keys, selecting objects in compressed display 209
Hierarchy Browser 371
enabling bit range display 207
arrow mouse pointers 370
buttons and options
asymmetric RAM examples 440 Project view 73
async clock report 178 By any transition command 98
asynchronous clock report 259 By input transitions command 98
attributes By output transitions command 98
Altera 643
byte-enable RAM examples 446
attributes (Xilinx) 705
byte-wide write enable RAM
auto constraints examples 449
Maximize option (Constraints tab) 136
C
B
c_diff command (collections) 296
Back command 97 c_intersect command (collections) 297
batch mode 26 c_print command (collections) 296

746 September 2016
Index
c_sub command (collections) 297 gated. See gated clocks

c_symdiff command (collections) 297 related 333
specifying as from/to points 323
c_symdiff command, examples 568
Clocks panel, SCOPE 331
c_union command (collections) 296
Close command 78
callback functions, customizing flow 389
Close Project command 79
camera mouse pointer 78
closing
canceling a synthesis run 143 project 79
case sensitivity, Tcl find command 550 Collapse All command 236
cck.rpt file collection commands
output files 248 c_diff 564
Certify popup menus 225 c_intersect 565
Certify tool c_list 566
views 39 c_print 567
c_symdiff 567
Change File command 101
c_union 568
Change Implementation Name SCOPE 296
command 228
collections
check boxes, Project view 73 Synopsys standard commands 587
Clearbox Collections panel, SCOPE 295
features 634
primitives 634 color coding
log file (.srr) 251
clock alias 182, 332 Text Editor 49
clock as object 182 commands
clock buffering report accessing 76
log file (.srr) 252 Hierarchy Browser 236
clock constraints menu
clock objects 332 See individual command entries
set_modules (Tcl) 571
clock enables Tcl
inferring registers (Altera) 612 See Tcl commands
inferring registers (Xilinx) 661 Tcl collection 563
clock groups 333 Tcl command equivalents 77
Clock Relationships (timing report) 255 Tcl expand 560
clock objects 332 Tcl find 544
Tcl hooks 389
clock paths, ignoring 315
Comment Code command 86
clock pin drivers, selecting all 44
commenting out code (Text Editor) 49
clock relationships, timing report 255
comments
clock report
about attributes (constraint file) 304
detailed 257
SCOPE 333
Clock to Clock panel, SCOPE 337
compilation
Clock Tree, HDL Analyst tool 44 incremental 119
clocks compile points
asynchronous report 259 Xilinx 692
determining what to define as 44
compiler directive
from/to points 323

September 2016 747
Index
_SEARCHFILENAMEONLY_ 123 styles 273

compiler directives types 270
UI option 119 Constraints panel
compiler directives (Verilog) 122 Options for implementation dialog
box 136
Compiler Directives and Design
Parameters 122 context of filtered schematic,
displaying 375
completing keywords
text editor 49 context sensitive help
using the F1 key 23
completion of keywords, Text Editor 49
context-sensitive popup menus
Configure External Programs See popup menus
command 198, 212
control-sets, Xilinx 668
Configure Verilog Compiler
command 197 Copy command 85
Configure VHDL Compiler Copy File command 227
command 197 Copy Implementation command 228
connectivity, enabling bit range copy_collection command 592
display 207
core voltage switch 624
constraint check
report 260 core voltage, Stratix III 624
Constraint Check command 260 create_clock timing constraint 475
constraint checker report (cck.rpt) 248 create_generated_clock timing
constraint 478
constraint file
critical paths
define_clock 331
custom timing reports 177
define_clock_delay 337
Timing Report panel, Options for
define_compile_point 540 implementation dialog box 138
define_current_design 541
define_input_delay 339 cross-hair mouse pointer 56
constraint file (.sdc) 244 crossprobing 361
definition 361
constraint files 271
comments 333 Ctrl key
fdc and sdc precedence order 275 multiple selection 55
PLL 609, 612 zooming using the mouse wheel 57
rise and fall 335 customer support, Synplicity 29
route option 340 customization
SCOPE spreadsheet 286, 329 callback functions 389
translating 143
Xilinx 652 Customize command 197
constraint files (.sdc) customizing
creating 60 project files 199
constraints Cut command 85
automatic. See auto constraints cutting (for pasting) 60
check constraints 141, 227 Cyclone 636
forward annotating (Xilinx) 696 device options 636
FPGA timing 474 file format options 638
legacy timing 513 set_option synthesis options 638
report file 260

748 September 2016
Index
D define_reg_input_delay timing
constraint 532
d 612 define_reg_output_delay constraint
DDR register inference SCOPE 343
Xilinx 662 define_reg_output_delay legacy timing
define_clock constraint
defining on an instance (Xilinx) 696 timing constraints
define_reg_output_delay 533
define_clock constraint
SCOPE 331 defining I/O standards 304
define_clock legacy timing delay paths
constraint 514 POS 322
define_clock_delay Delete all bookmarks command 86
SCOPE 337 Delete Device Assignments command 86
define_clock_delay legacy timing Delete Selected Assignments
constraint 517 command 86
define_compile_point deleting
Tcl 540 See removing
define_current_design design flow
Tcl 541 customizing with callback
define_false_path functions 389
SCOPE 315 design parameters (Verilog)
define_false_path legacy timing extracting 122
constraint 518 design size, schematic sheet
define_input_delay setting 364
multiple constraints 342 DesignWare options
SCOPE 339 VHDL panel 121, 128
define_input_delay legacy timing device options
constraint 521 Spartan technologies (Xilinx) 698
define_multicycle_path Virtex technologies (Xilinx) 698
SCOPE 312 Device panel
define_multicycle_path constraint Options for implementation dialog
specifying clocks 323 box 129
define_multicycle_path legacy timing dialog boxes
constraint 523 Options for implementation 114
define_output_delay directives
multiple constraints 342 _SEARCHFILENAMEONLY_ 123
define_output_delay constraint Altera 643
SCOPE 339 beta features 123
ignore syntax check 122
define_output_delay legacy timing specifying for the compiler (Verilog) 122
constraint 527
directives (Xilinx) 705
define_path_delay legacy timing
constraint 529 directory
.synplicity (UNIX) 244
define_reg_input_delay
home (UNIX) 244
SCOPE 343
Disable Sequential Optimizations
(Xilinx) 691

September 2016 749
Index
display preferences 214 execution 407

display settings output methods 405
Project view 199 syntax 403
Dissolve Instances command 195, 378 encryptP1735 script 397
command-line arguments 398
dissolving instances 195 public keys 399
distributed RAM examples 438 syntax 397
donut (transparent) display of enumeration encoding, default
hierarchical instances 353 (VHDL) 127
DSP blocks errors, warnings, notes, and messages
Altera megafunctions 618 report
formal verification (Altera) 623 log file (.srr) 251
packing resets (Altera) 622 est file 248
DSP blocks (Altera) 618 estimation file, area (.est) 248
DSP48 (Xilinx) 667 estimation log file (_est.srr) 248
DSP48 structures (Xilinx) 667 examples
DSP48E, wide adder inference 668 Tcl find command syntax 550
dual-port RAM Exit command 79
true dual-port RAM Expand command
See multi-port RAMs current level 190
dual-port RAM examples 422 hierarchical 189
duty cycle 333 Expand Inwards command 189
Expand Paths command
E current level 190
hierarchical 189
edif files
Expand to Register/Port command
Altera naming requirements 632
current level 190
port names (Xilinx) 696
hierarchical 189
Edit menu 85
expanding
Advanced submenu 86
paths between schematic objects 189
Editor Options command 197
Extract Design Parameters 122
enable prepacking 667
Enable Slack Margin 181 F
enable_io_map.txt file 613
fall constraints 335
encoding
enumeration, default (VHDL) 127 false paths
state machine architectural 315
FSM Compiler 51 clocks as from/to points 324
code-introduced 315
encryption defined 315
asymmetric 397 POS 322
methodologies 396 priority 316
symmetric 396
False Paths panel, SCOPE 315
encryption algorithms 396
Fanout Guide option (Xilinx) 689
encryptIP script 402
command-line arguments 403 fanouts (Altera) 624

750 September 2016
Index
fanouts (Xilinx) 688 opening recent project 79

Fast Synthesis mode (Synplify organization into folders 200
Premier) 133 output
See output files
FDC
project (.prj) 24, 244
set_reg_input_delay 509
removing from project 101
set_reg_output_delay 510
replacing in project 105
standard collection commands 587
RTL view (.srs) 249
fdc srr 250
precedence over sdc 275 srs See srs file
fdc constraints 276 stand-alone timing report (.ta) 176
generation process 274 state machine encoding (.fse) 248
fdc file Synplicity archive file (.sar) 249
relationship with other constraint synthesis output 248
files 271 temporary 195
timing report. See also timing report
file format options file 179
project command (Altera) 642 Verilog (.v) 244
File menu VHDL (.vhd) 244
Recent Projects submenu 79 files for synthesis 244
File Options command 229 Filter Schematic command 191
files popup menu 233
_est.srr 248 filtered schematic, compared with
.est 248 unfiltered 348
.fse 248
filtering
.info 248
designs 374
.ini 244
commands, definition 374
.prj 24, 244
compared with flattening 379
.sar 249
FSM states and transitions 46, 98
.sdc 244
paths from pins or ports 194
.srr 250
selected objects 191
.srs 249
timing reports 178
.ta 250
.ta See also timing report file 179 Find again command 85
.v 244 Find command
.vhd 244 HDL Analyst 88
.xnf (Xilinx). See xnf file (Xilinx) Text Editor 85
adding to project 102 find command
area estimation (.est) 248 filter properties 555
compiler output (.srs) 249
constraint (.sdc) 244 finding
copying 227, 228 information on synthesis tool 28
customized timing report (.ta) 250 GUI 23
design component info (.info) 248 finite state machines
est 248 See state machines
estimation log (_est.srr) 248 Fix gated clock conversion report
estimation, area (.est) 248 log file (.srr) 253
initialization (.ini) 244
log (.srr) 250 Flatten Current Schematic
command 378
log. See log file
filtered schematic 192

September 2016 751
Index
unfiltered schematic 191 FSM Viewer 45

Flatten Schematic command 378 popup menu 241
popup menu commands 241
flattened schematic, creating 188
FSMs (finite state machines)
Flattened View command 188 See state machines
flattening Full View command 96
commands 376
compared with filtering filtering 379
instances 195, 377 G
schematics 191
gated clocks (Altera) 627
Floating License Usage command 222
gated clocks (Xilinx) 690
folders for project files 200
generated clocks (Altera) 627
force function 120
generated clocks (Xilinx) 691
foreach_in_collection command 593
generic technology library 247
formal verification
get_object_name command 595
Altera DSP blocks 623
Go to SolvNet command 221
forward annotation
initial values 462 Go to Technical Resource Center
command 216
Forward Annotation of Initial Values
Verilog 462 Goto command 86
Forward command 97 Goto Net Driver command
current level 190
forward-annotation hierarchical 189
Altera RAM init values 463
Xilinx 696 graphical user interface (GUI),
overview 31
FPGA Implementation Tools
command 221 grey boxes
using 635
FPGA timing constraints 474
GTECH library. See generic technology
frequency library
and period 332
gtech.v library 247
from points
clocks 323 gui
multiple 319 synthesis software 22
object search order (Timing GUI (graphical user interface),
Analyzer) 182 overview 31
objects 318
timing analyzer 182 H
from/to constraints
point-to-point delays 344 HDL Analyst
Find command 88
fse file 248 Visual Properties 97
FSM Compiler, enabling and disabling HDL Analyst menu 188
locally, for specific register 52 Current Level submenu 190
FSM encoding file (.sfe) 248 Hierarchical submenu 189
FSM Explorer command 140 RTL submenu 188
Select All Schematic submenu 196
FSM Table command 98
Select All Sheet submenu 196
FSM toolbar 64

752 September 2016
Index
HDL Analyst Options command 197 Clock Tree 44

HDL Analyst tool 347 commands 236
Clock Tree 44 moving between objects 45
configuring 364 popup menu 236
crossprobing 361 refreshing 236
filtering designs 374 RTL view 42
finding objects 359 symbols (legend) 45
hierarchical instances trees of objects 44
hidden 354 hierarchy browser
transparent and opaque 353 enabling/disabling display 209
multiple-sheet schematics 364 hierarchy separator 511
object information, viewing 350
preferences 364 home directory (UNIX) 244
push/pop mode 367 HOME environment variable (UNIX) 244
ROM table viewer 467 How to Use Help command 222
schematics
filtering 374
multiple sheets 364
I
sheet size, setting 364 I/O constraints
status bar information 350 multiple on same port 342
title bar information 364
I/O insertion
HDL Analyst toolbar Altera Cyclone 637
See Analyst toolbar Altera Stratix 637
HDL Analyst views 348 Arria 637
header, timing report 254 VHDL automatic (Xilinx) 683
VHDL manual (Xilinx) 685
help
online I/O insertion (Altera) 626
accessing 23 I/O insertion (Xilinx) 674, 677
Help command 222 I/O locations
Help menu 222 assigning in SCOPE (Xilinx) 680
auto assigning (Xilinx) 681, 683
hidden hierarchical instances 354 manually assigning (Xilinx) 682, 685
are not flattened 378
I/O pads
Hide Instances command 194 instantiating (Xilinx) 674, 677
hiding instances 194 I/O Standard panel, SCOPE 304
hierarchical instances I/O standards
See instances, hierarchical QSF constraints 394
hierarchical schematic sheet, IEEE 1364 Verilog 95 standard 246
definition 364
images, printing 78
Hierarchical View command 188
Impact Analysis view popup menu 225
hierarchy
flattening 191 implementation options
compared with filtering 379 Options Panel 133
pushing and popping 367 Implementation Options
schematic sheets 364 command 101, 114
Hierarchy Browser 370 Implementation Results panel 117
changing size in view 42 implementations

September 2016 753
Index
creating 101 hiding and unhiding 194

naming 228 hierarchical
Import IP Package command 101, 106 compared with primitive 352
definition 352
include command dissolving 372
verilog library directories 121 hidden 354
incremental compilation 119 making transparent 372
indenting a block of text 49 opaque and transparent 353
isolating paths through 194
indenting text (Text Editor) 49
making transparent 195
index_collection command 596 name display 207
inference naming syntax, Verilog constraints 535
Xilinx BUFGMUX/BUFGMUX_1 675 naming syntax, VHDL constraints 537
Xilinx I/O buffers 675 primitive, definition 352
inferring RAMs (Xilinx) 669 selecting all in schematic 196
info file (design component info) 248 Instances command
schematic selection 196
ini file 244 sheet selection 196
initial value data file interface information, timing report 256
Verilog 459
IP cores (SYNCore)
Initial Values building ram models 146
forward annotation 462
Isolate Paths command 194
initial values
$readmemb 458
$readmemh 458 J
Xilinx 656 Job Status command 142, 143
initial values (Verilog) jobs
netlist file (.srs) 462 running in parallel 198
initialization file (.ini) 244
input files 244 K
.ini 244
.sdc 244 keyboard shortcuts 66
.v 244, 245 arrow keys (Hierarchy Browser) 371
.vhd 245 keyword completion, Text Editor 49
vhd 244
Inputs/Outputs panel, SCOPE 339 L
inserting
bookmarks (Text Editor) 49 labels, displaying 207
instances latches
dissolving 195 mapping (Xilinx) 666
expanding paths between 189 legacy sdc file. See sdc files, difference
expansion maximum limit 209 between legacy and Synopsys
expansion maximum limit (per filtered standard
sheet) 211 legacy timing constraints 513
expansion maximum limit (per define clock 514
unfiltered sheet) 211 define_clock_delay 517
finding by name 85 define_false_path 518
hidden 354 define_input_delay 521

754 September 2016
Index
define_multicycle_path 523 macro libraries (Xilinx) 677

define_output_delay 527 macros
define_path_delay 529 libraries 245
define_reg_input_delay 532
mapping
levels 64-bit 231
See hierarchy
Mapping of Multipliers During Formal
libraries Verification
general technology 246 Altera Stratix 628
macro, built-in 245
megafunctions
technology-independent 246
Clearbox 634
VHDL
grey boxes 635
attributes and constraints 245
memory compiler 146
license
floating 222 memory, saving 195
saving 223 menubar 76
specifying in batch mode 26 menus
License Agreement command 222 context-sensitive
Limit Number of Paths 181 See popup menus
Edit 85
Log File
HDL Analyst 188
HTML 100
Help 222
text 100
Options 197
log file popup
displaying 96 See popup menus
log file (.srr) 250 Project 101
Log File command Run 140
View menu 100 Tools 146
View 95
log file report 250
clock buffering 252 message viewer
errors, warnings, notes, and description 36
messages 251 Messages Tab 36
fix gated clock conversion 253 modules
net buffering 252 naming syntax, Verilog constraints 535
Lowercase command 86 naming syntax, VHDL constraints 536
LPMs mouse button operations 55
prepared components (Altera) 617 mouse operations 53
LUT6_2 primitives 667 Mouse Stroke Tutor 53
LUTRAM Mouse Stroke Tutor command 222
examples 429
mouse wheel operations 57
LUTRAMs 429
moving between objects in the Hierarchy
LUTRAMs, inferring 429 Browser 45
multicycle constraints
M start/end clock period 345
macro libraries multicycle paths
Altera Verilog 608 clocks as from/to points 323
Altera VHDL 608

September 2016 755
Index
define_multicycle_path. See Next Sheet command 97

define_multicycle_path Normal View command 96
examples 313
POS 322 nram
SCOPE UI 312 Xilinx implementations 673
using different start/end clocks 312
Multi-Cycle Paths panel, SCOPE 312 O
Multiple File Compilation Unit object prefixes
Verilog panel 120 Tcl find command 547
multiple projects object properties
displaying project files 200 annotated properties for analyst 555
multiple-sheet schematics 364 object search order (Timing
multi-port RAMs Analyzer) 182
Xilinx implementations 673 object types
multisheet schematics Tcl find command 547
transparent hierarchical instances 366 objects
crossprobing 361
N displaying compactly 209
dissolving 372
naming rules 511 expanding paths between 189
naming syntax filtering 191
Verilog 535 information, viewing (HDL Analyst
VHDL 537 tool) 350
making transparent 372
navigating status bar information 350
among hierarchical levels unselecting
by pushing and popping 367 all in schematic 196
with the Hierarchy Browser 370
among the sheets of a schematic 364 objects, schematic
See schematic objects
nesting design details (display) 372
online documents
net buffering report, log file 252 PDF reader (UNIX) 212
net drivers Online Documents command 222
displaying and selecting 189
Online help
netlist file F1 key 23
initial values (Verilog) 462
online help
nets accessing 23
expanding hierarchically from pins and
ports 189 opaque hierarchical instances 353
finding by name 85 are not flattened 378
naming syntax, Verilog constraints 535 Open command
naming syntax, VHDL constraints 537 File menu 78
selecting instances on 190 Open Project command 78
New command 78 opening
New Implementation command 101, 106 project 78
New Project command 79 openIP encryption 410
Next Bookmark command 86 operators
Next Error command 142 Tcl collection 563

756 September 2016
Index
optimization Options for implementation dialog box

state machines 51 Prototyping Tools 130
options parallel jobs 198
Altera Cyclone 636 parameters
Altera Stratix 638 SYNCore adder/subtractor 169
Project view 73 SYNCore byte-enable RAM 161
Spartan (Xilinx) 700 SYNCore counter 173
Virtex (Xilinx) 700 SYNCore FIFO 148
Options for implementation dialog SYNCore RAM 158
box 106, 114 SYNCore ROM 165
Constraints panel 136 parity bus, Xilinx block RAM 673
Device panel 129
Options panel 133 Partition Device view 39
Place and Route Jobs panel 130 Partition Info view 39
Prototyping Tools panel 130 Partition Tree view 39
Synplify Premier/DP 114
Timing Report panel 138 Partition view 39
Verilog panel 117 popup menu 225
VHDL panel 126 Partition/SLP panel 115
Options menu 197 partitioning of schematics into
sheets 364
Options panel
Options for implementation dialog Paste command 85
box 133 pasting 60
Other panel, SCOPE 346 path delays
output files 248 clocks as from/to points 324
_est.srr 248 path filtering 181
.est 248
paths
.info 248
expanding hierarchically from pins and
.sar 249 ports 189
.srr 250
.srs 249 performance summary, timing
.ta 250 report 255
.xnf (Xilinx). See xnf files (Xilinx). 648 period, relationship to frequency 332
log. See log file pin location constraints
srs QSF 393
See srs file
pin locations
See also files
automatic insertion (Xilinx) 683
overriding FSM Compiler 637 specifying (Xilinx) 675, 680
Overview of the Synplicity Synthesis pins
Tools 21 displaying
on technology-specific primitives 357
P on transparent instances 357
displaying names 207
pad cell insertion file, Altera 613 displaying on transparent
pads instances 195
disabling I/O insertion (Xilinx) 674 expanding hierarchically from 189
expanding paths between 189
Pan command 96
isolating paths from 194
panels maximum on schematic sheet 211

September 2016 757
Index
pipelining (Altera) 626 Timing Analyzer points 182

pipelining (Xilinx) 690 prepared components
Place and Route Jobs panel Altera VHDL 617
Options for implementation dialog Previous bookmark command 86
box 130 Previous Error/Warning command 142
PLL constraints 609, 612 Previous Sheet command 97
pointers, mouse primitive instances, definition 352
cross-hairs 56
push/pop arrows 370 Print command 78
zoom 96 Print Image command 78
popping up design hierarchy 367 Print Setup command 78
popup menus printing
Certify 225 schematic 78
FSM Viewer 241 view 78
Hierarchy Browser 236 private key 397
Impact Analysis view 225
Partition view 225 prj file 24, 244
Project view 226 Product of Sums
RTL view 235 See POS
Tcl window 225, 232 project command
Technology view 235 Altera file formats 642
Trace Assignments window 225 Spartan (Xilinx) 704
port names Virtex (Xilinx) 704
in EDIF files (Xilinx) 696 project files
ports organization into folders 200
displaying names 207 project files (.prj) 24, 244
expanding hierarchically from 189
Project menu 101
expanding paths between 189
commands 101
finding by name 85
isolating paths from 194 Project Options command 226
naming syntax, Verilog constraints 535 Project view 32
naming syntax, VHDL constraints 537 buttons and options 73
selecting all in schematic 196 display settings 199
Ports command options 73
schematic 196 popup menu 226
sheet 196 setting up 199
Synplify Premier/DP 32
POS
Synplify Pro 32
interface 321
Synplify tool 32
precedence of constraint files 275
Project View Options command 197
preferences
Project window 32
display 214
HDL Analyst tool 364 project_name_cck.rpt file 260
project file display 199 projects
Project view display 57 adding files 102
Preferred License Selection closing 79
command 223 creating (Build Project) 78
prefixes creating (New) 79

758 September 2016
Index
displaying multiple 200 recent projects, opening 79

opening 78 Redo command 85
properties reference manual, role in document
find command 555 set 17
Properties command 98 register inference (Xilinx) 661
prototyping overview 19 registers
Prototyping Tools panel, Options for DDR (Xilinx) 662
implementation dialog box 130 inferring clock enables (Xilinx) 661
public key 397 Registers panel, SCOPE 343
Push Tristates regular expressions
Verilog panel 119 Tcl find command 548
Push/Pop Hierarchy command 97 relative position, Xilinx components 686
push/pop mode, HDL Analyst tool 367 Reload command 236
Remove Files From Project
Q command 101
Remove Implementation command 228
QSF constraints
example 394 remove_from_collection command 598
supported 393 removing
qsf2sdc 392 bookmark (Text Editor) 49
syntax 392 Replace command
Quartus Text Editor 86
.vqm netlist 602 replacing
converting constraints to sdc 392 text 93
edif and vqm file names 632 replication
library versions 608 Altera 625
qsf2sdc utility. See qsf2sdc 392
reports
Quartus megafunctions constraint checking (cck.rpt) 260
pad cell insertion 612 resource usage (Xilinx) 693
quitting a synthesis run 143 resource usage, Altera 629
timing report (.ta file) 176
R reset_path timing constraint 481
resets
RAM inference
packing in Altera DSP blocks 622
Altera Stratix 614
resolving conflicting timing
RAM inference (Altera) 614 constraints 325
RAM inference (Xilinx) 669 Resource Center
RAM mapping See Technical Resource Center
Altera Stratix 614 resource sharing
RAM with control signals examples 432 Resource Sharing option 133
RAMs Resynthesize All command 140
initial values (Verilog) 458 retiming (Altera) 627
multi-port, Xilinx 673
retiming (Xilinx) 690
RAMs, inferring
advantages 414 rise constraints 335

September 2016 759
Index
ROM inference (Altera) 615 compared with filtering 379

ROM inference examples 467 selectively 377
hierarchical (definition) 364
ROM initialization multiple-sheet 364
with rom.info file 470 object information, viewing 350
with Verilog generate block 471 opening hierarchical RTL 188
rom.info file 467 partitioning into sheets 364
ROMs printing region 78
Altera implementations 616 sheet connectors 209, 351
sheets
RTL view 42
navigating among 364
displaying 62
size, setting 364
file (.srs) 249
size in view, changing 42
opening hierarchical view 188
unfiltered and filtered 348
popup menu 235
unfiltering 375
unselecting objects 196
printing 78
SCOPE
Run menu 140
Collections panel 295
Run Tcl Script command 141, 142 for legacy sdc 279
SCOPE spreadsheet
S naming syntax 287
s2o utility 410 starting 286
sar file sdc
Archive Project command 107 fdc precedence 275
Save All command 78 SCOPE for legacy files 279
Save As command 78 standard sdc collection commands 587
Save command 78 SDC constraints
from Altera QSF 393
scan chains
Altera DSP blocks 620 sdc file
difference between legacy and
schematic objects Synopsys standard 273
crossprobing 361
definition 350 sdc2fdc utility 382
displaying compactly 209 searching
dissolving 372 RTL/Technology views 359
expanding paths between 189 Select All command 85
filtering 191
information, viewing (HDL Analyst Select All States command 98
tool) 350 Select Net Driver command
making transparent 372 current level 190
status bar information 350 hierarchical 190
unselecting all 196 Select Net Instances command
schematics current level 190
crossprobing 361 hierarchical 190
displaying labels 207 Selected command 98
filtered and unfiltered 348
filtering 374 selecting
finding objects 359 text column (Text Editor) 49
flattening 191

760 September 2016
Index
selecting multiple objects using the Ctrl size, setting 364

key 55 shift registers
sequential elements Altera definition 612
naming 511 shortcuts
sequential optimizations keyboard
disabling 637 See keyboard shortcuts
disabling (Altera) 627 Show All Hier Pins command 195
disabling (Xilinx) 691
Show Context command 194
Set Library command 101
single-port RAM examples 420
set modules command (collections) 296
sizeof_collection command 600
set modules_copy command
(collections) 296 slack
defined 255
Set VHDL Library command 101
slack margin 181
set_clock_groups timing constraint 483
srd file 249
set_clock_latency timing constraint 486
SRL tables (Xilinx) 664
set_clock_route_delay timing
constraint 488 srm file
hidden logic not saved 195
set_clock_uncertainty timing
constraint 489 srr file 250
See log file
set_datapathonly_delay legacy timing
constraint 534 srs file 249
hidden logic not saved
set_datapathonly_delay timing
constraint 492 initial values (Verilog) 462
set_false_path timing constraint 494 standards, supported
Verilog 246
set_hierarchy_separator command 511 VHDL 245
set_input_delay timing constraint 497 start/end clock period
set_max_delay timing constraint 499 multicycle constraints 345
set_multicycle_path timing start/end points
constraint 502 Timing Report panel, Options for
set_option command implementation dialog box 138
Altera description 639 starting Synplify 25
Altera Stratix, Cyclone, and Arria starting Synplify Premier 25
device syntax 637
Altera Stratix, Cyclone, and Arria starting Synplify Premier DP 25
synthesis syntax 638 starting Synplify Pro 25
set_output_delay timing constraint 506 startup block (Xilinx) 655
set_reg_input_delay timing state machines
constraint 509 displaying in FSM viewer 196
set_reg_output_delay timing encoding
constraint 510 displaying 47
set_rtl_ff_names command 511 FSM Compiler 51
file, encoding (.fse) 248
sheet connectors 209, 351 filtering states and transitions 46, 98
sheets, schematic 364 optimization 51
hierarchical (definition) 364 state encoding, displaying 47
navigating among 364

September 2016 761
Index
Status Bar command 95 ROM parameters 165

status bar information, HDL Analyst SYNCore wizard 146
tool 350 synhooks.tcl file 389
stopping a synthesis run 143 Synopsys FPGA implementation tools
Stratix 636 product information 221
core voltage for Stratix III 624 Synopsys FPGA products 221
device options 636
file format options 638 Synopsys Home Page command 221
set_option device options 637 Synopsys standard sdc file. See sdc files,
set_option synthesis options 638 difference between legacy and
Synopsys standard
supported standards
Verilog 246 Synopsys Training Page command 221
VHDL 245 Synplicity
symbols product family 18
enabling name display 207 web site 223
finding by name 85 Synplicity customer support,
Hierarchy Browser (legend) 45 contacting 29
syn_keep synplicity directory (UNIX) 244
DSP block inference, Altera 621 Synplicity Support command 216
syn_loc attribute Synplicity Synthesis Tools
translating Altera QSF constraints 395 overview 21
syn_maxfan attribute Synplify
Altera 625 Project view 32
Xilinx designs 689
synplify command-line command 26
syn_multstyle
DSP block inference, Altera 621 Synplify Premier
prototyping 19
syn_preserve
DSP block inference, Altera 621 synplify premier command-line
command 26
syn_reference_clock attribute
synplify premier dp command-line
effect on multiple I/O constraints 342 command 26
syn_replicate attribute Synplify Premier DP tool
Altera fanouts 625 overview 19
SYN_TCL_HOOKS variable 389 Synplify Premier tool
syn_tristatetomux attribute overview 19
effect of tristate pushing 126 Synplify Premier/DP
syn_useioff Project view 32
DSP block inference, Altera 621 Synplify Premier/DP tools
synchronous sets/resets user interface 22
inferring registers with (Altera) 612 Synplify Pro synthesis tool
Xilinx 661 overview 18
SYNCore Synplify Pro tool
adder/subtractor parameters 169 Project view 32
byte-enable RAM parameters 161 user interface 22
counter parameters 173
FIFO parameters 148 Synplify synthesis tool
RAM parameters 158 overview 18

762 September 2016
Index
Synplify tool collections 296

user interface 22 constraint files 277
synplify_pro command-line pasting 35
command 26 syntax for Tcl hooks 389
syntax Tcl expand command 560
bus dimension separator 512 Tcl find command 544
bus naming 512 case sensitivity 550
Syntax Check command 141 examples 550
object prefixes 547
synthesis
object types 547
log file (.srr) 250
regular expression syntax 548
Synthesis Check command 141 special characters 548
Synthesis Constraints Optimization syntax 545
Environment (Legacy SCOPE) wildcards 548
See Legacy SCOPE spreadsheet TCL Help command 222
synthesis jobs Tcl scripts
monitoring 143 running 141, 142
synthesis software Tcl shell command
flow 28 sdc2fdc 382
gui 22
Tcl window
synthesis_off directive, handling 127 popup menu 225, 232
synthesis_on directive, handling 127 popup menu commands 35
Synthesize command 140 Tcl Window command 95
SystemVerilog 119 Technical Resource Center
accessing 221
T specifying web browser (UNIX) 212
web browser 212
ta file (customized timing report) 250 technologies
Tcl Spartan (Xilinx) 703
c_diff collection command 564 Virtex (Xilinx) 703
c_intersect collection command 565 Technology view
c_list collection command 566 popup menu 235
c_print collection command 567 printing 78
c_symdiff collection command 567
technology-specific primitives
c_union collection command 568
pin names, displaying 357
collection commands 563
set_modules collection command 571 text
copying, cutting and pasting 85
Tcl collection commands 563
replacing 93
c_diff 564
c_intersect 565 Text Editor
c_list 566 features 48
c_print 567 indenting a block of text 49
c_symdiff 567 opening 48
c_union 568 popup menu commands 232
set_modules 571 printing 78
selecting text column 49
Tcl collection operators 563
view 47
Tcl commands
text editor

September 2016 763
Index
completing keywords 49 customized (.ta file) 250

Text Editor view 47 defining through points 179
detailed clock report 257
The Synplicity Product Family 18 file (.ta) 176, 250
through constraints header 254
point-to-point delays 301, 345 interface information 256
through points performance summary 255
clocks 324 specifying slack margin 181
lists, multiple 321 using path filtering 181
lists, single 320 timing report file
multiple 321 generating custom 177
product of sums UI 321 stand-alone 179
single 320 Timing Report panel
specifying for timing exceptions 320 Number of Critical Paths 138
specifying for timing report 179 Options for implementation dialog
timing analyst box 138
generating report 176 Start/End Points 138
timing analyzer timing reports
wildcards 185 asynchronous clocks 259
timing annotated properties (.tap) 250 file. See timing report file
filtering 178
timing constraints parameters 176
checking 141, 227 stand-alone 176
conflict resolution 325 stand-alone (.ta file) 176
constraint priority 325
create_clock 475 Tip of the Day command 223
create_generated_clock 478 title bar information, HDL Analyst
FPGA 474 tool 364
reset_path 481 to points 182
See constraints clocks 323
set_clock_groups 483 multiple 319
set_clock_latency 486 objects 318
set_clock_route_delay 488 Timing Analyzer 182
set_clock_uncertainty 489
Toggle bookmark command 86
set_datapathonly_delay 492, 534
set_false_path 494 toolbars 59
set_input_delay 497 FSM 64
set_max_delay 499 Toolbars command 95
set_multicycle_path 502 Tools menu 146
set_output_delay 506 commands 146
set_reg_input_delay 509
set_reg_output_delay 510 tooltips
displaying 99
timing exceptions
False Paths panel 315 Trace Assignments window popup
multicycle paths 312 menu 225
priority 325 Translate Constraints command 141
specifying paths/points 315 translating constraints 143
timing report 254 transparent hierarchical instances 353
asynchronous clock report 178 lower-level logic on multiple sheets 366
clock relationships 255 operations resulting in 373

764 September 2016
Index
pins and pin names, displaying 357 V

transparent instances
displaying pins 195 v file 244
trees of objects, Hierarchy Browser 44 variables
HOME (UNIX) 244
trees, browser, collapsing and
expanding 44 vendor technologies
TriMatrix memory 615 Altera 601
Xilinx 647
tristates
pushing tristates, description 124 verification mode (Xilinx) 628, 691
pushing tristates, example 124 Verilog
pushing tristates, pros and cons 125 ifdef and define statements 122
true dual-port block RAM 673 beta features 123
compiler, configuring 197
true dual-port RAM extract design parameters 122
See also multi-port RAMs Forward Annotation of Initial
Values 462
U generic technology library 247
initial value data file 459
Undo command 85 initial values for RAMs 458
Unfilter command 98 library directories 121
naming syntax for constraints 535
unfiltered schematic, compared with
filtered 348 ROM inference 467
source files (.v) 244
unfiltering 194 specifying compiler directives 122
FSM diagram 98 supported standards 246
schematic 194, 375
Verilog 2001 246
Unflatten Current Schematic Verilog panel 119
command 192
Verilog 95 246
Unhide Instances command 194
Verilog include files
unhiding hidden instance 194 using _SEARCHFILENAMEONLY_
UNIX directive 123
configure external programs 198 Verilog panel 119
Unselect All command 196 Allow Duplicate Modules 120
View menu (FSM Viewer) 98 Multiple File Compilation Unit 120
updates from the Resource Center 221 options 119
Options for implementation dialog
Uppercase command 86 box 117
user interface Push Tristates 119
Synplify Premier/DP tools 22 SystemVerilog 119
Synplify Pro tool 22 Verilog source file (.v) 245
Synplify tool 22
version information 223
user interface, overview 31
vhd file 244
using the mouse 53
vhd source file 244
utilities
qsf2sdc 392 VHDL
s2o 410 compiler, configuring 197
sdc2fdc 382 enumeration encoding, default 127
ignoring code with synthesis off/on 127

September 2016 765
Index
libraries naming syntax, VHDL constraints 536

attributes, supplied with synthesis Tcl find command 547, 548
tool 245 text Find 87
naming syntax for constraints 536 text replacement 93
source files (.vhd) 244 timing analyzer 185
supported standards 245 window
VHDL libraries Project 32
setting up 105 windows 32
VHDL library wizards
specifying non-default (Altera) 608 Board 60
VHDL panel Workspace Options command 226
DesignWare options 121, 128
Options for implementation dialog
box 126 X
VHDL source file (.vhd) 245 xflow and xtclsh 697
View FSM command 196 Xilinx
View FSM Info File command 196 attributes 705
View Log File command 96 black boxes 658, 674
block RAMs 669
View menu 95 byte-enable RAM 446
Filter submenu 98 byte-wide write enable RAM 449
Log File command 100 compile point timing data 692
RTL and Technology view constraints 652
commands 97
core generator 653
View Result File command 96 DDR register inference 662
View Sheets command 97 defining clock on instance 696
views 32 directives 705
FSM 45 distributed RAM 438
HDL Analyst 348 dynamic SRL tables 664
managing 58 fanout limits 688
Project 32 forward-annotation 696
RTL 42 gated clocks 690
generated clocks 691
VIF I/O insertion 677
mapping multipliers (Altera I/O insertion, manual 685
Stratix) 628 I/O locations 675, 680
virtual clocks 333 inferring dynamic SRL 664
Visual Properties command 97 initial values 656
instantiating I/O pads 674, 677
vqm files
macro libraries 677
naming requirements 632
mapping latches 666
multi-port RAMs 673
W packing IOBs 655, 675
pin locations for automatically inserted
web browser, specifying for UNIX 212 I/Os 683
web updates 221 pipelining 690
wide adder/subtractor 668 port names 696
RAMs 669
wildcards register balancing 690
naming syntax, Verilog 535

766 September 2016
Index
register inference 661

relative locations attributes 686
resource usage report 693
retiming 690
Spartan device options 698
Spartan options 700
Spartan project command 704
Spartan technologies 703
specifying pin location 675, 680
startup blocks 655
technologies 647
translating PAD file to constraint
file 143
true dual-port RAM. See multi-port
RAMs
updating compile points 692
verification mode 628, 691
Virtex device options 698
Virtex options 700
Virtex project command 704
Virtex technologies 703
Xilinx differential I/O buffer
inference 675
Xilnx forward-annotation
datapath 534
datapath only 492
xnf file (Xilinx) 648
xtclsh executable 697
Z
zoom
using the mouse wheel and Ctrl key 57
zoom mouse pointer 96
Zoom Out command 96

September 2016 767
Index

768 September 2016
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September 2016 769
Index

770 September 2016
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September 2016 771
Index

772 September 2016
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September 2016 773
Index

774 September 2016
Index

September 2016 775
Index

776 September 2016
Index

September 2016 777
Index

778 September 2016
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September 2016 779
Index

780 September 2016

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Destination Control Statement

2016 Synopsys, Inc. Certify Reference Manual

Certify Reference Manual 2016 Synopsys, Inc.

2016 Synopsys, Inc. Certify Reference Manual

Chapter 1: Product Overview

Chapter 2: User Interface Overview

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Using The Mouse Wheel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Chapter 3: User Interface Commands

2016 Synopsys, Inc. Certify Reference Manual

Archive Project Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Certify Reference Manual 2016 Synopsys, Inc.

HDL Analyst Options Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Chapter 4: Input and Result Files

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Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Chapter 6: SCOPE Constraints Editor

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Specifying From, To, and Through Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

Chapter 7: HDL Analyst Tool

2016 Synopsys, Inc. Certify Reference Manual

Filtering and Flattening Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

Chapter 9: RAM and ROM Inference

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RAM with Control Signals Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

Chapter 10: Timing Constraint Syntax

Chapter 11: FPGA Design Constraint Syntax

2016 Synopsys, Inc. Certify Reference Manual

Tcl Find -filter Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

Appendix A: Designing with Altera

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Integration with Altera Tools and Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

Appendix B: Designing with Xilinx

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Specifying Pin Locations and Inserting I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

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2016 Synopsys, Inc. Certify Reference Manual

This document is part of a documentation set that includes reference and

The following provide an introduction to the synthesis tools.

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The Synopsys FPGA Product Family

FPGA DSP Prototyping

FPGA Synthesis DSP Design ASIC RTL Prototyping

Physical Synthesis Identify

Synplify and Synplify Pro Tools

These tools accept high-level input written in industry-standard hardware

2016 Synopsys, Inc. Certify Reference Manual

Synplify Premier Tool

The Synplify Premier product supports the following flows:

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Identify Tool Set

Synphony Model Compiler Tool

2016 Synopsys, Inc. Certify Reference Manual

resources of the FPGAs. Unlike traditional ASIC prototyping techniques, the

Overview of the Synthesis Tools

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During synthesis, the BEST algorithms recognize high-level abstract struc-

Graphic User Interface

Project window Flow/Results

Tcl window Message/Status

2016 Synopsys, Inc. Certify Reference Manual