ENS2456 Digital Electronics

Tutorial 04
Solutions
1. Trace the behaviour of an SR latch for the following situation: Q, S, and R have been
0 for a long time, then S changes to 1 and stays 1 for a long time, then S changes
back to 0. Using a timing diagram, show the values that appear on wires S, R, Q, and
Q. Assume logic gates have a tiny nonzero delay.

S
0

R
0

Q
0

Q'
0

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2. Trace the behaviour of a level-sensitive SR latch (see below) for the input pattern
in Figure 1. Assume S1, R1, and Q are initially 0. Complete the timing diagram,
assuming logic gates have a tiny but non-zero delay.

Figure 1.

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3. Trace the behaviour of a D latch (see below) for the input pattern in Figure 2. Assume Q is
initially 0. Complete the timing diagram, assuming logic gates have a tiny but non-zero
delay.

Figure 2.

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4. Create a circuit of three level-sensitive D latches connected in series (the output of one is
connected to the input of the next). Use a timing diagram to show how a clock with a long
high-time can cause the value at the input of the first D latch to trickle through more than
one latch during the same clock cycle.

5. Repeat problem 8 using edge-triggered D flip-flops, and use a timing diagram to show
how the input of the first D flip-flop does not trickle through to the next flip-flop no matter
how long the clock signal is high.

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6. Design a synchronous MOD-8 binary up/down counter. Use D flip-flops.

The PRESENT state/NEXT state table for MOD-8 binary up/dn counter

MOD-8 Binary UP/DN Counter

PRESENT NEXT Flip-Flops

State State Control Inputs

DEC UP/DN C B A C B A DC DB DA

0 0 0 0 0 0 0 1 0 0 1
1 0 0 0 1 0 1 0 0 1 0
2 0 0 1 0 0 1 1 0 1 1
3 0 0 1 1 1 0 0 1 0 0
4 0 1 0 0 1 0 1 1 0 1
5 0 1 0 1 1 1 0 1 1 0
6 0 1 1 0 1 1 1 1 1 1
7 0 1 1 1 0 0 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1
9 1 0 0 1 0 0 0 0 0 0
10 1 0 1 0 0 0 1 0 0 1
11 1 0 1 1 0 1 0 0 1 0
12 1 1 0 0 0 1 1 0 1 1
13 1 1 0 1 1 0 0 1 0 0
14 1 1 1 0 1 0 1 1 0 1
15 1 1 1 1 1 1 0 1 1 0

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Boolean equation for the input of each D flip-flop

DC DB
B B

0 0 1 0 0 1 0 1

1 1 0 1

0 1 0 1


C

C
0 1 1 1 1 0 1 0
UP/DN UP/DN
1 0 0 0 1 0 1 0

A A

DC = UP/DNC'B'A' + UP/DNCA + DB = UP/DN'B'A + UP/DN'BA +

+ CBA' + UP/DN'CB' + UP/DN'C'BA + UP/DNB'A' + UP/DNBA
DA
B

1 0 0 1
1 0 0 1


C
1 0 0 1
UP/DN
1 0 0 1

A
DA = A'

Implementation
A B C

D Q D Q D Q

A B C

CLK Q Q Q

C'
C
B'

UP/DN B
A
A'
UP/DN

UP/DN'

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7. Using the process for designing a controller, convert the FSM of figure below to a
controller, implementing the controller using a state register and logic gates.

Step 1 - Capture the FSM

The appropriate FSM is given above.

Step 2A - Set up the architecture

Step 2C - Fill in the truth table

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Step 2D - Implement the combinational logic

n1 = s1s0a + s1s0a + s1s0a = s1s0a + s1s0

n0 = s1s0a + s1s0a + s1s0a + s1s0a = s1a + s1s0
y = s1s0a + s1s0a + s1s0a + s1s0a = s1s0 + s1s0 = s1 xor s0

8. Reverse engineer the behaviour of the sequential circuit shown in figure below.

For this problem, we carry out the controller design process in reverse. We already
have step 2D completed above, so we will begin with step 2C.

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Step 2C - Fill in the truth table

Step 2B - Encode the states

We will name the encodings as states as follows: 00=A, 01=B, 10=C, and 11=D.

Step 2A- Set up the architecture

The architecture has already been defined

Step 1 - Capture the FSM

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