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Processor
What we are going to learn in this
session:
M68k hardware architecture:
M68k pin assignments
Pin functions.
The M68k Microprocessor
M68000, M68k microprocessor.
Motorola Semiconductors, 1979.
16-bit processor, but can perform 32-bit
operations.
Speed: 8-12 MHz.
The M68k Microprocessor
Very advanced compared to 8-bit
processors:
16-bit
data bus, 24-bit address bus.
Can execute instructions twice as fast.
AS
FC0 R/W
Processor Status FC1 UDS Asynchronous
Bus Control
FC2 68000 LDS
E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control
AS
FC0 R/W
Processor Status FC1 UDS Asynchronous
Bus Control
FC2 68000 LDS
E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control
10 ns 10 ns
Processor Status
Pins
+5V
AS
FC0 R/W
Processor Status FC1 UDS Asynchronous
Bus Control
FC2 68000 LDS
E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control
Data Bus
FC2 SUPERVISOR
EN
MEMORY
SPACE
AS
Address Bus
EN USER
MEMORY
SPACE
FC to Generate Interrupt
Acknowledge Signal
AS
FC0
68000 INTACK Device
Requesting
FC1
Interrupt
FC2
6800 Peripheral
Control
+5V
AS
FC0 R/W
Processor Status FC1 UDS Asynchronous
Bus Control
FC2 68000 LDS
E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control
Three pins:
E:Clock
VMA: Valid Memory Address.
VPA: Valid Peripheral Address.
Synchronous Data Exchange
Mode where:
Data exchange performed using same timing.
Timing generated by single clock signal.
Shared by all synchronous devices.
E 6800 Timing Signal
Synchronizes data transfer M68k &
6800:
Shared timing signal for slower 6800 devices.
Generated by M68k (output).
Modified CLK signal (/10).
AS
FC R/W
0
Processor Status FC UDS Asynchronous
1 Bus Control
FC 68000 LDS
2
E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control
Functions:
To receive error notifications.
Stop/reset M68k operations.
Stop/reset peripherals.
BERR Bus Error
Receives information of bus error.
From watchdog circuit.
Only informs M68k, doesnt do anything else.
One-directional: into M68k.
Possible causes:
Invalidmemory address.
Physical damage to bus.
Peripheral error.
HALT Halt Signal
Causes M68k to pause from executing instructions.
If active:
M68k stops execution after current cycle.
Waits until HALT is inactive.
Resumes execution.
Is bi-directional:
From external circuit / M68k (STOP command).
Both have same effect.
Also used to restart M68k (together with RESET).
RESET Reset Signal
Resets M68k / external circuit.
Is bi-directional:
If signal from external circuit, resets M68k
(together with HALT for 10 clock cycles).
If signal from M68k, resets external circuitry
connected to RESET pin (RESET instruction).
How M68k Manages Bus Errors
AS
FC R/W
0
Processor Status FC UDS Asynchronous
1 Bus Control
FC 68000 LDS
2
E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control
1 M68k is executing
instructions normally.
2 External peripheral has
important task for M68k.
7 Handle interrupt,
restore interrupt bits.
AS
FC R/W
0
Processor Status FC UDS Asynchronous
1 Bus Control
FC 68000 LDS
2
E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control
Interrupt
HDD Serial I/O
Circuit
System Bus
HDD
Micro- Interrupt
Serial I/O
Controller Circuit
System Bus
Less CPU overhead, CPU can process instructions that dont require bus.
BR Bus Request
Used by external circuit to request bus
control.
Input to M68k, 1 pin.
Connected to Bus Request output on
Alternate Bus Master (ABM).
Sends and waits for M68k response.
BG Bus Grant
Used by M68k to:
Acknowledge bus request.
Tell device that it will release bus control.
M68k
HDD
M68k
HDD
AS
FC R/W
0
Processor Status FC UDS Asynchronous
1 Bus Control
FC 68000 LDS
2
E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control
AS
FC R/W
0
Processor Status FC UDS Asynchronous
1 Bus Control
FC 68000 LDS
2
E DTACK
6800 Peripheral VMA
Control BR
VPA Bus Arbitration
BG Control
BERR BGACK
System Control RESET IPL0
HALT IPL1 Interrupt Control
(even (odd
addresses) addresses)
Chip #1 Chip #2
$1000 $12 $1001 $34
$1002 $56 $1003 $78
$1004 $1005
$1006 $1007
$1006 $1009
$1006 $100A
* Controlled by UDS * Controlled by LDS
How Data is Stored in Memory
$000000
Chip #1 Chip #2 Chip #3 Chip #4
$000001
$000000 $000001 $001000 $001001
$000002 $000003 $001002 $001003
$000002 $000004 $000005 $001004 $001005
$000006 $000007 $001006 $001007
$000003
$000004 EVEN ODD EVEN ODD
$000005
$000FFE $000FFF $001FFE $001FFF
$001FFE Controlled
Controlled
by LDS.
by UDS.
$001FFF
Activating the Correct Chip
Each memory chip has:
Data pins: outputs/receives to/from M68k.
Address pins: receives address from M68k.
OE (Output Enable): Allows data to be sent
from chip.
CS (Chip Select): Enables chip for data
transfer.
WE (Write Enable) (for RAM only): Allows
data to be written to chip.
Activating the Correct Chip
Chip activated only if:
CS is enabled.
OE is enabled.
D0
Address Bus
D1
UDS OE D2
R/W WE D3
CS D4
D5
D6
D7
Memory
Address
Decoder
D0
D1
AS D2
CS D3
R/W WE D4
LDS OE D5
D6
D7
Which one gets selected?
CLK
A1 A23
AS
LDS/UDS
R/W
DTACK
D0 D15
FC0 FC2
Step 1: Update FC & Specify Operation
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2
CLK
A1 A23
LDS/UDS
R/W
FC0 FC1 FC2 Type of bus cycle
DTACK 0 0 1 Accessing user data
0 1 0 Accessing User Program
D0 D15 1 0 1 Accessing SV Data
1 1 0 Accessing SV Program
FC0 FC2
FC0-2 informs what type of cycle is executing.
Step 2: Load Address Bus with Memory Address
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2
CLK
A1 A23
AS
LDS/UDS
R/W
DTACK
FC0 FC2
Step 3: Specify Byte & Activate AS
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2
AS
LDS/UDS
R/W
Specifies which data to access.
DTACK
UDS LDS What data to access
1 1 No valid data
D0 D15 1 0 D8-D15 (even bytes)
0 1 D0-D7 (odd bytes)
0 0 D0-D15 (word data)
FC0 FC2
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2
CLK
A1 A23
AS
If address exists, external device
activates DTACK.
LDS/UDS
R/W
DTACK
D0 D15
FC0 FC2
Step 5: Get Data
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2
CLK
A1 A23
AS
LDS/UDS
R/W
Memory puts data on data bus,
loaded into M68k.
DTACK
D0 D15
FC0 FC2
Step 6: Complete Transfer
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2
CLK
A1 A23
AS
DTACK
D0 D15
FC0 FC2
Write Cycle
M68k Write Cycle
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2
CLK
A1 A23
AS
LDS/UDS
R/W
DTACK
D0 D15
FC0 FC2
Step 1: Specify Operation
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2
CLK
A1 A23
AS
LDS/UDS
R/W
FC0 FC1 FC2 Type of bus cycle
DTACK 0 0 1 Accessing user data
0 1 0 Accessing User Program
D0 D15 1 0 1 Accessing SV Data
1 1 0 Accessing SV Program
FC0 FC2
FC0-2 informs what type of cycle is executing.
Step 2: Load Address Bus
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2
CLK
A1 A23
R/W
DTACK
D0 D15
FC0 FC2
Step 3: Activate AS, Specify Operation
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2
CLK
LDS/UDS
R/W
DTACK
FC0 FC2
Step 4: Load Data Bus
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2
CLK
A1 A23
AS
LDS/UDS
R/W
DTACK
D0 D15
CLK
UDS LDS What data to access
1 1 No valid data
A1 A23 1 0 D8-D15 (even bytes)
0 1 D0-D7 (odd bytes)
0 0 D0-D15 (word data)
AS
CLK
A1 A23
AS
When M68k done,
LDS/UDS all controls returned
to normal.
R/W
DTACK
D0 D15
Power & Clock Provides power, clock signal. Vcc, GND, CLK
Interrupt request
Interrupt Control IPL0, IPL1, IPL2
by external device.
Bus Arbitration
Allows bus takeovers by ABM. BR, BG, BGACK
Control
Asynchronous Allows asynchronous data transfer AS, R/W, UDS,
Bus Control between M68k and devices. LDS, DTACK
Please read:
Antonakos, pg. 238-254