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Data Sheet
High-Performance
Digital Signal Controllers
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
UART
SPI
I2C
CAN
SRAM EEPROM Timer Input Codec A/D 12-bit
Device Pins Comp/Std
Bytes Instructions Bytes Bytes 16-bit Cap Interface 100 Ksps
PWM
dsPIC30F3014 40/44 24K 8K 2048 1024 3 2 2 - 13 ch 2 1 1 0
dsPIC30F4013 40/44 48K 16K 2048 1024 5 4 4 AC97, I2S 13 ch 2 1 1 1
Pin Diagrams
40-Pin PDIP
MCLR 1 40 AVDD
AN0/VREF+/CN2/RB0 2 39 AVss
AN1/VREF-/CN3/RB1 3 38 AN9/RB9
AN2/SS1/LVDIN/CN4/RB2 4 37 AN10/RB10
AN3/CN5/RB3 5 36 AN11/RB11
AN4/CN6/RB4 AN5/CN7/RB5 6 35 AN12/RB12
dsPIC30F3014
PGC/EMUC/AN6/OCFA/RB6 7 34 EMUC2/OC1/RD0
PGD/EMUD/AN7/RB7 8 33 EMUD2/OC2/RD1
AN8/RB8 9 32 VDD
VDD 10 31 Vss
Vss 11 30 RF0
OSC1/CLKIN 12 29 RF1
OSC2/CLKO/RC15 13 28 U2RX/CN17/RF4
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 14 27 U2TX/CN18/RF5
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 15 26 U1RX/SDI1/SDA/RF2
INT0/RA11 16 25 EMUD3/U1TX/SDO1/SCL/RF3
IC2/INT2/RD9 17 24 EMUC3/SCK1/RF6
RD3 18 23 IC1/INT1/RD8
Vss 19 22 RD2
20 21
VDD
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 NC
EMUC3/SCK1/RF6 IC1/NT1/RD8
EMUD3/U1TX/SDO1/SCL/RF3
IC2/INT2/RD9 INT0/RA11
RD3
RD2
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
U1RX/SDI1/SDA/RF2 1 33 NC
U2TX/CN18/RF5 32 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
U2RX/CN17/RF4 2 31
3 OSC2/CLKO/RC15
RF1 4 30 OSC1/CLKIN
RF0 5 29 VSS
VSS 6 dsPIC30F3014 28 VDD
VDD 7 27 AN8/RB8
EMUD2/OC2/RD1 8 26 PGD/EMUD/AN7/RB7
EMUC2/OC1/RD0 9 25 PGC/EMUC/AN6/OCFA/RB6
AN12/RB12 10 24 AN5/CN7/RB5
AN11/RB11 11 23 AN4/CN6/RB4
12
13
14
15
16
17
18
19
20
21
22
NC
NC
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN9/RB9
AN10/RB10
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AVSS
MCLR
AVDD
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC3/SCK1/RF6 IC1/INT1/RD8
EMUD3/U1TX/SDO1/SCL/RF3
IC2/INT2/RD9 INT0/RA11
RD3
RD2
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
U1RX/SDI1/SDA/RF2 1 33 OSC2/CLKO/RC15
U2TX/CN18/RF5 2 32 OSC1/CLKIN
U2RX/CN17/RF4 3 31 VSS
RF1 4 30 VSS
RF0 5 29 VDD
VSS 6 dsPIC3 0F3014 28 VDD
VDD 7 27 AN8/RB8
VDD 8 26 PGD/EMUD/AN7/RB7
EMUD2/OC2/RD1 9 25 PGC/EMUC/AN6/OCFA/RB6
EMUC2/OC1/RD0 10 24 AN5/CN7/RB5
AN12/RB12 11 23 AN4/CN6/RB4
12
13
14
15
16
17
18
19
20
21
22
NC
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN9/RB9
AN10/RB10
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN11/RB11
AVSS
MCLR
AVDD
MCLR 1 40 AVDD
AN0/VREF+/CN2/RB0 2 39 AVSS
AN1/VREF-/CN3/RB1 3 38 AN9/CSCK/RB9
AN2/SS1/LVDIN/CN4/RB2 4 37 AN10/CSDI/RB10
AN3/CN5/RB3 5 36 AN11/CSDO/RB11
AN4/IC7/CN6/RB4 6 35 AN12/COFS/RB12
dsPIC30F4013
AN5/IC8/CN7/RB5 7 34 EMUC2/OC1/RD0
PGC/EMUC/AN6/OCFA/RB6 8 33 EMUD2/OC2/RD1
PGD/EMUD/AN7/RB7 9 32 VDD
AN8/RB8 10 31 VSS
VDD 11 30 C1RX/RF0
VSS 12 29 C1TX/RF1
OSC1/CLKIN 13 28 U2RX/CN17/RF4
OSC2/CLKO/RC15 14 27 U2TX/CN18/RF5
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 15 26 U1RX/SDI1/SDA/RF2
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 16 25 EMUD3/U1TX/SDO1/SCL/RF3
INT0/RA11 17 24 EMUC3/SCK1/RF6
IC2/INT2/RD9 18 23 IC1/INT1/RD8
OC4/RD3 19 22 OC3/RD2
VSS 20 21 VDD
44-Pin TQFP
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 NC
EMUC3/SCK1/RF6 IC1/INT1/RD8
EMUD3/U1TX/SDO1/SCL/RF3
IC2/INT2/RD9 INT0/RA11
VSS OC4/RD3
OC3/RD2 VDD
44
43
42
41
40
39
38
37
36
35
34
U1RX/SDI1/SDA/RF2 1 33 NC
U2TX/CN18/RF5 2 32 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
U2RX/CN17/RF4 3 31 OSC2/CLKO/RC15
CTX1/RF1 4 30 OSC1/CLKIN
5 29 VSS
CRX1/RF0
6 28 VDD
VSS
7
dsPIC30F4013 27
VDD AN8/RB8
EMUD2/OC2/RD1 8 26 PGD/EMUD/AN7/RB7
EMUC2/OC1/RD0 9 25 PGC/EMUC/AN6/OCFA/RB6
AN12/COFS/RB12 10 24 AN5/IC8/CN7/RB5
AN11/CSDO/RB11 11 23 AN4/IC7/CN6/RB4
12
13
14
15
16
17
18
19
20
21
22
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
NC
NC
AN10/CSDI/RB10
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN9/CSCK/RB9
AVSS
MCLR
AVDD
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC3/SCK1/RF6 IC1/NT1/RD8
EMUD3/U1TX/SDO1/SCL/RF3
IC2/INT2/RD9 INT0/RA11
VSS OC4/RD3
OC3/RD2 VDD
44
43
42
41
40
39
38
37
36
35
34
U1RX/SDI1/SDA/RF2 1 33 OSC2/CLKO/RC15
U2TX/CN18/RF5 2 32 OSC1/CLKIN
U2RX/CN17/RF4 3 31 VSS
CTX1/RF1 4 30 VSS
CRX1/RF0 5 29 VDD
VSS 6 dsPIC30F4013 28 VDD
VDD 7 27 AN8/RB8
VDD 8 26 PGD/EMUD/AN7/RB7
EMUD2/OC2/RD1 9 25 PGC/EMUC/AN6/OCFA/RB6
EMUC2/OC1/RD0 10 24 AN5/IC8/CN7/RB5
AN12/COFS/RB12 11 23 AN4/IC7/CN6/RB4
12
13
14
15
16
17
18
19
20
21
22
NC
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN11/CSDO/RB11
AN10/CSDI/RB10
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN9/CSCK/RB9
AVSS
MCLR
AVDD
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Y Data Bus
X Data Bus
16 16 16
16
Interrupt Data Latch Data Latch INT0/RA11
Controller PSV & Table
Data Access Y Data X Data
24 Control Block 8 16 RAM RAM
(1 Kbyte) (1 Kbyte)
Address Address PORTA
24 Latch Latch
16 16 16
24 X RAGU AN0/CN2/RB0
Y AGU
PCU PCH PCL X WAGU AN1/CN3/RB1
Program Counter AN2/SS1/LVDIN/CN4/RB2
Stack Loop 16
Address Latch AN3/CN5/RB3
Control Control
Program Memory Logic Logic AN4/CN6/RB4
(24 Kbytes) AN5/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
Data EEPROM PGD/EMUD/AN7/RB7
(1 Kbyte) Effective Address AN8/RB8
Data Latch 16 AN9/RB9
AN10/RB10
AN11/RB11
ROM Latch 16 AN12/RB12
24
PORTB
IR
16 16
EMUD1/SOSCI/T2CK/U1ATX/
16 x 16 CN1/RC13
W Reg Array EMUC1/SOSCO/T1CK/U1ARX/
Decode
CN0/RC14
Instruction
Decode and 16 16 OSC2/CLKO/RC15
Control PORTC
Y Data Bus
X Data Bus
16 16 16
16
Interrupt Data Latch Data Latch INT0/RA11
Controller PSV & Table
Data Access Y Data X Data
24 Control Block 8 16 RAM RAM
(1 Kbyte) (1 Kbyte)
Address Address PORTA
24 Latch Latch
16 16 16
24 X RAGU AN0/CN2/RB0
Y AGU
PCU PCH PCL X WAGU AN1/CN3/RB1
Program Counter AN2/SS1/LVDIN/CN4/RB2
Stack Loop 16
Address Latch AN3/CN5/RB3
Control Control
Logic Logic AN4/IC7/CN6/RB4
Program Memory
(48 Kbytes) AN5/IC8/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
Data EEPROM PGD/EMUD/AN7/RB7
(1 Kbyte) Effective Address AN8/RB8
Data Latch 16 AN9/CSCK/RB9
AN10/CSDI/RB10
AN11/CSDO/RB11
ROM Latch 16 AN12/COFS/RB12
24
PORTB
IR
16 16
EMUD1/SOSCI/T2CK/U1ATX/
16 x 16 CN1/RC13
W Reg Array EMUC1/SOSCO/T1CK/U1ARX/
Decode
CN0/RC14
Instruction
Decode & 16 16 OSC2/CLKO/RC15
Control
PORTC
D15 D0
W0/WREG PUSH.S Shadow
W1
DO Shadow
W2
W3 Legend
W4
DSP Operand W5
Registers
W6
W7
Working Registers
W8
W9
DSP Address
Registers W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
PC22 PC0
0 Program Counter
7 0
TABPAG
TBLPAG Data Table Page Address
7 0
PSVPAG Program Space Visibility Page Address
15 0
RCOUNT REPEAT Loop Counter
15 0
DCOUNT DO Loop Counter
22 0
DOSTART DO Loop Start Address
22
DOEND DO Loop End Address
15 0
CORCON Core Configuration Register
SRH SRL
S
a
40 40-bit Accumulator A 40 Round t 16
40-bit Accumulator B u
Logic r
a
Carry/Borrow Out t
Saturate e
Carry/Borrow In Adder
Negate
40 40 40
Barrel
16
Shifter
X Data Bus
40
Sign-Extend
Y Data Bus
32 16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16 16
To/From W Array
Vector Tables
space as defined by Table 3-1. Note that the program
00007E
space address is incremented by two between succes- Reserved 000080
sive program words in order to provide compatibility 000084
with data space addressing. Alternate Vector Table
0000FE
FIGURE 3-1: dsPIC30F3014 PROGRAM 000100
SPACE MEMORY MAP
00007E
Reserved 000080
007FFE
000084 004000
Reserved
Alternate Vector Table (Read 0s)
0000FE 7FFBFE
000100 7FFC00
Data EEPROM
User Flash
(1 Kbyte)
User Memory Space
Program Memory
(8K instructions) 7FFFFE
003FFE 800000
004000 Reserved
Configuration Memory Space
Reserved
(Read 0s) 8005BE
7FFBFE 8005C0
7FFC00 UNITID (32 instr.)
Data EEPROM 8005FE
(1 Kbyte) 800600
7FFFFE
800000 Reserved
Reserved
8005BE F7FFFE
8005C0 Device Configuration F80000
UNITID (32 instr.) Registers F8000E
8005FE F80010
800600
Configuration Memory Space
Reserved
Reserved
FEFFFE
FF0000
DEVID (2)
F7FFFE FF0002
Device Configuration F80000
Registers F8000E
F80010
Reserved
FEFFFE
FF0000
DEVID (2)
FF0002
23 bits
Using
Program 0 Program Counter 0
Counter
Select
1 EA
Using
Program 0 PSVPAG Reg
Space
Visibility 8 bits 15 bits
EA
User/
Configuration Byte
Space 24-bit EA
Select
Select
Note: Program space visibility cannot be used to access bits <23:16> of a word in program memory.
PC Address 23 16 8 0
0x000000 00000000
0x000002 00000000
0x000004 00000000
0x000006 00000000
TBLRDL.B (Wn<0> = 0)
Program Memory TBLRDL.W
Phantom Byte
(read as 0) TBLRDL.B (Wn<0> = 1)
TBLRDH.W
PC Address 23 16 8 0
0x000000 00000000
0x000002 00000000
0x000004 00000000
0x000006 00000000
TBLRDH.B (Wn<0> = 0)
Program Memory
Phantom Byte
(read as 0) TBLRDH.B (Wn<0> = 1)
3.1.2 DATA ACCESS FROM PROGRAM Note that by incrementing the PC by 2 for each
MEMORY USING PROGRAM SPACE program memory word, the LS 15 bits of data space
VISIBILITY addresses directly map to the LS 15 bits in the corre-
sponding program space addresses. The remaining
The upper 32 Kbytes of data space may optionally be bits are provided by the Program Space Visibility Page
mapped into any 16K word program space page. This register, PSVPAG<7:0>, as shown in Figure 3-6.
provides transparent access of stored constant data
from X data space without the need to use special Note: PSV access is temporarily disabled during
instructions (i.e., TBLRDL/H, TBLWTL/H instructions). table reads/writes.
Program space access through the data space occurs For instructions that use PSV which are executed
if the MS bit of the data space EA is set and program outside a REPEAT loop:
space visibility is enabled by setting the PSV bit in the The following instructions will require one
Core Control register (CORCON). The functions of instruction cycle in addition to the specified
CORCON are discussed in Section 2.4, DSP Engine. execution time:
Data accesses to this area add an additional cycle to - MAC class of instructions with data operand
the instruction being executed, since two program pre-fetch
memory fetches are required. - MOV instructions
Note that the upper half of addressable data space is - MOV.D instructions
always part of the X data space. Therefore, when a All other instructions will require two instruction
DSP operation uses program space mapping to access cycles in addition to the specified execution time
this memory region, Y data space should typically con- of the instruction.
tain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient For instructions that use PSV which are executed
(constant) data. inside a REPEAT loop:
Although each data space address, 0x8000 and higher, The following instances will require two instruction
maps directly into a corresponding program memory cycles in addition to the specified execution time
address (see Figure 3-6), only the lower 16 bits of the of the instruction:
24-bit program word are used to contain the data. The - Execution in the first iteration
upper 8 bits should be programmed to force an illegal - Execution in the last iteration
instruction to maintain machine robustness. Refer to - Execution prior to exiting the loop due to an
the Programmers Reference Manual (DS70030) for interrupt
details on instruction encoding.
- Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow
the instruction accessing data, using PSV, to
execute in a single cycle.
15 PSVPAG(1)
EA<15> = 0 0x00
8
Data 16
Space 0x8000
EA 15 23 15 0
Address
EA<15> = 1 Concatenation 23 0x000200
15
Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines
the page in program space to which the upper half of data space is being mapped).
The memory map shown here is for a dsPIC30F4013 device.
MS Byte LS Byte
Address 16 bits Address
MSB LSB
0x0001 0x0000
2 Kbyte SFR Space
SFR Space 0x07FE
0x07FF
0x0801 0x0800
8 Kbyte
X Data RAM (X)
Near
2 Kbyte 0x0BFF 0x0BFE Data
0x0C01 0x0C00
SRAM Space Space
Y Data RAM (Y)
0x0FFF 0x0FFE
0x1001 0x1000
0x1FFF 0x1FFE
0x8001 0x8000
Optionally X Data
Mapped Unimplemented (X)
into Program
Memory
0xFFFF 0xFFFE
X SPACE
UNUSED
X SPACE
X SPACE
UNUSED
Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11
and post-increments for stack pushes as shown in PC<15:0> W15 (before CALL)
Figure 3-10. Note that for a PC push during any CALL 000000000 PC<22:16>
instruction, the MSB of the PC is zero-extended before <Free Word> W15 (after CALL)
the push, ensuring that the MSB is always clear.
POP : [--W15]
Note: A PC push during exception processing PUSH : [W15++]
will concatenate the SRL register to the
MSB of the PC prior to the push.
Address
SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
(Home)
dsPIC30F3014/4013
ACCAU 0026 Sign-Extension (ACCA<39>) ACCAU 0000 0000 0000 0000
ACCBL 0028 ACCBL 0000 0000 0000 0000
ACCBH 002A ACCBH 0000 0000 0000 0000
ACCBU 002C Sign-Extension (ACCB<39>) ACCBU 0000 0000 0000 0000
PCL 002E PCL 0000 0000 0000 0000
PCH 0030 PCH 0000 0000 0000 0000
TBLPAG 0032 TBLPAG 0000 0000 0000 0000
PSVPAG 0034 PSVPAG 0000 0000 0000 0000
RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu
DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu
DOSTARTL 003A DOSTARTL 0 uuuu uuuu uuuu uuu0
DS70138C-page 33
dsPIC30F3014/4013
Address
SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
(Home)
CORCON 0044 US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000
MODCON 0046 XMODEN YMODEN BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000
XMODSRT 0048 XS<15:1> 0 uuuu uuuu uuuu uuu0
XMODEND 004A XE<15:1> 1 uuuu uuuu uuuu uuu1
YMODSRT 004C YS<15:1> 0 uuuu uuuu uuuu uuu0
YMODEND 004E YE<15:1> 1 uuuu uuuu uuuu uuu1
XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu
DISICNT 0052 DISICNT<13:0> 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Advance Information
2004 Microchip Technology Inc.
dsPIC30F3014/4013
4.0 ADDRESS GENERATOR UNITS 4.1.1 FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete (f) to directly address data present in the first 8192
reference source. For more information on the CPU, bytes of data memory (near data space). Most file
peripherals, register descriptions and general device register instructions employ a working register W0,
functionality, refer to the dsPIC30F Family Reference which is denoted as WREG in these instructions. The
Manual (DS70046). For more information on the device
destination is typically either the same file register, or
instruction set and programming, refer to the dsPIC30F
Programmers Reference Manual (DS70030). WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
The dsPIC core contains two independent address MOV instruction allows additional flexibility and can
generator units: the X AGU and Y AGU. The Y AGU access the entire data space during file register
supports word sized data reads for the DSP MAC class operation.
of instructions only. The dsPIC AGUs support three
types of data addressing: 4.1.2 MCU INSTRUCTIONS
Linear Addressing The three-operand MCU instructions are of the form:
Modulo (Circular) Addressing
Operand 3 = Operand 1 <function> Operand 2
Bit-Reversed Addressing
where Operand 1 is always a working register (i.e., the
Linear and Modulo Data Addressing modes can be addressing mode can only be register direct), which is
applied to data space or program space. Bit-reversed referred to as Wb. Operand 2 can be a W register,
addressing is only applicable to data space addresses. fetched from data memory, or a 5-bit literal. The result
location can be either a W register or an address
4.1 Instruction Addressing Modes location. The following addressing modes are
supported by MCU instructions:
The addressing modes in Table 4-1 form the basis of
the addressing modes optimized to support the specific Register Direct
features of individual instructions. The addressing Register Indirect
modes provided in the MAC class of instructions are Register Indirect Post-modified
somewhat different from those in the other instruction Register Indirect Pre-modified
types.
5-bit or 10-bit Literal
Note: Not all instructions support all the address-
ing modes given above. Individual
instructions may support different subsets
of these addressing modes.
Byte
Address MOV #0x800,W0
MOV W0,XMODSRT ;set modulo start address
MOV #0x863,W0
MOV W0,MODEND ;set modulo end address
0x0800 MOV #0x8001,W0
MOV W0,MODCON ;enable W1, X AGU for modulo
0x0863
Pivot Point
XB = 0x0008 for a 16-word Bit-Reversed Buffer
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 0 0 0 8
0 0 1 0 2 0 1 0 0 4
0 0 1 1 3 1 1 0 0 12
0 1 0 0 4 0 0 1 0 2
0 1 0 1 5 1 0 1 0 10
0 1 1 0 6 0 1 1 0 6
0 1 1 1 7 1 1 1 0 14
1 0 0 0 8 0 0 0 1 1
1 0 0 1 9 1 0 0 1 9
1 0 1 0 10 0 1 0 1 5
1 0 1 1 11 1 1 0 1 13
1 1 0 0 12 0 0 1 1 3
1 1 0 1 13 1 0 1 1 11
1 1 1 0 14 0 1 1 1 7
1 1 1 1 15 1 1 1 1 15
The dsPIC30F family of devices contains internal pro- 5.3 Table Instruction Operation
gram Flash memory for executing user code. There are
Summary
two methods by which the user can program this
memory: The TBLRDL and the TBLWTL instructions are used to
1. Run-Time Self-Programming (RTSP) read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
2. In-Circuit Serial Programming (ICSP)
Word or Byte mode.
5.1 In-Circuit Serial Programming The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
(ICSP)
and TBLWTH can access program memory in Word or
dsPIC30F devices can be serially programmed while in Byte mode.
the end application circuit. This is simply done with two A 24-bit program memory address is formed using
lines for Programming Clock and Programming Data bits<7:0> of the TBLPAG register and the effective
(which are named PGC and PGD respectively), and address (EA) from a W register specified in the table
three other lines for Power (VDD), Ground (VSS) and instruction, as shown in Figure 5-1.
Master Clear (MCLR). this allows customers to manu-
facture boards with unprogrammed devices, and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
24 bits
Using
Program 0 Program Counter 0
Counter
NVMADR Reg EA
Using
NVMADR 1/0 NVMADRU Reg
Addressing
8 bits 16 bits
Working Reg EA
Byte
User/Configuration Select
Space Select 24-bit EA
Note: In Example 5-2, the contents of the upper byte of W3 has no effect.
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All RESETS
NVMCON 0760 WR WREN WRERR TWRI PROGOP<6:0> 0000 0000 0000 0000
NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu
NVMADRU 0764 NVMADR<23:16> 0000 0000 uuuu uuuu
NVMKEY 0766 KEY<7:0> 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Advance Information
dsPIC30F3014/4013
DS70138C-page 45
dsPIC30F3014/4013
NOTES:
Read TRIS
I/O Cell
TRIS Latch
Data Bus D Q
WR TRIS CK
Data Latch
D Q I/O Pad
WR LAT +
WR Port CK
Read LAT
Read Port
1
PIO Module Output Data
0
Read TRIS
I/O Pad
Data Bus D Q
WR TRIS CK
TRIS Latch
D Q
WR LAT +
WR Port CK
Data Latch
Read LAT
Input Data
Read Port
7.2 Configuring Analog Port Pins 7.2.1 I/O PORT WRITE/READ TIMING
The use of the ADPCFG and TRIS registers control the One instruction cycle is required between a port
operation of the A/D port pins. The port pins that are direction change or port write operation and a read
desired as analog inputs must have their correspond- operation of the same port. Typically this instruction
ing TRIS bit set (input). If the TRIS bit is cleared would be a NOP.
(output), the digital output level (VOH or VOL) will be
converted. EXAMPLE 7-1: PORT WRITE/READ
When reading the Port register, all pins configured as EXAMPLE
analog input channels will read as cleared (a low level). MOV 0xFF00, W0 ; Configure PORTB<15:8>
Pins configured as digital inputs will not convert an ana- ; as inputs
log input. Analog levels on any pin that is defined as a MOV W0, TRISB ; and PORTB<7:0> as outputs
NOP ; additional instruction
digital input (including the ANx pins) may cause the
cylcle
input buffer to consume current that exceeds the btss PORTB, #11 ; bit test RB11 and skip if
device specifications. set
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
TRISF 02DE TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0000 0111 1111
PORTF 02E0 RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000
LATF 02E2 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138C-page 53
dsPIC30F3014/4013
7.3 Input Change Notification Module
The input change notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor, in response to a change of
state on selected input pins. This module is capable of
detecting input change of states even in Sleep mode,
when the clocks are disabled. There are up to 24 exter-
nal signals (CN0 through CN23) that may be selected
(enabled) for generating an interrupt request on a
change of state.
TABLE 7-2: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F3014 (BITS 15-8)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset State
CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE 0000 0000 0000 0000
CNEN2 00C2 0000 0000 0000 0000
CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE 0000 0000 0000 0000
CNPU2 00C6 0000 0000 0000 0000
Legend: u = uninitialized bit
TABLE 7-3: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F3014 (BITS 7-0)
SFR
Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000
CNEN2 00C2 CN18IE CN17IE CN16IE 0000 0000 0000 0000
CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000
CNPU2 00C6 CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000
Legend: u = uninitialized bit
TABLE 7-4: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F4013 (BITS 15-8)
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset State
Name
CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE 0000 0000 0000 0000
CNEN2 00C2 0000 0000 0000 0000
CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE 0000 0000 0000 0000
CNPU2 00C6 0000 0000 0000 0000
Legend: u = uninitialized bit
TABLE 7-5: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F4013 (BITS 7-0)
SFR
Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000
CNEN2 00C2 CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 0000 0000 0000
CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000
CNPU2 00C6 CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
SFR
ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
INTCON1 0080 NSTDIS OVATE OVBTE COVTE MATHERR ADDRERR STKERR OSCFAIL 0000 0000 0000 0000
INTCON2 0082 ALTIVT INT2EP INT1EP INT0EP 0000 0000 0000 0000
IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000
IFS1 0086 C1IF U2TXIF U2RXIF INT2IF INT1IF 0000 0000 0000 0000
IFS2 0088 LVDIF 0000 0000 0000 0000
IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000
IEC1 008E C1IE U2TXIE U2RXIE INT2IE INT1IE 0000 0000 0000 0000
IEC2 0090 LVDIE 0000 0000 0000 0000
IPC0 0094 T1IP<2:0> OC1IP<2:0> IC1IP<2:0> INT0IP<2:0> 0100 0100 0100 0100
IPC1 0096 T31P<2:0> T2IP<2:0> OC2IP<2:0> IC2IP<2:0> 0100 0100 0100 0100
IPC2 0098 ADIP<2:0> U1TXIP<2:0> U1RXIP<2:0> SPI1IP<2:0> 0100 0100 0100 0100
Advance Information
IPC3 009A CNIP<2:0> MI2CIP<2:0> SI2CIP<2:0> NVMIP<2:0> 0100 0100 0100 0100
IPC4 009C INT1IP<2:0> 0100 0100 0100 0100
IPC5 009E INT2IP<2:0> 0100 0100 0100 0100
IPC6 00A0 C1IP<2:0> U2TXIP<2:0> U2RXIP<2:0> 0100 0100 0100 0100
IPC7 00A2 0100 0100 0100 0100
IPC8 00A4 0100 0100 0100 0100
IPC9 00A6 0000 0100 0100 0100
dsPIC30F3014/4013
IPC10 00A8 LVDIP<2:0> DCIIP<2:0> 0000 0100 0100 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
DS70138C-page 61
TABLE 8-4: dsPIC30F4013 INTERRUPT CONTROLLER REGISTER MAP
DS70138C-page 62
dsPIC30F3014/4013
SFR
ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
INTCON1 0080 NSTDIS OVATE OVBTE COVTE MATHERR ADDRERR STKERR OSCFAIL 0000 0000 0000 0000
INTCON2 0082 ALTIVT INT2EP INT1EP INT0EP 0000 0000 0000 0000
IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000
IFS1 0086 C1IF U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000
IFS2 0088 LVDIF DCIIF 0000 0000 0000 0000
IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000
IEC1 008E C1IE U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000
IEC2 0090 LVDIE DCIIE 0000 0000 0000 0000
IPC0 0094 T1IP<2:0> OC1IP<2:0> IC1IP<2:0> INT0IP<2:0> 0100 0100 0100 0100
IPC1 0096 T31P<2:0> T2IP<2:0> OC2IP<2:0> IC2IP<2:0> 0100 0100 0100 0100
IPC2 0098 ADIP<2:0> U1TXIP<2:0> U1RXIP<2:0> SPI1IP<2:0> 0100 0100 0100 0100
Advance Information
IPC3 009A CNIP<2:0> MI2CIP<2:0> SI2CIP<2:0> NVMIP<2:0> 0100 0100 0100 0100
IPC4 009C OC3IP<2:0> IC8IP<2:0> IC7IP<2:0> INT1IP<2:0> 0100 0100 0100 0100
IPC5 009E INT2IP<2:0> T5IP<2:0> T4IP<2:0> OC4IP<2:0> 0100 0100 0100 0100
IPC6 00A0 C1IP<2:0> SPI2IP<2:0> U2TXIP<2:0> U2RXIP<2:0> 0100 0100 0100 0100
IPC7 00A2 0100 0100 0100 0100
IPC8 00A4 0100 0100 0100 0100
IPC9 00A6 0000 0100 0100 0100
IPC10 00A8 LVDIP<2:0> DCIIP<2:0> 0000 0100 0100 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
2004 Microchip Technology Inc.
dsPIC30F3014/4013
9.0 TIMER1 MODULE These Operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
Note: This data sheet summarizes features of this group presents a block diagram of the 16-bit timer module.
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU, 16-bit Timer Mode: In the 16-bit Timer mode, the timer
peripherals, register descriptions and general device increments on every instruction cycle up to a match
functionality, refer to the dsPIC30F Family Reference value preloaded into the Period register PR1, then
Manual (DS70046). resets to 0 and continues to count.
This section describes the 16-bit General Purpose When the CPU goes into the Idle mode, the timer will
(GP) Timer1 module and associated Operational stop incrementing unless the TSIDL (T1CON<13>)
modes. Figure 9-1 depicts the simplified block diagram bit = 0. If TSIDL = 1, the timer module logic will resume
of the 16-bit Timer1 module. the incrementing sequence upon termination of the
The following sections provide a detailed description CPU Idle mode.
including setup and control registers, along with asso- 16-bit Synchronous Counter Mode: In the 16-bit
ciated block diagrams for the Operational modes of the Synchronous Counter mode, the timer increments on
timers. the rising edge of the applied external clock signal
The Timer1 module is a 16-bit timer which can serve as which is synchronized with the internal phase clocks.
the time counter for the real-time clock, or operate as a The timer counts up to a match value preloaded in PR1,
free-running interval timer/counter. The 16-bit timer has then resets to 0 and continues.
the following modes: When the CPU goes into the Idle mode, the timer will
16-bit Timer stop incrementing unless the respective TSIDL bit = 0.
16-bit Synchronous Counter If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
16-bit Asynchronous Counter Idle mode.
Further, the following operational characteristics are 16-bit Asynchronous Counter Mode: In the 16-bit
supported: Asynchronous Counter mode, the timer increments on
Timer gate operation every rising edge of the applied external clock signal.
Selectable prescaler settings The timer counts up to a match value preloaded in PR1,
Timer operation during CPU Idle and Sleep then resets to 0 and continues.
modes When the timer is configured for the Asynchronous
Interrupt on 16-bit Period register match or falling mode of operation and the CPU goes into the Idle
edge of external gate signal mode, the timer will stop incrementing if TSIDL = 1.
PR1
Equal
Comparator x 16 TSYNC
1 Sync
TMR1
Reset
0
0
T1IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
SOSCO/
T1CK 1x
Gate Prescaler
LPOSCEN Sync 01 1, 8, 64, 256
SOSCI
TCY 00
When the CPU enters Sleep mode, the RTC will con-
tinue to operate provided the 32 kHz external crystal
oscillator is active and the control bits have not been
changed. The TSIDL bit should be cleared to 0 in
order for RTC to continue operation in Idle mode.
dsPIC30F3014/4013
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Advance Information
2004 Microchip Technology Inc.
dsPIC30F3014/4013
10.0 TIMER2/3 MODULE 16-bit Timer Mode: In the 16-bit mode, Timer2 and
Timer3 can be configured as two independent 16-bit
Note: This data sheet summarizes features of this group timers. Each timer can be set up in either 16-bit Timer
of dsPIC30F devices and is not intended to be a complete mode or 16-bit Synchronous Counter mode. See
reference source. For more information on the CPU,
peripherals, register descriptions and general device
Section 9.0, Timer1 Module for details on these two
functionality, refer to the dsPIC30F Family Reference Operating modes.
Manual (DS70046). The only functional difference between Timer2 and
This section describes the 32-bit General Purpose Timer3 is that Timer2 provides synchronization of the
(GP) Timer module (Timer2/3) and associated Opera- clock prescaler output. This is useful for high frequency
tional modes. Figure 10-1 depicts the simplified block external clock inputs.
diagram of the 32-bit Timer2/3 module. Figure 10-2 32-bit Timer Mode: In the 32-bit Timer mode, the timer
and Figure 10-3 show Timer2/3 configured as two increments on every instruction cycle, up to a match
independent 16-bit timers, Timer2 and Timer3, value preloaded into the combined 32-bit Period
respectively. register PR3/PR2, then resets to 0 and continues to
The Timer2/3 module is a 32-bit timer (which can be count.
configured as two 16-bit timers) with selectable For synchronous 32-bit reads of the Timer2/Timer3
Operating modes. These timers are utilized by other pair, reading the LS Word (TMR2 register) will cause
peripheral modules, such as: the MS word to be read and latched into a 16-bit
Input Capture holding register, termed TMR3HLD.
Output Compare/Simple PWM For synchronous 32-bit writes, the holding register
The following sections provide a detailed description, (TMR3HLD) must first be written to. When followed by
including setup and control registers, along with asso- a write to the TMR2 register, the contents of TMR3HLD
ciated block diagrams for the Operational modes of the will be transferred and latched into the MSB of the 32-
timers. bit timer (TMR3).
The 32-bit timer has the following modes: 32-bit Synchronous Counter Mode: In the 32-bit
Synchronous Counter mode, the timer increments on
Two independent 16-bit timers (Timer2 and the rising edge of the applied external clock signal
Timer3) with all 16-bit Operating modes (except which is synchronized with the internal phase clocks.
Asynchronous Counter mode) The timer counts up to a match value preloaded in the
Single 32-bit timer operation combined 32-bit period register PR3/PR2, then resets
Single 32-bit synchronous counter to 0 and continues.
Further, the following operational characteristics are When the timer is configured for the Synchronous
supported: Counter mode of operation and the CPU goes into the
Idle mode, the timer will stop incrementing unless the
ADC event trigger
TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
Timer gate operation module logic will resume the incrementing sequence
Selectable prescaler settings upon termination of the CPU Idle mode.
Timer operation during Idle and Sleep modes
Interrupt on a 32-bit period register match
These Operating modes are determined by setting the
appropriate bit(s) in the 16-bit T2CON and T3CON
SFRs.
For 32-bit timer/counter operation, Timer2 is the LS
Word and Timer3 is the MS Word of the 32-bit timer.
Note: For 32-bit timer operation, T3CON control
bits are ignored. Only T2CON control bits
are used for setup and control. Timer2
clock and gate inputs are utilized for the
32-bit timer module but an interrupt is gen-
erated with the Timer3 interrupt flag (T3IF)
and the interrupt is enabled with the
Timer3 interrupt enable bit (T3IE).
Data Bus<15:0>
TMR3HLD
16
16
Write TMR2
Read TMR2
16
Reset
TMR3 TMR2 Sync
MSB LSB
ADC Event Trigger
Comparator x 32
Equal
PR3 PR2
T3IF 0
Event Flag
1 Q D TGATE (T2CON<6>)
Q CK
TGATE
(T2CON<6>)
TGATE
TCS
TCKPS<1:0>
TON 2
T2CK 1x
Gate Prescaler
Sync 01 1, 8, 64, 256
TCY 00
Note: Timer configuration bit T32 (T2CON<3>) must be set to 1 for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.
PR2
Equal
Comparator x 16
TMR2 Sync
Reset
0
T2IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
T2CK 1x
Gate Prescaler
Sync 01 1, 8, 64, 256
TCY 00
PR3
TMR3
Reset
0
T3IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
T3CK Sync 1x
Prescaler
01 1, 8, 64, 256
TCY 00
Note: T3CK pin does not exist on dsPIC30F3014/4013 devices. The block diagram shown here illustrates
the schematic of Timer3 as implemented on the 30F6014 device.
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Advance Information
dsPIC30F3014/4013
DS70138C-page 71
dsPIC30F3014/4013
NOTES:
TMR5HLD
16
16
Write TMR4
Read TMR4
16
Reset
TMR5 TMR4 Sync
MSB LSB
Comparator x 32
Equal
PR5 PR4
0
T5IF
Event Flag 1 Q D TGATE (T4CON<6>)
Q CK
TGATE
(T4CON<6>)
TGATE
TCS
TCKPS<1:0>
TON 2
T4CK 1x
Prescaler
Gate
Sync 01 1, 8, 64, 256
TCY 00
Note: Timer configuration bit T32 (T4CON<3>) must be set to 1 for a 32-bit timer/counter operation. All control
bits are respective to the T4CON register.
PR4
Equal
Comparator x 16
TMR4 Sync
Reset
0
T4IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
T4CK 1x
Gate Prescaler
Sync 01 1, 8, 64, 256
TCY 00
PR5
TMR5
Reset
0
T5IF
Event Flag 1 Q D TGATE
Q CK
TGATE
TGATE
TCS
TCKPS<1:0>
TON 2
T5CK Sync 1x
Prescaler
01 1, 8, 64, 256
TCY 00
Note: In the dsPIC30F3014 device, there is no T5CK pin. Therefore, in this device the following modes should
not be used for Timer5:
1: TCS = 1 (16-bit counter)
2: TCS = 0, TGATE = 1 (gated time accumulation)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Advance Information
dsPIC30F3014/4013
DS70138C-page 75
dsPIC30F3014/4013
NOTES:
16 16
ICTMR
ICx pin 1 0
Prescaler Clock Edge FIFO
1, 4, 16 Synchronizer Detection R/W
Logic Logic
3 ICM<2:0>
Mode Select ICxBUF
ICBNE, ICOV
ICI<1:0>
Interrupt
ICxCON Logic
Note: Where x is shown, reference is made to the registers or bits associated to the respective input capture
channels 1 through N.
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138C-page 79
dsPIC30F3014/4013
NOTES:
OCxRS
Output S Q
OCxR
Logic R
OCx
Output
3 Enable
OCM<2:0>
Comparator Mode Select
OCTSEL OCFA
0 1 0 1 (for x = 1, 2, 3 or 4)
or OCFB
From GP (for x = 5, 6, 7 or 8)
Timer Module
Note: Where x is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
13.3 Dual Output Compare Match Mode 13.4 Simple PWM Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 100 When control bits OCM<2:0> (OCxCON<2:0>) = 110
or 101, the selected output compare channel is config- or 111, the selected output compare channel is config-
ured for one of two Dual Output Compare modes, ured for the PWM mode of operation. When configured
which are: for the PWM mode of operation, OCxR is the main latch
(read only) and OCxRS is the secondary latch. This
Single Output Pulse mode
enables glitchless PWM transitions.
Continuous Output Pulse mode
The user must perform the following steps in order to
13.3.1 SINGLE PULSE MODE configure the output compare module for PWM
operation:
For the user to configure the module for the generation
of a single output pulse, the following steps are 1. Set the PWM period by writing to the appropriate
required (assuming timer is off): period register.
Determine instruction cycle time TCY. 2. Set the PWM duty cycle by writing to the OCxRS
register.
Calculate desired pulse width value based on TCY.
3. Configure the output compare module for PWM
Calculate time to start pulse from timer start value
operation.
of 0x0000.
4. Set the TMRx prescale value and enable the
Write pulse width start and stop times into OCxR
Timer, TON (TxCON<15>) = 1.
and OCxRS Compare registers (x denotes
channel 1, 2, ...,N). 13.4.1 INPUT PIN FAULT PROTECTION
Set Timer Period register to value equal to, or FOR PWM
greater than value in OCxRS Compare register.
When control bits OCM<2:0> (OCxCON<2:0>) = 111,
Set OCM<2:0> = 100.
the selected output compare channel is again config-
Enable timer, TON (TxCON<15>) = 1. ured for the PWM mode of operation with the additional
To initiate another single pulse, issue another write to feature of input FAULT protection. While in this mode,
set OCM<2:0> = 100. if a logic 0 is detected on the OCFA/B pin, the respec-
tive PWM output pin is placed in the high impedance
input state. The OCFLT bit (OCxCON<4>) indicates
whether a FAULT condition has occurred. This state will
be maintained until both of the following events have
occurred:
The external FAULT condition has been removed.
The PWM mode has been re-enabled by writing
to the appropriate control bits.
Duty Cycle
TMR3 = PR3
TMR3 = PR3 T3IF = 1
T3IF = 1 (Interrupt Flag)
(Interrupt Flag) OCxR = OCxRS
OCxR = OCxRS
TMR3 = Duty Cycle TMR3 = Duty Cycle
(OCxR) (OCxR)
dsPIC30F3014/4013
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000
OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000
OC1CON 0184 OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000
OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000
OC2CON 018A OCSIDL OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit
OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000
OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000
Advance Information
OC1CON 0184 OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000
OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000
OC2CON 018A OCSIDL OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000
OC3RS 018C Output Compare 3 Secondary Register 0000 0000 0000 0000
OC3R 018E Output Compare 3 Main Register 0000 0000 0000 0000
OC3CON 0190 OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC4RS 0192 Output Compare 4 Secondary Register 0000 0000 0000 0000
OC4R 0194 Output Compare 4 Main Register 0000 0000 0000 0000
OC4CON 0196 OCSIDL OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
2004 Microchip Technology Inc.
dsPIC30F3014/4013
14.0 SPI MODULE In Master mode, the clock is generated by prescaling
the system clock. Data is transmitted as soon as a
Note: This data sheet summarizes features of this group value is written to SPIxBUF. The interrupt is generated
of dsPIC30F devices and is not intended to be a complete at the middle of the transfer of the last bit.
reference source. For more information on the CPU,
peripherals, register descriptions and general device In Slave mode, data is transmitted and received as
functionality, refer to the dsPIC30F Family Reference external clock pulses appear on SCK. Again, the inter-
Manual (DS70046). rupt is generated when the last bit is latched. If SSx
The Serial Peripheral Interface (SPI) module is a syn- control is enabled, then transmission and reception are
chronous serial interface. It is useful for communicating enabled only when SSx = low. The SDOx output will be
with other peripheral devices, such as EEPROMs, shift disabled in SSx mode with SSx high.
registers, display drivers and A/D converters, or other The clock provided to the module is (FOSC/4). This
microcontrollers. It is compatible with Motorola's SPI clock is then prescaled by the primary (PPRE<1:0>)
and SIOP interfaces. The dsPIC30F3014 and and the secondary (SPRE<2:0>) prescale factors. The
dsPIC30F4013 devices feature one SPI module, SPI1. CKE bit determines whether transmit occurs on transi-
tion from active clock state to Idle clock state, or vice
14.1 Operating Function Description versa. The CKP bit selects the Idle state (high or low)
for the clock.
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2) , used for shifting data in and 14.1.1 WORD AND BYTE
out, and a buffer register, SPIxBUF. A control register, COMMUNICATION
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates various status conditions. A control bit, MODE16 (SPIxCON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
The serial interface consists of 4 pins: SDIx (serial data 16-bit operation is identical to 8-bit operation except
input), SDOx (serial data output), SCKx (shift clock that the number of bits transmitted is 16 instead of 8.
input or output), and SSx (active low slave select).
The user software must disable the module prior to
In Master mode operation, SCK is a clock output but in changing the MODE16 bit. The SPI module is reset
Slave mode, it is a clock input. when the MODE16 bit is changed by the user.
A series of eight (8) or sixteen (16) clock pulses shift A basic difference between 8-bit and 16-bit operation is
out bits from the SPIxSR to SDOx pin and simulta- that the data is transmitted out of bit 7 of the SPIxSR for
neously shift in data from SDIx pin. An interrupt is gen- 8-bit operation, and data is transmitted out of bit15 of
erated when the transfer is complete and the the SPIxSR for 16-bit operation. In both modes, data is
corresponding interrupt flag bit (SPI1IF or SPI2IF) is shifted into bit 0 of the SPIxSR.
set. This interrupt can be disabled through an interrupt
enable bit (SPI1IE or SPI2IE). 14.1.2 SDOx DISABLE
The receive operation is double-buffered. When a com- A control bit, DISSDO, is provided to the SPIxCON reg-
plete byte is received, it is transferred from SPIxSR to ister to allow the SDOx output to be disabled. This will
SPIxBUF. allow the SPI module to be connected in an input only
If the receive buffer is full when new data is being trans- configuration. SDO can also be used for general
ferred from SPIxSR to SPIxBUF, the module will set the purpose I/O.
SPIROV bit indicating an overflow condition. The trans-
fer of the data from SPIxSR to SPIxBUF will not be 14.2 Framed SPI Support
completed and the new data will be lost. The module
will not respond to SCL transitions while SPIROV is 1, The module supports a basic framed SPI protocol in
effectively disabling the module until SPIxBUF is read Master or Slave mode. The control bit FRMEN enables
by user software. framed SPI support and causes the SSx pin to perform
the frame synchronization pulse (FSYNC) function.
Transmit writes are also double-buffered. The user The control bit SPIFSD determines whether the SSx
writes to SPIxBUF. When the master or slave transfer pin is an input or an output (i.e., whether the module
is completed, the contents of the shift register (SPIxSR) receives or generates the frame synchronization
are moved to the receive buffer. If any transmit data has pulse). The frame pulse is an active high pulse for a
been written to the buffer register, the contents of the single SPI clock cycle. When frame synchronization is
transmit buffer are moved to SPIxSR. The received enabled, the data transmission starts only on the
data is thus placed in SPIxBUF and the transmit data in subsequent transmit edge of the SPI clock.
SPIxSR is ready for the next transfer.
Note: Both the transmit buffer (SPIxTXB) and
the receive buffer (SPIxRXB) are mapped
to the same register address, SPIxBUF.
Internal
Data Bus
Read Write
SPIxBUF SPIxBUF
Receive Transmit
SPIxSR
SDIx bit 0
SDOx Shift
Clock
SS and Clock Edge
FSYNC Control Select
SSx Control
Secondary Primary
Prescaler Prescaler FCY
1:1-1:8 1:1, 1:4,
SCKx 1:16, 1:64
Note: x = 1 or 2.
Note: x = 1 or 2, y = 1 or 2.
dsPIC30F3014/4013
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
SPI1STAT 0220 SPIEN SPISIDL SPIROV SPITBF SPIRBF 0000 0000 0000 0000
SPI1CON 0222 FRMEN SPIFSD DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000
SPI1BUF 0224 Transmit and Receive Buffer 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Advance Information
2004 Microchip Technology Inc.
dsPIC30F3014/4013
15.0 I2C MODULE 15.1.1 VARIOUS I2C MODES
The following types of I2C operation are supported:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete I2C slave operation with 7-bit address
reference source. For more information on the CPU,
peripherals, register descriptions and general device
I2C slave operation with 10-bit address
functionality, refer to the dsPIC30F Family Reference I2C master operation with 7 or 10-bit address
Manual (DS70046).
See the I2C programmers model in Figure 15-1.
The Inter-Integrated Circuit (I2CTM ) module provides
complete hardware support for both Slave and Multi- 15.1.2 PIN CONFIGURATION IN I2C MODE
Master modes of the I2C serial communication 2
I C has a 2-pin interface: the SCL pin is clock and the
standard, with a 16-bit interface. SDA pin is data.
This module offers the following key features:
15.1.3 I2C REGISTERS
2I C
interface supporting both master and slave
operation. I2CCON and I2CSTAT are control and status registers,
I2C Slave mode supports 7 and 10-bit address. respectively. The I2CCON register is readable and writ-
able. The lower 6 bits of I2CSTAT are read only. The
I2C Master mode supports 7 and 10-bit address.
remaining bits of the I2CSTAT are read/write.
2I C
port allows bidirectional transfers between
master and slaves. I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
Serial clock synchronization for I2Cport can be
bytes are written, or from which data bytes are read.
used as a handshake mechanism to suspend and
I2CRCV is the receive buffer as shown in Figure 15-1.
resume serial transfer (SCLREL control).
I2CTRN is the transmit register to which bytes are
2I C
supports multi-master operation; detects bus written during a transmit operation, as shown in
collision and will arbitrate accordingly. Figure 15-2.
The I2CADD register holds the slave address. A status
15.1 Operating Function Description bit, ADD10, indicates 10-bit Address mode. The
The hardware fully implements all the master and slave I2CBRG acts as the baud rate generator reload value.
functions of the I 2C Standard and Fast mode In receive operations, I2CRSR and I2CRCV together
specifications, as well as 7 and 10-bit addressing. form a double-buffered receiver. When I2CRSR
Thus, the I2Cmodule can operate either as a slave or receives a complete byte, it is transferred to I2CRCV
a master on an I2C bus. and an interrupt pulse is generated. During
transmission, the I2CTRN is not double-buffered.
Note: Following a RESTART condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
I2CRCV (8 bits)
Bit 7 Bit 0
I2CTRN (8 bits)
Bit 7 Bit 0
I2CBRG (9 bits)
Bit 8 Bit 0
I2CCON (16 bits)
Bit 15 Bit 0
I2CSTAT (16 bits)
Bit 15 Bit 0
I2CADD (10 bits)
Bit 9 Bit 0
Internal
Data Bus
I2CRCV
Read
Shift
SCL Clock
I2CRSR
LSB
SDA Addr_Match
Match Detect
Write
I2CADD
Read
Start and
Stop bit Detect
Write
I2CSTAT
Start, RESTART,
Stop bit Generate
Read
Control Logic
Collision
Detect
Write
I2CCON
Acknowledge
Generation Read
Clock
Stretching Write
I2CTRN
Shift LSB
Read
Clock
Reload
Control Write
In the Slave modes, the module can synchronize buffer before the master device can initiate another receive
reads and write to the master device by clock stretching. sequence. This will prevent buffer overruns from
occurring.
15.5.1 TRANSMIT CLOCK STRETCHING
Both 10-bit and 7-bit Transmit modes implement clock Note 1: If the user reads the contents of the
stretching by asserting the SCLREL bit after the falling I2CRCV, clearing the RBF bit before the
edge of the ninth clock, if the TBF bit is cleared, falling edge of the ninth clock, the
indicating the buffer is empty. SCLREL bit will not be cleared and clock
stretching will not occur.
In Slave Transmit modes, clock stretching is always
performed irrespective of the STREN bit. 2: The SCLREL bit can be set in software
regardless of the state of the RBF bit. The
Clock synchronization takes place following the ninth user should be careful to clear the RBF bit
clock of the transmit sequence. If the device samples in the ISR before the next receive
an ACK on the falling edge of the ninth clock and if the sequence in order to prevent an overflow
TBF bit is still clear, then the SCLREL bit is automati- condition.
cally cleared. The SCLREL being cleared to 0 will
assert the SCL line low. The users ISR must set the 15.5.4 CLOCK STRETCHING DURING
SCLREL bit before transmission is allowed to continue. 10-BIT ADDRESSING (STREN = 1)
By holding the SCL line low, the user has time to ser-
Clock stretching takes place automatically during the
vice the ISR and load the contents of the I2CTRN
addressing sequence. Because this module has a
before the master device can initiate another transmit
register for the entire address, it is not necessary for
sequence.
the protocol to wait for the address to be updated.
Note 1: If the user loads the contents of I2CTRN, After the address phase is complete, clock stretching
setting the TBF bit before the falling edge will occur on each data receive or transmit sequence as
of the ninth clock, the SCLREL bit will not was described earlier.
be cleared and clock stretching will not
occur.
15.6 Software Controlled Clock
2: The SCLREL bit can be set in software, Stretching (STREN = 1)
regardless of the state of the TBF bit.
When the STREN bit is 1, the SCLREL bit may be
15.5.2 RECEIVE CLOCK STRETCHING cleared by software to allow software to control the
The STREN bit in the I2CCON register can be used to clock stretching. The logic will synchronize writes to the
enable clock stretching in Slave Receive mode. When SCLREL bit with the SCL clock. Clearing the SCLREL
the STREN bit is set, the SCL pin will be held low at the bit will not assert the SCL output until the module
end of each data receive sequence. detects a falling edge on the SCL output and SCL is
sampled low. If the SCLREL bit is cleared by the user
15.5.3 CLOCK STRETCHING DURING while the SCL line has been sampled low, the SCL out-
7-BIT ADDRESSING (STREN = 1) put will be asserted (held low). The SCL output will
remain low until the SCLREL bit is set, and all other
When the STREN bit is set in Slave Receive mode, the devices on the I2 Cbus have de-asserted SCL. This
SCL line is held low when the buffer register is full. The ensures that a write to the SCLREL bit will not violate
method for stretching the SCL output is the same for the minimum high time requirement for SCL.
both 7 and 10-bit Addressing modes.
If the STREN bit is 0, a software write to the SCLREL
bit will be disregarded and have no effect on the
SCLREL bit.
As per the 2I Cstandard, FSCK may be 100 kHz or The master will continue to monitor the SDA and SCL
400 kHz. However, the user can specify any baud rate pins, and if a Stop condition occurs, the MI2CIF bit will
up to 1 MHz. I2CBRG values of 0 or 1 are illegal. be set.
A write to the I2CTRN will start the transmission of data
EQUATION 15-1: SERIAL CLOCK RATE at the first data bit regardless of where the transmitter
left off when bus collision occurred.
In a multi-master environment, the interrupt generation
I2CBRG = ( FCY FCY ) 1
FSCK 1,111,111 on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the IC2
bus can be taken when the P bit is set in the I2CSTAT
15.12.4 CLOCK ARBITRATION register, or the bus is Idle and the S and P bits are
Clock arbitration occurs when the master de-asserts cleared.
the SCL pin (SCL allowed to float high) during any
receive, transmit, or RESTART/Stop condition. When 15.13 2I C Module Operation During CPU
the SCL pin is allowed to float high, the baud rate gen- Sleep and Idle Modes
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam- 15.13.1 I2C OPERATION DURING CPU
pled high, the baud rate generator is reloaded with the SLEEP MODE
contents of I2CBRG and begins counting. This ensures
that the SCL high time will always be at least one BRG When the device enters Sleep mode, all clock sources
rollover count in the event that the clock is held low by to the module are shutdown and stay at logic 0. If
an external device. Sleep occurs in the middle of a transmission and the
state machine is partially into a transmission as the
15.12.5 MULTI-MASTER COMMUNICATION, clocks stop, then the transmission is aborted. Similarly,
BUS COLLISION AND BUS if Sleep occurs in the middle of a reception, then the
ARBITRATION reception is aborted.
Multi-master operation support is achieved by bus arbi- 15.13.2 I2C OPERATION DURING CPU IDLE
tration. When the master outputs address/data bits MODE
onto the SDA pin, arbitration takes place when the
master outputs a 1 on SDA by letting SDA float high For the I2C,the I2CSIDL bit selects if the module will
while another master asserts a 0. When the SCL pin stop on Idle or continue on Idle. If I2CSIDL = 0, the
floats high, data should be stable. If the expected data module will continue operation on assertion of the Idle
on SDA is a 1 and the data sampled on the SDA mode. If I2CSIDL = 1, the module will stop on Idle.
pin = 0, then a bus collision has taken place. The
master will set the MI2CIF pulse and reset the master
portion of the I2C port to its Idle state.
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Advance Information
dsPIC30F3014/4013
DS70138C-page 95
dsPIC30F3014/4013
NOTES:
Write Write
Load TSR
UxTXIF
UTXBRK
Data
Transmit Shift Register (UxTSR)
0 (Start)
UxTX
or UxATX 1 (Stop)
if ALTIO=1
Parity 16x Baud Clock
Parity 16 Divider
Generator from Baud Rate
Generator
Control
Signals
Note: x = 1 or 2.
UxMODE UxSTA
LPBACK 8-9
From UxTX
1 Load RSR
to Buffer Control
FERR
PERR
Receive Shift Register Signals
0 (UxRSR)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
U1MODE 020C UARTEN USIDL ALTIO WAKE LPBACK ABAUD PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
U1STA 020E UTXISEL UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000
U1TXREG 0210 UTX8 Transmit Register 0000 000u uuuu uuuu
U1RXREG 0212 URX8 Receive Register 0000 0000 0000 0000
U1BRG 0214 Baud Rate Generator Prescaler 0000 0000 0000 0000
Legend: u = uninitialized bit
U2MODE 0216 UARTEN USIDL WAKE LPBACK ABAUD PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
U2STA 0218 UTXISEL UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000
Advance Information
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138C-page 103
dsPIC30F3014/4013
NOTES:
Acceptance Mask
BUFFERS RXM1
Acceptance Filter
RXF2
Acceptance Mask Acceptance Filter A
TXB0 TXB1 TXB2 RXM0 c
RXF3
A c
c Acceptance Filter Acceptance Filter e
MTXBUFF
MTXBUFF
MTXBUFF
MSGREQ
MSGREQ
MSGREQ
MESSAG
MESSAG
MESSAG
RXF0
TXLARB
TXLARB
TXLARB
c RXF4 p
TXERR
TXERR
TXERR
TXABT
TXABT
TXABT
e t
Acceptance Filter Acceptance Filter
p
E
E
RXF1 RXF5
t
R R
X Identifier M Identifier X
Message B A B
Queue 0 B 1
Control
Transmit Byte Sequencer Data Field Data Field
Receive RERRCNT
Error
Counter
PROTOCOL TERRCNT
ENGINE
Transmit Err Pas
Error Bus Off
Counter
Protocol
Finite
CRC Generator CRC Check
State
Machine
Bit
Transmit
Timing Bit Timing
Logic
Logic Generator
CiTX(1) CiRX(1)
Input Signal
Sample Point
TQ
17.6.6 SYNCHRONIZATION
17.6.3 PROPAGATION SEGMENT
To compensate for phase shifts between the oscillator
This part of the bit time is used to compensate physical
frequencies of the different bus stations, each CAN
delay times within the network. These delay times con-
controller must be able to synchronize to the relevant
sist of the signal propagation time on the bus line and
signal edge of the incoming signal. When an edge in
the internal delay time of the nodes. The Prop Seg can
the transmitted data is detected, the logic will compare
be programmed from 1 TQ to 8 TQ by setting the
the location of the edge to the expected time (Synchro-
PRSEG<2:0> bits (CiCFG2<2:0>).
nous Segment). The circuit will then adjust the values
of Phase1 Seg and Phase2 Seg. There are 2
17.6.4 PHASE SEGMENTS
mechanisms used to synchronize.
The phase segments are used to optimally locate the
sampling of the received bit within the transmitted bit 17.6.6.1 Hard Synchronization
time. The sampling point is between Phase1 Seg and
Hard synchronization is only done whenever there is a
Phase2 Seg. These segments are lengthened or short-
recessive to dominant edge during bus Idle indicating
ened by resynchronization. The end of the Phase1 Seg
the start of a message. After hard synchronization, the
determines the sampling point within a bit period. The
bit time counters are restarted with the Sync Seg. Hard
segment is programmable from 1 TQ to 8 TQ. Phase2
synchronization forces the edge which has caused the
Seg provides delay to the next transmitted data transi-
hard synchronization to lie within the synchronization
tion. The segment is programmable from 1 TQ to 8 TQ,
segment of the restarted bit time. If a hard synchroniza-
or it may be defined to be equal to the greater of
tion is done, there will not be a resynchronization within
Phase1 Seg or the information processing time (2 TQ).
that bit time.
The Phase1 Seg is initialized by setting bits
SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is 17.6.6.2 Resynchronization
initialized by setting SEG2PH<2:0> (CiCFG2<10:8>).
As a result of resynchronization, Phase1 Seg may be
The following requirement must be fulfilled while setting lengthened or Phase2 Seg may be shortened. The
the lengths of the phase segments: amount of lengthening or shortening of the phase
Prop Seg + Phase1 Seg > = Phase2 Seg buffer segment has an upper bound known as the syn-
chronization jump width, and is specified by the
SJW<1:0> bits (CiCFG1<7:6>). The value of the syn-
chronization jump width will be added to Phase1 Seg or
subtracted from Phase2 Seg. The resynchronization
jump width is programmable between 1 TQ and 4 TQ.
The following requirement must be fulfilled while setting
the SJW<1:0> bits:
Phase2 Seg > Synchronization Jump Width
dsPIC30F3014/4013
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
C1RXF0SID 0300 Receive Acceptance Filter 0 Standard Identifier <10:0> EXIDE 000u uuuu uuuu uu0u
C1RXF0EIDH 0302 Receive Acceptance Filter 0 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier <5:0> uuuu uu00 0000 0000
C1RXF1SID 0308 Receive Acceptance Filter 1 Standard Identifier <10:0> EXIDE 000u uuuu uuuu uu0u
C1RXF1EIDH 030A Receive Acceptance Filter 1 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF1EIDL 030C Receive Acceptance Filter 1 Extended Identifier <5:0> uuuu uu00 0000 0000
C1RXF2SID 0310 Receive Acceptance Filter 2 Standard Identifier <10:0> EXIDE 000u uuuu uuuu uu0u
C1RXF2EIDH 0312 Receive Acceptance Filter 2 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF2EIDL 0314 Receive Acceptance Filter 2 Extended Identifier <5:0> uuuu uu00 0000 0000
C1RXF3SID 0318 Receive Acceptance Filter 3 Standard Identifier <10:0> EXIDE 000u uuuu uuuu uu0u
C1RXF3EIDH 031A Receive Acceptance Filter 3 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF3EIDL 031C Receive Acceptance Filter 3 Extended Identifier <5:0> uuuu uu00 0000 0000
C1RXF4SID 0320 Receive Acceptance Filter 4 Standard Identifier <10:0> EXIDE 000u uuuu uuuu uu0u
Advance Information
C1RXF4EIDH 0322 Receive Acceptance Filter 4 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF4EIDL 0324 Receive Acceptance Filter 4 Extended Identifier <5:0> uuuu uu00 0000 0000
C1RXF5SID 0328 Receive Acceptance Filter 5 Standard Identifier <10:0> EXIDE 000u uuuu uuuu uu0u
C1RXF5EIDH 032A Receive Acceptance Filter 5 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXF5EIDL 032C Receive Acceptance Filter 5 Extended Identifier <5:0> uuuu uu00 0000 0000
C1RXM0SID 0330 Receive Acceptance Mask 0 Standard Identifier <10:0> MIDE 000u uuuu uuuu uu0u
C1RXM0EIDH 0332 Receive Acceptance Mask 0 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXM0EIDL 0334 Receive Acceptance Mask 0 Extended Identifier <5:0> uuuu uu00 0000 0000
C1RXM1SID 0338 Receive Acceptance Mask 1 Standard Identifier <10:0> MIDE 000u uuuu uuuu uu0u
C1RXM1EIDH 033A Receive Acceptance Mask 1 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RXM1EIDL 033C Receive Acceptance Mask 1 Extended Identifier <5:0> uuuu uu00 0000 0000
C1TX2SID 0340 Transmit Buffer 2 Standard Identifier <10:6> Transmit Buffer 2 Standard Identifier <5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX2EID 0342 Transmit Buffer 2 Extended Identifier Transmit Buffer 2 Extended Identifier <13:6> uuuu 0000 uuuu uuuu
<17:14>
C1TX2DLC 0344 Transmit Buffer 2 Extended Identifier <5:0> TXRTR TXRB1 TXRB0 DLC<3:0> uuuu uuuu uuuu u000
C1TX2B1 0346 Transmit Buffer 2 Byte 1 Transmit Buffer 2 Byte 0 uuuu uuuu uuuu uuuu
2004 Microchip Technology Inc.
C1TX2B2 0348 Transmit Buffer 2 Byte 3 Transmit Buffer 2 Byte 2 uuuu uuuu uuuu uuuu
C1TX2B3 034A Transmit Buffer 2 Byte 5 Transmit Buffer 2 Byte 4 uuuu uuuu uuuu uuuu
C1TX2B4 034C Transmit Buffer 2 Byte 7 Transmit Buffer 2 Byte 6 uuuu uuuu uuuu uuuu
C1TX2CON 034E TXABT TXLARB TXERR TXREQ TXPRI<1:0> 0000 0000 0000 0000
C1TX1SID 0350 Transmit Buffer 1 Standard Identifier <10:6> Transmit Buffer 1 Standard Identifier <5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX1EID 0352 Transmit Buffer 1 Extended Identifier Transmit Buffer 1 Extended Identifier <13:6> uuuu 0000 uuuu uuuu
<17:14>
C1TX1DLC 0354 Transmit Buffer 1 Extended Identifier <5:0> TXRTR TXRB1 TXRB0 DLC<3:0> uuuu uuuu uuuu u000
Legend: u = uninitialized bit
TABLE 17-1: dsPIC30F4013 CAN1 REGISTER MAP (CONTINUED)
2004 Microchip Technology Inc.
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
C1TX1B1 0356 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
C1TX1B2 0358 Transmit Buffer 1 Byte 3 Transmit Buffer 1 Byte 2 uuuu uuuu uuuu uuuu
C1TX1B3 035A Transmit Buffer 1 Byte 5 Transmit Buffer 1 Byte 4 uuuu uuuu uuuu uuuu
C1TX1B4 035C Transmit Buffer 1 Byte 7 Transmit Buffer 1 Byte 6 uuuu uuuu uuuu uuuu
C1TX1CON 035E TXABT TXLARB TXERR TXREQ TXPRI<1:0> 0000 0000 0000 0000
C1TX0SID 0360 Transmit Buffer 0 Standard Identifier <10:6> Transmit Buffer 0 Standard Identifier <5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX0EID 0362 Transmit Buffer 0 Extended Identifier Transmit Buffer 0 Extended Identifier <13:6> uuuu 0000 uuuu uuuu
<17:14>
C1TX0DLC 0364 Transmit Buffer 0 Extended Identifier <5:0> TXRTR TXRB1 TXRB0 DLC<3:0> uuuu uuuu uuuu u000
C1TX0B1 0366 Transmit Buffer 0 Byte 1 Transmit Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C1TX0B2 0368 Transmit Buffer 0 Byte 3 Transmit Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
C1TX0B3 036A Transmit Buffer 0 Byte 5 Transmit Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
C1TX0B4 036C Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
Advance Information
C1TX0CON 036E TXABT TXLARB TXERR TXREQ TXPRI<1:0> 0000 0000 0000 0000
C1RX1SID 0370 Receive Buffer 1 Standard Identifier <10:0> SRR RXIDE 000u uuuu uuuu uuuu
C1RX1EID 0372 Receive Buffer 1 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RX1DLC 0374 Receive Buffer 1 Extended Identifier <5:0> RXRTR RXRB1 RXRB0 DLC<3:0> uuuu uuuu 000u uuuu
C1RX1B1 0376 Receive Buffer 1 Byte 1 Receive Buffer 1 Byte 0 uuuu uuuu uuuu uuuu
C1RX1B2 0378 Receive Buffer 1 Byte 3 Receive Buffer 1 Byte 2 uuuu uuuu uuuu uuuu
C1RX1B3 037A Receive Buffer 1 Byte 5 Receive Buffer 1 Byte 4 uuuu uuuu uuuu uuuu
dsPIC30F3014/4013
C1RX1B4 037C Receive Buffer 1 Byte 7 Receive Buffer 1 Byte 6 uuuu uuuu uuuu uuuu
C1RX1CON 037E RXFUL RXRTRRO FILHIT<2:0> 0000 0000 0000 0000
C1RX0SID 0380 Receive Buffer 0 Standard Identifier <10:0> SRR RXIDE 000u uuuu uuuu uuuu
C1RX0EID 0382 Receive Buffer 0 Extended Identifier <17:6> 0000 uuuu uuuu uuuu
C1RX0DLC 0384 Receive Buffer 0 Extended Identifier <5:0> RXRTR RXRB1 RXRB0 DLC<3:0> uuuu uuuu 000u uuuu
C1RX0B1 0386 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 0 uuuu uuuu uuuu uuuu
C1RX0B2 0388 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 2 uuuu uuuu uuuu uuuu
C1RX0B3 038A Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 4 uuuu uuuu uuuu uuuu
C1RX0B4 038C Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 6 uuuu uuuu uuuu uuuu
C1RX0CON 038E RXFUL RXRTRRO DBEN JTOFF FILHIT0 0000 0000 0000 0000
C1CTRL 0390 CANCAP CSIDLE ABAT CANCKS REQOP<2:0> OPMODE<2:0> ICODE<2:0> 0000 0100 1000 0000
DS70138C-page 113
dsPIC30F3014/4013
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
C1INTF 0396 RX0OVR RX1OVR TXBO TXEP RXEP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000 0000 0000
C1INTE 0398 IVRIE WAKIE ERRIE TX2IE TX1IE TX0IE RX1E RX0IE 0000 0000 0000 0000
C1EC 039A Transmit Error Count Register Receive Error Count Register 0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Advance Information
2004 Microchip Technology Inc.
dsPIC30F3014/4013
18.0 DATA CONVERTER 18.2.3 CSDI PIN
INTERFACE (DCI) MODULE The serial data input (CSDI) pin is configured as an
input only pin when the module is enabled.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete 18.2.3.1 COFS PIN
reference source. For more information on the CPU,
peripherals, register descriptions and general device The Codec frame synchronization (COFS) pin is used
functionality, refer to the dsPIC30F Family Reference to synchronize data transfers that occur on the CSDO
Manual (DS70046).
and CSDI pins. The COFS pin may be configured as an
input or an output. The data direction for the COFS pin
18.1 Module Introduction is determined by the COFSD control bit in the
The dsPIC30F Data Converter Interface (DCI) module DCICON1 register.
allows simple interfacing of devices, such as audio The DCI module accesses the shadow registers while
coder/decoders (Codecs), A/D converters and D/A the CPU is in the process of accessing the memory
converters. The following interfaces are supported: mapped buffer registers.
Framed Synchronous Serial Transfer (Single or
18.2.4 BUFFER DATA ALIGNMENT
Multi-Channel)
Inter-IC Sound (I2 S) Interface Data values are always stored left justified in the buff-
ers since most Codec data is represented as a signed
AC-Link Compliant mode
2s complement fractional number. If the received word
The DCI module provides the following general length is less than 16 bits, the unused LS bits in the
features: receive buffer registers are set to 0 by the module. If
Programmable word size up to 16 bits the transmitted word length is less than 16 bits, the
Support for up to 16 time slots, for a maximum unused LS bits in the transmit buffer register are
frame size of 256 bits ignored by the module. The word length setup is
described in subsequent sections of this document.
Data buffering for up to 4 samples without CPU
overhead 18.2.5 TRANSMIT/RECEIVE SHIFT
REGISTER
18.2 Module I/O Pins
The DCI module has a 16-bit shift register for shifting
There are four I/O pins associated with the module. serial data in and out of the module. Data is shifted in/
When enabled, the module controls the data direction out of the shift register MS bit first, since audio PCM
of each of the four pins. data is transmitted in signed 2s complement format.
Sample Rate
FOSC/4 CSCK
Generator
FSD
Word Size Selection bits Frame
Frame Length Selection bits Synchronization COFS
DCI Mode Selection bits Generator
16-bit Data Bus
Receive Buffer
Registers w/Shadow
DCI Buffer
Control Unit
15 0
Transmit Buffer
DCI Shift Register CSDI
Registers w/Shadow
CSDO
When enabled, the DCI controls the data direction for The operation of the COFSM control bits depends on
the four I/O pins associated with the module. The Port, whether the DCI module generates the frame sync
LAT and TRIS register values for these I/O pins are signal as a master device, or receives the frame sync
overridden by the DCI module when the DCIEN bit is set. signal as a slave device.
It is also possible to override the CSCK pin separately The master device in a DSP/Codec pair is the device
when the bit clock generator is enabled. This permits that generates the frame sync signal. The frame sync
the bit clock generator to operate without enabling the signal initiates data transfers on the CSDI and CSDO
rest of the DCI module. pins and usually has the same frequency as the data
sample rate (COFS).
18.3.2 WORD SIZE SELECTION BITS The DCI module is a frame sync master if the COFSD
The WS<3:0> word size selection bits in the DCICON2 control bit is cleared and is a frame sync slave if the
SFR determine the number of bits in each DCI data COFSD control bit is set.
word. Essentially, the WS<3:0> bits determine the
counting period for a 4-bit counter clocked from the 18.3.5 MASTER FRAME SYNC
CSCK signal. OPERATION
Any data length, up to 16-bits, may be selected. The When the DCI module is operating as a frame sync
value loaded into the WS<3:0> bits is one less the master device (COFSD = 0), the COFSM mode bits
desired word length. For example, a 16-bit data word determine the type of frame sync pulse that is
size is selected when WS<3:0> = 1111. generated by the frame sync generator logic.
Note: These WS<3:0> control bits are used only A new COFS signal is generated when the frame sync
2 generator resets to 0.
in the Multi-Channel and I S modes. These
bits have no effect in AC-Link mode since In the Multi-Channel mode, the frame sync pulse is
the data slot sizes are fixed by the protocol. driven high for the CSCK period to initiate a data trans-
fer. The number of CSCK cycles between successive
18.3.3 FRAME SYNC GENERATOR frame sync pulses will depend on the word size and
The frame sync generator (COFSG) is a 4-bit counter frame sync generator control bits. A timing diagram for
that sets the frame length in data words. The frame the frame sync signal in Multi-Channel mode is shown
sync generator is incremented each time the word size in Figure 18-2.
counter is reset (refer to Section 18.3.2). The period for In the AC-Link mode of operation, the frame sync sig-
the frame synchronization generator is set by writing nal has a fixed period and duty cycle. The AC-Link
the COFSG<3:0> control bits in the DCICON2 SFR. frame sync signal is high for 16 CSCK cycles and is low
The COFSG period in clock cycles is determined by the for 240 CSCK cycles. A timing diagram with the timing
following formula: details at the start of an AC-Link frame is shown in
Figure 18-3.
EQUATION 18-1: COFSG PERIOD In the I2S mode, a frame sync signal having a 50% duty
cycle is generated. The period of the I2 S
frame sync
Frame Length = Word Length (FSG Value + 1) signal in CSCK cycles is determined by the word size
and frame sync generator control bits. A new I2 Sdata
Frame lengths, up to 16 data words, may be selected. transfer boundary is marked by a high-to-low or a low-
The frame length in CSCK periods can vary up to a to-high transition edge on the COFS pin.
maximum of 256 depending on the word size that is
selected.
Note: The COFSG control bits will have no effect
in AC-Link mode since the frame length is
set to 256 CSCK periods by the protocol.
CSCK
COFS
BIT_CLK
SYNC
CSCK
WS
2
Note: A 5-bit transfer is shown here for illustration purposes. The I S protocol does not specify word length - this will
be system dependent.
There is no direct coupling between the position of the Note: The transmit status bits only indicate sta-
AGU address pointer and the data frame boundaries. tus for buffer locations that are used by the
This means that there will be an implied assignment of module. If the buffer length is set to less
each transmit and receive buffer that is a function of the than four words, for example, the unused
BLEN control bits and the number of enabled data slots buffer locations will not affect the transmit
via the TSE and RSE control bits. status bits.
As an example, assume that a 4-word data frame is 18.3.17 RECEIVE STATUS BITS
chosen and that we want to transmit on all four time
slots in the frame. This configuration would be estab- There are two receive status bits in the DCISTAT SFR.
lished by setting the TSE0, TSE1, TSE2, and TSE3 The RFUL status bit is read only and indicates that new
control bits in the TSCON SFR. With this module setup, data is available in the receive buffers. The RFUL bit is
the TXBUF0 register would be naturally assigned to cleared automatically when all receive buffers in use
slot #0, the TXBUF1 register would be naturally have been read by the CPU.
assigned to slot #1, and so on.
The ROV status bit is read only and indicates that a
Note: When more than four time slots are active receive overflow has occurred for at least one of the
within a data frame, the user code must receive buffer locations. A receive overflow occurs
keep track of which time slots are to be when the buffer location is not read by the CPU before
read/written at each interrupt. In some new data is transferred from the shadow registers. The
cases, the alignment between transmit/ ROV status bit is cleared automatically when the buffer
receive buffers and their respective slot register that caused the overflow is read by the CPU.
assignments could be lost. Examples of When a receive overflow occurs for a specific buffer
such cases include an emulation break- location, the old contents of the buffer are overwritten.
point or a hardware trap. In these situa-
tions, the user should poll the SLOT status Note: The receive status bits only indicate status
bits to determine what data should be for buffer locations that are used by the
loaded into the buffer registers to module. If the buffer length is set to less
resynchronize the software with the DCI than four words, for example, the unused
module. buffer locations will not affect the transmit
status bits.
dsPIC30F3014/4013
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
DCICON1 0240 DCIEN DCISIDL DLOOP CSCKD CSCKE COFSD UNFM CSDOM DJST COFSM1 COFSM0 0000 0000 0000 0000
DCICON2 0242 BLEN1 BLEN0 COFSG<3:0> WS<3:0> 0000 0000 0000 0000
DCICON3 0244 BCG<11:0> 0000 0000 0000 0000
DCISTAT 0246 SLOT3 SLOT2 SLOT1 SLOT0 ROV RFUL TUNF TMPTY 0000 0000 0000 0000
TSCON 0248 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 0000 0000 0000 0000
RSCON 024C RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 0000 0000 0000 0000
RXBUF0 0250 Receive Buffer #0 Data Register 0000 0000 0000 0000
RXBUF1 0252 Receive Buffer #1 Data Register 0000 0000 0000 0000
RXBUF2 0254 Receive Buffer #2 Data Register 0000 0000 0000 0000
RXBUF3 0256 Receive Buffer #3 Data Register 0000 0000 0000 0000
TXBUF0 0258 Transmit Buffer #0 Data Register 0000 0000 0000 0000
TXBUF1 025A Transmit Buffer #1 Data Register 0000 0000 0000 0000
0000 0000 0000 0000
Advance Information
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
2004 Microchip Technology Inc.
dsPIC30F3014/4013
19.0 12-BIT ANALOG-TO-DIGITAL The A/D module has six 16-bit registers:
CONVERTER (A/D) MODULE A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
Note: This data sheet summarizes features of this group A/D Control Register 3 (ADCON3)
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU, A/D Input Select Register (ADCHS)
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
A/D Port Configuration Register (ADPCFG)
Manual (DS70046). A/D Input Scan Selection Register (ADCSSL)
The 12-bit Analog-to-Digital converter (A/D) allows The ADCON1, ADCON2 and ADCON3 registers con-
conversion of an analog input signal to a 12-bit digital trol the operation of the A/D module. The ADCHS reg-
number. This module is based on a Successive ister selects the input channels to be converted. The
Approximation Register (SAR) architecture and pro- ADPCFG register configures the port pins as analog
vides a maximum sampling rate of 100 ksps. The A/D inputs or as digital I/O. The ADCSSL register selects
module has up to 16 analog inputs which are multi- inputs for scanning.
plexed into a sample and hold amplifier. The output of
Note: The SSRC<2:0>, ASAM, SMPI<3:0>,
the sample and hold is the input into the converter BUFM and ALTS bits, as well as the
which generates the result. The analog reference volt- ADCON3 and ADCSSL registers, must
age is software selectable to either the device supply not be written to while ADON = 1. This
voltage (AVDD/AVSS) or the voltage level on the would lead to indeterminate results.
(VREF+/VREF-) pin. The A/D converter has a unique
feature of being able to operate while the device is in The block diagram of the 12-bit A/D module is shown in
Sleep mode with RC oscillator selection. Figure 19-1.
AVDD
AVSS
VREF+
VREF-
0000 Comparator
AN0
DAC
0001
AN1
0010
AN2
0011 12-bit SAR Conversion Logic
AN3
0100
AN4
Format
Data
AN6
0111
AN7
1000 Sample/Sequence
AN8 Sample Control
1001
AN9
1010 Input
AN10 Input MUX
Switches
1011 Control
AN11
1100
AN12
VREF- S/H CH0
AN1
Note: The ADCHS, ADPCFG and ADCSSL registers allow the application to configure AN13-AN15 as analog input pins.
Since these pins are not physically present on the device, conversion results from these pins will read 0.
VDD
RIC 250 Sampling R SS 3 k
Switch
VT = 0.6V
Rs ANx RSS
CHOLD
VA CPIN I leakage = DAC capacitance
VT = 0.6V 500 nA = 18 pF
VSS
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs 2.5 k.
19.8 Module Power-down Modes If the A/D interrupt is enabled, the device will wake-up
from Sleep. If the A/D interrupt is not enabled, the A/
The module has 2 internal Power modes. D module will then be turned off, although the ADON bit
When the ADON bit is 1, the module is in Active mode; will remain set.
it is fully powered and functional.
19.9.2 A/D OPERATION DURING CPU IDLE
When ADON is 0, the module is in Off mode. The dig-
MODE
ital and analog portions of the circuit are disabled for
maximum current savings. The ADSIDL bit selects if the module will stop on Idle or
continue on Idle. If ADSIDL = 0, the module will con-
In order to return to the Active mode from Off mode, the
tinue operation on assertion of Idle mode. If ADSIDL =
user must wait for the ADC circuitry to stabilize. The
1, the module will stop on Idle.
time required to stabilize is specified in the Electrical
Characteristics.
19.10 Effects of a Reset
19.9 A/D Operation During CPU Sleep A device Reset forces all registers to their Reset state.
and Idle Modes This forces the A/D module to be turned off, and any
conversion and sampling sequence is aborted. The val-
19.9.1 A/D OPERATION DURING CPU ues that are in the ADCBUF registers are not modified.
SLEEP MODE The A/D Result register will contain unknown data after
a Power-on Reset.
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic 0.
19.11 Output Formats
If Sleep occurs in the middle of a conversion, the con-
version is aborted. The converter will not continue with The A/D result is 12 bits wide. The data buffer RAM is
a partially completed conversion on exit from Sleep also 12 bits wide. The 12-bit data can be read in one of
mode. four different formats. The FORM<1:0> bits select the
Register contents are not affected by the device format. Each of the output formats translates to a 16-bit
entering or leaving Sleep mode. result on the data bus. Write data will always be in right
justified (integer) format.
The A/D module can operate during Sleep mode if the
A/D clock source is set to RC (ADRC = 1). When the RC
clock source is selected, the A/D module waits one
instruction cycle before starting the conversion. This
allows the SLEEP instruction to be executed which elim-
inates all digital switching noise from the conversion.
(When the conversion sequence is complete, the
DONE bit will be set.)
RAM Contents: d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0
Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0
Signed Integer d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Integer 0 0 0 0 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
dsPIC30F3014/4013
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
2004 Microchip Technology Inc.
dsPIC30F3014/4013
20.0 SYSTEM INTEGRATION 20.1 Oscillator System Overview
Note: This data sheet summarizes features of this group The dsPIC30F oscillator system has the following
of dsPIC30F devices and is not intended to be a complete modules and features:
reference source. For more information on the CPU,
peripherals, register descriptions and general device Various external and internal oscillator options as
functionality, refer to the dsPIC30F Family Reference clock sources
Manual (DS70046). For more information on the device An on-chip PLL to boost internal operating
instruction set and programming, refer to the dsPIC30F
frequency
Programmers Reference Manual (DS70030).
A clock switching mechanism between various
There are several features intended to maximize sys- clock sources
tem reliability, minimize cost through elimination of
Programmable clock postscaler for system power
external components, provide Power Saving Operating
savings
modes and offer code protection:
A Fail-Safe Clock Monitor (FSCM) that detects
Oscillator Selection clock failure and takes fail-safe measures
Reset Clock Control register (OSCCON)
- Power-on Reset (POR) Configuration bits for main oscillator selection
- Power-up Timer (PWRT)
Configuration bits determine the clock source upon
- Oscillator Start-up Timer (OST) Power-on Reset (POR) and Brown-out Reset (BOR).
- Programmable Brown-out Reset (BOR) Thereafter, the clock source can be changed between
Watchdog Timer (WDT) permissible clock sources. The OSCCON register
Power Saving Modes (Sleep and Idle) controls the clock switching and reflects system clock
related status bits.
Code Protection
Unit ID Locations Table 20-1 provides a summary of the dsPIC30F Oscil-
lator Operating modes. A simplified diagram of the
In-Circuit Serial Programming (ICSP)
oscillator system is shown in Figure 20-1.
dsPIC30F devices have a Watchdog Timer which is
permanently enabled via the configuration bits or can
be software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer
necessary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
Reset until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT) which provides a delay on
power-up only, designed to keep the part in Reset while
the power supply stabilizes. With these two timers on-
chip, most applications need no external Reset
circuitry.
Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit a wide variety of
applications. In the Idle mode, the clock sources are
still active but the CPU is shut-off. The RC oscillator
option saves system cost while the LP crystal option
saves power.
FPLL
OSC1
Primary PLL
Oscillator x4, x8, x16 PLL
OSC2
Lock COSC<2:0>
Primary Osc
NOSC<2:0>
Primary
Oscillator OSWEN
Stability Detector
Oscillator
POR Done Start-up
Timer Clock
Programmable
Switching
Secondary Osc Clock Divider System
and Control
Clock
SOSCO Block
32 kHz LP Secondary
Oscillator Oscillator 2
SOSCI Stability Detector
POST<1:0>
4
TUN<3:0>
Internal Fast RC
Oscillator (FRC)
CF
Fail-Safe Clock
FCKSM<1:0>
Monitor (FSCM)
2 Oscillator Trap
To Timer1
Lower Byte:
R/W-0 R/W-0 R-0 U-0 R/W-0 U-0 R/W-0 R/W-0
POST<1:0> LOCK CF LPOSCEN OSWEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
y = Value set from configuration bits on POR
Lower Byte:
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
TUN<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
y = Value set from configuration bits on POR
Middle Byte:
R/P R/P U U U R/P R/P R/P
FCKSM<1:0> FOS<2:0>
bit 15 bit 8
Lower Byte:
U U U R/P R/P R/P R/P R/P
FPR<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
Digital
Glitch Filter
MCLR
Sleep or Idle
WDT
Module
Illegal Opcode/
Uninitialized W Register
20.4.1 POR: POWER-ON RESET The POR circuit inserts a small delay, TPOR, which is
nominally 10 s and ensures that the device bias cir-
A power-on event will generate an internal POR pulse
cuits are stable. Furthermore, a user selected power-
when a VDD rise is detected. The Reset pulse will occur
up time-out (TPWRT) is applied. The TPWRT parameter
at the POR circuit threshold voltage (VPOR) which is
is based on device configuration bits and can be 0 ms
nominally 1.85V. The device supply voltage character-
(no delay), 4 ms, 16 ms, or 64 ms. The total delay is at
istics must meet specified starting voltage and rise rate
device power-up, TPOR + TPWRT. When these delays
requirements. The POR pulse will reset a POR timer
have expired, SYSRST will be negated on the next
and place the device in the Reset state. The POR also
leading edge of the Q1 clock and the PC will jump to the
selects the device clock source identified by the oscil-
Reset vector.
lator configuration fuses.
The timing for the SYSRST signal is shown in
Figure 20-3 through Figure 20-5.
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
FIGURE 20-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
dsPIC30F3014/4013
SFR
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Name
RCON 0740 TRAPR IOPUWR BGST LVDEN LVDL<3:0> EXTR SWR SWDTEN WDTO Sleep Idle BOR POR (Note 1)
OSCCON 0742 COSC<2:0> NOSC<2:0> POST<1:0> LOCK CF LPOSCEN OSWEN (Note 2)
OSCTUN 0744 TUN3 TUN2 TUN1 TUN0 0000 0000 0000 0000
PMD1 0770 T5MD T4MD T3MD T2MD T1MD DCIMD I2CMD U2MD U1MD SPI1MD C1MD ADCMD 0000 0000 0000 0000
PMD2 0772 IC8MD IC7MD IC2MD IC1MD OC4MD OC3MD OC2MD OC1MD 0000 0000 0000 0000
Note 1: Reset state depends on type of Reset.
2: Reset state depends on configuration bits.
3: For the dsPIC30F3014 device, the DCIMD, T4MD, T5MD, OC3MD, OC4,MD, IC7MD and IC8MD bits do not perform any function.
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
2004 Microchip Technology Inc.
dsPIC30F3014/4013
21.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
Note: This data sheet summarizes features of this group The W register (with or without an address
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU, modifier) or file register (specified by the value of
peripherals, register descriptions and general device Ws or f)
functionality, refer to the dsPIC30F Family Reference The bit in the W register or file register
Manual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30F (specified by a literal value or indirectly by the
Programmers Reference Manual (DS70030). contents of register Wb)
The dsPIC30F instruction set adds many The literal instructions that involve data movement may
enhancements to the previous PICmicro instruction use some of the following operands:
sets, while maintaining an easy migration from A literal value to be loaded into a W register or file
PICmicro instruction sets. register (specified by the value of k)
Most instructions are a single program memory word The W register or file register where the literal
(24 bits). Only three instructions require two program value is to be loaded (specified by Wb or f)
memory locations. However, literal instructions that involve arithmetic or
Each single word instruction is a 24-bit word divided logical operations use some of the following operands:
into an 8-bit opcode which specifies the instruction The first source operand which is a register Wb
type, and one or more operands which further specify without any address modifier
the operation of the instruction.
The second source operand which is a literal
The instruction set is highly orthogonal and is grouped value
into five basic categories: The destination of the result (only if not the same
Word or byte-oriented operations as the first source operand) which is typically a
Bit-oriented operations register Wd with or without an address modifier
Literal operations The MAC class of DSP instructions may use some of the
DSP operations following operands:
Control operations The accumulator (A or B) to be used (required
operand)
Table 21-1 shows the general symbols used in
describing the instructions. The W registers to be used as the two operands
The X and Y address space pre-fetch operations
The dsPIC30F instruction set summary in Table 21-2
lists all the instructions, along with the status flags The X and Y address space pre-fetch destinations
affected by each instruction. The accumulator write back destination
Most word or byte-oriented W register instructions The other DSP instructions do not involve any
(including barrel shift instructions) have three multiplication, and may include:
operands: The accumulator to be used (required)
The first source operand which is typically a The source or destination operand (designated as
register Wb without any address modifier Wso or Wdo, respectively) with or without an
The second source operand which is typically a address modifier
register Ws with or without an address modifier The amount of shift specified by a W register Wn
The destination of the result which is typically a or a literal value
register Wd with or without an address modifier The control instructions may use some of the following
However, word or byte-oriented file register instructions operands:
have two operands: A program memory address
The file register specified by the value f The mode of the table read and table write
The destination, which could either be the file instructions
register f or the W0 register, which is denoted as All instructions are a single word, except for certain
WREG double-word instructions, which were made double-
word instructions so that all the required information is
available in these 48 bits. In the second word, the
8 MSbs are 0s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
NOTICE:
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific
devices, please refer the the Family Cross Reference Table.
23.1 DC Characteristics
TABLE 23-1: OPERATING MIPS VS. VOLTAGE
Max MIPS
VDD Range Temp Range
dsPIC30FXXX-30I dsPIC30FXXX-20I dsPIC30FXXX-20E
4.5-5.5V -40C to 85C 30 20
4.5-5.5V -40C to 125C 20
3.0-3.6V -40C to 85C 15 10
3.0-3.6V -40C to 125C 10
2.5-3.0V -40C to 85C 10 7.5
VDD
LV10
LVDIF
(LVDIF set by hardware)
VDD
Load Condition 1 - for all pins except OSC2 Load Condition 2 - for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins except OSC2
VSS 5 pF for OSC2 output
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
OS20
OS30 OS30 OS31 OS31
OS25
CLKOUT
OS40 OS41
OS50 FPLLI PLL Input Frequency Range(2) 4 10 MHz EC, XT modes with PLL
OS51 FSYS On-chip PLL Output(2) 16 120 MHz EC, XT modes with PLL
OS52 TLOC PLL Start-up Time (Lock Time) 20 50 s
OS53 DCLK CLKOUT Stability (Jitter) TBD 1 TBD % Measured over 100 ms
period
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in Typ column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and
are not tested.
I/O Pin
(Input)
DI35
DI40
VDD SY12
MCLR
Internal SY10
POR
SY11
PWRT
Time-out
SY30
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
VBGAP
0V
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRX
TA10 TTXH TxCK High Time Synchronous, 0.5 TCY + 20 ns Must also meet
no prescaler parameter TA15
Synchronous, 10 ns
with prescaler
Asynchronous 10 ns
TA11 TTXL TxCK Low Time Synchronous, 0.5 TCY + 20 ns Must also meet
no prescaler parameter TA15
Synchronous, 10 ns
with prescaler
Asynchronous 10 ns
TA15 TTXP TxCK Input Period Synchronous, TCY + 10 ns
no prescaler
Synchronous, Greater of: N = prescale
with prescaler 20 ns or value
(TCY + 40)/N (1, 8, 64, 256)
Asynchronous 20 ns
OS60 Ft1 SOSC1/T1CK oscillator input DC 50 kHz
frequency range (oscillator enabled
by setting bit TCS (T1CON, bit 1))
TA20 TCKEXTMRL Delay from External TxCK Clock 2 TOSC 6 TOSC
Edge to Timer Increment
Note: Timer1 is a Type A.
TB10 TtxH TxCK High Time Synchronous, 0.5 TCY + 20 ns Must also meet
no prescaler parameter TB15
Synchronous, 10 ns
with prescaler
TB11 TtxL TxCK Low Time Synchronous, 0.5 TCY + 20 ns Must also meet
no prescaler parameter TB15
Synchronous, 10 ns
with prescaler
TB15 TtxP TxCK Input Period Synchronous, TCY + 10 ns N = prescale
no prescaler value
Synchronous, Greater of: (1, 8, 64, 256)
with prescaler 20 ns or
(TCY + 40)/N
TB20 TCKEXTMRL Delay from External TxCK Clock 2 TOSC 6 TOSC
Edge to Timer Increment
Note: Timer2 and Timer4 are Type B.
TABLE 23-25: TYPE C TIMER (TIMER3 AND TIMER5) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 ns Must also meet
parameter TC15
TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 ns Must also meet
parameter TC15
TC15 TtxP TxCK Input Period Synchronous, TCY + 10 ns N = prescale
no prescaler value
Synchronous, Greater of: (1, 8, 64, 256)
with prescaler 20 ns or
(TCY + 40)/N
TC20 TCKEXTMRL Delay from External TxCK Clock 2 TOSC 6 TOSC
Edge to Timer Increment
Note: Timer3 and Timer5 are Type C.
ICX
IC10 IC11
IC15
OCx
(Output Compare
or PWM Mode) OC11 OC10
OC20
OCFA/OCFB
OC15
OCx
CSCK
(SCKE = 0)
CSCK
(SCKE = 1)
CS20 CS21
COFS
CS55 CS56
CS35
CS51 CS50 70
CS30 CS31
CS40 CS41
BIT_CLK
(CSCK)
CS71 CS70
CS72
SYNC
(COFS)
CS76 CS75
CS80
SDI MSb IN
(CSDI)
CS65 CS66
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SP31 SP30
SP40 SP41
SP36
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SP35
SP20 SP21
SP40 SP30,SP31
SP41
SSX
SP50 SP52
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SP72 SP73
SP35
SP30,SP31 SP51
SP50 SP52
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SP35
SP72 SP73
SP52
SP30,SP31 SP51
SDIX
MSb IN BIT14------- 1 LSb IN
SP41
SP40
SCL
IM31 IM34
IM30 IM33
SDA
Start Stop
Condition Condition
SDA
Out
SCL
IS31 IS34
IS30 IS33
SDA
Start Stop
Condition Condition
SDA
Out
CA10 CA11
CXRX Pin
(input)
CA20
Device Supply
AD01 AVDD Module VDD Supply Greater of Lesser of V
VDD - 0.3 VDD + 0.3
or 2.7 or 5.5
AD02 AVSS Module VSS Supply VSS - 0.3 VSS + 0.3 V
Reference Inputs
AD05 VREFH Reference Voltage High AVSS + 2.7 AVDD V
AD06 VREFL Reference Voltage Low AVSS AVDD - 2.7 V
AD07 VREF Absolute Reference AVSS - 0.3 AVDD + 0.3 V
Voltage
AD08 IREF Current Drain 200 300 A A/D operating
.001 3 A A/D off
Analog Input
AD10 VINH-VINL Full-Scale Input Span VREFL VREFH V See Note
AD11 VIN Absolute Input Voltage AVSS - 0.3 AVDD + 0.3 V
AD12 Leakage Current 0.001 0.610 A VINL = AVSS = VREFL =
0V, AVDD = VREFH = 5V
Source Impedance =
2.5 k
AD13 Leakage Current 0.001 0.610 A VINL = AVSS = VREFL =
0V, AVDD = VREFH = 3V
Source Impedance =
2.5 k
AD15 RSS Switch Resistance 3.2K
AD16 CSAMPLE Sample Capacitor 18 pF
AD17 RIN Recommended Impedance 2.5K
of Analog Voltage Source
DC Accuracy
AD20 Nr Resolution 12 data bits bits
AD21 INL Integral Nonlinearity 0.75 TBD LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 5V
AD21A INL Integral Nonlinearity 0.75 TBD LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 3V
AD22 DNL Differential Nonlinearity 0.5 < 1 LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 5V
AD22A DNL Differential Nonlinearity 0.5 < 1 LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 3V
AD23 GERR Gain Error 1.25 TBD LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 5V
AD23A GERR Gain Error 1.25 TBD LSb VINL = AVSS = VREFL =
0V, AVDD = VREFH = 3V
Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
AD50
ADCLK
Instruction
Execution Set SAMP Clear SAMP
SAMP
ch0_dischrg
ch0_samp
eoc
AD61
AD60
TSAMP AD55
DONE
ADIF
ADRES(0)
1 2 3 4 5 6 7 8 9
Clock Parameters
AD50 TAD A/D Clock Period 667 ns VDD = 3-5.5V (Note 1)
AD51 tRC A/D Internal RC Oscillator Period 1.2 1.5 1.8 s
Conversion Rate
AD55 tCONV Conversion Time 14 TAD ns
AD56 FCNV Throughput Rate 100 ksps VDD = VREF = 5V
AD57 TSAMP Sampling Time 1 TAD ns VDD = 3-5.5V source
resistance
RS = 0-2.5 k
Timing Parameters
AD60 tPCS Conversion Start from Sample TAD ns
Trigger
AD61 tPSS Sample Start from Setting 0.5 TAD 1.5 TAD ns
Sample (SAMP) Bit
AD62 tCSS Conversion Completion to TBD ns
Sample Start (ASAM = 1)
AD63 tDPU Time to Stabilize Analog Stage TBD s
from A/D Off to A/D On
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2: These parameters are characterized but not tested in manufacturing.
XXXXXXXXXXXXXXXXXX dsPIC30F4013
XXXXXXXXXXXXXXXXXX -30I/P
XXXXXXXXXXXXXXXXXX
YYWWNNN 0510017
XXXXXXXXXX dsPIC
XXXXXXXXXX 30F4013
XXXXXXXXXX -301/PT
YYWWNNN 0510017
XXXXXXXXXX dsPIC
XXXXXXXXXX 30F4013
XXXXXXXXXX -30I/ML
YYWWNNN 0510017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
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d s P I C 3 0 F 4 0 1 3 A T - 3 0 I / P T-ES
Custom ID (3 digits) or
Trademark Engineering Sample (ES)
Architecture
Package
P = 40-pin PDIP
Flash PT = 44-pin TQFP (10x10)
ML = 44-pin QFN (8x8)
Memory Size in Bytes S = Die (Waffle Pack)
0 = ROMless W = Die (Wafers)
1 = 1K to 6K
2 = 7K to 12K
3 = 13K to 24K
4 = 25K to 48K Temperature
5 = 49K to 96K I = Industrial -40C to +85C
6 = 97K to 192K E = Extended High Temp -40C to +125C
7 = 193K to 384K
8 = 385K to 768K
Speed
9 = 769K and Up
20 = 20 MIPS
30 = 30 MIPS
Device ID T = Tape and Reel
Example:
dsPIC30F4013AT-30I/PT = 30 MIPS, Industrial temp., TQFP package, Rev. A
10/20/04