AND GATE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity sandhuuu is

Port ( a : in std_logic;

b : in std_logic;

c : out std_logic);

end sandhuuu;

architecture Behavioral of sandhuuu is

begin

c <= a and b ;

end Behavioral;
 OR GATE
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity sandhuuu is

Port ( a : in std_logic;

b : in std_logic;

c : out std_logic);

end sandhuuu;

architecture Behavioral of sandhuuu is

begin

c <= a or b ;

end Behavioral;
 NOT GATE
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dgrfdf is
Port ( a : in std_logic;
b : out std_logic);
end dgrfdf;

architecture Behavioral of dgrfdf is

begin
b <= not a ;

end Behavioral;
 FULL ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity add is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
s : out std_logic;
bb : out std_logic);
end add;

architecture Behavioral of add is

begin
s <= a xor b xor c ;
bb <= ( a and b ) or ( b and c ) or ( c and a ) ;

end Behavioral;
 HALF ADDER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ddd is
Port ( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
end ddd;

architecture Behavioral of ddd is

begin

s <= a xor b ;
c <= a and b ;

end Behavioral;
AND GATE
OR GATE
NOT GATE
FULL ADDER
HALF ADDER