Driver design for 3kW 13.
56 MHz
multiphase resonant inverter
Nguyen Kien Trung and Kan Akatsu
Department of Electrical Engineering, Shibaura Institute of Technology, Japan.
AbstractIn half-bridge inverter topology, it is well known that
the driver circuit design at high switching frequency is always
the challenge due to the ground floating of the high-side driver
circuit. At very high switching frequency such as 13.56 MHz, the
common mode noise becomes a critical issue because it strongly
effects to the stability and the efficiency of the inverter especially
in case of the high power condition. Furthermore, in the case
of multiphase resonant inverter topology, the synchronous of the
driver pulse among phases to obtain the same class DE operation
mode in every phase is also another challenge. In this paper, the
driver circuit design for 3kW 13.56 MHz multiphase resonant
inverter with the efficiency of 96.1% is presented in detail.
Index TermsWireless Power Transfer (WPT), Multiphase
inverter, High frequency inverter, 13.56 MHz inverter.
I. I NTRODUCTION
Recently, the wireless charging systems for electric vehicle
(EV) are almost using the switching frequency around 85 kHz.
The power is up to several kW with the efficiency of over
90% [1]. However, because of the low operating frequency,
the wireless transfer distance is only around 20 cm with the
big and heavy coupling system [1]. The MHz range operating
frequency is one of the future research trends where the
transfer distance will be extended up to several meters [2].
It makes more freedom for the EV position in both of static
wireless charging and dynamic charging systems. A lot of
material will be saved and the design is more freedom when
the coupling system is much smaller and lighter. Nevertheless,
the MHz operating frequency range is still hard to apply in EV
wireless charging system because it is still difficult to make
the high power inverter with high efficiency at MHz switching
frequency.
At 13.56 MHz switching frequency, the resonant inverter
with the soft-switching technique is the key solution to obtain
high efficiency. The class E or 2 inverter is suitable because
of these inverters can achieve zero voltage switching and zero
dv/dt switching condition with the simple gate-driver circuit.
However, these types of inverters are difficult to apply at
high power output because the topology of these inverters use
only one power switch and the stress voltage on the power
switch is very high in the comparison with the input DC
voltage [3]. Furthermore, when the inverter is connected to
the coupling system with the very high Q resonant coil, the
voltage across the switching device will be very high during
the startup transient state and it also limits the output power
of these types of inverter. In our research, the class D and
DE resonant inverter with half-bride topology are used. With
half-bridge topology, the voltage across the switching device
is equal to input DC voltage and the output power of the
inverter is easily extended by using multiphase topology. In
our previous research, a 1.2 kW class D resonant inverter
with the efficiency of 93.1% was achieved by using RF silicon
MOSFET [4-5]. Then by using GaN HEMT and multiphase
topology in class DE operation mode, the output power of the
inverter have been extended up to 3 kW with the efficiency of
96.1% [6]. In these inverters, the driver circuit design is one of
the design challenges because of the floating ground with very
high dv/dt of high-side driver circuit. In this paper, the detail
design of the driver circuit for these inverters is presented.
The challenges of driver circuit design in multiphase resonant
inverter are presented in section II. Then, the design of the
driver circuit including common mode noise immunity design,
PCB design, and the synchronous driver pulse among phases
are presented in section III. Section IV shows the experiment
results. Finally, the conclusion and future work are given in
section V.
II. C LASS DE RESONANT INVERTER AND DRIVE CIRCUIT
DESIGN CHALLENGE
Fig. 1 shows the topology of multiphase resonant inverter
consisting of several half-bridge inverters in parallel. Fig. 2
shows the driver circuit for high-side of one half-bridge in
multiphase inverter. At 13.56 MHz switching frequency, the
ground of high-side driver circuit is the output voltage point
of the half-bridge where the voltage is 13.56 MHz square
waveform with very high dv/dt. As shown in Fig. 2, the
very high dv/dt across the parasitic capacitors Cstray1 and
Cstray2 generates the common mode noise current in the
high-side driver circuit as calculated by equation (1). The
common noise current effects to the driver pulse as shown in
(2) which make noise in the driver pulse. The voltage supply
for the isolation device also has noise from the common
mode noise current as shown in (3). From these noises, the
high-side driver circuit may be unstable. To keep the stability
for high-side driver circuit, the limitation of the common
mode current and its effect are the key solutions.
dv
icm1 + icm2 + icm3 = Cstray (1)
dt
vp1 = vp + icm1 Z2 icm2 Z3 (2)
vsupply = vctr icm3 Z1 icm2 Z3 (3)
where Z1 , Z2 and Z3 are the impedance of the trace lines in
the driver circuit.
 Vctr
Ld1 Ld3 Ld2N-1 Z1
+VDC
Phase 1 Vdriv Vdc
V11 V12 V1N
Phase N
VCs1 +
VGS1 L1
Cb1 Z2
Cin 1 Cbypass - Cstray1 Output
Cb2 L2
2
CbN LN
N
V21 V22 V2N
Ground of
Z3 high-side
VCs2 CO
VGS2 Output driver circuit
load
board (floating with
GND
Ld2 Ld4 Ld2N Cstray2 high dv/dt)

Fig. 1: Multiphase resonant inverter Fig. 2: Common mode noise in high-side driver circuit

ZVS turn Peak

on voltage

cap
cap ZVS turn on
MOSFET-top diode
MOSFET-top
MOSFET-bot MOSFET-bot

(a) Class DE operation mode (b) Class D operation mode

Fig. 3: High dv/dt at the ground of high-side driver circuit

In the design, there are three combination solutions to limit
the common mode current and its effect. Firstly, the dv/dt
is limited from the inverter design. Fig. 3(a) and Fig. 3(b)
show the dv/dt value in the case of class DE and class D
operation mode, respectively. In class DE operation mode as
shown in Fig. 3(a), the value of dv/dt can be estimated by
(4). Then the design of the inverter with the considering of
dv/dt is more complicate and critical in 13.56 MHz inverter
as presented in [6]. In our design, the inverter is designed in
class DE operation mode. However when the circuit parameter
change or in the transient state, the inverter may be fallen to
class D operation mode where the dv/dt is much higher than
class DE mode as shown in Fig 3(b). Therefore, the design of
the inverter should have the margin in the maximum value of
dv/dt. In this design, the value of dv/dt in class DE operation
mode is designed at 25 V/ns when the maximum value of the
isolation device is 50 V/ns.
dv/dt = Vdc /td (4)
Second, as shown in (1), the stray capacitors Cstray1 and
Cstray2 of the isolation between the driver circuit and the
power circuit also affect the value of the common mode
current. Therefore, to reduce the common noise current, these
parasitic capacitors will be minimized by the design of the
driver circuit. Finally, the effect of the common current is also
limited by using the common mode filter in the driver circuit
design. The second and third solution is explained more detail
in the section III of this paper.
At 13.56 MHz switching frequency, in multiphase resonant
inverter, to obtain the highest efficiency of the inverter, the
switching condition must be optimized in every phase. How-
ever, as shown in Fig. 1, the parasitic inductance LdN of
the connection among phases make the optimized condition
is difficult to obtained. To overcome the parasitic inductance
 Power
-Dead time adjust
Isolator source
- Pulse width adjust

Gate High
HS drive Side
27.12MHz GaN
oscillator

Flip-flop Cstray1 Output

f/2 High dv/dt
icm
-Dead time adjust
Isolation - Pulse width adjust Isolator
DC/DC
Power Low
source LS Gate Side
+5V
drive GaN

Cstray21
Cstray22 icm=icm11+icm12 icm12
icm11

Fig. 4: Structure of driver pulse generator circuit

Cstray
Primary-side Secondary - side
13.56MHz Isolation Phase
pulse source device module
Z11
Module 1

Z21 Coax cable

Z12
Module 2
Z22
Coax cable
Z1N
Module N

Isolator Drive Z2N

No copper on board Coax cable
this area
Fig. 6: Synchronous driver pulse design
Fig. 5: PCB design for drive board

effect, the module design solution has been proposed in [6].
Then the parameter of every phase is the same. Therefore,
to obtain the same class DE operation mode on every phase
of the inverter to obtain highest efficiency, the driver pulse
for every phase must be synchronized. This is another design
challenge at 13.56 MHz for driver circuit.
III. D RIVE DESIGN
A. Common mode noise immunity
To obtain high isolation common mode noise immunity,
the optical fiber links or transformer are widely used. In this
design, the proposed solution leads to more compact design by
using integrated IC ISO721M. This device can obtain 50 V/ns
for typical common mode noise immunity, maximum delay
skew of 2 ns and the isolation voltage up to 4000V RMS.
The structure of the driver pulse generator is shown in Fig.
4. The value of stray capacitor Cstray2 which is shown in Fig.
2 depends on the isolation between the ground of driver pulse
generator circuit and ground of the power circuit. Therefore,
as shown in Fig. 4, the isolation device is also used for the
low-side driver circuit to isolate grounds of them. The high
isolation DC power source is used for driver pulse generator
circuit that also reduces the stray capacitor Cstray2 .
The PCB design in driver pulse generator circuit is also
very important because that affects the value of the parasitic
capacitors Cstray1 and Cstray2 . To obtain the low value of
these parasitic capacitors, the PCB design must separate the
 50 load
RF load
Phase
module 3
Phase
module 2
Phase
module 1
Output board
Drive board
Fig. 7: Prototype of 13.56 MHz, 3 kW, 5 phases inverter
PCB area of each side where is isolated by the isolation
devices. The area between the primary-side and secondary-
side of the isolation device is designed with no copper to
obtain lowest parasitic capacitance. The PCB design around
the isolation devices is shown in Fig. 5.
B. Synchronous drive pulse
To obtain class DE operation mode for all phase in multi-
phase resonant inverter operating at 13.56 MHz, the driver
pulse for all phase must be synchronized. It becomes a
challenge in the high-side driver circuit design due to the
floating high-side driver ground with very high dv/dt. The
proposed design solution is shown in Fig. 6. The driver IC and
the cascode GaN HEMT must be placed as near as possible to
minimize the parasitic inductance of the connection between
them. Therefore, the driver ICs are directly attached on each
module. Then, in order to synchronize the driver pulses in
every phase, every module is connected with the only one
driver pulse generator board.
In the driver pulse generator board, the design of PCB is
very critical to keep the minimum impedance of the trace line
and the similarity in two sides Z1N = Z2N . In the case of
multiphase, the impedance in each loop accompany with each
module is designed to balance with the other loop. The ferrite
beat is added in every loop to fill the high frequency noise
Phase
module 4
Phase
module 5
and make the impedance more balance as shown in Fig. 6.
To connect from the driver board to the phase modules, the
coaxial cable is used. The type and the length of all cable is
the same to keep impedance balance.
IV. E XPERIMENT RESULT
Fig. 7 shows the prototype of the 13.56 MHz, 3kW, 5 phases
inverter. The inverter includes 5 phase modules which are
all driven by the drive board. The IXRFD630 RF MOSFET
drive IC from IXYS is used to drive the cascode GaN HEMT
TPH3006 in the inverter. Fig. 8(a) shows the experiment results
of the drain-source voltage and gate-source voltage of the high-
side GaN in one phase of the five phase resonant inverter. The
input DC voltage is 260 V. The rising time and falling time
of the drain-source voltage in class DE operation mode is 12
ns including the rising and falling time of the oscilloscope.
In the design, the dead time is designed at 10 ns [6]. Then
the dv/dt in this case is about 25 V/ns. It is almost the same
with the design. The driver circuit and the inverter work stably.
No noise was observed in the gate-source voltage waveform
of high-side driver circuit. The class DE operation mode was
obtained.
Fig 8(b) shows the gate-source voltages of the high-side
GaN in five phases of the inverter in experiment. They are
almost synchronous. This is very importance condition to
 VDS (100V/div) VGS (5 V/div) Gate-source voltage of
Voltage scale: 5V/div five phases is synchronous
Time scale:4ns/div

(time scale: 4ns/ div)

td=12 ns

/ 25/ Time scale: 10ns/div

(a) High-side drain-source voltage and gate-source voltage (b) High-side gate-source voltage in five phases

Fig. 8: Driver signal test of 13.56MHz 3kW five phases inverter

100
99 Switching
98 power loss VDS (100V/div)
97 0.4* Output voltage
Percentage (%)

96 (100V/div)
95
94
93
92
91
90
Cal. Exp.
Conduction and
switching power loss 0.891 3.177
(%)
Drive power loss (%) 0.475 0.715
Pout (Efficiency %) 98.61 96.1

(a). Power loss distribution in calculation and experiment (b). Drain-source voltage and output voltage waveform

Fig. 9: Output voltage and efficiency test of five phases inverter at 3kW output power

obtain the same class DE operation mode in 5 phases of the R EFERENCES

inverter to obtain the highest efficiency. Finally, the power
loss distribution and the output waveform of the inverter in
experiment are shown in Fig. 9. The inverter works stably at
3kW output power with the efficiency of 96.1%.
V. C ONCLUSION
At 13.56 MHz multiphase resonant inverter, the common
mode noise in high-side driver circuit and the synchronous
driver pulse among phases are the critical design issues which
directly affect the stability and the efficiency of the inverter.
The design of the power circuit to limit the dv/dt value, the
devices selection for driver circuit, the PCB design and the
impedance matching design is the key solutions to overcome
these challenges. In experiment results, the designed driver
circuit works stably at 13.56 MHz, the dead time can be adjust
exactly, and the driver pulse among phases are synchronized.
Finally, the inverter could obtain 3 kW output power with the
efficiency of 96.1%.
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