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fully edited. Content may change prior to final publication.
> TPEL-Reg-2012-12-1698. R1 <
H6 Transformerless Full-Bridge PV Grid-tied
Inverters
Li Zhang, Member, IEEE, Kai Sun, Member, IEEE, Yan Xing, Member, IEEE and Mu Xing
AbstractTransformerless inverters are widely used in
grid-tied photovoltaic (PV) generation systems, due to the benefits
of achieving high efficiency and low cost. Various transformerless
inverter topologies have been proposed to meet the safety
requirement of leakage currents, such as specified in the
VDE-4105 standard. In this paper, a family of H6 transformerless
inverter topologies with low leakage currents is proposed, and the
intrinsic relationship between H5 topology, HERIC topology and
proposed H6 topology has been discussed as well. One of the
proposed H6 inverter topologies is taken as an example for detail
analysis with operation modes and modulation strategy. The
power losses and power device costs are compared among the H5,
the HERIC and the proposed H6 topologies. A universal
prototype is built for these three topologies mentioned for
evaluating their performances in terms of power efficiency and
leakage currents characteristics. Experimental results show that
the proposed H6 topology and the HERIC achieve similar
performance in leakage currents, which is slightly worse than that
of the H5 topology, but it features higher efficiency than that of
H5 topology.
Index TermsGrid-tied inverter, Leakage current,
Common-mode voltage, Transformerless inverter, Photovoltaic
generation system
I. INTRODUCTION
T HE applications of distributed photovoltaic (PV)
generation systems in both commercial and residential
structures have rapidly increased during recent years. Although
the price of PV panel has been declined largely, the overall cost
of both the investment and generation of PV grid-tied system
are still too high, comparing with other renewable energy
sources. Therefore, the grid-tied inverters need to be carefully
designed for achieving the purposes of high efficiency, low
cost, small size, and low weight, especially in the low-power
single-phase systems (less than 5kW). From the safety point of
Manuscript received December 13, 2012; revised March 12; accepted April
21, 2013. This work was supported by the National Natural Science Foundation
of China under Project 51177083.
L. Zhang and K. Sun are with the State Key Lab of Power Systems,
Department of Electrical Engineering, Tsinghua University, Beijing 100084,
China (e-mail: zhanglinuaa@mail.tsinghua.edu.cn; sun-kai@mail.tsinghua.
edu.cn).
Y. Xing is with the Jiangsu Key Laboratory of Renewable Energy
Generation and Power Conversion, Nanjing University of Aeronautics and
Astronautics, Nanjing 210016, China (e-mail: xingyan@nuaa.edu.cn)
M. Xu is with the State Grid Corporation of China, Xuancheng 242000,
China (ericxu@nuaa.edu.cn).
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1
Bridge
Filters
A
U PV
L1
Co vg
PV B L2
Cdc
Measuring Point of
Cpv1 Cpv2 N iLeakage leakage current Zg
Fig. 1. Leakage current path for transformerless PV inverters.
view, most of the PV grid-tied inverters employ line-frequency
transformers to provide galvanic isolation in commercial
structures in the past. However, line-frequency transformers
are large and heavy, making the whole system bulky and hard
to install. Compared with line-frequency isolation, inverters
with high-frequency isolation transformers have lower cost,
smaller size and weight. However, the inverters with
high-frequency transformers have several power stages, which
increase the system complexity and reduce the system
efficiency [1-6]. As a result, the transformerless PV grid-tied
inverters, as shown in Fig.1, are widely installed in the
low-power distributed PV generation systems. Unfortunately,
when the transformer is removed, the common mode (CM)
leakage currents (ileakage) may appear in the system and flow
through the parasitic capacitances between the PV panels and
the ground [7, 8]. Moreover, the leakage currents lead to
serious safety and radiated interference issues [9]. Therefore,
they must be limited within a reasonable range [10].
As shown in Fig. 1, the leakage current iLeakage is flowing
through the loop consisting of the parasitic capacitances (CPV1
and CPV2), bridge, filters (L1 and L2), utility grid, and ground
impedance Zg. The leakage current path is equivalent to an LC
resonant circuit in series with the CM voltage [11], and the CM
voltage vCM is defined as
v v L L1
vCM AN BN (vAN vBN ) 2 (1)
2 2( L1 L2 )
where vAN is the voltage difference between point A and N, vBN
is the voltage difference between point B and N. L1 and L2 are
the output filter inductors.
In order to eliminate leakage currents, the CM voltage must
be kept constant or only varied at low frequency, such as
50Hz/60Hz. The conventional solution employs the half-bridge
inverter [12, 13]. The filter inductor L2 is zero in the half-bridge
inverters. Therefore, equation (1) is simplified as,
v v (v v )
vCM AN BN AN BN vBN (2)
2 2
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> TPEL-Reg-2012-12-1698. R1 < 2

The CM voltage vCM is constant due to the neutral line of the

utility grid connecting to the midpoint of the split dc-link S5 S1 S3
capacitors directly. However, a drawback of half-bridge U PV
Cdc
L1
A
inverters is that, the dc voltage utilization of half-bridge type Co vg
PV B
topologies is half of the full-bridge topologies. As a result,
either large numbers of PV panels in series are involved or a S2 S4 L2
boost dc/dc converter with extremely high voltage transfer ratio N

is required as the first power conditioning stage, which could (a)

decrease the system efficiency. S1 S3
The full-bridge inverters only need half of the input voltage U PV L1
value demanded by the half-bridge topology, and the filter Cdc A S5
Co vg
inductors L1 and L2 are usually with the same value. As a result, PV
B
equation (1) is simplified as, S6
S2 S4 L2
v v
vCM AN BN (3) N
2 (b)
Many solutions have been proposed to realize CM voltage
constant in the full-bridge transformerless inverters [14-25]. A S1 S3
L1
traditional method is to apply the full-bridge inverter with the
A
bipolar sinusoidal pulse width modulation (SPWM). The CM U PV
Cdc
B Co vg
voltage of this inverter is kept constant during all operating S6 S5
PV L2
modes. Thus, it features excellent leakage currents D1
characteristic. However, the current ripples across the filter D2
inductors and the switching losses are likely to be large. The S2 S4
full-bridge inverters with uniploar SPWM control are attractive N

due to the excellent differential mode (DM) characteristics such (c)

as smaller inductor current ripple, and higher conversion
efficiency. However, the CM voltage of conventional unipolar
SPWM full-bridge inverter varies at switching frequency,
which leads to high leakage currents [12]. Two solutions could
be applied to solve this problem. One solution is to connect the
PV negative terminal with the neutral line of the utility grid
directly, such as the Karschny inverter derived from buck-boost
converter [15], and the inverters derived from virtual dc bus
concept [16]. The CM voltage is kept constant by these
full-bridge topologies with unipolar modulation methods.
Another solution is to disconnect the DC and AC sides of the
full-bridge inverter in the freewheeling modes. Various
topologies have been developed and researched based on this
method for keeping the CM voltage constant, such as the H5
topology [17], the highly efficient and reliable inverter concept
(HERIC) topology [18], the H6-type topology [19], and the
Hybrid-bridge topology [20], etc., are shown in Fig. 2.
Fig. 2(a) shows the H5 topology. It employs an extra switch
on the DC side of inverter. As a result, the PV array is
disconnected from the utility grid when the inverter output
voltage is at zero voltage level, and the leakage current path is
cut off. The HERIC topology shown in Fig. 2(b) employs two
extra switches on the AC side of inverter, so the leakage current
path is cut off as well. However, its power device cost is higher
than that of the H5 topology. Fig. 2(c) and Fig. 2(d) show the
H6-type topology and the Hybrid-bridge topology respectively.
Comparing with a full bridge inverter, two extra switches are
employed in the DC sides of these two topologies. Furthermore,
both the H5 topology and the HERIC topology have been
compared in terms of efficiency and leakage currents
characteristic [22]. However, these topologies have never been
S1 S3 S5
U PV D1 L1
Cdc
A B Co vg
PV
D2
S2 S4 S6 L2
N
(d)
Fig. 2. Four typical topologies of transformerless full-bridge inverters. (a). H5.
(b) HEIRC. (c) H6-type. (d) Hybrid-bridge.
analyzed form the point of view of topological relationships.
In this paper, a family of novel H6 full-bridge topologies is
proposed for the transformerless PV grid-tied inverters. An
extra switch is inserted to the H5 topology for forming a new
current path and for the purpose of reducing conduction loss.
Therefore, in the active modes, the inductor current of the
proposed H6 topology flows through two switches during one
of the half line periods, and flows through three switches
during another half line period. As a result, for comparing with
the topologies presented in [17], [19] and [20], the proposed H6
topology has achieved the minimum conduction loss, and also
has featured with low leakage currents. On the other hand, the
topological relationship between H5 topology and HERIC
topology is revealed, and the methods for generating HERIC
topology from H6-type topology and from Hybrid-bridge
topology are presented respectively.
This paper is organized as follows. In Section II, the
operation modes and characteristics of the H5 topology and the
HERIC topology are presented and compared. The methods of

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> TPEL-Reg-2012-12-1698. R1 < 3

S1 S3
S5 S1 S3 U PV L1
U PV L1 Cdc S5
Cdc A A vg
PV Co
Co vg B
PV B S6
S2 S4 L2
S2 S4 L2
N
N
(a)
(a)
S1 S3
S1 S3 U PV L1
S5 Cdc
U PV L1 S5
A vg
Cdc A PV Co
B
Co vg S6
PV B L2
S2 S4
S2 S4 L2 N
N (b)
(b)
S1 S3
U PV L1
S5 S1 S3 Cdc S5
U PV L1 A vg
PV Co
Cdc A
B
S6
Co vg L2
PV B S2 S4
N
S2 S4 L2
N (c)
(c) S1 S3
U PV L1
Cdc S5
S5 S1 S3 A
Co vg
U PV L1 PV B
Cdc A
S6
Co vg S2 S4 L2
PV B
N
S2 S4 L2 (d)
N
Fig. 4. Operation modes of HERIC topology. (a) Active mode in the positive
(d)
half period. (b) Freewheeling mode in the positive half period. (c) Active mode
Fig. 3. Operation modes of H5 topology. (a) Active mode in the positive half in the negative half period. (d) Freewheeling mode in the negative half period.
period. (b) Freewheeling mode in the positive half period. (c) Active mode in
the negative half period. (d) Freewheeling mode in the negative half period. flowing through two switches.
There are four operation modes in each period of the utility
generating HERIC topology from the H6-type topology or grid of the HEIRC topology, as shown in Fig. 4. It can be seen
from the Hybrid-bridge topology are given. A family of H6 that the inductor current of HERIC topology is always flowing
topologies is proposed, and the topological relationship through two switches in the active modes. In the freewheeling
between H5 topology and HERIC topology is analyzed. In modes, the inductor current of HERIC topology is flowing
Section III, one of the proposed H6 topologies is taken as an through two switches.
example for analysis in detail with operational principle and Therefore, although the H5 topology features less power
modulation strategy. The comparisons between H5, HERIC devices than the HERIC topology, its conduction loss is higher
and the proposed H6 topology are given in terms of power loss than that of the HERIC topology. Moreover, the conduction
and device cost. Experimental results are presented in Section losses of the H6-type topology and the Hybrid-bridge topology
IV, and Section V concludes the paper. are also higher than that of the HERIC topology due to extra
switches in the DC side. As a result, the conduction losses of
II. COMPARATIVE ANALYSIS ON EXISTING TOPOLOGIES
H5 topology, H6-type topology and Hybrid-bridge topology
A. Operation modes of H5 and HERIC should be reduced for the harvest of higher efficiency.
The operation modes of H5 topology and HERIC topology B. Topology Relationship
are taken as examples for analysis. There are four operation The H6-type topology is taken as an example to analysis first.
modes in each period of the utility grid of the H5 topology, as From Fig. 2(c), it can be seen that there are two switches
shown in Fig. 3. It can be seen that in the active modes, the between the terminal (A) and the negative terminal of the PV
inductor current of H5 topology is always flowing through array, and there are another two switches between the terminal
three switches due to its extra switch S5 in DC side. In the (B) and the negative terminal of the PV array. Therefore, the
freewheeling modes, the inductor current of H5 topology is inductor current is controlled to flow through three switches in

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> TPEL-Reg-2012-12-1698. R1 < 4

Bi-direcitonal Switch
S1 S3 S1 S3
L1
U PV S6 L1
Cdc D2
A vg A
U PV B Co vg
Cdc PV Co
S6 S5 B
PV D1 L2 D1 S5
S2 S4 L2
D2 N
S2 S4
Fig. 6. Another circuit structure of HERIC topology.
N
(a)

S1 S3 S1 S6
L1 S3
U PV D1 L1
A Cdc
U PV B Co vg A B vg
Cdc PV Co
S6 S5
L2 D2
PV D1 S2 S4 S5 L2
N
D2
S2 S4
N Fig. 7. Another circuit structure of HERIC topology derived from
(b) Hybrid-bridge topology.

Fig. 5. Modified H6-type inverter topologies. (a) Circuit Structure A. (b) Circuit S1 S3
Structure B. S5
U PV L1
A

the active modes of H6-type topology. In order to reduce the Co vg

PV C B
dc
conduction loss, the collector of switch S2 is disconnected from L2
S2 S4
the anode of diode D1, and then it is connected to the terminal N
(A), as shown in Fig. 5(a). As a result, the inductor current (a)
flows through S2 and S3 instead of S2, S3 and S6 in the active
mode during the negative half cycle of the grid voltage. The DC S5 S1 S3
U PV L1
and AC sides of this topology are still disconnected in the A

freewheeling modes. The same means are applied to another PV C B

leg, where the switch S4 is disconnected from the diode D2 and
then connected to the terminal (B), as shown in Fig. 5(b).
Hence, a circuit structure of HERIC topology is derived by
the methods described in Fig. 5. The topology is shown in Fig.
6. Compared with the HERIC topology shown in Fig. 2(c), the
form of the bi-directional switch in AC side is changed.
Similarly, another circuit structure of HERIC topology can
be derived from the Hybrid-bridge shown in Fig. 2(d). The
switches S3 and S4 are disconnected from D1 and D2
respectively, and then connect both of them to the terminal (B),
as shown in Fig. 7. However, there is only one extra switch in
DC side of the H5 topology. When the emitter of S5 is
disconnected from S1 and connected to the terminal (A), the
inductor current flows through S4 and S5 instead of S1, S4 and S5
in the active mode of positive half cycle of the grid voltage.
Hence, the conduction loss is reduced. Unfortunately, in the
active mode of negative half cycle of the grid voltage, there is
no inductor current path, as shown in Fig. 8(a). Therefore, an
extra switch S6 is introduced into the topology between the
positive terminal of the PV array and the terminal (B) to form a
new current path. As a result, the circuit structure of the HERIC
topology shown in Fig .2(b) is derived from the H5 topology, as
shown in Fig. 8(b).
Therefore, we can derive various HERIC topologies based
on the existing topologies, such as the H6-type topology,
Hybrid- bridge topology and H5 topology, for the purpose of
Co vg
dc
L2
S2 S4
N
S6
(b)
Fig. 8. Relationship between HERIC topology and H5 topology. (a) Modified
H5 topology. (b) HERIC topology derived from H5 topology.
reducing conduction loss.
III. ANALYSIS ON THE H6 TOPOLOGY AND COMPARISON WITH
OTHER TOPOLOGIES
A. Novel H6 Topology
From the analysis above, an extra switch S6 is introduced
into the H5 inverter topology between the positive terminal of
the PV array and the terminal (B) to form a new current path.
As a result, a novel H6 transformerless full-bridge inverter
topology is derived, as shown in Fig. 9(a).
Similarly, the extra switch S6 can be introduced into the H5
inverter topology between the positive terminal of the PV array
and the terminal (A) to form a new current path as well, as
shown in Fig. 9(b). Therefore, a new circuit structure of novel
H6 inverter is presented. As a result, the conduction loss of the
proposed H6 topologies is higher than HERIC topology and
less than H5 topology.

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> TPEL-Reg-2012-12-1698. R1 < 5

vg
S5 S1 S3 iref t
U PV L1
A
Co vg vgs1
PV B
Cdc t
S6 S2 S4 L2
vgs3
N t
(a) vgs4 , vgs5
t
S5 S1 S3 vgs2 , vgs6
U PV L1 t
A
Co vg Fig. 10. Schematic of gate drive signals with unity power factor.
PV B
Cdc
S6 S S4 L2
2
N
S5 S1 S3
(b) U PV L1
A
Fig. 9. A family of proposed H6-type inverter topologies. (a). Circuit structure Co vg
A. (b) Circuit structure B. PV C B
dc
L2
S6 S2 S4
B. Operation Mode Analysis N

The circuit structure of proposed novel H6 inverter (a)

topologies shown in Fig. 9(a) is taken as an example to analysis.
PV grid-tied systems usually operate with unity power factor. S5 S1 S3
U PV L1
The waveforms of the gate drive signals for the proposed novel A
H6 topology are shown in Fig. 10, where vg is the voltage of PV C B
Co vg
utility grid. iref is the inductor current reference. vgs1 to vgs6 dc
L2
represent the gate drive signals of switches S1 to S6, S6 S2 S4
N
respectively.
(b)
There are four operation modes in each period of the utility
grid, as shown in Fig. 11, where vAN represents the voltage
S1 S3
between terminal (A) and terminal (N), and vBN represents the S5
L1
U PV
voltage between terminal (B) and terminal (N). vAB is the A
differential-mode voltage of the topology, vAB = vAN-vBN. The Co vg
PV C B
dc
CM voltage vCM = 0.5(vAN+vBN). L2
S6 S2 S4
a) Mode I is the active mode in the positive half period of the N
utility grid voltage, as shown in Fig. 11(a). S1, S4, and S5 are (c)
turned ON, and the other switches are turned OFF. The
inductor current is flowing through S1, S4, and S5. vAN = UPV, S1 S3
S5
vBN = 0, thus, vAB = UPV, and the CM voltage vCM = (vAN+vBN)/2 U PV L1
= 0.5UPV. A
Co vg
b) Mode II is the freewheeling mode in the positive half PV
Cdc B

period of the utility grid voltage, as shown in Fig. 11(b). S1 is L2

turned ON, the other switches are turned OFF. The inductor
current is flowing through S1 and the anti-paralleled diode of S3.
vAN = vBN 0.5UPV, thus, vAB = 0, and the CM voltage vCM =
(vAN+vBN)/2 0.5UPV.
(c) Mode III is the active mode in the negative half period of
the utility grid voltage, as shown in Fig. 11(c). S2, S3, and S6 are
turned ON, the other switches are turned OFF. The inductor
current is flowing through S2 and S6. Although S3 is turned ON,
there is no current flowing through it, and the switch S3 has no
conduction loss in this mode. Nevertheless, in the H5 topology,
the inductor current flows through S2, S3, and S5. Therefore, the
conduction loss of proposed topology is less than that of H5
topology. In this mode, vAN = 0, vBN = UPV, thus, vAB = -UPV, and
the CM voltage vCM = (vAN+vBN)/2 = 0.5UPV.
S6 S2 S4
N
(d)
Fig. 11. Equivalent circuits of operation modes (a) Active mode in the positive
half period. (b) Freewheeling mode in the positive half period. (c) Active mode
in the negative half period. (d) Freewheeling mode in the negative half period.
(d) Mode IV is the freewheeling mode in the negative half
period of the utility grid voltage, as shown in Fig. 11(d). S3 is
turned ON, and the other switches are turned OFF. The
inductor current is flowing through S3 and the anti-paralleled
diode of S1. vAN = vBN 0.5UPV, thus, vAB = 0, and the CM
voltage vCM = (vAN+vBN)/2 0.5UPV.
Based on the above analysis, the PV array can be
disconnected from the utility grid when the output voltage of
the proposed H6 inverter is at zero voltage level, and the leak-

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> TPEL-Reg-2012-12-1698. R1 < 6

vg TABLE I. CALCULATED POWER LOSSES ON DEVICE

t S1 S2 S3 S4 S5 S6 Total
iref (W) (W) (W) (W) (W) (W) losses(W)
H5 4.911 4.472 4.911 4.472 8.944 N.C. 27.71
vgs1 HEIRC 4.472 4.472 4.472 4.472 2.571 2.571 23.03
t H6 4.911 4.472 2.571 4.472 4.472 4.472 25.37
vgs3 Note: UPV = 380V
t
vgs4 , vgs5 TABLE II. COMPARISON OF OPERATING DEVICES IN THESE THREE
t TOPOLOGIES
H5 HERIC H6
vgs2 , vgs6
t Total device number 5 6 6
Isolated power supply for devices 4 3 4
Fig. 12. Schematic of gate drive signals with power factor other than unity. Switching device number 2 2 2
Conducting vg>0 3 2 3
age current path is cut off. The CM voltage of the proposed device number vg<0 3 2 2
topology in each operation mode is equals to 0.5UPV, and it Diodes number with freewheeling 2 2 2
Diodes number with reverse recovery 1 1 1
results in low leakage current characteristic of the proposed H6
Gate drive number 2 2 2
topologies.
The proposed H6 topology with unipolar SPWM method not
only can achieve unity power factor, but also has the ability to S1 S2 S3 S4 S5 S6
30
control the phase shifts between voltage and current waveforms.
The modulation strategy is shown in Fig. 12. The drive signal is Device Losses (W) 25
20
in phase with the grid-tied current. Therefore, it has the
15
capability of injecting or absorbing reactive power, which
10
meets the demand for VDE-4105 standard.
5
C. Comparisons of H5, HERIC and the Proposed H6 0
Topologies H5 Heric H6

The power losses of power switches of the proposed H6

topology (Fig. 9(a)), H5 topology (Fig. 2(a)) and HERIC Fig. 13. Device losses distribution for these three topologies with 1 kW power
rating.
topology (Fig. 2(b)), are calculated with the same parameters as
given in Table III, and are illustrated in Table I and Fig. 13. The TABLE III. PARAMETERS OF THE EXPERIMENTAL PROTOTYPE
calculation methods and theories are studied and verified in Parameter Value
detail in literatures [22, 26-29], but not the contribution of this Rate power 1000 W
paper. On the other hand, the inductor losses in the three Input voltage 380~700 V
topologies are the same due to the same vAB modulation. Grid voltage/frequency 230V/50Hz
Switching frequency 20kHz
Therefore, the inductor losses of these three topologies are Input Capacitance Cdc 940uF
regardless. The comparison of operating devices in these three Filter inductor L1, L2 3mH
topologies are summarized in Table II. The main power losses Filter Capacitor Co 0.47uF
of switches in each operation mode include the turn on/off loss, Power Devices S1~S6 (IGBT) IRG4PH40U
PV parasitic capacitances CPV1, CPV2 0.1uF
conduction loss, diode freewheeling loss, diode reverse
recovery loss, and gate loss.
From Table I and Table II, it can be seen that the H5
topology only has five power devices. Thus, it has the lowest
device cost. The device cost of HERIC and H6 is the same. The
switching loss, diode freewheeling loss, diode reverse recovery
loss, and gate drive loss of these three topologies are the same.
However, H5 topology has the highest conduction loss, and the
conduction loss of the proposed H6 is higher than that of the
HERIC topology. From Fig. 13, it can be seen that HERIC
topology has the best thermal stress distribution, while the H5
topology is the worst. The power loss of HERIC topology is the
lowest. Fig. 14. Picture of the universal prototype

IV. EXPERIMENTAL RESULTS verify the operation principle and compare their performances.
A universal prototype of H5 (Fig. 2(a)), HERIC (Fig. 2(b)), The specifications of these three inverter topologies are listed
and novel H6 (Fig. 9(a)) topologies has been built up in order to in Table III. The control circuit is implemented based on a DSP

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> TPEL-Reg-2012-12-1698. R1 < 7

vAN , vBN (200V / div) vCM (500V / div)

vAN , vBN (200V / div) vCM (500V / div)

vg (400V / div) ig (10A / div) vg vg

vg (400V / div) ig (10A / div)

ig
ig

vAN 2 vCM vAN

vBN 2 vCM vBN

t (4ms / div) t (4ms / div)

(a) (a)

vg vg

ig (5A / div)
ig (5A / div)

iLeakage (10mA / div)

iLeakage (10mA / div)

ig ig

iLeakage

vg (200V / div)
vg (200V / div)

iLeakage

6mA 9mA

t (4ms / div
5kHz / div) t (4ms / div
5kHz / div)
(b) (b)

Fig. 15. CM voltage and leakage current in H5 topology. (a) CM voltage. (b) Fig. 17. CM voltage and leakage current in H6 topology. (a) CM voltage. (b)
Leakage current. Leakage current.
vAN , vBN (200V / div) vCM (500V / div)

vg vg
ig (5A / div)
vg (400V / div) ig (10A / div)

ig
vdS5 , vdS6 (200V / div)

ig

2 vCM vAN vds5

vg (200V / div)

vBN

vds6

t (4ms / div) t (4ms / div)

(a) (a)

vg
ig (5A / div)
ig (5A / div)

vg
vdS5 , vdS6 (200V / div)
iLeakage (10mA / div)

ig
ig
vg (200V / div)

vds5
vg (200V / div)

iLeakage

9mA vds6

t (4ms / div
5kHz / div) t (20us / div)
(b) (b)

Fig. 16. CM voltage and leakage current in HERIC topology. (a) CM voltage. (b) Fig. 18. Drain-source voltages in H6 topology. (a) Voltage stress on S5 and S6.
Leakage current. (b) Detailed waveforms.

chip TMS320F2808. The measure point of leakage currents is
shown in Fig. 1. Because Zg is very small, it is not being
considered. The picture for the universal prototype is depicted
in Fig. 14. The YOKOGAWA WT1800 precision power
analyzer was utilized as the measurement instrument to mea-
sure the efficiency of these three different topologies.
The CM voltage and the leakage current waveforms of these
three topologies in unified experimental conditions are shown
in Fig. 15-17, respectively, where vg and ig are the grid voltage
and grid-tied current, respectively. vAN and vBN are the voltages

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 This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
ig (5A / div)
vAB (200V / div)
vg (200V / div)
vAB
t (4ms / div)
Fig. 19. Differential-mode characteristic of H6 topology.
98%
97%
96%
Efficiency
95%
94%
93%
92%
0 200 400
Grid-tied power(W)
Fig. 20. Efficiency comparison of H5, HERIC and H6 topologies.
between the midpoint A and B to terminal N respectively. vCM
is the CM voltage, which equals to 0.5(vAN+vBN). iLeakage
represents the leakage current.
The leakage current measured for the H5, HERIC and H6
inverters at the switching frequency are 6mA (Fig. 15(b)), 9mA
(Fig. 16(b)), and 9mA (Fig. 17(b)) respectively. The FFT
results show that the leakage current of H5 topology is the
lowest, and the leakage current of HERIC topology and H6
topology is almost the same.
The drain-source voltage waveforms of switches in the novel
H6 topology are shown in Fig. 18, where vds5 and vds6 are
drain-source voltages of S5 and S6, respectively.
From Fig. 18(b), it can be seen that in the negative half
period of the utility grid voltage, the voltage potential of the
positive terminal of the PV array is equal to that of the terminal
(B), so the drain-source voltage of switch S5 is zero. Thus, the
switch S5only has switching loss in the positive half period of
the utility grid, and the switch S6 only has switching loss in the
negative half period of the utility grid. As a result, the switching
loss of H5 topology and the proposed H6 topology is the same.
The experimental results agree closely with the results from
theoretical analysis. Due to the freewheeling path disconnected
from the PV array in the freewheeling modes, the ringing of the
voltage envelopes of S5 and S6 depends on the parasitic
parameters of the leakage current path and the utility grid
voltage amplitude.
Fig. 19 shows the differential-mode characteristic of the
proposed H6 topology, where vAB is the differential-mode
voltage. It can be seen that the output voltage vAB has three
levels as UPV, 0, and UPV, which indicates that the proposed
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> TPEL-Reg-2012-12-1698. R1 < 8
H6 topology employs unipolar SPWM as modulation strategy,
vg
and the differential-mode characteristic is excellent.
ig
Fig. 20 is the conversion efficiency comparison of H5,
HERIC and H6 topologies under the same condition. It is
obvious that the efficiency of the HERIC is the highest and that
the efficiency of the proposed H6 topology takes the second
place. The experimental results are in agreement with the
power losses analysis in Section III (B). The European
efficiencies of H5, HERIC, and H6 are 96.78%, 97%, and
97.09%, respectively.
In summary, the H5 topology has the best leakage current
characteristic, but its efficiency is the lowest. The HERIC
topology has the highest efficiency, but the leakage current
characteristic is worse than that of H5 topology. The leakage
current characteristic of proposed H6 topology is almost the
same as that of HERIC topology. The efficiency of proposed
H6 topology is a little less than the HERIC topology, but it is
H5
Heric higher than H5 topology.
H6
V. CONCLUSION
600 800 1000
In this paper, from the topological relationship point of view,
the intrinsic relationship between H5 topology and HERIC
topology is revealed. The HERIC topology can be derived from
H5, H6-type, and Hybrid Bridge topologies by the idea of
reducing conduction loss. Moreover, based on the H5 topology,
a new current path is formed by inserting a power device
between the terminals of PV array and the midpoint of one of
bridge legs. As a result, a family of single-phase
transformerless full-bridge H6 inverter topologies with low
leakage currents is derived. The proposed H6 topologies have
the following advantages and evaluated by experimental results.
1) The conversion efficiency of the novel H6 topology is better
than that of the H5 topology, and its thermal stress distribution
is better than that of the H5 topology. 2) The leakage current is
almost the same as HERIC topology, and meets the safety
standard. 3) The excellent DM performance is achieved like the
isolated full-bridge inverter with uniploar SPWM. Therefore,
the proposed H6 topologies are good solutions for the
single-phase transformerless PV grid-tied inverters.
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Li Zhang (S11-M13) was born in Jiangsu
Province, China, in 1985. He received the B.S. and
Ph.D. degree in electrical engineering from
Nanjing University of Aeronautics and
Astronautics (NUAA), Nanjing, China, in 2007,
and 2012, respectively. He is currently a
Postdoctoral Research Fellow with the Department
of Electrical Engineering, Tsinghua University.
His main research interests include topology,
control of dc-ac converter and distributed
generation technology.
Kai Sun (M12) received the B.E., M.E., and Ph.D.
degrees in electrical engineering all from Tsinghua
University, Beijing, China, in 2000, 2002, and
2006, respectively. In 2006, he joined the faculty of
Electrical Engineering, Tsinghua University, and is
currently an Associate Professor. From Sep. 2009
to Aug. 2010 he was a Visiting Scholar of
Electrical Engineering at Institute of Energy
Technology, Aalborg University, Denmark.
His research interests are power converters for
renewable generation systems, application
technologies for power semiconductor devices, and
high performance ac motor drives.
Yan Xing (M03) was born in Shandong Province,
China, in 1964. She received the B.S. and M.S.
degrees in automation and electrical engineering
from Tsinghua University, Beijing, China, in 1985
and 1988, respectively, and the Ph.D. degree in
electrical engineering from Nanjing University of
Aeronautics and Astronautics (NUAA), Nanjing,
China, in 2000.
Since 1988, she has been with the Faculty of
Electrical Engineering, NUAA, and is currently a
professor with College of Automation Engineering,
NUAA. She has authored more than 100 technical
papers published in journals and conference proceedings and has also published
three books. Her research interests include topology and control for dc-dc and
dc-ac converters.
Dr. Xing is an Associate Editor for the IEEE TRANSACTIONS ON POWER
ELECTRONICS and JOURNAL OF POWER ELECTRONICS. She is a member of
IEEE IES Renewable Energy Systems Technical Committee.
Ming Xu was born in Anhui Province, China, in
1987. He received the B.S. degree in
Microelectronics from Northwestern Polytechnical
University (NWPU), Xian, China, in 2010, and the
M.S. degrees in electrical engineering from
Nanjing University of Aeronautics and
Astronautics (NUAA), Nanjing, China, in 2013.
He is currently working at State Grid
Corporation of China, Anhui, China. He research
interest is power generation of PV system.