Leakage Current Suppression for PV Cascaded

Multilevel Inverter Using GaN Devices

Yan Zhou and Hui Li

Department of Electrical and Computer Engineering
Florida State University
Tallahassee, FL, USA
hli@caps.fsu.edu

AbstractThis paper emphasizes on the leakage current
suppression of a PV cascaded multilevel quasi-Z-source
inverters (qZSIs) using GaN devices. This new type of PV
inverters is capable of achieving high efficiency and high
switching frequency. However, the leakage current issue
remains a challenging that needs to be dealt with. In this
paper, the leakage current paths in PV cascaded inverter are
firstly analyzed. Based on that, a filter-based leakage current
suppression method is proposed for the PV cascaded inverter
operated at high switching frequency. The simplified leakage
current analytical model is derived to study the suppression
mechanism and design the suppression filters. The
performance of the method is validated with both simulation
and experimental results.
I. INTRODUCTION
To maximize the energy harvest from the solar panels,
the cascaded multilevel inverter topology has been
considered in PV applications for decades [1], [2]. This
topology features several advantages including independent
maximum power point tracking of each dc input, lower cost
and higher inverter efficiency. To cope with the PV wide-
range input voltage, the authors in [3] presented a new
topology to use the qZSI in the cascaded structure where a
single-phase PV module-integrated converter (MIC) was
realized based on 4 cascaded qZSIs. In order to decrease the
size of the quasi-Z-source network and output line filter, the
switching frequency of each qZSI module was raised to
100kHz. The GaN devices were therefore used to achieve
high inverter efficiency at high switching frequency. In the
final design, each 250W qZSI module can reach 98.06%
peak efficiency.
However, the leakage current resulted from the stray
capacitance between the PV panels and the earth remains a
challenging issue in PV systems based on cascaded
multilevel inverter. The problem is more complicated than
the case in single transformerless inverter. There are very
few papers discussing about the leakage current in the PV
cascaded inverter.
This paper firstly identifies the leakage current paths in
PV cascaded inverter. The differences between the
transformerless cascaded inverter and string inverter
concerning the leakage current behaviors are also discussed.
Then a leakage current suppression method is presented to
solve the leakage current issue in the PV cascaded inverter
operated at high switching frequency. The simplified leakage
current analytical model for the PV system is developed to
demonstrate the principle and introduce the filter design
criteria. Finally, the effectiveness of the proposed
suppression approach is verified by simulation and
experimental results.
II. LEAKAGE CURRENT ISSUE IN PV CASCADED
MULTILEVEL INVERTER
The analysis starts with the inverter consisted of
cascaded H-bridges. It will be illustrated later that the
obtained conclusions can also be applied for the cascaded
qZSIs. Fig. 1(a) shows a generic diagram of a PV cascaded
inverter where the parasitic capacitors are added to study the
leakage current issue. C pvi , i = 1, 2, ... , n represent the stray
capacitances between the PV panels and the earth, which
vary depending on the panel structure and weather-related
factors. Two same inductors L are symmetrically allocated
at the output stage as the line filter. By modeling each
inverter phase leg as a voltage source with respect to the
negative terminal of its dc bus, the equivalent circuit of Fig.
1(a) is obtained in Fig. 1(b). The phase-leg voltage sources
are named as via and vib , i = 1, 2, ... , n . There are basically
two kinds of leakage current loops. The first kind of loop,
denoted as module-line leakage current loop, is formed by
the PV panel ground, stray capacitance, inverter-bridge, line
inductor and grid ground. The other loop, denoted as inter-
module leakage current loop, is formed among the inverter

This work was supported by National Science Foundation under

Award Number ECCS-1125658.

978-1-4799-0336-8/13/$31.00 2013 IEEE 1304

bridges. It is a capacitive coupling path with negligible
inductance so the high-frequency PWM voltages would
generate pulsewise leakage current in the loop. Compared
with the transformerless string inverter, the inter-module
leakage current loop is a unique loop exists in the PV
cascaded inverter. And it cannot be eliminated even if there
is a transformer at the total output of the cascaded inverter.
Similar capacitive coupling loop is also mentioned in [4]
where the cascaded multilevel inverter is applied for a

Fig. 2 System equivalent circuit by replacing the phase-leg voltages with DM

and CM voltage sources.

magnetic imaging system. The stray capacitors exist between

the Si and the base plate of the semiconductor devices.
However, the main concern of that paper is the MHz-
frequency voltage ringing across the inverter switches
instead of the ground leakage current.
For transformerless string inverter, the leakage current is
(a) mainly determined by the inverter common-mode (CM)
output [5], [6]. Several modified inverter topologies and
modulation strategies are proposed to maintain the CM
output to be constant to solve the leakage current issue [5]-
[7]. In cascaded inverter, we can define v DMi = via vib and
v CMi = (v ia + v ib ) 2 as the differential-mode (DM) and CM
outputs of the ith module respectively. The system
equivalent circuit can be redrawn in Fig. 2 by replacing via
and vib with v DMi and vCMi . Due to the extra inter-module
circulating loops, the leakage currents are no longer
determined only by the CM outputs from the inverter
modules. Instead, the DM outputs also contribute. Therefore,
the aforementioned modulation or topology based
suppression solutions for transformerless string inverters
cannot be directly applied in PV cascaded inverter to solve
the leakage current issue.

III. PROPOSED LEAKAGE CURRENT SUPPRESSION

TECHNIQUE
A. Leakage Current Suppression Solution
The PV cascaded inverter with the proposed leakage
(b) current suppression is provided in Fig. 3(a). Compared with
Fig. 1 Basic PV cascaded multilevel inverter: (a) circuit diagram and (b)
equivalent circuit.
the basic structure shown in Fig. 1(a), dc-side CM chokes

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Lcm _ dc , CM capacitors Ccm , and ac-side CM chokes Lcm _ ac
are added in each inverter module. The voltage across C pvi
and the current through C pvi are denoted as vcpvi and ileak _ Hi ,
i = 1, 2, ... , n , respectively. The leakage current flowing into
the grid ground is labeled as ileak _ g . The equivalent circuit of
leakage current issue. It is also noticed that the Lcm _ ac and
Lcm _ dc can be merged to the same position in the equivalent
circuit, which implies that they would have the same
contribution on leakage current suppression. Lcm _ ac and
Lcm _ dc are both used in the circuit is because they can

the system is given in Fig. 3(b) where the leakage inductance
of the CM chokes is ignored due to its minor impact on the
respectively help mitigate the ac-side and dc-side EMI CM
noises due to their same position with the ac and dc side EMI
filters. Therefore, the design effort for the ac and dc side
EMI filters can be lessened, and this could compensate the
cost of Lcm _ ac and Lcm _ dc to some extent. Because this paper
is emphasized on the leakage issue, Lcm _ ac and Lcm _ dc will
be designed as one choke Lcm _ dc + Lcm _ ac . The optimal
distribution of Lcm _ ac and Lcm _ dc should further consider the
EMI problem, because the requirements for the ac and dc
side EMI filters are different.

B. The filter design criteria

According to the DIN VDE 0126-1-1 standard [8], in
case that the leakage current is greater than 300mA or the
effective value of the suddenly occurring residual current
exceeds 30mA, the residual current protection device needs
to be triggered. To better understand the suppression
mechanism and introduce the filter design criteria, the
analytical expression of the leakage currents is derived based
on the equivalent model shown in Fig. 3(b). The xth inverter
module is selected arbitrarily for the analysis. According to
the superposition theory, the branch current iZx through the
inductance Lcm _ dc + Lcm _ ac of the xth inverter module, which
(a) is labeled in Fig. 3(b), can be first calculated as in (1).

v1a + v nb
i Zx =
Z L + (Z1 // ... // Z n ) // Z L
(Z1 // ... // Z x1 // Z x+1 // ... // Z n ) // Z L
Z x + (Z1 // ... // Z x 1 // Z x +1 // ... // Z n ) // Z L
via v(i 1)b

(Z1 // ... // Z i 1 ) // Z L + (Z i // ... // Z n ) // Z L
x
+ (Z // ... // Z // Z // ... // Z ) // Z
i x 1 x +1 n L

(1)
i=2
Z x + (Z i // ... // Z x 1 // Z x +1 // ... // Z n ) // Z L
vib v (i +1)a

n 1
( ) + ( )

Z
i +1 // ... // Z n // Z L Z 1 // ... // Z i // Z L
+
(Z // ... // Z // Z // ... // Z ) // Z
1 x 1 x +1 i L
i= x
Z x + (Z1 // ... // Z x 1 // Z x +1 // ... // Z i ) // Z L

where Z i = j (Lcm _ dc + Lcm _ ac ) +

1
, i = 1, 2, ... , n
(
j C pvi + 2Ccm )
and Z L = jL . via and vib contain dc components,
fundamental-frequency components and baseband
harmonics, carrier harmonics and its sideband harmonics [9].
(b)
Fig. 3 The proposed leakage current suppression solution: (a) circuit The fundamental-frequency leakage current, of which
diagram and (b) equivalent circuit. amplitude is relatively small, can be simply estimated by
shorting the inductors in the circuit due to their low

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impedances around the fundamental frequency. At the
frequencies of the carrier harmonics, Z L is usually much
smaller than the impedance of the designed Zi , so the values
of the terms containing Z L in (1) should be close to the
value of Z L . As a result, eq. (1) can be simplified as in (2).
x 1 n
(via vib ) + (vib via ) + (vxa + vxb )
i =1 i = x +1
i Zx
2(Z x + Z L )
The simplified model implies an equivalent circuit shown
in Fig. 4, which is composed of a voltage source connected
with a LC branch in series. The voltage source is related to
the phase leg voltages of all cascaded inverter modules. The
LC circuit is formed by Lcm _ dc + Lcm _ ac + L and C pvx + 2Ccm .
ileak _ Hx can be obtained by (3).
C pvx
ileak _ Hx = iZx
C pvx + 2Ccm
According to the simplified model, we can design the
filters that most high-frequency harmonic voltages are
dropped across the inductance, in which case the high-
frequency harmonics across C pvx are lessened. In order to
fulfill the requirement, the resonant frequency of the formed
LC circuit needs to be designed lower than the frequencies of
the carrier harmonics, specifically the device switching
frequency. The final parameters of the filters can be specified
according to (2) and (3), providing that via and vib (
i = 1, 2, ... , n ) are known.
Since the value of C pvx highly depends on the weather
conditions, Ccm is added in the circuit in case that C pvx gets
too small. However, the value of Ccm is usually limited by
safety requirements [6], [10], so the resonant frequency of
the formed LC filter cannot be designed very low.
Otherwise, large CM inductors are needed. Therefore, the
proposed solution is more suitable for the cascaded inverter
operated at high switching frequency. The applicability of
this solution at pre-selected switching frequency depends on
the constraint on the filter size and cost.
Fig. 4 Simplified leakage current analytical model for the system with
leakage current suppression method 1.
(2)
Fig. 5. System diagram of a PV system composed of four cascaded qZSIs
(3) with leakage current suppression solution.
IV. APPLICATION IN THE PV CASCADED MULTILEVEL
QUASI-Z-SOURCE INVERTERS
The proposed leakage current suppression method is
applied in a single-phase PV MIC based on cascaded qZSIs
[3]. As shown in Fig. 5, the PV system is composed of 4
cascaded modules, where each module is rated at 250W with
25~50-V input voltage range. Because of the cascaded
structure, the 100V low-voltage GaN FETs from EPC can be
used to improve system efficiency at high switching
frequency [11]. The sawtooth-carrier based PWM
modulation strategy is used for each module and the carrier
waveforms are phase shifted to minimize the total output
harmonics. The quasi-Z-source network is formed by
L1 = 39H , L2 = 39H , C1 = 8.8mF , C2 = 198F and D1 .
Resistive load is used in the study instead of the utility grid
as in [12]. This load resistance Rload = 36 has minor
contribution to the total impedance of the leakage current
loops at the switching frequency. The inverter total output
voltage is 120Vrms and the line inductor is L = 20H .
In the qZSI, although the voltage across D1 is high
frequency PWM voltage under boost operation mode, it does
not contribute to the ground leakage current, because the
L2 C2 and L1 C1 Cin loops can provide low-impedance
paths for the high-frequency noises. Therefore, the
conclusions derived for the cascaded H-bridges can also be
applied for the cascaded qZSIs.
A. Filter Design
The suppression CM filters are designed by calculating
the leakage currents based on (2) and (3). The calculated
results of ileak _ H 1 and ileak _ g with different values of
Lcm _ dc + Lcm _ ac and parasitic capacitors are shown in Fig. 6,
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 (a)

(a)

(b)
Fig. 6 Design results for the PV system with leakage current suppression
solution 1: (a) ileak _ H 1 and (b) ileak _ g .

where Ccm is selected as 2.2nF. The fundamental-frequency

leakage currents are included in the calculated results. It is
seen that the RMS value of ileak _ g slightly decreases with
the increased parasitic capacitance. This is because the
impedance of the LC circuit in Fig. 4 is increased at the
frequencies of the carrier harmonics. The RMS value of
ileak _ H 1 increases with the increased parasitic capacitance
when C pvx Ccm , and it becomes almost constant when (b)
C pvx >> Ccm . In order to limit the leakage currents below the Fig. 7 Simulation waveforms of the PV cascaded qZSIs: (a) without leakage
standard requirement [8] with certain safety margin, 8mH of current suppression and (b) with leakage current suppression solution.
Lcm _ dc + Lcm _ ac is used.
applied, there were high-frequency harmonics in vcpv1 and
vcpv2 , which induced large leakage currents. ileak _ H 1 was
B. Simulation results pulsewise current with very high peak value due to the
The PV system with the designed CM filters is simulated capacitive inter-module leakage current loop. The peak value
in PSIM. C pvi ( i = 1, 2, 3, 4 ) were assumed to be 1nF and the of ileak _ g was smaller because of the line filter L in the
input voltages of the cascaded modules were 45V. The module-line leakage current loop, but it still exceeded the
simulated waveforms of vcpv1 , vcpv2 , ileak _ g , ileak _ H 1 are standard requirement. By introducing the suppression
method, the high-frequency harmonics in vcpv1 and vcpv2
given in Fig. 7. When the suppression method was not

1308
were significantly attenuated. The RMS values of ileak _ H 1
and ileak _ g had been reduced to 0.61mA and 8.1mA
respectively, which were well below the standard
requirement. Moreover, the simulated leakage current values
Fig. 8 Photograph of the two cascaded qZSI modules built in the laboratory.
(a)
(b)
Fig. 9 The experimental results without the leakage current
suppression : (a) voltage across the parasitic capacitors and (b) the
corresponding spectrums.
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were consistent with the calculated values provided in Fig. 6.
The accuracy of the simplified leakage current analytical
model was confirmed by the simulation results.
C. Experimental results
Two cascaded qZSI modules using GaN devices are built
in the laboratory, as shown in Fig. 8, to validate the
performance of the proposed method. The parameters of the
qZSI module are the same as in the simulation. C pv1 and
C pv 2 were purposely chosen to be different, C pv1 = 30 nF and
C pv2 = 1nF . Fig. 9 shows the measured waveforms and the
spectrums of vcpv1 and vcpv2 without the CM filters added in
the system. It is seen that vcpv1 and vcpv2 contained around
0.3pu 100kHz harmonics (normalized values with respect to
the input dc voltage). When the leakage current suppression
was applied, the 100kHz harmonics in vcpv1 and vcpv2 were
readily reduced to 0.003pu and 0.023pu respectively as
(a)
(b)
Fig. 10 The experimental results with leakage current suppression
solution 1, Cpv1=30nF and Cpv2=1nF: (a) voltage across the
parasitic capacitors and (b) the corresponding spectrums.
shown in Fig. 10. Obviously, the carrier harmonics across
C pv1 were better attenuated in this case. This was consistent
with the derived simplified leakage current analytical model
given in Fig. 4. The increased parasitic capacitance leaded to
a lower resonant frequency of the formed LC circuit, so the
harmonics in vcpv1 were better attenuated.
V. CONCLUSIONS
The leakage current issue in PV CMI features inter-
module leakage current loops formed among the cascaded
inverter modules. The inter-module leakage current loop
exists even there is a transformer at the total output of the
CMI and it prevents the existed string inverter leakage
current suppression techniques to be directly applied in the
CMI. A filter-based leakage current suppression method,
which is suitable for the cascaded inverter with high
switching frequency, was presented. It was successfully
applied in the PV cascaded multilevel quasi-Z-source
inverters operated at 100kHz switching frequency. Based on
the simplified leakage current analytical model, the
parameters of the CM filters can be designed by limiting the
resonant frequencies of the leakage current path under the
bridge switching frequency. The proposed method and the
design methodology were verified by simulation and
experiments.
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