Inventec drawing and specification document block diagram

8 7 6 5 4 3 2 1
THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC

CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION,INVENTEC CORPORATION,2009 ALL RIGHT RESERVED.
F HSF Property:ROHS or Halogen-Free F
E E
DAKAR10F/FG
D
(45W CPU) D
MP(A02) BUILD
2012.03.23
C C
B B
A A
DRAWER
DESIGN
EE
LOREN
LOREN
DATE
2012.03.23
2012.03.23
POWER
EDISON
EDISON
DATE
2012.03.23
2012.03.23
INVENTEC
CHECK BRYAN 2012.03.23 BY 2012.03.23 TITLE MODEL,PROJECT,FUNCTION
RESPONSIBLE BRYAN 2012.03.23 BY 2012.03.23 DAKAR10F/FG MAIN BOARD
21-OCT-2002 SIZE= VER: SIZE CODE DOC.NUMBER REV
FILE NAME: C CS 1310xxxxx-0-0
1310A2491301-0-MTR X01
DATE CHANGE NO. REV P/N XXX SHEET 1 of 70
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE OF CONTENTS
D
D
PAGE PAGE PAGE

1. COVER PAGE 26. CARDREADER 51. PCH 5 USB
2. INDEX 27. MINI1 WLAN/DEBUG CARD 52. PCH 6 MISC
3. BLOCK DIAGRAM 53. PCH 7 POWER
28. MINI2 3G/LTE 54. PCH 8 POWER
4. POWER MAP 29. SATA HDD/ODD CONN 55. PCH 9 GND
5. POWER CHARGER 30. USB 2.0 CONN 56. VGA 1
6. POWER +V3LA/+V3A/+5A 31. USB 3.0 CONTROLLER(REMOVE) 57. VGA 2
7. POWER +V1.5/+V0.75 32. USB 3.0 CONN W/ S&C 58. VGA 3
C
8. POWER +V1.8S 33. USB 3.0 CONN 59. VGA 4 C
9. POWER VCCIO 34. LCM CONN 60. VGA 5

10. POWER VCCSA 35. CRT CONN 61. VGA 6
11. POWER VCORE 36. HDMI CONN 62. VRAM 1
12. POWER VGFX 37. HDMI CEC 63. VRAM 2
13. POWER VCORE_DGPU 38. DDR3 DIMM0 64. VRAM 3
14. ENABLE PIN 39. DDR3 DIMM1 65. VRAM 4
15. LOAD SWITCH-1 40. FAN & THERMAL SENSOR 66. USB BOARD
16. LOAD SWITCH-2 41. CPU 1 67. PICK BUTTON BOARD(4 PIN)
17. PCB SCREW 42. CPU 2 68. POWER BUTTON BOARD
B 18. HALL SENSOR 43. CPU 3 DRAM 69. EMI B
19. LED 44. CPU 4 POWER 70. PICK BUTTON BOARD(8 PIN)
20. K/B & TP/B CONN 45. CPU 5 POWER
21. EC 46. CPU 6 GND
22. LAN 47. PCH 1
23. RJ45 & TRANSFORMER 48. PCH 2
24. AUDIO CODEC 49. PCH 3
25. SPEAKER/HP JACK/MIC JACK 50. PCH 4 AXG
A A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 2 of 70
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DDR3@1.5/0.75V
AMD PEG IVY BRIDGE \ DDR3 INTERFACE (1333/1600 MHZ)
W/ POWER EXPRESS
THAMES LE \ THAMES XT \
SANDY BRIDGE 204-PIN SODIMM0
QC 45W
SEYMOUR XTX SOCKET-RPGA989
37.5 X 37.5 X 5 mm DDR3 INTERFACE
29X 29 MM DDR3@1.5/0.75V
D (1333/1600 MHZ)
D
204-PIN SODIMM1
FDI DMI 2.0
INTERNAL MIC IN
AUDIO CODEC
REA_ALC269Q_VB6
EXT MIC IN
HDA
C HDMI C
HEADPHONE
PCH
USB2.0 USB_0: USB CONN
CRT PANTHER POINT USB_2: USB CONN
25 X 25 X 2.3 mm
USB_8: CARD READER
LVDS USB_9: MINICARD WLAN
LCM
USB_10:WEBCAM
SLEEP & CHARGE
B B
RJ45
PCIE_1:LAN PCIE USB3.0 USB_1: USB3.0 CONN
ATHEROS_AR8161/8162
PCIE USB2.0 USB_8: CARD READER

PCIE_2:WLAN REA_RTS5129
SATA SATA0:HDD
SPI SATA2 ESATA
SATA5: ODD
A ENE-P2809A EC WINDBOND SPI SPI FLASH 4MB A
THERMAL SENSOR NPCE885LA0DX WINB_W25Q32BVSSIG
BATTERY CHARGER &

DC/DC & IMVP 7
KEYBOARD TOUCH PAD INVENTEC
LI-ION BATTERY TITLE
6-Cell Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ADAPTOR +VBAT +V5A_+-5% +V5S
FUSE BQ24725RGRR TPS51123 NMOS

CHARGER
EC_SMB2 POWER BUDGET 14.745 A POWER BUDGET 4.711A INRUSH 0.55A
65W-75W 8A 6036A0003401 CHG_EN F 300K PEAK2.592A 122.42UF_0.658M
90W 10A 6036A0002901 BATT_IN OCP 10.52A R=140K +V0.85S_+-0.5%
120W 12A 6036A0006001 ACPRES PEAK 9.23A AVG 1.809A
D 330UF_25M // 49.1UF_6.648M TSP51461
D
POWER BUDGET 6A
F 340K
BATTERY PACK OCP 6A
PEAK 6A AVG 1.262A
+V3LA_+-5%
+VCORE_+-0.5% +V3A +V3_LAN
+VCORE_+-0.5% TPS51650 TPS51123 NMOS NMOS
POWER BUDGET 94A POWER BUDGET 12.186 A POWER BUDGET 4.711A INRUSH 0.984A POWER BUDGET 4.711A INRUSH 0.464A
F 375K PEAK2.592A
3.6UF_8.409M PEAK2.592A 5.9UF_9.497M
F 280K OCP 8.40A R=120K +V3S +V1.8S
OCP 104.5A PEAK 7.31A AVG1.7 A
C C
PEAK 94A AVG 45.3A 3300UF_25M //6.7UF_5.458M NMOS RT8068
1880UF_1.1M // 2276UF_0.203M
POWER BUDGET 4.711A INRUSH 1.06A POWER BUDGET 4.711A INRUSH 0.6A
PEAK2.592A 75.6UF_0.986M PEAK2.592A 56.12UF_1.505M
+V3S_DGPU
VDD_CORE NMOS
TPS51728 POWER BUDGET 4.711A INRUSH 0.496A
+V1.5_+-5% +V0.75S PEAK2.592A 13UF_5.803M
POWER BUDGET 46A
F 340K
OCP 50A TPS51216
PEAK 46A AVG 38.7A
B 560UF_25M // 80UF_0.93M +V1.5S_DGPU B
TPS51216 NMOS
POWER BUDGET 33.033 A +V1.5S
F 340K
OCP 20.1A R=56.2K
PEAK 19.82A AVG8.802 A
330UF_15M // 480UF_0.560M NMOS
+V1.5_CPU
CHANGING POINTS~~ NMOS

A TPS51211 IS NEW IC A
+V1.8S IS NEW IC RT8068
VDD CORE IS NEW IC TPS51728 +V1.05_+-5%
CHARGE IS NEW IC BQ24725
VCC CORE IS NEW IC TPS51650
VTT IS NEW IC TPS51219
V0.85 IS NEW IC TPS 51641 TPS51219
V3_V5 IS NEW IC TPS51123
POWER BUDGET ~~IC SPEC (MAX CURRENT ) POWER BUDGET 19.218 A INVENTEC
PEAK CURRENT ~~RATIO OF INTERNAL PREDICTION F 340K TITLE
AVG CURRENT ~~TEST RESULT(MAX CURRENT) OCP 13.2A R=115K MODEL,PROJECT,FUNCTION

Block Diagram
INRUSH ~~L/S TURN NO PEAK 11.53A AVG 6.704A DOC.NUMBER REV
560UF_25M // 359.9UF_0.213M SIZE
A3
CODE
CS
1310xxxxx-0-0 X01
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FUSE6000 CN6000 L7600 PVADPTR

65W-75W 8A(6036A0003401) FUSE6000 NFE31PT222Z1E9L
90W 10A(6036A0002901) 1 1 1 2 1 2 PVPACK
PVBAT FUSE6050
1
120W 12A(6036A0006001) 2 2
G1 5 3 3 LITTLEFUSE_R451012_12A_65V
C7602 P3V3AL 1 2
1
G2 4
3
6 4
C7601
2
10PF_50V_2 C6050 LITTLEFUSE_R451015_15A_65V
ACES_50315_0047N_002_4P 1000PF_50V_2
1 R6054 2 1 R6053 2 1000PF_50V_2
2
R6800
RSC_0603_DY
TP6003 TP60041 TP6005
1M_5%_2 220K_1%_2
2
1 1 CN6050
1
1
BATT+
TP30 TP30 TP30 2 BATT+
HW_V_ADC 1 R6802 2 3
21E8 21E6 OUT ID
Q6002 R6052
1 1K_5%_2
2 4
3 2 33K_5%_2_DY 21E8 21E6 OUT B-I
BATT_IN 5
2
D S
TS
R6050
1 33_5%_2
2 6 G1
21D3 21D2 BI SMD G
D 21D2 EC_SMB1_DATA 1 2 7 G2
BI SMC G
G
R6801 21D3 EC_SMB1_CLK 8 G3 D
2
SSM3K7002FU_DY C6800 R6051 33_5%_2 GND G
RSC_0603_DY 9 G4
0.1UF_16V_2_DY GND G
R6021 R6022
1
NEAR EC
1
1 2 2 1 D6701 D6702 D6703 SYN_200045GR009G18TZR_9P
PVADPTR EZJZ0V500AA_DY EZJZ0V500AA_DY EZJZ0V500AA_DY
1M_5%_2_DY 3M_5%_2_DY
R6015
1
1 2
4.7K_5%_3
1 R6014 2 PVBAT PVPACK
RSC_0603_DY
Q6010 Q6011 R6000 Q6012 C6033
8 D S 1 1 S D 8 1 2 8 D S 1 1 2
7 2 2 7 3 4 7 2
6 3 3 6 0.01_1%_6 6 3 0.1UF_25V_3
5 4 4 5
RSC_1206_DY CSC0805_DY
G G 5 G 4
1
NMOS_4D3S NMOS_4D3S NMOS_4D3S

C6020
C6014
1
TPCA8065_H TPCA8065_H 1 2 TPCA8065_H
C6030 C6031
1 2 1 2 0.1UF_16V_2
1
PAD6000
2
PVADPTR POWERPAD_2_0610
1
2200PF_50V_2 0.1UF_25V_3
2
C C
RSC_1206_DY
R6006
1
1
1 2 3
2
D6000
R6018
2 R6019
RSC_0603_DY D6002
2
1 2
2
DIODES_BAV99 A1 A2
P3V3AL
R6002 C6021 C6022
C
2
R6004 R6005 0.1UF_25V_3
20.5K_1%_2
2
4.3K_5%_2 4.3K_5%_2 BAT54C_30V_0.2A
2
0.1UF_25V_3
2
3
1
5
6
7
8
R6013
1
10K_5%_3 Q6000
R6012
D
AON7410
10_5%_5
NMOS_4D3S
C6001 C6002 C6003 C6004
1
470PF_50V_2 4.7UF_25V_5 4.7UF_25V_5 CSC0805_DY

21E6 OUT
1
5
4
3
2
ACPRES C6026
2
U6000 1UF_25V_3
G
ACOK
ACDRV
CMSRC
ACP
ACN
1 2
S
TI_BQ24725ARGRR_QFN_20P
21
4
3
2
1
TML
VRCHARGER_HG
6 ACDET
VCC 20 L6000 R6001
21E8 21E6 OUT HW_I_ADC 7 IOUT
PHASE 19 VRCHARGER_PH 1 2 1 2
B 8 SDA
18 3 4 B
9 HIDRV R6020 C6027 ETQP3W4R7WFN
SCL
1
BTST 17 1 2 1 2
10 ILIM
REGN 16 0.02_1%_6
CSC0805_DY
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7_5%_3
BATDRV
C6036
1
3
5
6
7
8
2
LODRV
0.047UF_16V_2
C6037 100PF_50V_2 GND
SRN
C6010
C6011
C6012
C6013
SRP
Q6001
100PF_50V_2 P3V3AL R7600
SBR3U40P1_DY
C
1
D
AON7410
NEAR IC RSC_0603_DY
NMOS_4D3S
1
1
1 2
2
NEAR EC
2
A1 A2 C6023
1
D6700
1 2
11
12
13
14
15
C6034
R6003
CSC0402_DY
2
C6029
1
3.32K_1%_3
CSC0603_DY C6028 D6001 0.1UF_16V_2
1
2
S
1UF_10V_2 BAT54C_30V_0.2A
0.1UF_25V_3
0.1UF_25V_3
C6035
1
CSC0402_DY
2
2
1
C7600
C6024
C6025
2
4
3
2
2
R6007
1
CSC0402_DY
110K_5%_2
2
R6016
1
EC_SMB2_DATA 1 2 VRCHARGER_LG
2
21D3 21D2 BI
56C8 37C3
SHORT_0402
R6017
56D8 37C6 21D3 21D2 EC_SMB2_CLK 1 2
BI
SHORT_0402
R6011
A 1 2 A
1
2
C6032 SHORT_0402
0.1UF_16V_2
R6008 R6010
2 1
91K_5%_2
0_5%_2
2
1
1 R6009 2
4.3K_5%_2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
14D7 EN_5V
IN
140K_1%_2
1
D
R6160
D
2
PVBAT
2VREF VRP5V0A_PH 6D3
14C7 IN EN_3V OUT OUT
120K_1%_2
5V_PG
R6110
PAD6110 OUT
1
POWERPAD_2_0610
2
2 VBATP 6C3 14C8
OUT VBATP
14C8 6C6 IN
1
8
7
6
5
5
6
7
8
1
C6123
1
1
Q6100 Q6150
1
25
6
5
4
3
2
0.22UF_6.3V_2
D
C6160 C6161
AON7410
AON7410
C C6111 C
NMOS_4D3S
NMOS_4D3S
C6110
TML
TRIP2
VFB2
TONSEL
VREF
VFB1
TRIP1
4.7UF_25V_5 4.7UF_25V_5
2
4.7UF_25V_5
4.7UF_25V_5
2
2
R6114 7 VO2 VO1 24
S
G
S 2.2_5%_3 8 23
C6115 VREG3 PGOOD R6155 C6155
1 21 2 9 22
1 2.2_5%_3
12 2
VBST2 VBST1
2
3
4
4
3
2
1
1
L6100 VRP3V3A_HG10 DRVH2 U6100 DRVH1 21 VRP5V0A_HG 0.1UF_16V_2 L6150 14D6
14D6 VRP3V3A 1 2 0.1UF_16V_2 VRP3V3A_PH 11 20 VRP5V0A_PH 1 2 VRP5V0A 14C8
OUT VRP3V3A_LG 12
LL2 LL1 OUT
DRVL2 DRVL1 19 VRP5V0A_LG 14D4
ETQP3W3R3WFN ETQP3W3R3WFN
1
1
SKIPSEL
8
7
6
5
5
6
7
8
1
VREG5
Q6101 R6150
Q6151
GND
ENC
EN0
R7610 R7615
VIN
D
AON7702A
D
AON7702A
R6100 RSC_0603_DY VRP3V3A_LDO RSC_0603_DY

21
14C6 OUT TI_TPS51123RGER_QFN_24P
21
1
14C8 15.4K_1%_2
13
14
15
16
17
18
1
6.8K_1%_2
2
2
SKIP_3V_5V C7615
+
14C7 IN C6150
C7610 EN_3V_5V CSC0402_DY
G
+
1
S
C6100 150UF_6.3V
G
IN
S
CSC0402_DY
150UF_6.3V
1
VRP5V0A_VIN VRP5V0A_LDO
2
2
3
4
4
3
2
2
14C7 14D6
1
1
IN OUT R6151
2
R6101 10K_1%_2
1
1UF_25V_3
1
1
B 10K_1%_2 B
2
C6122
C6121 C6120
2
1UF_6.3V_2 R6113
RSC_0402_DY 10UF_6.3V_3
2
2
VO=(( R6150/R6151)+1)*2
VOUT=((R6100/R6101)+1)*2 VRP5V0A_LG
OUT 6B3 14D5
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PVBAT
POWERPAD_2_0610
2
P5V0A
PAD6210
2
D
D
1
P0V75S
1
2.2UF_6.3V_3
1
C6216
5
6
7
8
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
1
1
Q6200
FDMC8884
C6210
C6211
C6212
NMOS_4D3S
2
2
U6200
S
R6215 C6215
12 V5IN VBST 15 1 2 1 2
4
3
2
1
14 VRP1V5_HG 2.2_5%_3
DRVH 0.1UF_16V_2
L6200
14D1 EN_0V75 17 13 VRP1V5_PH 1 2 VRP1V5 14C2
IN S3 SW OUT
RSC_0603_DY
3 4
POWERPAD1X1M
EN_1V5 16
2
14D1 IN S5 PCMC104T_1R0MN
2
C C
R7620
5
6
7
8
11 VRP1V5_LG
FDMS0310AS
DRVL
PAD6220
Q6201
560UF_2.5V
1
D
2
R6200
DDR3L_SEL 1 2
CSC0402_DY
6 10
IN VREF PGND
+
C6200
1
11
10.2K_1%_2 PGOOD 20
C7620
1
G
9
2
VDDQSNS
8 2
4
3
2
1
REFIN VLDOIN
2
VTT 3
VTTSNS 1
7
0.01UF_50V_2
GND
0.1UF_16V_2
P0V75M_VREF
54.9K_1%_2
2
1
C6217
C6218
19 4
R6201
MODE VTTGND
18 TRIP VTTREF 5
100K_5%_2
R6203 1
0.22UF_6.3V_2
10UF_6.3V_3
21
2
2
1
75K_1%_2
TML
1
B 1V5_PG B
1 R6202
C6220
C6221
OUT 14C2
TI_TPS51216RUKR_QFN_20P
2
2
VOUT=REFIN=1.8*(R6201/(R6200+R6201))
MODE=100KOHM:TRACKING DISCHARGE
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
P3V3S
C C
10UF_6.3V_3
1
C6971
1
10_5%_2
R6970
2
U6970
11 TML
10 PVIN LX 1 L6970
2
9 2 1 2 VRP1V8S 14A2
PVIN LX OUT
8 SVIN LX 3 R6971
7 NC PGOOD 4 1 2 PAN_ELL5PR2R2N
10UF_6.3V_3
10UF_6.3V_3
CSC0402_DY
6 FB EN 5 100K_5%_2
20.5K_1%_2
1
1
1UF_10V_2
1
R6973
C6974
C6970
C6975
RICHTEK_RT8068AZQW_WDFN_10P
C6972
1V8S_PG OUT
2
EN_1V8
2
IN 14B1
B B
10K_1%_2
R6972
2
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
14B7 EN_VCCP PVBAT

IN
POWERPAD_2_0610
2
PAD6310
100K_5%_2
1
2
R6303
1
2
1
14B6 14A8 VCCP_PG
C OUT C
5
6
7
8
R6315 C6315
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
1
1
1 2 1 2
Q6300
FDMC8884
17
16
15
14
13
C6310
C6311
C6312
2.2_5%_3
NMOS_4D3S
0.1UF_16V_2
U6300
PWPD
PGOOD
EN
BST
MODE
2
G
S
1 VREF SW 12 VRP1VO_VCCP_PH
R6307
4
3
2
1
VCCIO_SEL VRP1VO_VCCP_HG
1
1 2 2 11
2.2UF_6.3V_3
10K_1%_2
46B4 IN REFIN DH
1
VSS_SENSE_VCCIO 0_5%_2_DY VRP1V0_VCCP_LG

R6306
C6318
44A3 3 10 L6300
IN GSNS DL
VRP1V05S
1 2 14A8
P5V0A
1 2 OUT
RSC_0603_DY
44A3 VCC_SENSE_VCCIO 4 9 3 4
IN VSNS V5 3 4
5
6
7
8
2
2
COMP
PGND
CYN_PCMB063T_R68MS_4P
TRIP
R7630
GND
2
FDMS0310AS
0.01UF_50V_2
11.3K_1%_2
Q6301
1
D
2.2UF_6.3V_3
22UF_6.3V_5
560UF_2.5V
1
1
1
C6320
TI_TPS51219RTER_QFN_16P
R6308
C6316
CSC0402_DY
+
C6300
C6301
11
C6319
5
26
52.3K_1%_2 7
8
2 1
C7630
S
2
0.01UF_50V_2
R6302
2
B B
4
3
2
1
2
1
VOUT=1.05V@REFIN=3.3V; VOUT=1.0V@REFIN=GND
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
1
C6522
0.01UF_50V_2
C6520 R6520
1 2 1 2
2
3300PF_50V_2 5.11K_1%_2
1
VCCSA_SENSE 45A2
IN
C6521
P5V0A 0.22UF_6.3V_2 R6521
1 2
RSC_0402_DY
1
2
3
4
5
6
C C
COMP
MODE
GND
SLEW
VOUT
VREF
TI_TPS51461RGER_QFN_24P
25 TML L6500
24 7 VRPVSA_PH 1 2 VRPVCCSA 14A6
VIN SW 1 2 OUT
23 VIN SW 8 3 3 4 4
22 VIN U6500 SW 9
1
21 PGND SW 10 CYN_PCMB063T_R33MS_4P
C6510 C6511 20 PGND SW 11 C6515
1
0.1UF_16V_2 19 PGND BST 12 1 2
22UF_6.3V_5
V5FILT
C6500 C6501 C6502 C6503
PGOOD
V5DRV
1
VID0
VID1
0.1UF_16V_2
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5_DY
2
EN
R7650
2
RSC_0603_DY
18
17
16
15
14
13
EN_SA
12
IN 14B5
R6524
1 2 VCCSA_VID0 C7650
IN 45A2
CSC0402_DY
SHORT_0402
R6525
2
1 2 VCCSA_VID1 45A2
IN
1UF_6.3V_2
1UF_6.3V_2
1
B SHORT_0402 B
C6523
C6524
2
SA_PG 14A6 21B6

OUT
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R6620 2 R6622 2
UMA/PX DIS. 11D7 11D4 11C8 11B7 11A7 11A4 IN VREF_CPU 1 1 PVBAT PAD6610 PVBAT_CPU
1
3+2 3+0 2+1 2+0 71.5K_1%_2 100K_1%_2 1 1 2
2
OUT
R6624
R6620 71.5K 71.5K 44.2K 44.2K
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
RSC_0402_DY POWERPAD_2_0610
1
12D5
R6621 42.2K 42.2K 90.9K 90.9K
C6611
C6612
C6613
C6614
C6615
C6616
C6617
C6618
C6619
C6620
C6621
R6623
1 R6621 2 1 2 C6699
C6610
R6622 100K 100K 39K 39K
+
68UF_25V
R6626 4.7K DNP 3.3K DNP 42.2K_1%_2
24K_1%_2
R6627 75K DNP 56K DNP
2
P3V3A
C6632
IN
R6711 100K DNP 200K DNP
11C3
11C3
VREF_CPU 1 2
IN
IN
1
R6712 24K DNP 30K DNP R6635
1
47PF_50V_2 1 2
R6719 DNP 0 DNP 0 C6631 11D5 OUT CPU_CSN1
11D3
11D3
RSC_0402_DY
44B3
44B3
R6723 DNP 0 DNP 0 R6618 0.1UF_16V_2_DY
R6625
1 2 1 R6636 2 100K_5%_NTC
R6635 DNP DNP 0 0
D
2
C6623
2
R6636 DNP DNP 0 0 15.4K_1%_2 RSC_0402_DY R6619 D
OUT CPU_CSP1 1 2
IN
IN
2 VREF_CPU 11D5
1
1 11A4 11A7 11B7 11C8 11D6
R6714 DNP 0 DNP 0 IN 11D7
15.4K_1%_2 0.022UF_16V_2
IN
IN
IN
IN
R6626 P5V0A
CPU_CSN3
CPU_CSP3
R6716 DNP 0 DNP 0
4.7K_1%_2 PVBAT_CPU 11B3 11D1 12D5 R6605
R6721 DNP 0 0 0 IN
11 VCCSENSE
1 2
12 VSSSENSE
6 CPU_CSN2
7 CPU_CSP2
4 CPU_CSP1
V5_CPU R6617 2
5
6
7
8
1
CPU_CSN1
R6725 DNP 0 0 0 OUT
1
10_5%_3 240K_1%_2
Q6610
FDMC7696
D
R6726 0 DNP DNP DNP
NMOS_4D3S
R6602 R6603 R6604
PVCORE
1
R6724 0 DNP 0 DNP C6629 C6630 1 2 1 2 1 2
10
1
9
2
R6722 0 DNP DNP DNP R6627 2.2UF_10V_3 4.7UF_10V_3
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2
2
R6720 0 DNP 0 DNP 75K_1%_2
S
CCOMP
CGFB
CVFB
CCSN3
CCSP3
CCSP2
CCSN2
CCSN1
CCSP1
CF-IMAX
COCP-R
CTHERM
ETQP4LR36AFM
R6713 0 DNP 0 DNP 3 4
2
4
3
2
1
R6715 0 DNP 0 DNP GND 49 1 2
1
5
6
7
8
L6610
P3V3A 13 48 V5_CPU 11D5
FDMS0306AS
11D6 11D7 GOCP-R V5 IN R7661
Q6611
D
11C8 11D4
1
11B7 VREF_CPU RSC_0603_DY C6600 C6601
1
14 47
VREF_CPU
IN 11A4 OUT VREF CDH1
470UF_2V
21
11A7 R6601 C6622 470UF_2V
+
15 46 1 2 1 2
+
V3R3 CBST1
1
C7661
C C6634 VR_ON 2.2_5%_3 0.1UF_16V_2 CSC0402_DY C
G
16 45
S
IN VR_ON CSW1
3
2.2UF_6.3V_3
3
CORE_PG 17 44
OUT CPU_CSN2
2
4
3
2
40B4 11A4 U6600 11D5
1
C6633 OUT CPGOOD CDL1
1
49B7
1
2.2UF_6.3V_3 P5V0A
2
R6711 R6628 44C2 11A3 VR_SVID_CLK 18 43

IN VCLK V5DRV
RSC_0402_DY VR_SVID_ALERT# 19 42
44C2 OUT ALERT# PGND C6625
100K_1%_2
VR_SVID_DATA
11D6 OUT CPU_CSP2 1 2
20 41
2
44C2 11A3 BI VDIO TI_TPS51650RSLR_QFN_48P CDL2

0.022UF_16V_2
41D6 21C3 CPU_PROCHOT# 21 40
OUT VR_HOT# CSW2 PVBAT_CPU
IN 11D1 11D3 12D5 1 R6610 2
R6606 C6624
5
6
7
8
22 SLEW CBST2 39 1 2 1 2
240K_1%_2
2.2_5%_3 0.1UF_16V_2
Q6620
FDMC7696
AXG_PG
D
11A4 23 38 R6607 R6608 R6609
OUT GPGOOD CDH2
PVCORE
NMOS_4D3S
R6616 1 2 1 2 1 2
24 GF_IMAX VBAT 37 1 2
GTHERM
GPWM1
GCOMP
GPWM2
CPWM3
GSKIP#
GCSN1
GCSP1
GCSN2
GCSP2
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2

GGFB
GVFB
10K_5%_3
G
1
S
R6629 ETQP4LR36AFM
20K_1%_2 3 4
4
3
2
1
R6712 GFX_VSS_SENSE 1 2 1 2
B IN PVBAT B
1
25
26
27
28
29
30
32
33
34
35
36
31
R6713 0_5%_2 L6620
5
6
7
8
24K_1%_2 GFX_VCC_SENSE 1 2
45C3 IN
OUT GPWM1
OUT CPWM3
2
R7662
FDMS0306AS
0_5%_2
GPWM2
R6715
Q6621
D
RSC_0603_DY
1
1
11D7 P3V3A
21
11D6 VREF_CPU C6726 C6602 C6603
11C8 470UF_2V 470UF_2V
1 2 1 2
+
11A4 IN C7662
11A7
1
0_5%_2_DY
OUT
47PF_50V_2 1 R6719 2
11D4 CSC0402_DY
S
R6721 0_5%_2_DY
2
3
R6714 R6716 1 2
2
R6718
0_5%_2_DY 0_5%_2_DY
4
3
2
1
1 2 R6723 0_5%_2_DY
1 2
12D7
12B7
12A7
0_5%_2_DY
2
R6725
7.5K_1%_2
0_5%_2
0_5%_2
0_5%_2
0_5%_2
21D3 EN_PVCORE R6731

IN
1 2 VREF_CPU 11A7 11B7 11C8 11D4 11D6 11D7
IN
1
RSC_0402_DY
1
R6724
R6720
R6722
R6726
R6630 GSKIP# 12B7

OUT
0_5%_2
IN GPU_CSN1 2
IN GPU_CSP1 2
IN GPU_CSP2 2
GPU_CSN2 2
100K_5%_2
1
2
R6730
A P3V3A P1V05S A
VR_ON 11C7
OUT
1
R6631
0.1UF_16V_2
IN
1
54.9_1%_2
130_1%_2
1
2K_5%_2
RSC_0402_DY
R6732
R6632
R6633
C6635
2K_5%_2
R6634
R6728
2
VREF_CPU 1 2
100K_5%_NTC
11D7 11D6 11D4 11C8 11B7 11A4 IN

1
2
INVENTEC
12C5
12C5
12A5
12B5
15.4K_1%_2
R6729
2
2
C6727
0.1UF_16V_2_DY
49B7 40B4 11C7 OUT CORE_PG 11C7
44C2
IN VR_SVID_CLK
TITLE
2
1
11B7 OUT AXG_PG 44C2 11C7 BI VR_SVID_DATA MODEL,PROJECT,FUNCTION

Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
11D6 CPU_CSN3
OUT
C6628
11D6 CPU_CSP3 1 2
OUT
0.022UF_16V_2
PVBAT_CPU R6615
IN 11B3 11D1 11D3 1 2
5
6
7
8
240K_1%_2
R6611 C6626
Q6630
FDMC7696
D
1 2 1 2 R6612 R6613 R6614
PVCORE
NMOS_4D3S
1 2 1 2 1 2
2.2_5%_3 0.1UF_16V_2
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2
D P5V0A U6630
G
9
S
PAD
ETQP4LR36AFM D
1 BST DRVH 8 3 4
4
3
2
1
2 SKIP# SW 7 1 2
CPWM3
1
11B5 3 6 L6630
IN PWM VDD
5
6
7
8
4 GND DRVL 5
FDMS0306AS
R7663
Q6631
D
TI_TPS51601DRBR_SON_8P P5V0A RSC_0603_DY
21
1UF_6.3V_2
1
C6627
C7663
S
CSC0402_DY
2
PVBAT
4
3
2
1
2
11A6 GPU_CSN1
OUT
1
1
PAD6710
POWERPAD_2_0610
2
C6722
GPU_CSP1 1 2 PVBAT_AXG
2
11A6 OUT OUT 12A5 12C5
C C
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
1
1
0.022UF_16V_2
C6710
C6711
C6712
C6713
C6714
C6715
C6716
C6717
PVBAT_AXG R6705
IN 12A5 12C1 1 2
5
6
7
8
169K_1%_2
R6701 C6720
Q6710
FDMC7696
2
1 2 1 2 R6702 R6703 R6704
PVAXG
NMOS_4D3S
1 2 1 2 1 2
2.2_5%_3 0.1UF_16V_2
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2
U6710
G
9
S
GSKIP# PAD
11A4 IN ETQP4LR36AFM
1 BST DRVH 8 3 4
4
3
2
1
2 SKIP# SW 7 1 2
1
11B5 GPWM1 3 6 L6710
IN PWM VDD
5
6
7
8
4 GND DRVL 5
R7671
FDMS0306AS
Q6711
D
P5V0A RSC_0603_DY
TI_TPS51601DRBR_SON_8P
1
21
C6700
1UF_6.3V_2
1
470UF_2V
+
C6721
C7671
CSC0402_DY
G
B S B
3
2
4
3
2
1
2
11A5 GPU_CSN2
OUT
C6725
11A6 GPU_CSP2 1 2
OUT
0.022UF_16V_2
PVBAT_AXG R6710
IN 12C1 12C5 1 2
5
6
7
8
169K_1%_2
R6706 C6723
Q6720
FDMC7696
1 2 1 2 R6707 R6708 R6709

PVAXG
NMOS_4D3S
1 2 1 2 1 2
2.2_5%_3 0.1UF_16V_2
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2
P5V0A U6720
G
A 9 A
S
PAD
ETQP4LR36AFM
1 BST DRVH 8 3 4
4
3
2
1
2 SKIP# SW 7 1 2
1
11B5 GPWM2 3 6 L6720

IN PWM VDD
5
6
7
8
4 GND DRVL 5
R7672
FDMS0306AS
Q6721
D
P5V0A RSC_0603_DY
TI_TPS51601DRBR_SON_8P
1
21
C6701
470UF_2V
+
1UF_6.3V_2
INVENTEC
1
C7672
C6724
CSC0402_DY
G
3
2
4
3
2
1
TITLE
2
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R7016
16A1 13B2 DGPU_PWR_EN
1 2 EN_DGPU 13C8
16C4 16A8
IN OUT
10K_5%_2
PVBAT
45D3 21D6 R7020
SLP_S3#_3R1 2
0.1UF_16V_2
14A6 13A2 IN
1
14D2 14B8
POWERPAD_2_0610
1
C7010
49A1
0_5%_2_DY
PAD6760
1
D
2
2
D
1
1
P5V0A R6755
5
6
7
8
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
C6761
C6762
1 2 PVCORE_DGPU
C6760
Q6750
FDMS7692
D
240K_5%_2
NMOS_4D3S
R6752 C6753 PAD6750
U6750 2.2_5%_3 0.1UF_16V_2
2
VRPVCORE_DGPU 1 2
2
16 13 1 2 1 2 13C3 IN 1 2
1 R6756 2 TON BOOT
1UF_6.3V_2
1UF_6.3V_2
1
G
9 POWERPAD_2_0610
S
10_5%_2 VDDP
C6754
C6757
12 VRPVCORE_DGPU_HG PAD6751
4
3
2
L6750
1
UGATE 1 2
PAN_ETQP4LR36WFC_4P 1 2
2 VDD PHASE 11 VRPVCORE_DGPU_PH 1 2 VRPVCORE_DGPU OUT 13C2
2
POWERPAD_2_0610
1
3 4
RSC_0603_DY
1
1
5
6
7
8
2.2K_1%_2
LGATE 8 VRPVCORE_DGPU_LG
C6751
FDMS0306AS
+
R7675
Q6751
R6750
D
52C6 13B2 OUT DGPU_PWRGD 4 PGOOD
1
560UF_2.5V
470UF_2V
C 10 7 PWRCNTL_0 C6752 C
1 2
2
CS G0 IN 56D5 56F7
2 C6750
CSC0402_DY
+
2
1
470UF_2V
13K_1%_2
R6758
C7675
FB 3
1
S
10K_1%_2
56F7
3
14 PWRCNTL_1 56C5
G1 IN
R6751
4
3
2
1
EN_DGPU
15 5 1 2
2
2
13D1 IN EN_DEM D1
R6753 10K_1%_2 P3V3S_DGPU
2
17 GND D0 6 1 2
R6754 16.5K_1%_2
1
1
10K_5%_2
VOUT
REA_RT8208BGQW_WQFN_16P
R7017
2
DGPU_PWRGD
VGA TYPE SEYMOUR XTX THAMES XT THAMES LE P.S. R6750(R1)R6751(R2)R6753(R3)R6754(R4) IN OUT
G0 G1 VOUT VOUT VOUT RESISTOR VALUE

B 1.15 N/A N/A R6750(R1) 2.2 K B
0 0 P1V5S_DGPU
0 1 1.05 N/A N/A R6751(R2) 10 K
P1V5S_DGPU
1 0 1 1 1 R6754(R3) 16.5 K 1
R7018
1 1 0.9 0.9 0.9 R6753(R4) 10 K
22UF_6.3V_5
1 100K_5%_2_DY
2
C6955
P5V0A 16C4
16A8
13D2 1 R7019
DGPU_PWR_EN 2 EN_VPCIE 13A6
16A1
IN OUT
1K_5%_2
2
1UF_6.3V_2
VRPVPCIE
1
13A2 49A1
OUT 21D6
C7011
14B8 R7030
13D2 IN SLP_S3#_3R 1 2
68PF_50V_2
14A6
1
2.7K_1%_2
14D2
C6952
45D3 0_5%_2_DY
R6950
U6950
2
5 VIN VOUT 4
22UF_6.3V_5
6 3
1UF_10V_2
1
1
VCNTL VOUT
2
C6951
C6950
7 2
8
POK FB PVPCIE
13B1 EN_VPCIE
A IN A
1
EN
10K_1%_2
9 1
VIN GND PAD6950
1UF_10V_2
1
R6951
2
13A3 VRPVPCIE 1 2
IN
C6954
ANPEC_APL5930KAI_TRL_SOP_8P 1 2
POWERPAD_2_0610
2
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DDR_P1V5
3V & 5V 49A1
21D6
14A6 R7010
13A2 SLP_S3#_3R 1 2 EN_0V75 7C7
EN_5V 13D2
IN OUT
OUT 6D6 VRP5V0A 47K_5%_2
1
P5V0A 14D6 14C8 6C1 IN 14B8
45D3
0.047UF_16V_2
3
1
Q7000 PAD6150
VRP5V0A 1 C7005
C7000
2
2
14D4 14C8 6C1 IN
1
1 2
15D4 EC_PW_ON# 1 G C6151 0.1UF_16V_2
21C3
IN POWERPAD_2_0610
2
+
330UF_6.3V_DY
S
2 13
SSM3K7002BFU
2
C7001 D7001
2
0.1UF_16V_2 DIODES_BAV99
P3V3AL R7012
21D3 SLP_S5#_3R 1 2 EN_1V5 7C7
1
49B3
IN OUT
D
1
PAD6100 0_5%_2
6C8 VRP3V3A 1 2 D
IN
1
1
1 2
C7006
1
POWERPAD_2_0610 C6101
2
CSC0402_DY
A1
C7002 C7003
+
330UF_6.3V_DY
0.1UF_16V_2
2
0.1UF_16V_2
6B3 VRP5V0A_LG 2 13 P3V3S
IN
2
21F6
2
P5VAUXON 3 D7000
14C8
15D6
IN C P5V0AL
D7002 P15V0A
2
DIODES_BAV99
1 1
BAT54C_30V_0.2A_DY VRP5V0A_LDO1 2
6B4 IN 1 2 R7013
A2
RSC_0402_DY
PAD6120 C7004 1V5_PG 1V5_PG
EN_3V POWERPAD1X1M 14C2 7B3 IN OUT
6D6
1
OUT 1UF_25V_3
2
VRP3V3A_LDO 1 R7000 2
2
14C6 6B6 IN P3V3_LDO
RSC_0402_DY P1V5
VRP5V0A 1 R7001 2 SKIP_3V_5V VRP3V3A_LDO
1 2 PAD6200
14D4 6C1 IN OUT 6B5 14C8 6B6 IN 1 2 1 2
14D6 10K_5%_2 1 2
PAD6121 POWERPAD_2_0610
VBATP 1 R7002 2 VRP5V0A_VIN POWERPAD1X1M PAD6201
6C6 6C3 IN OUT 6B5
C 0_5%_3 7C1 VRP1V5 1 2 C
IN 1 2
21F6 R7003 2
14D8 P5VAUXON 1 EN_3V_5V 6B4 POWERPAD_2_0610
15D6
IN OUT
0_5%_2
VCCIO VCCSA DGPU P1V8S
49A1 R7040
21D6 VCCP_PG 1 2 EN_SA
14A6 R7021 14A8 9C6 IN OUT 10B4
13A2 SLP_S3#_3R 1 2 EN_VCCP 9D6
IN OUT
1
13D2 0_5%_2
14D2 P3V3S
0.1UF_16V_2
45D3 47K_5%_2 C7040

1
C7020
CSC0402_DY R7050
1 2 EN_1V8 8B4
OUT
2
10K_5%_2
B B
2
1
C7050
0.01UF_50V_2
P3V3S
2
1
P3V3S
R7041
10K_5%_2
2
10K_5%_2
R7022
21B6 14A6 10A5 SA_PG SA_PG

IN OUT
2
1
VCCP_PG VCCP_PG D7040

14A8 9C6 IN OUT P1V8S
NC
14B6 49A1
14B8 13D2 13A2 SLP_S3#_3R 3 1
45D3 21D6 14D2
IN
PAD6900
BAT54_30V_0.2A VRP1V8S 1 2
8B2 IN 1 2
A A
POWERPAD_2_0610
P1V05S
PAD6300 PVSA
1 1 2
2
POWERPAD_2_0610 PAD6500
10C1 VRPVCCSA 1 2
IN 1 2
9B1 IN VRP1V05S 1
PAD6301
POWERPAD_2_0610
1 2
2 POWERPAD_2_0610
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P15V0A P3V3AL P3V3A

P3V3AL
Q7102 PAD7100
1
1 D S 4 1 1 2
2
1
2
R7105 5 POWERPAD_2_0610
R7104 100K_5%_2 6 3
G
PVBAT P3V3_LDO NMOS_4D1S
100K_5%_2_DY
1
AO6402AL
3
R7106
1
Q7101 200_5%_2
1
4
R7491
D
U7490 EC_PW_ON#
510K_1%_2 21C3 14D8 1 G C7100
IN
2
VDD
D
2
2200PF_50V_2
S
D
2
D7490
1
NC SSM3K7002BFU
2
56D6
2
OUT THRM_SHUTDWN# 3 1 5 3 P5VAUXON
3
40A8 SENSE RESET# OUT 14C8 14D8 21F6
40B1 R7100
Q7103
1
10K_5%_2
D
BAT54_30V_0.2A R7492 1 G
GND
GND
S
120K_1%_2 TI_TPS3801_01_SC70_5P
SSM3K7002BFU
2
2
1
2
P3V3AL
P15V0A P3V3S
C PAD7101 C
POWERPAD_2_0610
Q7105
1 D S 4 2 1
1
470K_5%_2
2 1
2
R7107
1
22UF_6.3V_5
200_5%_2
1
5
R7109
C7103
6 G 3
NMOS_4D1S
AO6402AL
2
R7108
1 2
32
680PF_50V_2
2
1
3
SHORT_0402
2200PF_50V_2
Q7106
C7102
49B1
1
Q7104
D
15B8
SLP_S3_3R
C7101
15A4 1 G
IN
D
16A7
15A4 SLP_S3_3R 1 G 15B4
IN 16A7
S
15B4
49B1
2
S
SSM3K7002BFU
SSM3K7002BFU
2
2
2
P5V0A P5V0S
PAD7102
POWERPAD_2_0610
Q7107 2 1
B 1 D S 4 2 1 B
1
2
200_5%_2
R7111
5
22UF_6.3V_5
1
6 G 3
C7105
NMOS_4D1S
AO6402AL
R7110
23
1 2
CSC0402_DY
Q7108
1
2
49B1
SHORT_0402
D
15B8
C7104
15A4 SLP_S3_3R 1 G
15B4
IN
16A7
S
SSM3K7002BFU
2
2
P1V5 P1V5S
PAD7103
POWERPAD_2_0610
Q7109
8 D S 1 1 1 2
2
200_5%_2
1
7 2
R7113
6 3
22UF_6.3V_5
1
5 G 4
A A
C7107
NMOS_4D3S
23
AM7330N P0V75S
Q7112 Q7110
8 1
D
D S
200_5%_2
7 2 SLP_S3_3R 1
2
15B8 15B4 IN G
R7114
6 3 49B1 16A7
S
5 G 4
NMOS_4D3S
SSM3K7002BFU
AM7330N_DY
2
R7112
23
INVENTEC
1 2
Q7111
CSC0402_DY
1
SHORT_0402
D
C7106
1 G
TITLE
S
SSM3K7002BFU Block Diagram
2
2
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V5 P1V5S_DGPU
Q7113
8 D S 1
7 2
6 3
5 G 4
NMOS_4D3S
AM7330N
8
Q7114
1
POWER EXPRESS
D S
7 2
6 3
5 G 4
NMOS_4D3S
DURING RESET AFTER RESET
AM7330N
Q7121
D 8 D S 1
7 2 0 : DGPU POWER SWITCH TURNED ON D
6 3 DGPU_PWR_EN# HIGH HIGH
5 G 4 1 : POWER SWITCH TURNED OFF
1
NMOS_4D3S
AM7330N_DY R7115
16B7 16A5 DGPU_PWR_EN_15R 1 R7116 2 200_5%_2
0 : DGPU POWER IS NOT STABLE
IN DGPU_PWRGD
1
220K_5%_2
1 : DGPU POWER IS STABLE
2
C7108
680PF_50V_2
LOW LOW 0 : KEEP DGPU IN RESET
DGPU_HOLD_RST#
3
1 : RESET IS RELEASED
Q7115
D
16B7 16A6 IN DGPU_PWR_EN_3R 1 G
P3V3S P3V3S_DGPU
S
SSM3K7002BFU
R7042 0_5%_2_DY
2
1 2
P3V3S Q7003
C C
CSC0402_DY
CSC0402_DY
S D
10K_5%_2
1
1
P1V8S P1V8S_DGPU
S D
R7031
C7023
C7024
R7038
0_5%_6_DY
G
1 2
G
Q7118
23
2
1 4 Q7002
D S
2 SSM3K7002BFU
DIODES_DMP2305U_SOT23_3P
D
5 R7039
16A8 16A1 13D2 13B2 DGPU_PWR_EN 1 2 1 G
6 G 3 IN
NMOS_4D1S 0_5%_2
S
CSC0402_DY
1
AO6402AL
1
C7021
2
R7120 R7119
16D7 16A5 IN DGPU_PWR_EN_15R 1 2
200_5%_2
1
220K_5%_2
2
2
C7110
680PF_50V_2
3
2
B B
Q7119
D
16C7 16A6 IN DGPU_PWR_EN_3R 1 G

S
SSM3K7002BFU P3V3S
2
1
R7121
10K_5%_2
DGPU_PWR_EN
3 2
OUT 13B2 13D2 16A8
16C4
P15V0A
1M_5%_2
Q7120
R7034 1
D
51C7 51B6 IN DGPU_PWR_EN#1 G SSM3K7002BFU
P3V3_LDO
S
10K_5%_2
R7033 1
DGPU_PWR_EN_15R 16B7 16D7

OUT
23
2
16B7 IN Q7019
16C7 SSM3K7002BFU
D
DGPU_PWR_EN_3R 1 G
A A
23
Q7018
SSM3K7002BFU
S
R7047
D
16C4 16A1 13D2 13B2 DGPU_PWR_EN 1R7035 2 1 G SLP_S3_3R1 2

IN IN
2
0_5%_2
1
CSC0402_DY
S
C7022
0_5%_2_DY
2
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 0~49(PCB SCREW)
D
D
BOUNDARY SCAN TEST POINT

1 FIX1 1 FIX5
PVCORE PVBAT
FIX_MASK FIX_MASK
1 TP1
1 TP3 1 TP4 1 TP5
1 FIX2 1 FIX6
TP30
TP30 TP30 TP30
FIX_MASK FIX_MASK PVCORE_DGPU PVAXG
1 FIX3 1 FIX7
1 TP2
FIX_MASK FIX_MASK 1 TP6 1 TP7
TP30
FIX4 FIX8 PVADPTR TP30 TP30
1 1
FIX_MASK FIX_MASK
1 TP8 1 TP9 1 TP10
TP30 TP30 TP30

C C
PCB CPU GPU WLAN

1 S1 1 S10 1 S14 1 ST16
SCREW300_1000_1P
SCREW330_600_1P SCREW330_600_1P STDPAD_1.15_6-TOP
4.2MM
1 S2 1 S11 1 S15
SCREW300_1000_1P
SCREW330_600_1P SCREW330_600_1P
S3 S12
3G
1 1 ST17
SCREW300_1000_1P 1
SCREW330_600_1P STDPAD_1.15_6-TOP
S13 4.2MM
1 S5 1
SCREW300_1000_1P 1 ST18
B SCREW330_600_1P B
STDPAD_1.15_6-TOP
1 S6 4.2MM
SCREW300_1000_1P
1 S7
SCREW300_1000_1P
1 S8
SCREW300_1000_1P
FAN
1 ST21
1 S18
SCREW220_700_1P STDPAD_1.15_6.0_TOP
2MM
1 S20
SCREW540_1000_NP_1P
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 50-99(HALL SENSOR)
D
D
C P3V3AL C
1
R50
U50 100K_5%_2
VDD 1
2
3 GND
OUT 2 LID_SW#_3 OUT 21D3
1
1
MAG_MH248BESO_SOT23_3P D50
1
C50
1000PF_50V_2
SFI_SFI0402ML120C_LF_SMD_2P_DY
2
2
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 100~199(LED)
D POWER ON LED D
D154 BRIGHT WHEN SYSTEM IS POWER ON
D154 BLINK WHEN SYSTEM GO TO SLEEP
P5V0A
D154
TP100 R160
21B6 PWR_WLED# 1 1 2 1 2
IN
TP30
220_5%_2
19_217_T1D_CP1Q2QY_3T
C C
P3V3S
WIFI/WIMAX/3G/LTE LED
D156
TP104 R155
21D6 IN WL_OLED# 1 1 2 1 2
TP30
150_5%_2
HT_191UY
DC IN / BATTERY CHARGE LED

B D152 BRIGHT:BOTH AC-ADAPTER IS PLUGGED IN AND BATTERY IS FULL CHARGED B
D155 BRIGHT:WHILE CHARGING BATTERY FROM AC-ADAPTER
BLINK:LOW BATTERY
P5V0A
D152
TP102 R152
21B6 IN DCIN_WLED# 1 1 2 1 2
TP30
220_5%_2
19_217_T1D_CP1Q2QY_3T
P3V3AL
D155
A BAT_OLED# TP103 R154 A
21B6 1 1 2 1 2
IN
TP30
150_5%_2
HT_191UY
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 200~249(POWER CONN)

R253
REFERENCE 250~299(KB/TP CONN) 1 2
0_5%_2_DY
P3V3S
SCAN_OUT<17..0> CN250
21B3 34
OUT SCAN_OUT<16>
34
16 33 33
32 32
17 SCAN_OUT<17> 31 31 G G2
30 30 G G1
29 29
D 4 SCAN_OUT<4> 28 28
2 SCAN_OUT<2> 27 27
D
13 SCAN_OUT<13> 26 26
15 SCAN_OUT<15> 25 25
1 SCAN_OUT<1> 24 24
0 SCAN_OUT<0> 23 23
11 SCAN_OUT<11> 22 22
9 SCAN_OUT<9> 21 21
5 SCAN_OUT<5> 20 20 SCAN_IN<7..0>
6 SCAN_OUT<6> 19 21B3 20C6
19 IN 0 SCAN_IN<0> D250 1 2 SFI_SFI0402ML120C_LF_SMD_2P_DY
10 SCAN_OUT<10> 18 18
1 2
14 SCAN_OUT<14> 17 17
1 SCAN_IN<1> D251 1 2 SFI_SFI0402ML120C_LF_SMD_2P_DY
8 SCAN_OUT<8> 16 16
1 2
12 SCAN_OUT<12> 15 15
2 SCAN_IN<2> D252 1 1 2 2 SFI_SFI0402ML120C_LF_SMD_2P_DY
7 SCAN_OUT<7> 14 14
3 SCAN_OUT<3> 13 13
21B3 20D3 IN SCAN_IN<7..0> 7 SCAN_IN<7> 12 12
2 SCAN_IN<2> 11 11
3 SCAN_IN<3> 10 10
4 SCAN_IN<4> 9 9
0 SCAN_IN<0> 8 8
5 SCAN_IN<5> 7 7
6 SCAN_IN<6> D256 1 2 SFI_SFI0402ML120C_LF_SMD_2P_DY
6 SCAN_IN<6> 6 6
1 2
C 1 SCAN_IN<1> 5 C
5
4 4
21B6 IN CAPS_LED#_3 R250 1 2 200_5%_2 3 3
21D6 IN SCROLL_LED#_3 R251 1 2 200_5%_2_DY 2 2
21D6 IN NUM_LED#_3 R252 1 2 200_5%_2 1 1
PTWO_196094_34021_3_34P
KEYBOARD CONN
2
2
2
D258 D259 D260
1
1
1
SFI_SFI0402ML120C_LF_SMD_2P_DY SFI_SFI0402ML120C_LF_SMD_2P_DY SFI_SFI0402ML120C_LF_SMD_2P_DY
B B
P5V0S P3V3S
CN200
CN280 P5V0S 21D3 OUT PWR_SWIN#_3 1 1 G 3

G1 G1
2 2 G 4
1 1
2
21D3 20A5 IM_CLK_5 2 CN281
BI 2 ACES_50224_0020N_001_2P
21D3 20A5 IM_DAT_5 3
BI 3 1
2
1
4 4
21D3 20A7 IM_CLK_5 2
5 5 BI 3
2
G1 D200
21D3 20A7 IM_DAT_5
48A8 39C8 38C8 BI PCH_3S_SMCLK 6 6 BI 4
3 G
G2
4 G
48A8 39C8 38C8 PCH_3S_SMDATA 7
BI 7
1
8 8 ACES_50503_0044N_001_4P SFI_SFI0402ML120C_LF_SMD_2P_DY
1
2
G2
1
G2
D280
ACES_50503_0084N_001_8P
PHP_PESD5V2S2UT_SOT23_3P_DY
A
POWER CONN A
3
TOUCHPAD CONN
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3AL
REFERENCE 300~389(KBC)
1
R320
2
100K_5%_2
D300
NC
2
P3V3AL P3V3AL_R P3V3S 15D6 14D8 14C8 IN P5VAUXON 3 1 VCC_POR# OUT 21B6
F CLOSE PIN4
F
R318
1 2 BAT54_30V_0.2A
10UF_6.3V_5_DY
4.7UF_6.3V_3
1
1
2.2_5%_3
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
C313
C300
C301
C302
C303
C304
C312
C306
FOR ESD PROTECT
2
P3V3AL_EC
1
R301 0_5%_1
56D6 IN VGA_LCM_BKLTEN 1 2 LCM_BKLTEN OUT 21E6 R323
10_5%_2 P3V3AL_R P3V3AL_EC
R302 0_5%_1
50D7 IN PCH_LCM_BKLTEN 1 2
12
P3V3AL P3V3AL_EC P3V3S P3V3S
1
C323
GM: 100K
115
102
1
R344 R345
19
46
76
88
L300 0.1UF_16V_2
1 2 PM: 10K
4
100K_5%_2 10K_5%_2_DY R332
10UF_6.3V_5_DY
FBM_11_160808_121T U301
10K_5%_2 P3V3S
1
AVCC
VDD
VCC2
VCC3
VCC4
VCC5
2
VCC1
0.1UF_16V_2
2
C314
C305
2
E 104 VREF LRESET#/GPIOF7 7 BUF_PLT_RST#
IN 27C3 27C7 28C3 51A8 57A6 E
2 CLK_KBPCI 51A7
LCLK/GPIOF5
BI
R326 1
HW_I_ADC 97 3 LPC_3S_FRAME#
2
21E8 5B7 IN BI 27C3 47C3
10K_5%_2
GPIO90/AD0 LFRAME#/GPIOF6
10K_5%_2
21E8 5D5 HW_V_ADC 98 1 LPC_3S_AD<3> 27C3 47C3
IN GPIO91/AD1 LAD3/GPIOF4
BI
R312
21E8 5D3 BATT_IN 99 128 LPC_3S_AD<2> 27C3 47C3
IN 1 100
GPIO92/AD2 LAD2/GPIOF3
127 LPC_3S_AD<1>
BI
TP311 GPIO93/AD3 LAD1/GPIOF2
BI 27C3 47C3
34B5 EC_BKLTEN TP30 108 126 LPC_3S_AD<0> 27C3 47C3
OUT GPIO05/AD4 LAD0/GPIOF1
BI
AGND_KBC GM:3CELL OPEN LCM_BKLTEN 96 125 PCI_3S_SERIRQ
2
21E6 IN GPIO04/AD5 SERIRQ/GPIOF0
BI 27B7 47C2
3 CELL ID 5B8 ACPRES 95 8 PCI_3S_CLKRUN# 49A5 49B3
PM:6CELL STUFF IN GPIO03/AD6 GPIO11/CLKRUN#
OUT
R303 1 2 94 GPIO07/AD7 GPIO65/SMI# 91 TP324 TP30
21E6 5B7 HW_I_ADC 10K_5%_2 29 RUNSCI0#_3 51C7 52D6
IN HW_V_ADC EC_CTL3 101
ECSCI#/GPIO54
124 TP30 1
OUT
21E6 5D5 IN 32A8 OUT GPIO94/DA0 GPIO10/LPCPD#
21E6 5D3 BATT_IN TP314 1 105 121 EC_3S_A20GATE TP325 52C2
OUT SLP_S3#_3R TP30 106
GPIO95/DA1 GPIO85/GA20
122 KBRST#
OUT
49A1 45D3 14D2 14B8 14A6 13D2 13A2 IN GPIO96/DA2 KBRST#/GPIO86
OUT 52C2
P3V3AL
1
37B1 36B2 HDMI_HPD_EC 107

OUT
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
GPIO97/DA3
2 R300 1
C317
C316
C315
10K_5%_2
TP315 1 79 27 PWR_SWIN#_3 20B3
SCROLL_LED#_3 TP30 114
GPIO02 GPIO52/PSDAT3/RDY#
25 TP30 1 RSMRST#
OUT
P3V3AL 20C7 OUT GPIO16 GPIO50/PSCLK3/TDO TP306 OUT 21D1 49B7 49C2
TP316 1 6 11 EN_PVCORE
2
GPIO24 GPIO27/PSDAT2
OUT 11A8
20C7 NUM_LED#_3 TP30 109 10 USB_OC#_2 30A3
R346 OUT ACPRESENT 14
GPIO30/F_WP# GPIO26/PSCLK2
71 IM_DAT_5
IN
2 1 49A6 49A5 IN GPIO34/CIRRXL GPIO35/PSDAT1
BI 20A5 20A7
EC_PWRSW# TP307 1 15 72 IM_CLK_5 20A5 20A7
IN LOW_BAT#_3 TP30 80
GPIO36 GPIO37/PSCLK1
BI
100K_5%_2 49A8 OUT GPIO41/F_WP# P3V3AL
19B4 WL_OLED# 26
OUT USB_OC#_1 123
GPIO51/N2TCK
70 EC_SMB1_CLK
33C6 OUT GPIO67/N2TMS GPIO17/SCL1/N2TCK
BI 5D3 21D2 EC_SMB1_CLK 2 1
21D3 5D3 3.3K_5%_2
24A2 OUT EC_MUTE# 73 GPIO70 GPIO22/SDA1/N2TMS 69 EC_SMB1_DATA
BI 5D3 21D2 BI EC_SMB1_DATA
R322
2 1
21D3 5D3 3.3K_5%_2
D 22D7 OUT WOL_AUX_ON# 74 GPIO71 GPIO73/SCL2 67 EC_SMB2_CLK
BI 5A7 21D2 37C6 56D8 BI EC_SMB2_CLK
R321
2 1 D
56D8 37C6 21D3 5A7 1.8K_5%_2
TP317 1 75 GPIO72 GPIO74/SDA2 68 EC_SMB2_DATA
BI 5A7 21D2 37C3 56C8 BI EC_SMB2_DATA
R317
EC_SMB1 EC_SMB2 EC_SMB3 TP30 119 AOAC_ON# 21D2 27C2
56C8 37C3 21D3 5A7 BI R316 2 1 1.8K_5%_2
GPIO23/SCL3A
120 WLON#
BI 27C2 21D3 BI AOAC_ON# R334 2 1 10K_5%_2
GPIO31/SDA3A
BI 21D2 27B2 WLON#
1.BATTERY 1.CHARGE TP330 1 117 24 FLASH_OVERRIDE 47B7 47B8
27B2 21D3 BI R335 2 1 10K_5%_2
EC_ILIM_SEL TP30 112
GPIO20/TA2/IOX_DIN_DIO GPIO47/SCL4A
28 LID_SW#_3
OUT
32A8 OUT GP(I)O84/IOX_SCLK/XORTR# GPIO53/SDA4A
IN 18C4
2.GPU THERMAL 32A8 EC_CTL2 110 17 TP30 TP326 1 SB_USB_0
OUT 1 93
GPO82/IOX_LDSH/TEST# GPIO42/SCL3B/TCK
20
OUT 32A8
TP331 GPIO06/IOX_DOUT GPIO43/SDA3B/TMS TP30 TP303 1 SLP_S5#_3R
IN 14D2 49B3
3.CEC TP30 21 TP30 TP304 1 H_PROCHOT_EC
GPIO44/SCL4B/TDI
23
OUT 21B1
GPIO46/SDA4B/CIRRXM/TRST# TP30 TP305 1 SB_USB_2
OUT 30B6
TP318 1 91 GPIO81/F_WP#
47A6 21C8 EC_SPI_CS0# TP30 90 RSMRST# 21D3 49B7 49C2
OUT EC_SPI_CLK R342 1 33_5%_2
2 EC_SPI_CLK_R 92
F_CS0#
OUT
47A6 21C7 OUT F_SCK
1
82 EC_PW_ON# 14D8 15D4
EC_SPI_SO R340 1 33_5%_2
2 EC_SPI_SO_R 86
GPIO75/SPI_SCK
84 SB_USB_1
OUT
47A6 21C8 IN F_SDI_F_SDIO1 GPIO77/SPI_DI
OUT 33D8 R333
47A6 21C7 EC_SPI_SI R341 1 2 EC_SPI_SI_R 87 83 EC_CTL1 32A8 10K_5%_2
OUT F_SDIO_F_SDIO0 GPIO76/SPI_DO
OUT
33_5%_2
P3V3A 44 VCORF
2
P3V3A
R313 2 10K_5%_2
AGND
GND1
GND2
GND3
GND4
GND5
GND6
1
1
U300
EC_SPI_CS0# 1 8 C310 WINB_NPCE885LA0DX_LQFP_128P
47A6 21D6 IN /CS VCC
1
7 1 R314 2 3.3K_5%_2 1UF_6.3V_2

0.1UF_16V_2
EC_SPI_SO 2
18
45
78
89
116
5
103
21C8 21C6 OUT DO_IO1 /HOLD_IO3
47A6
47A6 1 2 3 6
C309
EC_SPI_CLK 21C7 21D6

4
/WP_IO2 CLK
5 EC_SPI_SI
IN
2
R330 3.3K_5%_2 GND DI_ID0
IN 21C6 21C7
PAD319
47A6
2 2 1
1
WINB_W25Q32BVSSIG_SOIC_8P
2
C POWERPAD1X1M C
P3V3A P3V3A
R315 10K_5%_2_DY
1 2
U302
EC_SPI_CS1# 1 8 AGND_KBC
0.1UF_16V_2_DY
47A6 IN /CS VCC

1
EC_SPI_SO 2 71 R319 2 3.3K_5%_2_DY

21C8 21C6 OUT DO_IO1 /HOLD_IO3
47A6
1 2 3 6
C318
47A6 EC_SPI_CLK 21C7 21D6

4
/WP_IO2 CLK
5 EC_SPI_SI
IN
R331 3.3K_5%_2_DY GND DI_ID0
IN 21C6 21C7
47A6
WINB_W25Q32BVSSIG_SOIC_8P_DY
2
41D6 11C7 OUT CPU_PROCHOT#
3
U301 Q300
SCAN_OUT<17..0> OUT 20D6
D
TP319 1 31 GPIO56/TA1 KBSOUT0/GPOB0/JENK# 53 SCAN_OUT<0> 0 G 1 H_PROCHOT_EC IN 21D3
FAN_TACH1 IN 21B6 40C8 40C8 21B6 IN FAN_TACH1 TP30 63 GPIO14/TB1 KBSOUT1/GPIOB1/TCK 52 SCAN_OUT<1> 1
1
S
SCAN_OUT<2>
1
14A6 10A5 SA_PG 64 51 2

IN GPIO01/TB2 KBSOUT2/GPIOB2/TMS
50 SCAN_OUT<3>
C311 KBSOUT3/GPIOB3/TDI 3 SSM3K7002BFU R324
USB_OC#_0 TP320 1 32 49 SCAN_OUT<4> 4 100K_5%_2
2
32A6 IN GPIO15/A_PWM KBSOUT4/GPOB4/JEN0#
680PF_50V_2 PCH_PWROK TP30 118 48 SCAN_OUT<5> 5
49B7 49A6 OUT GPIO21/B_PWM KBSOUT5/GPIOB5/TDO
19A7 BAT_OLED# 62 47 SCAN_OUT<6> 6
OUT GPIO13/C_PWM KBSOUT6/GPIOB6/RDY#
2
DCIN_WLED# 65 43 SCAN_OUT<7> 7
2
19A7 OUT GPIO32/D_PWM KBSOUT7/GPIOB7

TP321 1 22 GPIO45/E_PWM KBSOUT8/GPIOC0 42 SCAN_OUT<8> 8
40C6 FAN1_PWM TP30 81 41 SCAN_OUT<9> 9
OUT GPIO66/G_PWM KBSOUT9/GPOC1/SDP_VIS#
SCAN_OUT<10>
B 20C7 OUT CAPS_LED#_3 66 GPIO33/H_PWM KBSOUT10_P80_CLK/GPIOC2 40 10 B
19C7 PWR_WLED# 16 39 SCAN_OUT<11> 11
OUT GPIO40/F_PWM KBSOUT11_P80_DAT/GPIOC3
38 SCAN_OUT<12>
KBSOUT12/GPIO64 12
KBSOUT13/GPIO63 37 SCAN_OUT<13> 13
TP322 1 111 GP(I)O83/SOUT_CR/TRIST# KBSOUT14/GPIO62 36 SCAN_OUT<14> 14
TP323 1
TP30 113 GPIO87/CIRRXM/SIN_CR KBSOUT15/GPIO61/XOR_OUT 35 SCAN_OUT<15> 15
TP30 GPIO60/KBSOUT16 34 SCAN_OUT<16> 16
GPIO57/KBSOUT17 33 SCAN_OUT<17> 17
49B3 EC_32KHZ 77
IN LAN_RST# 30
GPIO00/EXTCLK
54 SCAN_IN<0> SCAN_IN<7..0>
22B5 0 20C6 20D3
OUT GPIO55/CLKOUT/IOX_DIN_DIO KBSIN0/GPIOA0/N2TCK
55 SCAN_IN<1>
IN
KBSIN1/GPIOA1/N2TMS 1
KBSIN2/GPIOA2 56 SCAN_IN<2> 2
21F4 VCC_POR# 85 57 SCAN_IN<3> 3
IN VCC_POR# KBSIN3/GPIOA3
58 SCAN_IN<4>
KBSIN4/GPIOA4 4
R339 KBSIN5/GPIOA5 59 SCAN_IN<5> 5
52C2 41D5 BI H_PECI 1 2 EC_PECI 13 PECI KBSIN6/GPIOA6 60 SCAN_IN<6> 6
43_5%_2 12 VTT KBSIN7/GPIOA7 61 SCAN_IN<7> 7
P1V05S WINB_NPCE885LA0DX_LQFP_128P
A A
INVENTEC
TITLE
Block Diagram
SIZE CODE DOC.NUMBER REV

C CS 1310xxxxx-0-0 X01
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 400~499(LAN)
D
P3V3A Q400 P3V3A_LAN PAVDDVCO_LAN D
DIODES_DMP2305U_SOT23_3P PAD400
10UF_6.3V_5_DY
S D 1 2
0.1UF_16V_2
4.7UF_6.3V_3
S D 1 2
1UF_6.3V_2
1
1
CSC0402_DY
1UF_6.3V_2_DY
0.047UF_16V_2
POWERPAD_2_0610
1
C403
C405
G
C400
C401
C402
C404
0.1UF_16V_2
C424
C425
G
2
1
2
2
WOL_AUX_ON# 1 R400 2
21D6 IN
100K_5%_2 R402
0_5%_3
PDVDDL_LAN PAVDDL_LAN
2
1UF_6.3V_2
1
1
0.1UF_16V_2
C427
C426
PVLX_LAN C423
0.1UF_16V_2
48C7 48D7 48D8
2
C FOR LDO MODE C
2 R403 1
10K_5%_2 PCIE_LAN_TX_DN IN 48D8
2 R404 1 PCIE_LAN_TX_DP IN 48D8
CLKREQ_LAN# 10K_5%_2_DY CLK_PCIE_LAN_DP IN 48C7
OUT CLK_PCIE_LAN_DN IN 48C7
41
40
39
38
37
36
35
34
33
32
31
P3V3A_LAN
P3V3S U400
LED_0
DVDDL_REG
AVDDL
AVDDL
LX
RX_P
REFCLK_P
GND
RX_N
REFCLK_N
LED_1
2
1
LAN_RST# 2
VDD33
TX_P
30 PCIE_LAN_RX_C_DP C421 1 2 0.1UF_16V_2 PCIE_LAN_RX_DP OUT 48D8
R401 21B6 IN PERSTN 29 PCIE_LAN_RX_C_DN 1 2 PCIE_LAN_RX_DN
PCIE_WAKE# 3 TX_N C422 0.1UF_16V_2 OUT 48D8
PAVDDL_LAN 30K_5%_2 OUT WAKEN 28
PVLX_LAN PDVDDL_LAN 4 CLKREQN NC
27
L400 R406 5 ISOLATN TESTMODE
PAVDDH_LAN
26
10UF_6.3V_3_DY
1
6
0.1UF_16V_2_DY
1 2 1 2 SMDATA
1000PF_50V_2_DY
1UF_6.3V_2
AVDDL_REG 25
1
1
22A5 PAVDDH_LAN IN LAN_X1 7 XTLO SMCLK
24
1
LQM21PN2R2MC0D_DY LAN_X2 8
C412
C413
RSC_0603_DY 22A5 PPS

IN 9
XTLI
LED_2
23
C406
C407
0.1UF_16V_2
AVDDH_REG 22
C408
R405
1UF_6.3V_2
10
1
1 2 RBIAS AVDDH
21
0.1UF_16V_2
1
2.37K_1%_2 TRXN3
AVDD33
C420
B C414 B
AVDDL
AVDDL
TRXN0
TRXN1
TRXN2
2
TRXP0
TRXP1
TRXP2
TRXP3
C415
0.1UF_16V_2
2
2
FOR SW MODE 23D6 ATHEROS_AR8161_BL3A_R_QFN_40P
2
2
LAN_TRD0_DP
12
13
14
15
16
17
18
19
20
23C8
11
BI LAN_TRD0_DN
23C8 BI
23B8 23D6 LAN_TRD1_DP
23C6
BI LAN_TRD1_DN
23B8 BI
23B8 23C6 LAN_TRD2_DP
BI LAN_TRD2_DN P3V3A_LAN
23B8 BI
23B8 LAN_TRD3_DP
BI LAN_TRD3_DN
23B8 BI
1
PAVDDL_LAN
C418 C419
1
0.1UF_16V_2
LAN_X1 1UF_6.3V_2_DY
OUT 22B5
LAN_X2 C416
2
OUT 22B5 C417
X400 0.1UF_16V_2 0.1UF_16V_2
1 2
2
1
1
33PF_50V_2
33PF_50V_2
25MHZ
C409
C410
A C417:8161 STUFF 8162 OPEN A

2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 400~499(LAN)
LAN_TD_DP JACK470
23D3 23C2 1
IN LAN_TD_DN
TX+
23D3 23C2 2
IN LAN_RD_DP
TX-
23C3 23B2 3 G1
IN LAN_C_DP
RX+ G
23C2 23B2 4 G2
IN LAN_C_DN
P4 G
23C2 23B2 5
IN LAN_RD_DN
P5
23C3 23B2 6
IN LAN_D_DP
RX-
23C2 23B2 7
IN LAN_D_DN
P7
23C2 23B2 8
D IN P8
SANTA_130456_051_8P D
U471
2 TCT TCT 15
23C8 22B5 LAN_TRD0_DN 3 14 LAN_TD_DN 23C2 23D5
IN LAN_TRD0_DP
TD- TX-
LAN_TD_DP
OUT
P3V3AL 23C8 22B5 1 16 23C2 23D5
IN TD+ TX+ OUT
7 RCT RCT 10
23B8 22B5 LAN_TRD1_DN 8 9 LAN_RD_DN 23B2 23D5
1 U460 6
IN LAN_TRD1_DP
RD- RX-
LAN_RD_DP
OUT
23B8 22B5 6 11 23B2 23D5
I/O 1 I/O 4 IN RD+ RX+ OUT
1
2 5
1
4 12
75_5%_3
75_5%_3
GND VDD NC NC
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
3 4 R476 LAN_C_DN
1
5 13 2 1 23B2 23D5
I/O 2 I/O 3 NC NC OUT
2 R474
2 R475
C478
C479
RSC_0603_DY
PANJIT_PJSRV05_4_DSSOT236P BOTH_TS21C_HF_SOP_16P
C460
2 R478 1 LAN_C_DP
OUT 23B2 23D5
RSC_0402_DY
2
2 R477 1 LAN_D_DN
2
OUT 23B2 23D5

RSC_0603_DY
2 R479 1 LAN_D_DP
OUT 23B2 23D5
C RSC_0402_DY
C
U470
23D6 22B5 LAN_TRD0_DP 1 24 LAN_TD_DP 23D3 23D5
IN TD+ TX+ OUT
23D6 22B5 LAN_TRD0_DN 2 23 LAN_TD_DN 23D3 23D5
IN TD1- TX1- OUT
3 TDCT TXTC 22
4 TDCT TXTC 21
23C6 22B5 LAN_TRD1_DP 5 20 LAN_RD_DP 23C3 23D5

IN TD2+ TX2+ OUT
23C6 22B5 LAN_TRD1_DN 6 19 LAN_RD_DN 23C3 23D5
IN TD2- TX2- OUT
22B5 LAN_TRD2_DP 7 18 LAN_C_DP 23C2 23D5
IN TD3+ TX3+ OUT
22B5 LAN_TRD2_DN 8 17 LAN_C_DN 23C2 23D5
IN TD3- TX3- OUT
9 TDCT TXTC 16
B 10 TDCT TXTC 15 B
22B5 LAN_TRD3_DP 11 14 LAN_D_DP 23C2 23D5
IN TD4+ TX4+ OUT
22B5 LAN_TRD3_DN 12 13 LAN_D_DN 23C2 23D5
IN TD4- TX4- OUT
P3V3AL BOTH_NA0069RLF_SMD_24P
1
U461
75_5%_3
75_5%_3
75_5%_3
75_5%_3
1 I/O 1 I/O 4 6
2 5
2 R470
2 R471
2 R472
2 R473
GND VDD
3 I/O 2 I/O 3 4
1
0.1UF_16V_2
PANJIT_PJSRV05_4_DSSOT236P
C461
2
1
CSC0402_DY
CSC0402_DY
CSC0402_DY
CSC0402_DY
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
1
1
1UF_6.3V_2
C475
A A
C480
C481
C482
C483
C470
C471
C472
C473
C474
1000PF_2000V_6
2
2
CSC0402_DY
10PF_50V_2
1
1
C476
C477
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 500~549(AUDIO CODEC)

CLOSE TO PIN27
P5V0S P5V0S_AUDIO_AVDD
1
C519 C513
1
R515
C512 1 2
C503
2.2UF_6.3V_3 0.1UF_16V_2 0_5%_3
AGND_AUDIO 2.2UF_6.3V_3 10UF_6.3V_3
2
BLM18PG121SN1(6014B0041601_0603)
2
AGND_AUDIO
D P5V0S_AUDIO_AVDD
HP_R
1
OUT 25B3
D
C502 HP_L OUT 25A3
P5V0S BLM18PG121SN1(6014B0041601_0603) 2.2UF_6.3V_3 MIC_REF_L OUT 25D3 P5V0S_AUDIO_AVDD
R516 P5V0S_PVDD MIC_REF_R OUT 25D3
4.7UF_6.3V_3
2
1 2
0.1UF_16V_2
1
1
10UF_6.3V_3_DY
0.1UF_16V_2_DY
C536
C500
4.7UF_6.3V_3
4.7UF_6.3V_3
0_5%_3
36
35
34
33
32
31
30
29
28
27
26
25
0.1UF_16V_2
1
1
0.1UF_16V_2
1
1
C505
C507
C504
C532
C506
C501
2
2
U500
CBN
HP-OUT-L
MIC1-VREFO-L
HP-OUT-R
MIC1-VREFO-R
MIC2-VREFO
VREF
CBP
CPVEE
LDO-CAP
AVSS1
AVDD1
2
2
2
2
37 AVSS2 LINE1-R 24
AGND_AUDIO
38 AVDD2 ANALOG LINE1-L 23
39 PVDD1 MIC1-R 22 MIC_R BI 25C2 AGND_AUDIO

25B8 OUT SPK_OUT_L_P 40 SPK-L+
DIGITAL MIC1-L 21 MIC_L BI 25C2
C C
25B8 OUT SPK_OUT_L_N 41 SPK-L- MONO-OUT 20
R514
42 PVSS1 JDREF 19 1 2
(THERMAL PAD 4X4 VIAS)
43 PVSS2 Sense-B 18 20K_1%_2
25B8 OUT SPK_OUT_R_N 44 SPK-R- MIC2-R 17

AGND_AUDIO
25B8 OUT SPK_OUT_R_P 45 SPK-R+ MIC2-L 16
46 PVDD2 LINE2-R 15
47 14 CLOSE TO PIN13
4.7UF_6.3V_3
EAPD LINE2-L
0.1UF_16V_2
1
GPIO0/DMIC-DATA
R500 MICS
GPIO1/DMIC-CLK
48 13 1 2 25C5
SPDIFO Sense A IN
C529
C531
20K_1%_2
SDATA-OUT
49
SDATA-IN
GND
BIT-CLK
DVDD-IO
R501
PCBEEP
HPS
RESET#
1 2 25B2
DVDD1
DVSS2
IN
SYNC
39.2K_1%_2
2
PD#
REA_ALC269Q_VB6_CGT_QFN_48P
B C520
B
P3V3S R507
1 2 1 2 PCSPKR_PCH_3 IN 47C8
C514
10
12
1
11
2 1 47K_1%_2 C521
0.1UF_16V_2 2 1
CSC0402_DY
0.1UF_16V_2
100PF_50V_2
1UF_6.3V_2
1
C515 1 R506 2
C508
C509
2 1 4.7K_1%_2
CSC0402_DY HDA_3S_RST# IN 47C7

2
C516 HDA_3S_SYNC IN 47C7

2 1
HDA_R_SDIN0 1 R502 2 HDA_3S_SDIN0 IN 47B7
CSC0402_DY 22_5%_2
C517 HDA_R_BITCLK 1 R503 2 HDA_3S_BITCLK
2 1 IN 47C7
SHORT_0402 HDA_3S_SDOUT IN 47B7
CSC0402_DY MIC_IN_DATA EC_MUTE#
TIED UNDER OR NEAR CODEC BI IN 21D6
R505
PAD500 34B3 BI MIC_IN_CLK 1 2 MIC_IN_CLK_R P3V3A
AGND_AUDIO 1 1 2
2
100_5%_2
POWERPAD1X1M
1
A A
22PF_50V_2_DY
C523
0.1UF_16V_2
1UF_6.3V_2
1
1
CSC0402_DY
C518
C510
C522
AGND_AUDIO
2
RESERVE FOR EMI

2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERCE 600~649(JACK/MIC/SPEAKER)
AUDIO JACKS
D MIC_REF_L 24D3
IN D
MIC_REF_R IN 24D3
MICPHONE
2
R605 R604
2.2K_5%_2 2.2K_5%_2
JACK600 TP30
1
5 TP607
14 MICS OUT C606 2.2UF_6.3V_3
24B2 R602
3 1 1 2 1K_5%_2 1 2 MIC_R BI 24C2
6
TP30 TP605
2 1 1 2 1 2 MIC_L BI 24C2
11 1K_5%_2 C607 2.2UF_6.3V_3
TP30 TP604 R603
G1
TP30
G2 TP606
SINGA_2SJ_T351_019_6P
1
C600 C601
C AGND_AUDIO C
CSC0402_DY CSC0402_DY
2
EMI CAPACITORS TO CLOSE TO JACK SIDE
AGND_AUDIO
D600
2
3
B 1 B
INTERNAL SPEAKERS AGND_AUDIO

HEADPHONE
NOTE:SPK TRACE SHOULD 30~40 MILS WIDTH CN600 JACK601
24C7 IN SPK_OUT_L_P 4 4 G2 G2 R601 TP603 5
24C7 SPK_OUT_L_N 120_5%_2 24B2 HPS 1 TP30 4
IN SPK_OUT_R_N
3 3 G1 G1
HP_R 1 2
OUT
24C7 IN 2 2 24D3 IN TP601 1 3
24C7 IN SPK_OUT_R_P 1 1 TP30 6
24D3 IN HP_L 1 2 TP600 1 2
ACES_50224_0040N_001_4P TP30 1 TP30 1
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
R600 TP602 G1
470PF_50V_2_DY
120_5%_2
470PF_50V_2_DY
1
G2
1
1
C602
C603
C604
C605
SINGA_2SJ_T351_019_6P
470PF_50V_2_DY
470PF_50V_2_DY
C609
C608
1
C611
C610
2
2
2
AGND_AUDIO
2
A A
RESERVE FOR EMI
RESERVE FOR EMI

AGND_AUDIO
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERNCE 900~999(CARDREADER)
D
D
SD_CMD BI 26B3
R901
SD_R_CLK 1 2 SD_CLK 26B3
BI
SHORT_0402
RESERVE FOR EMI
SD_CD#
BI 26B3
18
17
16
15
14
13
C P3V3S_CR C
U900 SP10
GPIO0
SP9
SP8
SP7
SP6
1
C905 C906
19 SP11 SP5 12
2.2UF_6.3V_3 0.1UF_16V_2
26B3 BI SD_D3 20 SP12 SP4 11 SD_D0 BI 26B3
2
26B3 BI SD_D2 21 SP13 SP3 10 SD_D1 BI 26B3
CN900
22 SP14 SP2 9 26C7 BI SD_D3 1 CD-DAT3
26D5 BI SD_CMD 2 CMD
23 XD_D7 SP1 8 SD_WP BI 26B3 3 VSS1
4 VDD
24 V18 XD_CD# 7 26C5 BI SD_CLK 5 CLK
1
CARD_3V3
6 VSS2
SD_D0 7
SDREG
26C5
3V3_IN
BI DAT0
RREF
C901 25 SD_D1 8
TML 26C5 BI DAT1
DM
DP
1UF_6.3V_2 26C7 BI SD_D2 9 DAT2

REA_RTS5129_QFN_24P 26C5 BI SD_CD# 10 CARD_DETECT
SD_WP 11 G1
2
26B5 BI WRIT_PROTECT G1
B B
61
G2
2
5
1
G2
C904
TAI_PSDAT0_09GLBS1ZZ4H1_11P
1UF_6.3V_2
R900
1 2 CARD_REF
2
6.2K_1%_2
P3V3S_CR
51B2 BI USB_CR_DN
1
51B2 BI USB_CR_DP
C902
0.1UF_16V_2
2
P3V3S
PAD900
1 1 2
2 P3V3S_CARD
A POWERPAD_2_0610 A
1
C900
C903
4.7UF_6.3V_3
0.1UF_16V_2
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 1300~1349(WLAN)
D
D
SUPPORT AOAC:OPEN SUPPORT AOAC:STUFF
P3V3S
1
P3V3A
P1V5S
R1304
Q1300
0_5%_5 1 4
D S
2
2
5
1
6 G 3
PMOS_4D1S
C1302 C1304 C1307
AM3423P_DY
1
10UF_6.3V_3 0.1UF_16V_2 CSC0402_DY
C1305 C1301
2
2
C1306
0.1UF_16V_2 10UF_6.3V_3 CSC0402_DY
2
AOAC_ON# IN 21D2 21D3
R1300 CN1300
C 49B3 49A5 22B5 PCIE_WAKE# 1 2 0_5%_2 1 2 C
BI WAKE# 3.3V
3 CH_DATA GND 4
52B6 27B7 BTIFON# 1 R1301 2 0_5%_2 5 6
BI CH_CLK 1.5V
48D8 48D7 48B7 CLKREQ_WLAN# 7 8 LPC_3S_FRAME# 21E3 47C3
IN CLKREQ# LPC_FRAME# IN
9 10 LPC_3S_AD<3> 21E3 47C3
GND LPC_AD3 IN
48B7 CLK_PCIE_WLAN_DN 11 12 LPC_3S_AD<2> 21E3 47C3
IN REFCLK- LPC_AD2 IN
48B7 CLK_PCIE_WLAN_DP 13 14 LPC_3S_AD<1> 21E3 47C3
IN REFCLK+ LPC_AD1 IN
15 16 LPC_3S_AD<0> 21E3 47C3
GND LPC_AD0 IN
57A6 51A8 28C3 27C3 21E3 BUF_PLT_RST# 17 18
IN LPC_DEBUG_RST# GND
51A7 CLK_PCI_DEBUG 19 20
IN LPC_PCI_CLK W_DISABLE#
1 2 21 22 BUF_PLT_RST# 21E3 27C7
GND PERST# IN
3
48D8 PCIE_WLAN_RX_DN C1303 CSC0402_DY 23 24 28C3 51A8
OUT PERN0 +3.3VAUX
57A6 Q1301
48D8 PCIE_WLAN_RX_DP 25 26
OUT PERP0 GND
D
27 28
GND 1.5V 48D3 G 1 WLON# IN 21D2 21D3
29 30 PCH_3A_ALERT_CLK 48D2
RESERVE FOR EMI GND SMB_CLK BI
48D8 PCIE_WLAN_TX_DN 31 32 PCH_3A_ALERT_DAT 48D2 48D3
IN BI
S
PETN0 SMB_DATA
48D8 PCIE_WLAN_TX_DP 33 34
IN PETP0 GND
SSM3K7002BFU
35 36 USB_WLAN_DN 51B2
GND USB_D- BI
2
37 38 USB_WLAN_DP 51B2
Reserved USB_D+ BI
39 Reserved GND 40
41 Reserved LED_WWAN# 42
43 Reserved LED_WLAN# 44
B 0_5%_2
45 +V3AL LED_WPAN# 46 B
BTIFON# 1 R1302 2 47 48
52B6 27C7 BI PWR_LED# 1.5V
49 NUM_LED# GND 50
PCI_3S_SERIRQ 1 R1303 2 51 52
47C2 21E3 IN 0_5%_2_DY CAPS_LED# 3.3V
G1 G G G2
BELLW_80003_4021_52P
A A
MINI CARD 1(WLAN)

INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 1400~1499(3G) P1V5S
1
0.1UF_16V_2
0.1UF_16V_2
22UF_6.3V_5
C1410
C1411
C1412
2
2
P3V3S
D
D
1
C1402 C1401 C1400
CN1400
1 WAKE# 3.3V 2 0.1UF_16V_2 0.1UF_16V_2
3 4 22UF_6.3V_5
CH_DATA GND
2
5 CH_CLK 1.5V 6
7 CLKREQ# LPC_FRAME# 8 UIM_PWR OUT 28A4 28B6
9 GND LPC_AD3 10 UIM_DATA BI 28A6
11 REFCLK- LPC_AD2 12 UIM_CLK BI 28A4
13 REFCLK+ LPC_AD1 14 UIM_RST OUT 28A4
15 GND LPC_AD0 16
17 LPC_DEBUG_RST# GND 18
CLOSE TO CONN SIDE 19 LPC_PCI_CLK W_DISABLE# 20 3G_OFF#
21 GND PERST# 22 BUF_PLT_RST# IN 21E3 27C3
47B3 SATA_MINICARD_RX_DP C1405 1 2 0.01UF_50V_2 SATA_MINICARD_C_RX_DP 23 24 27C7 51A8
BI SATA_MINICARD_RX_DN
PERN0 +3.3VAUX
57A6
47B3 BI
C1406 1 2 0.01UF_50V_2 SATA_MINICARD_C_RX_DN 25 PERP0 GND 26
27 GND 1.5V 28
3
29 GND SMB_CLK 30 TP24 1
SATA_MINICARD_TX_DN C1407 1 2 0.01UF_50V_2 SATA_MINICARD_C_TX_DN 31 32 TP24 1 TP1400 Q1400
47B3 BI PETN0 SMB_DATA
SATA_MINICARD_TX_DP 0.01UF_50V_2 SATA_MINICARD_C_TX_DP TP1401
D
47B3 C1408 1 2 33 34
BI PETP0 GND
USB_3G_DN G 1 3G_ON# IN 52D6
C 35 GND USB_D- 36
BI 51B2 C
37 38 USB_3G_DP BI 51B2
S
Reserved USB_D+
39 Reserved GND 40
41 42 SSM3K7002BFU
Reserved LED_WWAN#
2
43 Reserved LED_WLAN# 44
45 +V3AL LED_WPAN# 46
47 PWR_LED# 1.5V 48
1 TP24 49 NUM_LED# GND 50
MSATA_DET TP1402 51 52
52D6 OUT CAPS_LED# 3.3V
G1 G G G2
BELLW_80003_4021_52P
B P3V3S B
U1400
28D3 28A4 IN UIM_PWR 1 VIO VIO 6
2 GND VBUS 5
3 VIO VIO 4
NXP_IP4223CZ6_SOT457_6P_DY
CN1401
P5 GND VCC P1 UIM_PWR IN 28B6 28D3
P6 VPP RST P2 UIM_RST IN 28C3
28D3 BI UIM_DATA P7 I_O CLK P3 UIM_CLK BI 28C3
G2 G G G1
TAI_PMPAT5_06GLBS7NI4H1_6P
4.7UF_6.3V_3
A A
1
1
0.1UF_16V_2
C1404
C1403
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 1700~1749(HDD)
REFERENCE 1750~1799(ODD)
SATA HDD
D 1
CN1700
GND
47C3 SATA_HDD_TX_DP C1704 1 2 0.01UF_50V_2 SATA_HDD_TX_C_DP 2 D
IN SATA_HDD_TX_DN 0.01UF_50V_2 SATA_HDD_TX_C_DN
A+
47C3 IN C1705 1 2 3 A-
4 GND
47C3 SATA_HDD_RX_DN C1700 1 2 0.01UF_50V_2 SATA_HDD_RX_C_DN 5
OUT SATA_HDD_RX_DP 0.01UF_50V_2 SATA_HDD_RX_C_DP
B-
47C3 OUT C1701 1 2 6 B+
7 GND
8 V3.3
PLACE CLOSE TO CONNECTOR(<100MILS) 9 V3.3
10 V3.3
P5V0S 11 GND
12 GND
40MIL 13 GND
14 V5
15
22UF_6.3V_5
22UF_6.3V_5
0.1UF_16V_2
V5
1
16 V5
C1706
C1703
C1702
17 GND
18 RESERVED
19 GND
20 V12
2
21 V12 G1 G1
22 V12 G2 G2
SANTA_194911_1_22P
C C
P5V0S
1
P3V3S
R1752 C1754
4
CSC0402_DY
1M_5%_2_DY
1
1
S
G
R1751
1 2 PMOS_4D1S
2
R1750 R1754
10K_5%_2_DY 0_5%_6
100K_5%_2_DY
Q1751
2
TPC6111_DY D
2
Q1750
6
5
2
1
D
B 52D2 IN SATA_ODD_PWREN 1 G B
C1758
S
2 1
SSM3K7002BFU_DY
22UF_6.3V_5
22UF_6.3V_5
0.1UF_16V_2
2
1
CSC0402_DY
C1757
C1756
C1755
2
CN1750
P6 GND
P5 GND
51C7 51B6 OUT SATA_ODD_DA# P4 MD
P3 +5V
P2 +5V
SATA_ODD_PRSNT#
SATA ODD
52D7 52B6 P1
OUT DP
A S7 GND A
47B3 OUT SATA_ODD_RX_DP C1750 1 2 0.01UF_50V_2 SATA_ODD_RX_C_DP S6 B+
47B3 OUT SATA_ODD_RX_DN C1751 1 2 0.01UF_50V_2 SATA_ODD_RX_C_DN S5 B-
S4 GND
47B3 IN SATA_ODD_TX_DN C1753 1 2 0.01UF_50V_2 SATA_ODD_TX_C_DN S3 A-
47B3 IN SATA_ODD_TX_DP C1752 1 2 0.01UF_50V_2 SATA_ODD_TX_C_DP S2 A+ G G1
S1 GND G G2
SYN_127382FR013G212ZR_13P
PLACE CLOSE TO CONNECTOR(<100MILS)
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 2000~2099(USB)
D
D
P5V0A_USB3
CN2002
1 1
51C2 BI USB_P2_DN 2 2
51C2 BI USB_P2_DP 3 3 G1 G1
4 4 G2 G2
ACES_50224_0040N_001_4P
C C
P5V0A
PAD2000 P5V0A_USB_PW1
1 1 2
2
1
POWERPAD_2_0610
C2000 C2001
22UF_6.3V_5_DY 1UF_6.3V_2
2
B P5V0A_USB3 B
U2000
1 GND OUT 8
1
2 IN OUT 7
3 6 R2000
SB_USB_2 IN OUT
C2002 C2003
21D3 4 5
IN EN OC#
22UF_6.3V_5
ROHM_BD82020FVJ_TSSOP_8P 0.1UF_16V_2
1
RSC_0402_DY
2
C2004
CSC0402_DY
P3V3AL
2
1
R2001
10K_5%_2
USB_OC#_2
2
OUT 21D3
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 2400~2499
D
D
C C
REMOVE USB3.0 CONTROLLER IC
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 2400~2499(USB3.0)
D
D
P5V0A_USB2 P5V0A_USB1
1
R2448
0_5%_5_DY
2
USB2.0 FROM SLEEP&CHARGE IC
USB_IC_DP 1 R2446 2
32A8 BI 0_5%_2
1
C 32A8 BI USB_IC_DN 1 2 0_5%_2 C
C2427
R2447 C2432
C2426
0.1UF_16V_2 1000PF_50V_2
22UF_6.3V_5
L2404
2
USB2.0 FROM PCH WCM_2012_900T 1
CN2401
VBUS
USB_P0_DN 1 R2459 2 USB_P0_R1_DN USB_P0_R_DN USB_P0_L_DN
32B8 BI 0_5%_2 R2455 1 2 0_5%_2 1 2 2 D-
51C2
BI USB_P0_DP 1 2 0_5%_2 USB_P0_R1_DP R2454 1 2 0_5%_2 USB_P0_R_DP 4 3 USB_P0_L_DP 3 D+
R2460 L2432 4 PGND
51C6 BI USB3_PCH_RX1_DN 4 3 USB3_SSRX1_DN 5 SSRX-
51C6 BI USB3_PCH_RX1_DP 1 2 USB3_SSRX1_DP 6 SSRX+ G G1
7 G2
L2440 WCM_2012_900T
GND G
32B4 BI USB3_PCH_TX1C_DN 1 2 USB3_SSTX1_DN 8 SSTX- G G3
32B4 BI USB3_PCH_TX1C_DP 4 3 USB3_SSTX1_DP 9 SSTX+ G G4
WCM_2012_900T
LOTES_AUSB0026_P002A_9P
C2440
51C6 BI USB3_PCH_TX1_DN 1 2 USB3_PCH_TX1C_DN BI 32B6
0.1UF_16V_2
B C2441 B
51C6 BI USB3_PCH_TX1_DP 1 2 USB3_PCH_TX1C_DP BI 32B6
0.1UF_16V_2
USB_P0_DN 1 R2456 2 0_5%_2

51C2 32C8 BI P5V0A
USB_P0_DP 1 R2457 2 0_5%_2
51C2 32C8 BI P3V3AL
1
C2442
21D6 IN EC_ILIM_SEL R2408
0.1UF_16V_2
10K_5%_2
1
4
3
2
U2401
2
DP_OUT
DM_OUT
ILIM_SEL
IN
PWPD 17
21D3 IN SB_USB_0 5 DSC ILIM0 16
21C3 IN EC_CTL1 6 CTL1 ILIM1 15
EC_CTL2
1
21D6 7 14
IN EC_CTL3
CTL2 GND
USB_OC#_0
8 13
DM_IN
21E6 21B6
DP_IN
IN CTL3 FAULT# OUT R2435 R2436

OUT
NC
A 20K_1%_2
A
P5V0A 0_5%_2_DY
TI_TPS2541A_QFN_16P
9
10
11
12
2
2
R2458 P5V0A_USB1
1 2
100K_5%_2_DY
32C7 BI USB_IC_DP
32C7 BI USB_IC_DN
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 2400~2499(USB3.0)
P5V0A_USB2
1
P5V0A
USB 3.0 CONNECTOR

D
C2450
+
CURRENT LIMIT 2.5A 330UF_6.3V
U2404
2
1 GND OUT 8
2 IN OUT 7
3 IN OUT 6 P3V3AL P5V0A_USB2
21C3 IN SB_USB_1 4 EN OC# 5
1
1
ROHM_BD82024FVJ_TSSOP_8P
C2454 R2409
1
47UF_6.3V_5
10K_5%_2 C2452
2
2
USB_OC#_1 C2453
OUT 21D6
0.1UF_16V_2 1000PF_50V_2
2
CN2402
C L2405 WCM_2012_900T 1 VBUS C
51C2 BI USB_P1_DN 1 2 USB_P1_L_DN 2 D-
USB2.0 FROM PCH 51C2 BI USB_P1_DP 4 3 USB_P1_L_DP 3 D+
L2439 4 PGND
51C6 BI USB3_PCH_RX2_DN 4 3 USB3_SSRX2_DN 5 SSRX-
51C6 BI USB3_PCH_RX2_DP 1 2 USB3_SSRX2_DP 6 SSRX+ G G1
WCM_2012_900T 7 GND G G2
33B3 USB3_PCH_TX2C_DN 4 L2402 3 USB3_SSTX2_DN 8 G3
BI USB3_PCH_TX2C_DP 1 2 USB3_SSTX2_DP
SSTX- G
33B3 9 G4
BI SSTX+ G
WCM_2012_900T LOTES_AUSB0026_P002A_9P
C2445
51C6 BI USB3_PCH_TX2_DN 1 2 USB3_PCH_TX2C_DN BI 33C4
0.1UF_16V_2
C2446
51C6 BI USB3_PCH_TX2_DP 1 2 USB3_PCH_TX2C_DP BI 33C4
0.1UF_16V_2
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFFERENCE 3000~3049(LCM)
P3V3S
Q3000 PAD3003
P3V3S_MOS_LCM P3V3S_LCM
S S D D 1 1 2
2
0.01UF_50V_2
POWERPAD_2_0610
0.1UF_16V_2
10UF_6.3V_3
1
1
G
1
1
C3000
C3001
47K_5%_2
C3003
C3002
DIODES_DMP2305U_SOT23_3P
R3000
2 1
G
680PF_50V_2
D
2
2
2
2
D
2
R3001 R3004
R3011 1 2 PCH_LCM_VDDEN#
VGA_LCM_VDDEN 1 2 0_5%_1 100_5%_2
3
57B6 IN
Q3001 470K_5%_2
13
R3012
D
50D7 PCH_LCM_VDDEN 1 2 0_5%_1 LCM_VDDEN 1 G
Q3002
IN P3V3S
D
1 G
S
GM:2.2K P3V3S
SSM3K7002BFU
S
PM:4.7K
2
SSM3K7002BFU
0.1UF_16V_2
(60130B4720ZT)
1
2
1 R3002 2
1 R3005 2
2.2K_5%_2
2.2K_5%_2
C3004
2
VGA_LVDS_DDCCLK 1 R3015 2 0_5%_1
56D6 BI
56D6 BI VGA_LVDS_DDCDATA 1 2 0_5%_1 CN3000
1 1
R3016 2 2
3 3
PCH_LVDS_DDCCLK 1 R3017 2 0_5%_1 LVDS_DDCCLK 4
50D7 BI 4
C 50C7 PCH_LVDS_DDCDATA 1 2 0_5%_1 LVDS_DDCDATA 5 C
BI 5
6 6
R3018 LVDS_TXDL0_DN 7
34A6 IN 7
34A6 LVDS_TXDL0_DP 8
IN 8
9 9
34A6 IN LVDS_TXDL1_DN 10 10
34A6 IN LVDS_TXDL1_DP 11 11
12 12
34A6 IN LVDS_TXDL2_DN 13 13
34A6 IN LVDS_TXDL2_DP 14 14
15 15
34A6 IN LVDS_TXCL_DN 16 16
LVDS_TXCL_DP 17
57B6 VGA_INV_PWM_3 1 R3013 2 0_5%_1 34A6 IN 17
IN 100_5%_2 18 18
19
50D7 PCH_INV_PWM_3 1 R3014 2 0_5%_1 1 R3009 2 19
IN INV_PWM_3_R 20 20
EC_BKLTEN EC_BKLTEN_R 21 21
1 2
22
IN 22
1
R3003 USB_CAM_DN
1
51B2 23
100_5%_2 BI USB_CAM_DP
23
C3007 51B2 24
21E6
BI 24
1
1
R3006 25 25
GM:OPEN R3035 C3006 100K_5%_2 CSC0402_DY 24A6 BI MIC_IN_CLK 26 26
B 50C6 IN PCH_LVDS_TXDL0_DN R3019 1 2 0_5%_1 24A6 BI MIC_IN_DATA1 2 MIC_IN_DATA_R 27 27 G G1 B
PM: 10K 10K_5%_2 1000PF_50V_2
2
PCH_LVDS_TXDL0_DP R3020 1 2 0_5%_1 28 G2
2
50C6 IN R3010 28 G
100_5%_2 29 29
2
PCH_LVDS_TXDL1_DN R3021 1 2 0_5%_1 30
2
50C6 IN 30
50C6 IN PCH_LVDS_TXDL1_DP R3022 1 2 0_5%_1
ACES_50203_03001_001_30P
50C6 PCH_LVDS_TXDL2_DN R3023 1 2 0_5%_1 PVBAT

IN PCH_LVDS_TXDL2_DP
50C6 IN R3024 1 2 0_5%_1
50C6 PCH_LVDS_TXCL_DN R3025 1 2 0_5%_1

IN PCH_LVDS_TXCL_DP
50C6 IN R3026 1 2 0_5%_1
0.1UF_25V_3
4.7UF_25V_5
1
1
C3009
C3010
P3V3S
57A6 IN VGA_LVDS_TXDL0_DN R3027 1 2 0_5%_1 LVDS_TXDL0_DN OUT 34C3
0.1UF_16V_2
VGA_LVDS_TXDL0_DP LVDS_TXDL0_DP
1
57A6 IN R3028 1 2 0_5%_1
OUT 34C3
C3011
57A6 IN VGA_LVDS_TXDL1_DN R3029 1 2 0_5%_1 LVDS_TXDL1_DN OUT 34C3
57A6 IN VGA_LVDS_TXDL1_DP R3030 1 2 0_5%_1 LVDS_TXDL1_DP OUT 34C3
VGA_LVDS_TXDL2_DN R3031 1 2 0_5%_1 LVDS_TXDL2_DN
2
57A6 IN OUT 34C3
57A6 IN VGA_LVDS_TXDL2_DP R3032 1 2 0_5%_1 LVDS_TXDL2_DP OUT 34C3
A 57A6 IN VGA_LVDS_TXCL_DN R3033 1 2 0_5%_1 LVDS_TXCL_DN OUT 34B3 A

57A6 IN VGA_LVDS_TXCL_DP R3034 1 2 0_5%_1 LVDS_TXCL_DP OUT 34B3
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 3050~3099(CRT)
P5V0S
2 2
D3050
SS3040HE
R3064
56E2 56D3 VGA_CRTR 1 2 0_5%_1
IN
1
50B7 PCH_CRTR 1 R3065 2 0_5%_1 CRTR L3052 1 2 120NH,5% CRTR_L 35A7 35C3
IN OUT
1
P5V0S_CRT1
56E2 56D3 VGA_CRTG 1 R3066 2 0_5%_1
IN L3051
PCH_CRTG 1 R3067 2 0_5%_1 CRTG 1 2 CRTG_L
50B7 IN 120NH,5% OUT 35A7 35C3
D
D
2
56E2 56D3 VGA_CRTB 1 R3068 2 0_5%_1
IN L3050 CRTB_L FUSE3050
50B7 PCH_CRTB 1 R3069 2 0_5%_1 CRTB 1 2 120NH,5% 35A7 35C3
IN OUT
SMD1812P110TF
18PF_50V_2
1
1
18PF_50V_2
18PF_50V_2
1
1
2 R3054 1
1
150_1%_2
150_1%_2
150_1%_2
C3050
C3051
C3052
P5V0S_CRT2
R3055
R3056
CN3051
P5V0S_CRTVDD
2
CRTR_L 1
2
35D4 35A7 IN 1
35D4 35A7 CRTG_L 2
IN CRTB_L 3
2
35D4 35A7 IN 3
1 TP24 4 4
TP3050 5 5
GM:2.2K
1
1
6 6
PM:2K R3050 R3051 7 7
(60130B2020ZT) 8 8
2.2K_5%_2 9
2.2K_5%_2 9
10 10
2
2
1TP24 11 11
CRT_DDCDATA_OUT 1 R3053 2 CRT_DDCDATA_R_OUT TP3051 12 G1
35A3 BI 12 G1
C 35A3 CRT_HSYNC_R_OUT 13 G2 C
100_5%_2 IN CRT_VSYNC_R_OUT 14
13 G2
35A3 IN 14
CRT_DDCCLK_OUT 1 R3052 2 CRT_DDCCLK_R_OUT 15
35A3 BI 15
100_5%_2 SUYIN_070546HR015M25KZR_15P
1
C3053 C3054
0.1UF_16V_2_DY 0.1UF_16V_2_DY
2
RESERVE CAP FOR EMI
B 1 R3070 2 0_5%_1 VGA_CRT_VSYNC 56D3 56F7

B
IN
35A4 CRT_VSYNC 1 R3071 2 0_5%_1 PCH_CRT_VSYNC 50A6
OUT IN
1 R3072 2 0_5%_1 VGA_CRT_HSYNC 56D3 56F7

IN
35A4 CRT_HSYNC 1 R3073 2 0_5%_1 PCH_CRT_HSYNC 50A6
OUT IN
P5V0S P3V3S 1 R3074 2 0_5%_1 VGA_CRT_DDCDATA 56A3
IN
CRT_DDCDATA 1 R3075 2 0_5%_1 PCH_CRT_DDCDATA
1
35A4 OUT IN 50A6

GM:2.2K
1
C3056
PM:10K 1 R3076 2 0_5%_1 VGA_CRT_DDCCLK 56A3
(60130B1030ZT) R3060 R3061 IN
0.22UF_6.3V_2
2.2K_5%_2 2.2K_5%_2 35A4 CRT_DDCCLK 1 R3077 2 0_5%_1 PCH_CRT_DDCCLK 50A6
OUT IN
2
P3V3S
U3050 CRT_VSYNC_OUT R3062 CRT_VSYNC_R_OUT
1 16 1 2 30_5%_2 35C3
VCC-SYNC SYNC_OUT2
CRT_VSYNC OUT
2 15 35B4
CRTR_L
VCC-VIDEO SYNC_IN2
CRT_HSYNC_OUT IN R3063 CRT_HSYNC_R_OUT
A 35D4 35C3 IN 3 VIDEO_1 SYNC_OUT1 14 1 2 30_5%_2
OUT 35C3 A
1
35D4 35C3 IN CRTG_L 4 VIDEO_2 SYNC_IN1 13 CRT_HSYNC IN 35B4

C3055 35C3 IN CRTB_L 5 VIDEO_3 DCC_OUT2 12 CRT_DDCDATA_OUT OUT 35C5
P5V0S_CRTVDD 35D4 6 11 CRT_DDCDATA 35A4
GND DDC_IN2
CRT_DDCCLK IN
0.22UF_6.3V_2 7 10 35A4
VCC-DCC DDC_IN1 IN CRT_DDCCLK_OUT
8 9 35C5
BYP DDC_OUT1 OUT
2
TI_TPD7S019_15DBQR_SSOP_16P
C3057
0.22UF_6.3V_2
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 3150~3199(HDMI)
PLACE CLOSE TO CONNECTOR
R3174
50B3 BI PCH_HDMI_DDCDATA 1 2 0_5%_1
P5V0AL
PCH_HDMI_DDCCLK 1 R3175 2 0_5%_1 L3151
50B3 BI HDMI_TX2_C_DP HDMI_TX2_R_DP
36A7 36A2 IN 2 3
1
36A7 36A2 IN HDMI_TX2_C_DN 1 4 HDMI_TX2_R_DN
D3150
R3176
WCM_2012HDMI_121T
56B3 BI VGA_HDMI_DDCDATA 1 2 0_5%_1 HDMI_DDCDATA BI 36C8 2 NC
BAT54_30V_0.2A
VGA_HDMI_DDCCLK 1 R3177 2 0_5%_1 HDMI_DDCCLK
56B3 BI BI 36C8
D
3
L3152 D
36A7 36A2 IN HDMI_TX1_C_DP 2 3 HDMI_TX1_R_DP
36A7 36A2 IN HDMI_TX1_C_DN 1 4 HDMI_TX1_R_DN
1
GM: 2.2K
1
R3152
WCM_2012HDMI_121T R3153
PM:2K
2.2K_5%_2
2.2K_5%_2
(60130B2020ZT)
2
2
L3153
36A7 36A2 IN HDMI_TX0_C_DP 2 3 HDMI_TX0_R_DP
36B7 36A2 IN HDMI_TX0_C_DN 1 4 HDMI_TX0_R_DN
P3V3S CN3150
1 TMDS Data2+
WCM_2012HDMI_121T 2 TMDS Data2 Shield
P3V3S 3 TMDS Data2-
GM: 2.2K
1
4 TMDS Data1+
PM:10K 5 TMDS Data1 Shield
(60130B1030ZT) R3178 R3179 6 TMDS Data1-
L3154 7 TMDS Data0+
2.2K_5%_2 2.2K_5%_2 36B7 36A2 IN HDMI_TXC_C_DP 2 3 HDMI_TXC_R_DP
G
8 TMDS Data0 Shield

Q3151 36B7 36A2 IN HDMI_TXC_C_DN 1 4 HDMI_TXC_R_DN
9
2
TMDS Data0-
10
G
SSM3K17FU WCM_2012HDMI_121T TMDS Clock+

11 TMDS Clock Shield
36D6 BI HDMI_DDCDATA S S D D HDMI_CN_DDCDATA BI 36C3 37C3 12 TMDS Clock-
C 37D6 HDMI_CEC 13 G1 C
BI TP24 1
CEC G1
14 Reserved G2 G2
G
P5V0AL HDMI_CN_DDCCLK TP3151 15 G3

37D3 36C6 BI DDC Clock G3
Q3150 HDMI_CN_DDCDATA 16 G4
D3155 37C3 36C6 BI DDC Data G4
G
SSM3K17FU FUSE3150 17 DDC/CEC GND

40MIL 2 1 P5V0AL_HDMI_VDD1 1 2 P5V0AL_HDMI_VDD2 18 +5V Power
36D6 BI HDMI_DDCCLK S S D D HDMI_CN_DDCCLK BI 36C3 37D3 19 Hot Plug Detect
SMD1812P110TF
R3154 SYN_100042GR019M26DZL_19P
SBR3U40P1 37C1 OUT HPDET_IC 1 2
1
P3V3S 1K_5%_2
C3150 R3150
C3151
100PF_50V_2
22PF_50V_2_DY
470K_5%_2
2
1
2
CLOSE TO CONNECTOR
GM:680_5% R3165
PM:499_5% 100K_5%_2
(6013A0076801)
1
Q3152 P3V3S
G
B B
HDMI_TXC_C_DP 1 R3164 2 3 2
36C5 36A2 IN D S R3180
5
50B3 OUT PCH_HPDET 1 2 0_5%_1 U3150
680_5%_2
SSM3K7002BFU 1 HDMI_HPD_EC
+
R3181 IN 21D6 37B1
HDMI_TXC_C_DN R3163 VGA_HPDET 1 2 0_5%_1 HPDET 4
1 2 56C5 OUT
36C5 36A2 IN 2 PLT_RST# IN 41C7 51A7
680_5%_2
-
TC7SZ08FU
R3162
3
36D5 36A2 HDMI_TX0_C_DN 1 2
IN
680_5%_2
R3161
36D5 36A2 IN HDMI_TX0_C_DP 1 2
680_5%_2
R3160
36D5 36A2 IN HDMI_TX1_C_DN 1 2
C3152
680_5%_2 VGA_HDMI_TX2_DN 1 2 0.1UF_6.3V_1
56F3 IN C3153
R3159 56F3 IN VGA_HDMI_TX2_DP C3154 1 2 0.1UF_6.3V_1
36D5 36A2 IN HDMI_TX1_C_DP 1 2 56F3 IN VGA_HDMI_TX1_DN 1 2 0.1UF_6.3V_1 C3155
56F3 IN VGA_HDMI_TX1_DP C3156 1 2 0.1UF_6.3V_1
680_5%_2 VGA_HDMI_TX0_DN 1 2 0.1UF_6.3V_1
56F3 IN C3157
A R3158 56F3 IN VGA_HDMI_TX0_DP C3158 1 2 0.1UF_6.3V_1 A
36D5 36A2 IN HDMI_TX2_C_DN 1 2 56F3 IN VGA_HDMI_TXC_DN 1 2 0.1UF_6.3V_1 C3159
56F3 IN VGA_HDMI_TXC_DP 1 2 0.1UF_6.3V_1
680_5%_2
R3157
36D5 36A2 IN HDMI_TX2_C_DP 1 2
C3160
680_5%_2 PCH_HDMI_TX2_DN 1 2 0.1UF_6.3V_1 HDMI_TX2_C_DN
50B3 IN C3161 OUT 36A7 36D5
50B3 IN PCH_HDMI_TX2_DP C3162 1 2 0.1UF_6.3V_1 HDMI_TX2_C_DP OUT 36D5 36A7 36D5
50B3 IN PCH_HDMI_TX1_DN 1 2 0.1UF_6.3V_1 C3163 HDMI_TX1_C_DN OUT 36A7
50B3
50B3
50B3
IN
IN
IN
PCH_HDMI_TX1_DP
PCH_HDMI_TX0_DN
PCH_HDMI_TX0_DP
C3164
1
C3166
2 0.1UF_6.3V_1
1
C3165
1
2 0.1UF_6.3V_1
2 0.1UF_6.3V_1
HDMI_TX1_C_DP
HDMI_TX0_C_DN
HDMI_TX0_C_DP
OUT
OUT
OUT
36A7
36D5
36C5
INVENTEC
36A7 36D5
50B3 PCH_HDMI_TXC_DN 1 2 0.1UF_6.3V_1 C3167 HDMI_TXC_C_DN 36B7
IN PCH_HDMI_TXC_DP HDMI_TXC_C_DP OUT TITLE
50B3 1 2 0.1UF_6.3V_1 36B7
IN OUT 36C5 MODEL,PROJECT,FUNCTION
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3AL
P3V3AL
1
2 D3200 R3201
Q3201
G
NC
2.2K_5%_2
BAT54_30V_0.2A SSM3K17FU
G
D
2
3
37B3 BI HDMI_DDCCLK_CEC S S D DHDMI_CN_DDCCLK
BI 36C3 36C6 D
P3V3AL
1
P3V3AL
R3204
27K_5%_2
1
5
NC
U3203
+
R3214 HDMI_CEC
1
37B6 IN CEC_IN1 24 2
BI 36C3
R3200
G
- Q3200
68_5%_2 2.2K_5%_2
3
SSM3K17FU
G
74LVC1G14GV Q3203
3
2
R3206
D
G 1 1 2 CEC_OUT OUT 37B6 37B3 BI HDMI_DDCDATA_CEC S S D DHDMI_CN_DDCDATA

BI 36C3 36C6
P3V3AL
1
S
22K_5%_2
SSM3K7002BFU
0.1UF_16V_2
2
1
R3205
C3200
100K_5%_2 P3V3AL
2
C P3V3AL C
2
R3215 2
1
1
1
1
4.7K_5%_2
4.7K_5%_2
R3209
R3208
R3213 0_5%_2_DY
R3210
4.7K_5%_2
4.7K_5%_2
1
5
NC
2
U3202 U3200
2
2
EC_SMB2_CLK 1 20 EC_SMB2_DATA
+
BI P3_5-SSCK-SCL-CMP1_2 P3_4-SCS#-SDA-CMP1_1 BI R3227
2 P3_7-CNTR0#-SSO-TXD1 P3_3-TCIN-INT3#-SSI00-CMP1_0 19 1 2 4 2 HPDET_IC IN 36C4
3 18 HDMI_DDCDATA_CEC 37C5
CEC_XOUT
RESET# P1_0-KI0#-AN8-CMP0_0 BI
37A8 4 17 HDMI_DDCCLK_CEC 37D5 33_5%_2 -
OUT XOUT-P4_7 P1_1-KI1#-AN9-CMP0_1 BI
5 VSS-AVSS P4_2-VREF 16
CEC_XIN 6 15 PHP_74LVC1G17_SOT753_5P
3
37A6 IN XIN-P4_6 P1_2-KI2#-AN10-CMP0_2
7 VCC-AVCC P1_3-KI3#-AN11-TZOUT 14
8 MODE P1_4-TXD0 13
37D8 IN CEC_IN 9 P4_5-INT0#-RXD1 P1_5-RXD0-CNTR01-INT11# 12
37C6 OUT CEC_OUT 10 P1_7-CNTR00-INT10# P1_6-CLK0-SSI01 11
RENESAS_R5F211B4D61SP_LSSOP_20P HDMI_HPD_EC OUT 21D6 36B2
RSC_0402_DY
1
B P3V3AL B
R3202
0.1UF_16V_2
1UF_6.3V_2
1
1
C3202
C3205
2
2
2
P3V3AL
1
1
47K_5%_2
47K_5%_2
R3211
R3212
2
37B6 OUT CEC_XOUT CEC_XIN IN 37B6
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4100~4299(DDR)
43A4 BI
M_A_A<15..0>
M_A_DQ<63..0>
CHA
CN4100 BI 43D8
0 M_A_A<0> 98 A0 DQ0 5 M_A_DQ<0> 0
1 M_A_A<1> 97 A1 DQ1 7 M_A_DQ<1> 1
2 M_A_A<2> 96 A2 DQ2 15 M_A_DQ<2> 2
3 M_A_A<3> 95 A3 DQ3 17 M_A_DQ<3> 3
4 M_A_A<4> 92 A4 DQ4 4 M_A_DQ<4> 4
5 M_A_A<5> 91 A5 DQ5 6 M_A_DQ<5> 5
6 M_A_A<6> 90 A6 DQ6 16 M_A_DQ<6> 6
7 M_A_A<7> 86 A7 DQ7 18 M_A_DQ<7> 7
8 M_A_A<8> 89 A8 DQ8 21 M_A_DQ<8> 8
D 9 M_A_A<9> 85 A9 DQ9 23 M_A_DQ<9> 9 P1V5
CN4100
10 M_A_A<10> 107 A10/AP DQ10 33 M_A_DQ<10> 10 D
LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN 75 VDD1 VSS16 44
11 M_A_A<11> 84 A11 DQ11 35 M_A_DQ<11> 11
76 VDD2 VSS17 48
12 M_A_A<12> 83 A12/BC# DQ12 22 M_A_DQ<12> 12
81 49
1
M_A_A<13> 119 24 M_A_DQ<13> VDD3 VSS18
13 A13 DQ13 13 82 54
14 M_A_A<14> 80 34 M_A_DQ<14> 14 C4101 C4102 C4103 C4104 C4105 C4106 C4107 VDD4 VSS19
A14 DQ14 C4100 87 55
+
M_A_A<15> 78 36 M_A_DQ<15> VDD5 VSS20
15 A15 DQ15 15 88 60
39 M_A_DQ<16> VDD6 VSS21
DQ16 16 330UF_2.5V_DY 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 93 61
43A8 IN M_A_BS0 109 BA0 DQ17 41 M_A_DQ<17> 17 94
VDD7 VSS22
65
2
VDD8 VSS23
66
VDD9 VSS24
71
M_CS#0 114 40 M_A_DQ<20> NOTE:PLACE C4100 ON COMMON PATH FOR BOTH DIMM'S VDD10 VSS25
1
43C5 IN S0# DQ20 20 105 72
43C5 IN M_CS#1 121 S1# DQ21 42 M_A_DQ<21> 21 C4110 C4109 C4108 106
VDD11 VSS26
127
43D4 M_CLK_DDR0_DP 101 50 M_A_DQ<22> 22 P3V3S VDD12 VSS27
IN M_CLK_DDR0_DN 103
CK0 DQ22
52 M_A_DQ<23>
111 VDD13 VSS28 128
43D4 23
IN M_CLK_DDR1_DP 102
CK0# DQ23
57 M_A_DQ<24> 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 112 VDD14 VSS29 133
43D4 24
CK1 DQ24
59 M_A_DQ<25>
117 VDD15 VSS30 134
25
2
43D4 IN CK1# DQ25 118 138
43D4 IN M_CKE0 73 CKE0 DQ26 67 M_A_DQ<26> 26
123
VDD16 VSS31
139
1
43D4 IN M_CKE1 74 CKE1 DQ27 69 M_A_DQ<27> 27 124
VDD17 VSS32
144
43A8 IN M_A_CAS# 115 CAS# DQ28 56 M_A_DQ<28> 28 C4114 C4115
VDD18 VSS33
145
43A8 IN M_A_RAS# 110 RAS# DQ29 58 M_A_DQ<29> 29 199
VSS34
150
43A8 IN M_A_WE# 113 WE# DQ30 68 M_A_DQ<30> 30 2.2UF_6.3V_3 0.1UF_16V_2
VDDSPD VSS35
151
38A6 OUT SA0_DIM0 197 SA0 DQ31 70 M_A_DQ<31> 31 77
VSS36
155
2
38A6 OUT SA1_DIM0 201 SA1 DQ32 129M_A_DQ<32> 32 122
NC1 VSS37
156
C 48A8 39C8 20A7 PCH_3S_SMCLK 202 131M_A_DQ<33> 33 NC2 VSS38 C
IN PCH_3S_SMDATA 200
SCL DQ33
141M_A_DQ<34>
125 NCTEST VSS39 161
48A8 39C8 20A7 IN SDA DQ34 34 162
143M_A_DQ<35> VSS40
DQ35 35 167
43C5 M_ODT0 116 130M_A_DQ<36> 36 VSS41
IN M_ODT1 120
ODT0 DQ36
132M_A_DQ<37> 39C3 38B5 OUT PM_EXTTS#1_R 198 EVENT# VSS42 168
43C5 37
IN ODT1 DQ37
140M_A_DQ<38> DIMM0_VREF_DQ 41A5 39C3 OUT DDR3_DRAMRST# 30 RESET# VSS43 172
DQ38 38
VSS44 173
11 DM0 DQ39 142M_A_DQ<39> 39
VSS45 178
28 DM1 DQ40 147M_A_DQ<40> 40 ALL VREF TRACES SHOULD HAVE 20 MIL TRACE WIDTH 1 VREF_DQ VSS46 179
46 DM2 DQ41 149M_A_DQ<41> 41 126 VREF_CA VSS47 184
63 157M_A_DQ<42>
1
DM3 DQ42 42 185
136 159M_A_DQ<43> VSS48
DM4 DQ43 43 189
153 DM5 DQ44 146M_A_DQ<44> 44 C4150 C4116 VSS49 P0V75S
2 VSS1 VSS50 190
170 DM6 DQ45 148M_A_DQ<45> 45
2.2UF_6.3V_3 0.1UF_16V_2 3 VSS2 VSS51 195
187 DM7 DQ46 158M_A_DQ<46> 46 8 VSS3 VSS52 196
160M_A_DQ<47> 47
2
DQ47 DIMM0_VREF_CA 9
43B5 IN M_A_DQS0_DP 12 DQS0 DQ48 163M_A_DQ<48> 48 13
VSS4
43B5 IN M_A_DQS1_DP 29 DQS1 DQ49 165M_A_DQ<49> 49 14

VSS5
43B5 M_A_DQS2_DP 47 175M_A_DQ<50> 50 VSS6

IN M_A_DQS3_DP 64
DQS2 DQ50
177M_A_DQ<51>
19 VSS7
1
43B5 51
IN DQS3 DQ51 20
43B5 IN M_A_DQS4_DP
M_A_DQS5_DP
137
154
DQS4 DQ52 164M_A_DQ<52>
166M_A_DQ<53>
52
C4117 C4118 25
VSS8
VSS9 VTT1 203 1.5A
43B5 53
IN M_A_DQS6_DP 171
DQS5 DQ53
174M_A_DQ<54>
26 VSS10 VTT2 204
43B5 54
IN M_A_DQS7_DP 188
DQS6 DQ54
176M_A_DQ<55> P3V3S 2.2UF_6.3V_3 0.1UF_16V_2 31 VSS11
B 43B5 IN DQS7 DQ55 55 32 G1 B
M_A_DQS0_DN 10 181M_A_DQ<56> 56 VSS12 G1
2
43B5 IN DQS0# DQ56 37 G2
43B5 IN M_A_DQS1_DN 27 DQS1# DQ57 183M_A_DQ<57> 57 38
VSS13 G2
M_A_DQS2_DN 45 191M_A_DQ<58> VSS14
1
43B5 IN DQS2# DQ58 58 43
43B5 IN M_A_DQS3_DN 62 DQS3# DQ59 193M_A_DQ<59> 59 VSS15
43B5 IN M_A_DQS4_DN 135 DQS4# DQ60 180M_A_DQ<60> 60 R4104

M_A_DQS5_DN 152 182M_A_DQ<61> 61 BELLW_80001_1021_204P
43B5 IN DQS5# DQ61 10K_5%_2
43B5 IN M_A_DQS6_DN 169 DQS6# DQ62 192M_A_DQ<62> 62
M_A_DQS7_DN 186 194M_A_DQ<63> 63
2
43B5 IN DQS7# DQ63
39C3 38C3 PM_EXTTS#1_R
BELLW_80001_1021_204P
IN
PLACE THESE CAPS CLOSE TO VTT1 AND VTT2
1
P3V3S P1V5 P0V75M_VREF DIMM0_VREF_CA P1V5 P0V75M_VREF DIMM0_VREF_DQ C4119 C4120 C4121 C4122
1
1
1
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2
2
NOTE: R4100 R4101
R4132
R4145
R4118 R4115
1 2 1 2
10K_5%_2_DY 10K_5%_2_DY 1K_1%_2 1K_1%_2
IF SA0_DIM0=1 , SA1_DIM0=0
A SO-DIMMA SPD ADDRESS IS 0XA2 0_5%_2_DY 0_5%_2_DY A
2
2
SA0_DIM0 IN 38C8
SO-DIMMA TS ADDRESS IS 0X32
1
1
SA1_DIM0 IN 38C8 R4133 R4117
1
IF SA0_DIM0=0 , SA1_DIM0=0 1K_1%_2 1K_1%_2

SO-DIMMA SPD ADDRESS IS 0XA0 R4102 R4103
2
2
10K_5%_2 10K_5%_2
SO-DIMMA TS ADDRESS IS 0X30
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4100~4299(DDR)
43A1 BI
M_B_A<15..0>
M_B_DQ<63..0>
CHB
BI 43D4
CN4101
0 M_B_A<0> 98 A0 DQ0 5 M_B_DQ<0> 0
1 M_B_A<1> 97 A1 DQ1 7 M_B_DQ<1> 1
2 M_B_A<2> 96 A2 DQ2 15 M_B_DQ<2> 2
3 M_B_A<3> 95 A3 DQ3 17 M_B_DQ<3> 3
4 M_B_A<4> 92 A4 DQ4 4 M_B_DQ<4> 4
5 M_B_A<5> 91 A5 DQ5 6 M_B_DQ<5> 5
6 M_B_A<6> 90 A6 DQ6 16 M_B_DQ<6> 6
D 7 M_B_A<7> 86 A7 DQ7 18 M_B_DQ<7> 7
8 M_B_A<8> 89 A8 DQ8 21 M_B_DQ<8> 8 D
9 M_B_A<9> 85 A9 DQ9 23 M_B_DQ<9> 9 P1V5
10 M_B_A<10> 107 A10_AP DQ10 33 M_B_DQ<10> 10 CN4101
LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN 75 VDD1 VSS16 44
11 M_B_A<11> 84 A11 DQ11 35 M_B_DQ<11> 11 76 VDD2 VSS17 48
12 M_B_A<12> 83 A12 DQ12 22 M_B_DQ<12> 12 81 49
1
M_B_A<13> 119 24 M_B_DQ<13> VDD3 VSS18
13 A13 DQ13 13 82 54
14 M_B_A<14> 80 34 M_B_DQ<14> 14 C4124 C4125 C4126 C4127 C4128 C4129 C4130 VDD4 VSS19
A14 DQ14 87 55
M_B_A<15> 78 36 M_B_DQ<15> VDD5 VSS20
15 A15 DQ15 15 88 60
39 M_B_DQ<16> VDD6 VSS21
DQ16 16 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 93 61
43A4 IN M_B_BS0 109 BA0 DQ17 41 M_B_DQ<17> 17 94
VDD7 VSS22
65
2
VDD8 VSS23
66
VDD9 VSS24
71
M_CS#2 114 40 M_B_DQ<20> VDD10 VSS25
1
43C1 20
IN M_CS#3 121
S0# DQ20
42 M_B_DQ<21>
105 VDD11 VSS26 72
43C1 21 C4133 C4132 C4131
S1# DQ21
50 M_B_DQ<22> P3V3S 106 VDD12 VSS27 127
43D1 22
CK0 DQ22
52 M_B_DQ<23>
111 VDD13 VSS28 128
43D1 23
CK0# DQ23
57 M_B_DQ<24> 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 112 VDD14 VSS29 133
43D1 24
CK1 DQ24
59 M_B_DQ<25>
117 VDD15 VSS30 134
25
2
43D1 IN CK1# DQ25 118 138
M_CKE2 73 67 M_B_DQ<26> VDD16 VSS31
43D1 IN CKE0 DQ26 26 123 139
1
M_CKE3 74 69 M_B_DQ<27> VDD17 VSS32
43D1 IN CKE1 DQ27 27 124 144
M_B_CAS# 115 56 M_B_DQ<28> VDD18 VSS33
43A4 IN CAS# DQ28 28 C4138 C4137 145
43A4 IN M_B_RAS# 110 RAS# DQ29 58 M_B_DQ<29> 29 199
VSS34
150
43A4 IN M_B_WE# 113 WE# DQ30 68 M_B_DQ<30> 30 2.2UF_6.3V_3 0.1UF_16V_2
VDDSPD VSS35
151
C 39A7 SA0_DIM1 197 70 M_B_DQ<31> 31 VSS36 C
OUT SA0 DQ31 77 155
2
39A6 OUT SA1_DIM1 201 SA1 DQ32 129M_B_DQ<32> 32 122
NC1 VSS37
156
IN PCH_3S_SMCLK 202 SCL DQ33 131M_B_DQ<33> 33 125
NC2 VSS38
161
48A8 38C8 20A7 PCH_3S_SMDATA 200 141M_B_DQ<34> 34 NCTEST VSS39
IN SDA DQ34
143M_B_DQ<35> VSS40 162
DQ35 35
M_ODT2 116 130M_B_DQ<36> 38C3 38B5 OUT PM_EXTTS#1_R 198 EVENT# VSS41 167
43C1 36
IN M_ODT3 120
ODT0 DQ36
132M_B_DQ<37> DIMM1_VREF_DQ 41A5 38C3 OUT DDR3_DRAMRST# 30 RESET# VSS42 168
43C1 37
IN ODT1 DQ37
140M_B_DQ<38> VSS43 172
DQ38 38
VSS44 173
11 DM0 DQ39 142M_B_DQ<39> 39 ALL VREF TRACES SHOULD HAVE 20 MIL TRACE WIDTH 1 VREF_DQ VSS45 178
28 DM1 DQ40 147M_B_DQ<40> 40 126 VREF_CA VSS46 179
46 DM2 DQ41 149M_B_DQ<41> 41
VSS47 184
63 157M_B_DQ<42>
1
DM3 DQ42 42 185
136 159M_B_DQ<43> VSS48
DM4 DQ43 43 2 189
153 DM5 DQ44 146M_B_DQ<44> 44 C4151 C4139 VSS1 VSS49 P0V75S
3 VSS2 VSS50 190
170 DM6 DQ45 148M_B_DQ<45> 45
2.2UF_6.3V_3 0.1UF_16V_2 8 VSS3 VSS51 195
187 DM7 DQ46 158M_B_DQ<46> 46 9 VSS4 VSS52 196
160M_B_DQ<47> 47
2
DQ47 13
43B1 M_B_DQS0_DP 12 163M_B_DQ<48> 48 VSS5
IN M_B_DQS1_DP 29
DQS0 DQ48
165M_B_DQ<49>
14 VSS6
43B1 49
IN M_B_DQS2_DP 47
DQS1 DQ49
175M_B_DQ<50>
19 VSS7
43B1 50
IN M_B_DQS3_DP 64
DQS2 DQ50
177M_B_DQ<51> DIMM1_VREF_CA 20 VSS8
43B1 51
IN DQS3 DQ51 25
43B1 IN M_B_DQS4_DP
M_B_DQS5_DP
137
154
DQS4 DQ52 164M_B_DQ<52>
166M_B_DQ<53>
52
26
VSS9
VSS10 VTT1 203 1.5A
B 43B1 IN DQS5 DQ53 53 31 VSS11 VTT2 204 B
43B1 IN M_B_DQS6_DP 171 DQS6 DQ54 174M_B_DQ<54> 54 32
1
M_B_DQS7_DP 188 176M_B_DQ<55> VSS12
43B1 IN DQS7 DQ55 55 37 G1
M_B_DQS0_DN 10 181M_B_DQ<56> VSS13 G1
43B1 IN DQS#0 DQ56 56 C4140 C4141 38 G2
43B1 IN M_B_DQS1_DN 27 DQS#1 DQ57 183M_B_DQ<57> 57 43
VSS14 G2
43B1 IN M_B_DQS2_DN 45 DQS#2 DQ58 191M_B_DQ<58> 58 2.2UF_6.3V_3 0.1UF_16V_2

VSS15
43B1 IN M_B_DQS3_DN 62 DQS#3 DQ59 193M_B_DQ<59> 59 BELLW_80001_5021_204P
2
43B1 IN M_B_DQS4_DN 135 DQS#4 DQ60 180M_B_DQ<60> 60
43B1 IN M_B_DQS5_DN 152 DQS#5 DQ61 182M_B_DQ<61> 61
43B1 M_B_DQS6_DN 169 192M_B_DQ<62> 62
IN M_B_DQS7_DN 186
DQS#6 DQ62
194M_B_DQ<63>
43B1 63
IN DQS#7 DQ63
BELLW_80001_5021_204P
PLACE THESE CAPS CLOSE TO VTT1 AND VTT2
P1V5 P0V75M_VREF DIMM1_VREF_CA P1V5 P0V75M_VREF DIMM1_VREF_DQ
1
NOTE: P3V3S
1
1
C4142 C4143 C4144 C4145
SO-DIMMB SPD ADDRESS IS 0XA4 R4122 R4166 R4167
R4134
SO-DIMMB TS ADDRESS IS 0X34 1 2 1 2
1
1K_1%_2 1K_1%_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2
2
R4105 R4106
0_5%_2_DY 0_5%_2_DY
A A
2
2
10K_5%_2_DY 10K_5%_2
1
1
2
R4121
SA0_DIM1 SA1_DIM1 R4135
39C8 IN IN 39C8 1K_1%_2
1K_1%_2
1
R4107 R4108 2
10K_5%_2 10K_5%_2_DY
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4300~4349(FAN)
REFERENCE 4411~4449(THERMAL ) P5V0S
PAD4300 P5V0S_FAN
1 1 2
2
POWERPAD_2_0610
L4300
22UF_6.3V_5_DY
1 2
4.7UF_6.3V_3
0.1UF_16V_2
1
1
KC_FBM_11_160808_101_T_2P_DY
C4301
C4302
C4307
D
2
P3V3S D
10K_5%_2
2 R4300
CN4300
1 1
2
21B6
FAN_TACH1 1 TP4300 3
2
G1
IN 3 G
4 4 G G2
TP30
ACES_50273_0047N_001_4P
220pF_50V_2
CSC0402_DY
1
1
P3V3S
C4300
C4305
2
1
C C
10K_5%_2
R4306
FAN CN
2
FAN1_PWM 1 TP4301
21B6 IN
TP30
CSC0402_DY
1
C4306
2
P5V0AL
100K_1%_NTC 48.7K_1%_2
1
R4442
B B
P5V0AL
49B7 11C7 11A4 IN CORE_PG
0.1UF_16V_2
1
1 2
THRM_SHUTDWN# OUT 15D8 40A8 56D6

1
C4441
R4445
1
R4444
100K_5%_2 P5V0AL R4414

2
3
1
2M_5%_2
59K_1%_2
2
U4441 Q4411
2
R4446
1 VCC TMSNS1 8
D
2
R4443 1 G
2 GND RHYST1 7 1 2
S
C
39K_1%_2
2
THRM_SHUTDWN# Q4412
1
56D6 40B1 15D8 3 6 R4413 SSM3K7002BFU
OUT OT1 TMSNS2
PM_THRMTRIP# 1 2 B
C E
2
52C1 41D5 IN B C4412
100K_1%_NTC
4 OT2 RHYST2 5 1 R4441 2 330_5%_2

1
MMBT4401
R4447
ENE_P2809A2_SOT23_8P 75K_1%_2 CSC0402_DY
2
2
A A
THERMAL SHOUTDOWN
GM THERMAL SHOUTDOWN CPU SIDE AT 68.6 C 10F 10FG
GM THERMAL SHOUTDOWN VGA SIDE AT 63.4 C
R4442 48.7K 43.2K
PM THERMAL SHOUTDOWN CPU SIDE AT 71.9 C R4443 39K 30.1K
PM THERMAL SHOUTDOWN VGA SIDE AT 80.2 C
R4446 59K 32.4K
R4441 75K 18.2K INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4500~4699(CPU) CN4500
P1V8S
A28 CLK_DMI_PCH_DP
CLOCKS
BCLK IN 48B3
MISC
41D8 OUT H_SNB_IVB# C26 PROC_SELECT# BCLK# A27 CLK_DMI_PCH_DN
IN 48B3
P1V05S
2
TP4500 1 AN34 SKTOCC#
R4500 R4502 DPLL_REF_CLK A16 R4510 1 2 1K_5%_2
TP24
2.2K_5%_2 2.2K_5%_2_DY DPLL_REF_CLK# A15 R4511 1 2 1K_5%_2
TP4501 1
2
P1V05S
1
AL33 CATERR#
H_SNB_IVB# 1 R4501 2 NV_CLE TP24

41D5 OUT OUT 52B2
THERMAL
D 1K_5%_2
DDR3
1
PLACE CLOSE TO CPT AND NVRAM CONNECTOR H_PECI AN33 R8 CPU_DRAMRST# D
MISC
52C2 21A6 OUT PECI SM_DRAMRST# OUT 41A5
R4503
62_5%_2
CPU_PROCHOT# 1 R4504 2 CPU_PROCHOT#_R AL32 AK1 SM_RCOMP0 R4512 1 2
1 2
21C3 11C7 OUT 140_1%_2
PROCESS STRAP SETTING PROCHOT# SM_RCOMP[0]
SM_RCOMP[1] A5 SM_RCOMP1 R4513 1 2 25.5_1%_2
56_5%_2 A4 SM_RCOMP2
SM_RCOMP[2] R4514 1 2 200_1%_2
C4500
SANDY BRIDGE ONLY STUFF R4502 CSC0402_DY 40A4 PM_THRMTRIP# AN32
52C1
OUT THERMTRIP#
SANDY BRIDGE/IVY BRIDGE STUFF R4500/R4501
2
PRDY# AP29 TP30 1 TP4502 H_PRDY# OUT
PREQ# AP27 TP30 1 TP4503 H_PREQ# IN 41B2
P1V5S AR26 TP30 1 TP4504 H_TCK 41B2
PWR MANAGEMENT
LOW IN C6/C7
TCK
H_TMS IN
DMI&FDI TERMINATIONVOLTAGE TMS AR27 TP30 1 TP4505 IN 41B2
JTAG & BPM

H_PM_SYNC TP30 1 H_TRST#
1
49A3 AM34 AP30 TP4506 41B2
BI PM_SYNC TRST# IN
NV_CLE SET TOVSS WHEN LOW (DEFAULT) R4505 TDI AR28 TP30 1 TP4507 H_TDI IN 41B2
200_5%_2 TDO AP26
TP30 1 TP4508 H_TDO OUT
C SET TOVCC WHEN HIGH 52C2 IN H_CPUPWRGD AP33 UNCOREPWRGOOD C
2
R4506 DBR# AL35 TP30 1 TP4509 SYS_RESET# OUT 49B8
49B7 IN PM_DRAM_PWRGD 1 2 PM_DRAM_PWRGD_R V8 SM_DRAMPWROK
130_1%_2 AT28
BPM#[0]
BPM#[1] AR29 CAD NOTE: ALL DDR_COMP SIGNALS SHOULD BE ROUTED SUCH TAHT
R4507 BPM#[2] AR30 - MAX LENGTH = 500 MILS
51A7 36B2 IN PLT_RST# 1 2 AR33 RESET# BPM#[3] AT30 - TRACE WIDTH = 15MILS AND
BPM#[4] AP32 - MB TRACE IMPEDANCE < 68 MOHMS
1.5K_5%_2 BPM#[5] AR31 (WORST CASE RESISTANCE)
1
BPM#[6] AT31
BPM#[7] AR32
R4509
R4508
10K_5%_2
750_1%_2 P1V05S
2
LOTES_ACA_ZIF_069_P01_989P 41C1 IN H_TMS R4516 1 2 51_5%_2
41C1 IN H_TDI R4517 1 2 51_5%_2
41C1 IN H_PREQ# R1418 1 2 51_5%_2_DY
B B
H_TCK 1 2 51_5%_2
S3 CIRCUIT: DRAM_RST# TO MEMORY SHOULD BE HIGH DURING S3 41C1 IN
H_TRST#
R4519
41C1 R4520 1 2 51_5%_2
IN
P3V3A P1V5
1
R4602
R4601
1K_5%_2 1K_5%_2
2
R4603 DDR3_DRAMRST#
1 2 38C3 39C3
DRAMRST_CNTRL OUT
45D6 OUT
45D8 1K_5%_2
3
Q4600
DRAMRST_CNTRL_PCH 1 R4600
D
48D3 2 1 G
IN
SHORT_0402
S
A SSM3K7002BFU CPU_DRAMRST# A
IN 41D2
12
1
C4620 R4604
0.047UF_16V_2
4.99K_1%_2
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V05S
REFERENCE 4500~4699(CPU) CAD NOTE: PEG_ICOMPI AND RCOMPO SIGNALS
SHOULD BE SHORTED AND ROUTED WITH
1
- MAX LENGTH = 500 MILS
R4522
- TYPICAL IMPEDANCE = 43 MOHMS
24.9_1%_2
CN4500
J22 P1V0S_VCCP_PEG_ICOMPI
2
PEG_ICOMPI
J21 PEG_ICOMPO SIGNALS SHOULD BE ROUTED WITH
PEG_ICOMPO
49D6 DMI_TX0_DN B27 H22 - MAX LENGTH = 500 MILS
OUT DMI_RX#[0] PEG_RCOMPO
49D6 DMI_TX1_DN B25
OUT DMI_RX#[1]
- TYPICAL IMPEDANCE = 14.5 MOHMS
49D6 DMI_TX2_DN A25
OUT DMI_RX#[2]
PEG_C_RX15_DN
49C6 DMI_TX3_DN B24 K33 57B1
OUT DMI_RX#[3] PEG_RX#[0]
PEG_C_RX14_DN IN
M35 57B1
PEG_RX#[1]
PEG_C_RX13_DN IN
D 49C6 OUT DMI_TX0_DP B28 DMI_RX[0] PEG_RX#[2] L34
IN 57B1
49C6 DMI_TX1_DP B26 J35 PEG_C_RX12_DN 57B1 D
DMI
OUT DMI_RX[1] PEG_RX#[3]
PEG_C_RX11_DN IN
49C6 DMI_TX2_DP A24 J32 57B1
OUT DMI_RX[2] PEG_RX#[4]
PEG_C_RX10_DN IN
49C6 DMI_TX3_DP B23 H34 57C1
OUT DMI_RX[3] PEG_RX#[5] IN
PEG_RX#[6] H31 PEG_C_RX9_DN
PEG_C_RX8_DN IN 57C1 CLOSE TO CPU
49D6 DMI_RX0_DN G21 G33 57C1
OUT DMI_TX#[0] PEG_RX#[7]
PEG_C_RX7_DN IN
49D6 DMI_RX1_DN E22 G30 57C1
OUT DMI_TX#[1] PEG_RX#[8]
PEG_C_RX6_DN IN PEG_TX0_DN PEG_C_TX0_DN
49D6 OUT DMI_RX2_DN F21 DMI_TX#[2] PEG_RX#[9] F35
IN 57C1 42B4 IN C4580 1 2 0.22UF_6.3V_2 OUT 57D6
49D6 OUT DMI_RX3_DN D21 DMI_TX#[3] PEG_RX#[10] E34 PEG_C_RX5_DN IN 57C1
PEG_RX#[11] E32 PEG_C_RX4_DN IN 57D1 42B4 IN PEG_TX1_DN C4581 1 2 0.22UF_6.3V_2 PEG_C_TX1_DN OUT 57D6
49D6 OUT DMI_RX0_DP G22 DMI_TX[0] PEG_RX#[12] D33 PEG_C_RX3_DN IN 57D1
49D6 OUT DMI_RX1_DP D22 DMI_TX[1] PEG_RX#[13] D31 PEG_C_RX2_DN IN 57D1 42B4 IN PEG_TX2_DN C4582 1 2 0.22UF_6.3V_2 PEG_C_TX2_DN OUT 57D6
49D6 OUT DMI_RX2_DP F20 DMI_TX[2] PEG_RX#[14] B33 PEG_C_RX1_DN IN 57D1
49D6 DMI_RX3_DP C21 C32 PEG_C_RX0_DN 57D1 42B4 PEG_TX3_DN C4583 1 2 0.22UF_6.3V_2 PEG_C_TX3_DN 57D6
OUT DMI_TX[3] PEG_RX#[15] IN IN OUT
PEG_RX[0] J33 PEG_C_RX15_DP IN 57B1 42B4 IN PEG_TX4_DN C4584 1 2 0.22UF_6.3V_2 PEG_C_TX4_DN OUT 57D6
PCI EXPRESS* - GRAPHICS

PEG_RX[1] L35 PEG_C_RX14_DP IN 57B1
PEG_RX[2] K34 PEG_C_RX13_DP IN 57B1 42B4 IN PEG_TX5_DN C4585 1 2 0.22UF_6.3V_2 PEG_C_TX5_DN OUT 57C6
49D3 OUT FDI_TX0_DN A21 FDI0_TX#[0] PEG_RX[3] H35 PEG_C_RX12_DP IN 57B1
49D3 OUT FDI_TX1_DN H19 FDI0_TX#[1] PEG_RX[4] H32 PEG_C_RX11_DP IN 57B1 42B4 IN PEG_TX6_DN C4586 1 2 0.22UF_6.3V_2 PEG_C_TX6_DN OUT 57C6
49D3 OUT FDI_TX2_DN E19 FDI0_TX#[2] PEG_RX[5] G34 PEG_C_RX10_DP IN 57C1
49D3 OUT FDI_TX3_DN F18 FDI0_TX#[3] PEG_RX[6] G31 PEG_C_RX9_DP IN 57C1 42B4 IN PEG_TX7_DN C4587 1 2 0.22UF_6.3V_2 PEG_C_TX7_DN OUT 57C6
49D3 OUT FDI_TX4_DN B21 FDI1_TX#[0] PEG_RX[7] F33 PEG_C_RX8_DP IN 57C1
49D3 OUT FDI_TX5_DN C20 FDI1_TX#[1] PEG_RX[8] F30 PEG_C_RX7_DP IN 57C1 42B4 IN PEG_TX8_DN C4588 1 2 0.22UF_6.3V_2 PEG_C_TX8_DN OUT 57C6
C C
Intel(R) FDI
49D3 OUT FDI_TX6_DN D18 FDI1_TX#[2] PEG_RX[9] E35 PEG_C_RX6_DP IN 57C1
49D3 OUT FDI_TX7_DN E17 FDI1_TX#[3] PEG_RX[10] E33 PEG_C_RX5_DP IN 57D1 42B4 IN PEG_TX9_DN C4589 1 2 0.22UF_6.3V_2 PEG_C_TX9_DN OUT 57C6
PEG_RX[11] F32 PEG_C_RX4_DP IN 57D1
D34 PEG_C_RX3_DP 57D1 42B4 PEG_TX10_DN C4590 1 2 0.22UF_6.3V_2 PEG_C_TX10_DN 57C6
PEG_RX[12]
PEG_C_RX2_DP IN IN OUT
49D3 FDI_TX0_DP A22 E31 57D1
OUT FDI0_TX[0] PEG_RX[13]
PEG_C_RX1_DP IN PEG_TX11_DN C4591 1 2 PEG_C_TX11_DN
49D3 FDI_TX1_DP G19 C33 57D1 42B4 0.22UF_6.3V_2 57B6
OUT FDI0_TX[1] PEG_RX[14]
PEG_C_RX0_DP IN IN OUT
49D3 FDI_TX2_DP E20 B32 57D1
OUT FDI0_TX[2] PEG_RX[15] IN PEG_TX12_DN C4592 1 2 PEG_C_TX12_DN
49D3 FDI_TX3_DP G18 42B4 0.22UF_6.3V_2 57B6
OUT FDI0_TX[3]
PEG_TX15_DN IN OUT
49C3 FDI_TX4_DP B20 M29 42B3
OUT FDI1_TX[0] PEG_TX#[0]
PEG_TX14_DN OUT PEG_TX13_DN C4593 1 2 PEG_C_TX13_DN
49C3 FDI_TX5_DP C19 M32 42B3 42C4 0.22UF_6.3V_2 57B6
PEG_TX13_DN OUT IN OUT
49C3 FDI_TX6_DP D19 M31 42C3
49C3 FDI_TX7_DP F17 L32 42C3 42C4 0.22UF_6.3V_2 57B6
L29 42C3
PEG_TX#[4]
49C3 FDI_FSYNC0 J18 K31 42C3 42C4 0.22UF_6.3V_2 57B6
IN FDI0_FSYNC PEG_TX#[5]
49C3 FDI_FSYNC1 J17 K28 42C3
IN FDI1_FSYNC PEG_TX#[6]
PEG_TX8_DN OUT PEG_TX0_DP PEG_C_TX0_DP
PEG_TX#[7] J30
OUT 42C3 42A4 IN C4596 1 2 0.22UF_6.3V_2 OUT 57D6
P1V05S 49C3 FDI_INT H20 J28 PEG_TX7_DN 42C3
IN FDI_INT PEG_TX#[8]
PEG_TX#[9] H29
PEG_TX5_DN
1
49C3 FDI_LSYNC0 J19 G27 42C3

IN FDI0_LSYNC PEG_TX#[10]
49C3 IN FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29
R4521 PEG_TX#[12] F27 PEG_TX3_DN OUT 42C3
24.9_1%_2 PEG_TX#[13] D28 PEG_TX2_DN OUT 42D3 42A4 IN PEG_TX3_DP C4599 1 2 0.22UF_6.3V_2 PEG_C_TX3_DP OUT 57D6
B PEG_TX#[14] F26 PEG_TX1_DN OUT 42D3 B
E25 PEG_TX0_DN PEG_TX4_DP C4600 1 2 PEG_C_TX4_DP
2
PEG_TX#[15] OUT 42D3 42A4 IN 0.22UF_6.3V_2 OUT 57D6

P1V0S_VCCP_EDP_COMPIO A18 eDP_COMPIO
A17 eDP_ICOMPO PEG_TX[0] M28 PEG_TX15_DP OUT 42A3 42A4 IN PEG_TX5_DP C4601 1 2 0.22UF_6.3V_2 PEG_C_TX5_DP OUT 57D6
CAD NOTE: DP_COMPIO AND ICOMPO SIGNALS B16 eDP_HPD PEG_TX[1] M33 PEG_TX14_DP OUT 42A3
PEG_TX[2] M30 PEG_TX13_DP OUT 42A3 42A4 IN PEG_TX6_DP C4602 1 2 0.22UF_6.3V_2 PEG_C_TX6_DP OUT 57C6
SHOULD BE SHORTED NEAR BALLS AND ROUTED WITH L31 PEG_TX12_DP
PEG_TX[3] OUT 42A3
- TYPICAL IMPEDANCE < 25 MOHMS C15 eDP_AUX PEG_TX[4] L28 PEG_TX11_DP OUT 42A3 42B4 IN PEG_TX7_DP C4603 1 2 0.22UF_6.3V_2 PEG_C_TX7_DP OUT 57C6
D15 K30 PEG_TX10_DP
eDP
eDP_AUX# PEG_TX[5] OUT 42A3

K27 PEG_TX9_DP 42B3 42B4 PEG_TX8_DP C4604 1 2 0.22UF_6.3V_2 PEG_C_TX8_DP 57C6
PEG_TX[6]
PEG_TX8_DP OUT IN OUT
J29 42B3
PEG_TX[7]
PEG_TX7_DP OUT PEG_TX9_DP PEG_C_TX9_DP
C17 eDP_TX[0] PEG_TX[8] J27
OUT 42B3 42B4 IN C4605 1 2 0.22UF_6.3V_2 OUT 57C6
F16 eDP_TX[1] PEG_TX[9] H28 PEG_TX6_DP OUT 42B3
C16 eDP_TX[2] PEG_TX[10] G28 PEG_TX5_DP OUT 42B3 42B4 IN PEG_TX10_DP C4606 1 2 0.22UF_6.3V_2 PEG_C_TX10_DP OUT 57C6
G15 eDP_TX[3] PEG_TX[11] E28 PEG_TX4_DP OUT 42B3
PEG_TX[12] F28 PEG_TX3_DP OUT 42B3 42B4 IN PEG_TX11_DP C4607 1 2 0.22UF_6.3V_2 PEG_C_TX11_DP OUT 57B6
C18 eDP_TX#[0] PEG_TX[13] D27 PEG_TX2_DP OUT 42B3
E16 eDP_TX#[1] PEG_TX[14] E26 PEG_TX1_DP OUT 42B3 42B4 IN PEG_TX12_DP C4608 1 2 0.22UF_6.3V_2 PEG_C_TX12_DP OUT 57B6
D16 eDP_TX#[2] PEG_TX[15] D25 PEG_TX0_DP OUT 42B3
F15 eDP_TX#[3] 42B4 IN PEG_TX13_DP C4609 1 2 0.22UF_6.3V_2 PEG_C_TX13_DP OUT 57B6
42B4 IN PEG_TX14_DP C4610 1 2 0.22UF_6.3V_2 PEG_C_TX14_DP OUT 57B6

LOTES_ACA_ZIF_069_P01_989P
42B4 PEG_TX15_DP C4611 1 2 0.22UF_6.3V_2 PEG_C_TX15_DP 57B6
IN OUT
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4500~4699(CPU)
SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR CN4500
CN4500
M_A_DQ<63..0> 39D5 BI M_B_DQ<63..0>

38D5 BI AE2 M_CLK_DDR2_DP
SB_CLK[0] OUT 39C8
M_CLK_DDR0_DP SB_CLK#[0] AD2 M_CLK_DDR2_DN OUT 39C8
AB6 38C8
SA_CLK[0]
M_CLK_DDR0_DN OUT 0 M_B_DQ<0> C9 SB_DQ[0] SB_CKE[0] R9 M_CKE2 OUT 39C8
AA6 38C8
M_A_DQ<0>
SA_CLK#[0]
M_CKE0
OUT 1 M_B_DQ<1> A7 SB_DQ[1]
0 C5 V9 38C8
D M_A_DQ<1>
SA_DQ[0] SA_CKE[0] OUT 2 M_B_DQ<2> D10 SB_DQ[2]
1 D5 SA_DQ[1]
3 M_B_DQ<3> C8 SB_DQ[3] D
2 M_A_DQ<2> D3
M_A_DQ<3>
SA_DQ[2]
4 M_B_DQ<4> A9 SB_DQ[4] SB_CLK[1] AE1 M_CLK_DDR3_DP OUT 39C8
3 D2
M_A_DQ<4>
SA_DQ[3]
M_CLK_DDR1_DP 5 M_B_DQ<5> A8 SB_DQ[5] SB_CLK#[1] AD1 M_CLK_DDR3_DN OUT 39C8
4 D6 AA5 38C8
M_A_DQ<5>
SA_DQ[4] SA_CLK[1]
M_CLK_DDR1_DN OUT 6 M_B_DQ<6> D9 SB_DQ[6] SB_CKE[1] R10 M_CKE3 OUT 39C8
5 C6 AB5 38C8
M_A_DQ<6>
SA_DQ[5] SA_CLK#[1]
M_CKE1 OUT 7 M_B_DQ<7> D8 SB_DQ[7]
6 C2 V10 38C8
M_A_DQ<7>
SA_DQ[6] SA_CKE[1] OUT 8 M_B_DQ<8> G4 SB_DQ[8]
7 C3 SA_DQ[7]
9 M_B_DQ<9> F4 SB_DQ[9]
8 M_A_DQ<8> F10 SA_DQ[8]
10 M_B_DQ<10> F1 SB_DQ[10] RSVD_TP[11] AB2
9 M_A_DQ<9> F8 SA_DQ[9]
11 M_B_DQ<11> G1 SB_DQ[11] RSVD_TP[12] AA2
10 M_A_DQ<10> G10 SA_DQ[10] RSVD_TP[1] AB4
12 M_B_DQ<12> G5 SB_DQ[12] RSVD_TP[13] T9
11 M_A_DQ<11> G9 SA_DQ[11] RSVD_TP[2] AA4
13 M_B_DQ<13> F5 SB_DQ[13]
12 M_A_DQ<12> F9 SA_DQ[12] RSVD_TP[3] W9
14 M_B_DQ<14> F2 SB_DQ[14]
13 M_A_DQ<13> F7 SA_DQ[13]
15 M_B_DQ<15> G2 SB_DQ[15]
14 M_A_DQ<14> G8 SA_DQ[14]
16 M_B_DQ<16> J7 SB_DQ[16] RSVD_TP[14] AA1
15 M_A_DQ<15> G7 SA_DQ[15]
17 M_B_DQ<17> J8 SB_DQ[17] RSVD_TP[15] AB1
16 M_A_DQ<16> K4 SA_DQ[16] RSVD_TP[4] AB3
18 M_B_DQ<18> K10 SB_DQ[18] RSVD_TP[16] T10
17 M_A_DQ<17> K5 SA_DQ[17] RSVD_TP[5] AA3
19 M_B_DQ<19> K9 SB_DQ[19]
18 M_A_DQ<18> K1 SA_DQ[18] RSVD_TP[6] W10
20 M_B_DQ<20> J9 SB_DQ[20]
19 M_A_DQ<19> J1 SA_DQ[19]
21 M_B_DQ<21> J10 SB_DQ[21]
20 M_A_DQ<20> J5
M_A_DQ<21>
SA_DQ[20]
22 M_B_DQ<22> K8 SB_DQ[22] SB_CS#[0] AD3 M_CS#2 OUT 39C8
21 J4
M_A_DQ<22>
SA_DQ[21]
M_CS#0 23 M_B_DQ<23> K7 SB_DQ[23] SB_CS#[1] AE3 M_CS#3 OUT 39C8
22 J2 AK3 38D8
M_A_DQ<23>
SA_DQ[22] SA_CS#[0]
M_CS#1 OUT 24 M_B_DQ<24> M5 SB_DQ[24] RSVD_TP[17] AD6
23 K2 AL3 38C8
M_A_DQ<24>
SA_DQ[23] SA_CS#[1] OUT 25 M_B_DQ<25> N4 SB_DQ[25] RSVD_TP[18] AE6
C 24 M8 SA_DQ[24] RSVD_TP[7] AG1
26 M_B_DQ<26> N2 SB_DQ[26]
C
25 M_A_DQ<25> N10 SA_DQ[25] RSVD_TP[8] AH1
27 M_B_DQ<27> N1 SB_DQ[27]
26 M_A_DQ<26> N8 SA_DQ[26]
28 M_B_DQ<28> M4 SB_DQ[28]
27 M_A_DQ<27> N7 SA_DQ[27]
29 M_B_DQ<29> N5 AE4 M_ODT2 39C8
28 M_A_DQ<28> M10 SA_DQ[28] M_B_DQ<30>
SB_DQ[29] SB_ODT[0]
M_ODT3 OUT
30 M2 AD4 39C8
29 M_A_DQ<29> M9 SA_DQ[29] SA_ODT[0] AH3 M_ODT0 OUT 38C8 M_B_DQ<31>
SB_DQ[30] SB_ODT[1] OUT
31 M1 AD5
DDR SYSTEM MEMORY B

30 M_A_DQ<30> N9 SA_DQ[30] SA_ODT[1] AG3 M_ODT1 OUT 38C8 M_B_DQ<32>
SB_DQ[31] RSVD_TP[19]
32 AM5 SB_DQ[32] RSVD_TP[20] AE5
31 M_A_DQ<31> M7 SA_DQ[31] RSVD_TP[9] AG2
33 M_B_DQ<33> AM6
DDR SYSTEM MEMORY A
M_A_DQ<32> SB_DQ[33]
32 AG6 SA_DQ[32] RSVD_TP[10] AH2
34 M_B_DQ<34> AR3 SB_DQ[34]
33 M_A_DQ<33> AG5 SA_DQ[33]
35 M_B_DQ<35> AP3 SB_DQ[35]
34 M_A_DQ<34> AK6 SA_DQ[34]
36 M_B_DQ<36> AN3 SB_DQ[36]
35 M_A_DQ<35> AK5 SA_DQ[35]
37 M_B_DQ<37> AN2 D7 M_B_DQS0_DN 39B8
36 M_A_DQ<36> AH5 SA_DQ[36] M_B_DQ<38>
SB_DQ[37] SB_DQS#[0] OUT
38 AN1 F3 M_B_DQS1_DN 39B8
37 M_A_DQ<37> AH6 SA_DQ[37] SA_DQS#[0] C4 M_A_DQS0_DN
OUT 38B8 M_B_DQ<39>
39 AP2 K6 M_B_DQS2_DN 39B8
38 M_A_DQ<38> AJ5 SA_DQ[38] SA_DQS#[1] G6 M_A_DQS1_DN
OUT 38B8 M_B_DQ<40>
40 AP5 N3 M_B_DQS3_DN 39B8
39 M_A_DQ<39> AJ6 SA_DQ[39] SA_DQS#[2] J3 M_A_DQS2_DN
OUT 38B8 M_B_DQ<41>
41 AN9 AN5 M_B_DQS4_DN 39B8
40 M_A_DQ<40> AJ8 SA_DQ[40] SA_DQS#[3] M6 M_A_DQS3_DN
OUT 38B8 M_B_DQ<42>
42 AT5 AP9 M_B_DQS5_DN 39B8
41 M_A_DQ<41> AK8 SA_DQ[41] SA_DQS#[4] AL6 M_A_DQS4_DN
OUT 38B8 M_B_DQ<43>
43 AT6 AK12 M_B_DQS6_DN 39B8
42 M_A_DQ<42> AJ9 SA_DQ[42] SA_DQS#[5] AM8 M_A_DQS5_DN
OUT 38B8 M_B_DQ<44>
44 AP6 AP15 M_B_DQS7_DN 39B8
43 M_A_DQ<43> AK9 SA_DQ[43] SA_DQS#[6] AR12 M_A_DQS6_DN
OUT 38B8 M_B_DQ<45>
45 AN8 SB_DQ[45]
44 M_A_DQ<44> AH8 AM15 M_A_DQS7_DN 38B8
M_A_DQ<45>
SA_DQ[44] SA_DQS#[7] OUT 46 M_B_DQ<46> AR6 SB_DQ[46]
45 AH9 SA_DQ[45]
47 M_B_DQ<47> AR5 SB_DQ[47]
46 M_A_DQ<46> AL9 SA_DQ[46]
B 48 M_B_DQ<48> AR9 SB_DQ[48] B
47 M_A_DQ<47> AL8 SA_DQ[47]
49 M_B_DQ<49> AJ11 C7 M_B_DQS0_DP 39B8
48 M_A_DQ<48> AP11 SA_DQ[48] M_B_DQ<50>
SB_DQ[49] SB_DQS[0] OUT
50 AT8 G3 M_B_DQS1_DP 39B8
49 M_A_DQ<49> AN11 SA_DQ[49] SA_DQS[0] D4 M_A_DQS0_DP
OUT 38B8 M_B_DQ<51>
51 AT9 J6 M_B_DQS2_DP 39B8
50 M_A_DQ<50> AL12 SA_DQ[50] SA_DQS[1] F6 M_A_DQS1_DP
OUT 38B8 M_B_DQ<52>
52 AH11 M3 M_B_DQS3_DP 39B8
51 M_A_DQ<51> AM12 SA_DQ[51] SA_DQS[2] K3 M_A_DQS2_DP
OUT 38B8 M_B_DQ<53>
53 AR8 AN6 M_B_DQS4_DP 39B8
52 M_A_DQ<52> AM11 SA_DQ[52] SA_DQS[3] N6 M_A_DQS3_DP
OUT 38B8 M_B_DQ<54>
54 AJ12 AP8 M_B_DQS5_DP 39B8
53 M_A_DQ<53> AL11 SA_DQ[53] SA_DQS[4] AL5 M_A_DQS4_DP
OUT 38B8 M_B_DQ<55>
55 AH12 AK11 M_B_DQS6_DP 39B8
54 M_A_DQ<54> AP12 SA_DQ[54] SA_DQS[5] AM9 M_A_DQS5_DP
OUT 38B8 M_B_DQ<56>
56 AT11 AP14 M_B_DQS7_DP 39B8
55 M_A_DQ<55> AN12 SA_DQ[55] SA_DQS[6] AR11 M_A_DQS6_DP
OUT 38B8 M_B_DQ<57>
57 AN14 SB_DQ[57]
56 M_A_DQ<56> AJ14 AM14 M_A_DQS7_DP 38B8
M_A_DQ<57>
SA_DQ[56] SA_DQS[7] OUT 58 M_B_DQ<58> AR14 SB_DQ[58]
57 AH14 SA_DQ[57]
59 M_B_DQ<59> AT14 SB_DQ[59]
58 M_A_DQ<58> AL15
M_A_DQ<59>
SA_DQ[58]
60 M_B_DQ<60> AT12 SB_DQ[60] M_B_A<15..0> OUT
59 AK15
M_A_DQ<60>
SA_DQ[59] M_A_A<15..0> OUT 38D8 61 M_B_DQ<61> AN15 SB_DQ[61] SB_MA[0] AA8 M_B_A<0> 0
60 AL14 SA_DQ[60]
62 M_B_DQ<62> AR15 SB_DQ[62] SB_MA[1] T7 M_B_A<1> 1
61 M_A_DQ<61> AK14 SA_DQ[61] SA_MA[0] AD10 M_A_A<0> 0
63 M_B_DQ<63> AT15 SB_DQ[63] SB_MA[2] R7 M_B_A<2> 2
62 M_A_DQ<62> AJ15 SA_DQ[62] SA_MA[1] W1 M_A_A<1> 1
SB_MA[3] T6 M_B_A<3> 3
63 M_A_DQ<63> AH15 SA_DQ[63] SA_MA[2] W2 M_A_A<2> 2
SB_MA[4] T2 M_B_A<4> 4
SA_MA[3] W7 M_A_A<3> 3
SB_MA[5] T4 M_B_A<5> 5
SA_MA[4] V3 M_A_A<4> 4
SB_MA[6] T3 M_B_A<6> 6
V2 M_A_A<5> 5
SA_MA[5]
M_A_A<6> 39D8 OUT M_B_BS0 AA9 SB_BS[0] SB_MA[7] R2 M_B_A<7> 7
W3 6
M_A_BS0
SA_MA[6]
M_A_A<7> 39D8 OUT M_B_BS1 AA7 SB_BS[1] SB_MA[8] T5 M_B_A<8> 8
38D8 AE10 W6 7
OUT M_A_BS1
SA_BS[0] SA_MA[7]
M_A_A<8> 39C8 OUT M_B_BS2 R6 SB_BS[2] SB_MA[9] R3 M_B_A<9> 9
38D8 AF10 V1 8
OUT M_A_BS2
SA_BS[1] SA_MA[8]
M_A_A<9> SB_MA[10] AB7 M_B_A<10> 10
38D8 V6 W5 9
A OUT SA_BS[2] SA_MA[9]
M_A_A<10> SB_MA[11] R1 M_B_A<11> 11 A
SA_MA[10] AD8 10
SB_MA[12] T1 M_B_A<12> 12
V4 M_A_A<11> 11
SA_MA[11]
M_A_A<12> 39C8 OUT M_B_CAS# AA10 SB_CAS# SB_MA[13] AB10 M_B_A<13> 13
W4 12
M_A_CAS#
SA_MA[12]
M_A_A<13> 39C8 OUT M_B_RAS# AB8 SB_RAS# SB_MA[14] R5 M_B_A<14> 14
38C8 AE8 AF8 13
OUT M_A_RAS#
SA_CAS# SA_MA[13]
M_A_A<14> 39C8 OUT M_B_WE# AB9 SB_WE# SB_MA[15] R4 M_B_A<15> 15
38C8 AD9 V5 14
OUT M_A_WE#
SA_RAS# SA_MA[14]
M_A_A<15>
38C8 AF9 V7 15
OUT SA_WE# SA_MA[15]
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
F F
POWER
CN4500
REFERENCE 4500~4699(CPU)
E PVCORE P1V05S E
AG35 VCC1
AG34 VCC2 VCCIO1 AH13
1
AG33 VCC3 VCCIO2 AH10
AG32 VCC4 VCCIO3 AG10
2 C4531 1
2 C4533 1
2 C4535 1
2 C4537 1
1
22UF_6.3V_5
1
22UF_6.3V_5
1
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
C4510 C4511 C4512 C4513 AG31 VCC5 VCCIO4 AC10
22UF_6.3V_5
C4534
C4536
C4542
C4540
AG30 Y10
C4541
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 VCC6 VCCIO5
C4532
AG29 VCC7 VCCIO6 U10
AG28 P10
2
VCC8 VCCIO7
AG27 VCC9 VCCIO8 L10
2
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF32 VCC14 VCCIO13 H14
1
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
PEG AND DDR

C4514 C4515 C4516 C4517 AF27 G12
VCC19 VCCIO18
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 AF26 F14
VCC20 VCCIO19
AD35 VCC21 VCCIO20 F13
2
2
AD32 VCC24 VCCIO23 E14
D AD30 VCC26 D
AD28 VCC28 VCCIO26 D14
AC35 VCC31 VCCIO29 D11
1
1
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
C4518 C4519 C4520 C4521 AC32 C12
VCC34 VCCIO32
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 AC31 C11
VCC35 VCCIO33
AC30 VCC36 VCCIO34 B14
2
2
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
AA31 VCC45
1
1 AA30 VCC46
P1V05S
AA29 VCC47
C4522
22UF_6.3V_5
C4523
22UF_6.3V_5
C4524
22UF_6.3V_5
C4525
22UF_6.3V_5
AA28 VCC48 PLACE CLOSE TO CPU
AA27 VCC49
AA26 VCC50
1
CORE SUPPLY
2
Y35 VCC51
Y34 VCC52
R4528 R4527
C Y33 VCC53
130_1%_2 75_5%_2
C
Y32 VCC54
Y31 VCC55
2
Y30 VCC56
Y29 VCC57
Y28 VCC58
Y27
Y26
VCC59
VCC60
SVID SIGNAL TO VR
V35 VCC61
SVID
V34 VCC62 VIDALERT# AJ29 H_CPU_SVIDALRT# R4529 1 2 43_5%_2 VR_SVID_ALERT# OUT 11C7
V33 VCC63 VIDSCLK AJ30 H_CPU_SVIDCLK R4530 1 2 SHORT_0402 VR_SVID_CLK OUT 11A3 11C7
V32 VCC64 VIDSOUT AJ28 H_CPU_SVIDDAT R4531 1 2 SHORT_0402 VR_SVID_DATA OUT 11A3 11C7
V31 VCC65
V30 VCC66
V29 VCC67 PVCORE
V28 VCC68
V27 VCC69
1
V26 VCC70
U35 VCC71
U34 R4532
VCC72
U33 100_1%_2
VCC73
U32 VCC74
VCCSENSE
2
U31 OUT 11D6
VCC75
VSSSENSE OUT 11D6
U30 VCC76
1
U29 VCC77
U28 VCC78
U27 R4533
VCC79
100_1%_2
B U26 VCC80 B
R35 VCC81
2
R34 VCC82
R33 VCC83
R32 VCC84
R31 VCC85
R30 VCC86
P1V05S
R29 VCC87
R28
SENSE LINES
VCC88
1
R27 VCC89 VCC_SENSE AJ35
R26 VCC90 VSS_SENSE AJ34
P35 R4534
VCC91
P34 10_1%_2
VCC92
P33 VCC93
2
P32 VCC94 VCCIO_SENSE B10 VCC_SENSE_VCCIO OUT 9B7
P31 VCC95 VSSIO_SENSE A10 VSS_SENSE_VCCIO OUT 9B7
1
P30 VCC96
P29 VCC97
P28 R4535
VCC98
P27 10_1%_2
VCC99
P26 VCC100
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PROCESSOR DRIVEN VREF PATH WAS STUFFED BY DEFAULT:

ROUTE WITH MIN. TRACE WIDTH OF 10 MILS DIMM0_VREF_DQ DIMM1_VREF_DQ
R4572 P0V75M_VREF P0V75M_VREF_H
R4570 1 2
1 2
0_5%_2_DY
0_5%_2_DY
CPUDDR_WR_VREF1 46C4 IN CPUDDR_WR_VREF2 2 3
46C4 2 3 S D 3 2
IN S D D S
Q4502
Q4501
1
AM2302N
G
AM2302N
Q4500
1
45D8 41A8 DRAMRST_CNTRL AM2302N R4541
1
DRAMRST_CNTRL
IN
45D6 41A8 IN 100K_5%_2
D
D
2
49A1 21D6 14D2 14B8 14A6 R4538
PVAXG 13A2 IN SLP_S3#_3R 1 2
POWER 13D2
SHORT_0402
1
1
PVAXG R4539
CN4500
10_1%_2
C4578
470PF_50V_2
2
AK35 GFX_VCC_SENSE
SENSE
AT24
2
VAXG1 VAXG_SENSE OUT 11B8
LINES
AT23 AK34 GFX_VSS_SENSE 11B8
VAXG2 VSSAXG_SENSE OUT
AT21 VAXG3
1
1
AT20 VAXG4
AT18 VAXG5
AT17 R4540
VAXG6
C4651 C4545 C4546 C4547 C4548 C4549 C4550 AR24 VAXG7 10_1%_2
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5AR23 VAXG8
AR21
2
2
VAXG9
AR20 P0V75M_VREF_H
VREF
VAXG10
AR18 VAXG11
AR17 VAXG12
C AP24 VAXG13 SM_VREF AL1 C
AP23 VAXG14
AP21 VAXG15
AP20 VAXG16
AP18 VAXG17
AP17 VAXG18
AN24 VAXG19
AN23 VAXG20 NOTE : DDR_WR_VREF SHOULD HAVE 20/20 MIL WHEREVER POSSIBLE
AN21 VAXG21
AN20 VAXG22
P1V5S
AN18 VAXG23
AN17 VAXG24
5A
GRAPHICS
DDR3 -1.5V RAILS

AM24 VAXG25 VDDQ1 AF7
1
AM20 VAXG28 VDDQ4 AC7
+
AL24 Y7 C4567 C4568 C4569 C4570 C4571 C4572 C4573
VAXG31 VDDQ7
AL23 Y4 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 220UF_2.5V
2
VAXG32 VDDQ8
AL21 VAXG33 VDDQ9 Y1
AL20 VAXG34 VDDQ10 U7
B AL18 VAXG35 VDDQ11 U4 B
AL17 VAXG36 VDDQ12 U1
AK24 VAXG37 VDDQ13 P7
AK20 VAXG40
AK18 VAXG41
AK17 VAXG42
AJ24 VAXG43
AJ23 VAXG44
AJ21 VAXG45
AJ20 VAXG46
AJ18 VAXG47
AJ17 VAXG48
AH24 VAXG49
PVSA
AH23 VAXG50
AH21 VAXG51 VCCSA1 M27
SA RAIL
1
AH20 VAXG52 VCCSA2 M26
1
AH18 VAXG53 VCCSA3 L26
AH17 VAXG54 VCCSA4 J26
+
J25 C4577
VCCSA5 C4574 C4575 C4576
VCCSA6 J24 PVSA 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 100UF_6.3V
H26
2
VCCSA7
2
VCCSA8 H25
1
A A
R4544
P1V8S
1.8V RAIL
100_5%_2
L4500
1.2A
2
1 2 P1V8S_VCCPLL B6 VCCPLL1 VCCSA_SENSE H23 VCCSA_SENSE OUT 10C4
MISC
A6 VCCPLL2
MPZ1608S221AT
1
A2 VCCPLL3
FC_C22 C22 VCCSA_VID0 OUT 10B4

C4562 C4563 C4564
C4565
22UF_6.3V_5
VCCSA_VID1 C24
1
VCCSA_VID1 OUT 10B4
INVENTEC
1
10UF_6.3V_3 1UF_6.3V_2 1UF_6.3V_2
2
R4556 R4547 TITLE

LOTES_ACA_ZIF_069_P01_989P MODEL,PROJECT,FUNCTION
1K_5%_2 1K_5%_2 Block Diagram
2
2
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CN4500 CN4500
CN4500
RSVD28 L7
AT35 VSS1 VSS81 AJ22 T35 VSS161 VSS234 F22 RSVD29 AG7
AT32 VSS2 VSS82 AJ19 T34 VSS162 VSS235 F19
OUT CFG<0> AK28 CFG[0] RSVD30 AE7
AT29 VSS3 VSS83 AJ16 T33 VSS163 VSS236 E30
OUT CFG<1> AK29 CFG[1] RSVD31 AK2
AT27 VSS4 VSS84 AJ13 T32 VSS164 VSS237 E27 46A6 OUT CFG<2> AL26 CFG[2] RSVD32 W8
OUT CFG<3> AL27 CFG[3]
AT22 VSS6 VSS86 AJ7 T30 VSS166 VSS239 E21 46A6 OUT CFG<4> AK26 CFG[4]
AT19 VSS7 VSS87 AJ4 T29 VSS167 VSS240 E18 46A6 OUT CFG<5> AL29 CFG[5] RSVD33 AT26
AT16 VSS8 VSS88 AJ3 T28 VSS168 VSS241 E15 46A6 OUT CFG<6> AL30 CFG[6] RSVD34 AM33
AT13 VSS9 VSS89 AJ2 T27 VSS169 VSS242 E13 46A6 OUT CFG<7> AM31 CFG[7] RSVD35 AJ27
OUT CFG<8> AM32 CFG[8]
AT7 VSS11 VSS91 AH35 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P5 VSS174 VSS247 E6
OUT CFG<12> AN28 CFG[12]
D AR22 AH29 P3 E5 CFG<13> AN31 T8
VSS15 VSS95 VSS175 VSS248 OUT CFG<14>
CFG[13] RSVD37
D
AR19 AH28 P2 E4 AN26 J16
CFG[14] RSVD38
AR16 AH26 N35 E3 AM27 H16
CFG[15] RSVD39
AR13 AH25 N34 E2 AK31 G16
CFG[16] RSVD40
AR10 AH22 N33 E1 AN29
VSS19 VSS99 VSS179 VSS252 OUT CFG[17]
AR7 VSS20 VSS100 AH19 N32 VSS180 VSS253 D35
AP34 VSS23 VSS103 AH4 N29 VSS183 VSS256 D26 RSVD41 AR35
AP31 VSS24 VSS104 AG9 N28 VSS184 VSS257 D20 AJ31 VAXG_VAL_SENSE RSVD42 AT34
AP28 VSS25 VSS105 AG8 N27 VSS185 VSS258 D17 AH31 VSSAXG_VAL_SENSE RSVD43 AT33
AP25 VSS26 VSS106 AG4 N26 VSS186 VSS259 C34 AJ33 VCC_VAL_SENSE RSVD44 AP35
AP22 VSS27 VSS107 AF6 M34 VSS187 VSS260 C31 AH33 VSS_VAL_SENSE RSVD45 AR34
AP19 VSS28 VSS108 AF5 L33 VSS188 VSS261 C28
AP16 VSS29 VSS109 AF3 L30 VSS189 VSS262 C27
AP13 VSS30 VSS110 AF2 L27 VSS190 VSS263 C25 AJ26 RSVD5
RESERVED
AP10 VSS31 VSS111 AE35 L9 VSS191 VSS264 C23
AP7 VSS32 VSS112 AE34 L8 VSS192 VSS265 C10
AP4 VSS33 VSS113 AE33 L6 VSS193 VSS266 C1 RSVD46 B34
AP1 VSS34 VSS114 AE32 L5 VSS194 VSS267 B22 45D8 OUT CPUDDR_WR_VREF1 B4 RSVD6 RSVD47 A33
AN30
AN27
VSS35
VSS36
VSS115
VSS116
AE31
AE30
L4
L3
VSS195
VSS196
VSS_1 VSS268
VSS269
B19
B17
45D6 OUT CPUDDR_WR_VREF2 D1 RSVD7 RSVD48
RSVD49
A34
B35
C
AN25
AN22
VSS37
VSS38
VSS VSS117
VSS118
AE29
AE28
L2
L1
VSS197
VSS198
VSS270
VSS271
B15
B13
RSVD50 C35
C
AN19 VSS39 VSS119 AE27 K35 VSS199 VSS272 B11 F25 RSVD8
AN10 VSS42 VSS122 AD7 K26 VSS202 VSS275 B7 D24 RSVD11 RSVD51 AJ32
AN7 VSS43 VSS123 AC9 J34 VSS203 VSS276 B5 G25 RSVD12 RSVD52 AK32
AN4 VSS44 VSS124 AC8 J31 VSS204 VSS277 B3 G24 RSVD13
AM29 VSS45 VSS125 AC6 H33 VSS205 VSS278 B2 E23 RSVD14
AM25 VSS46 VSS126 AC5 H30 VSS206 VSS279 A35 D23 RSVD15
AM22 VSS47 VSS127 AC3 H27 VSS207 VSS280 A32 C30 RSVD16 VCC_DIE_SENSE AH27
AM19 VSS48 VSS128 AC2 H24 VSS208 VSS281 A29 A31 RSVD17
AM16 AB35 H21 A26 B30
AM13
VSS49
VSS50
VSS129
VSS130 AB34 H18
VSS209
VSS210
VSS282
VSS283 A23 B29
RSVD18
RSVD19
REMOVE
AM10 VSS51 VSS131 AB33 H15 VSS211 VSS284 A20 D30 RSVD20 RSVD54 AN35 CLK_XDP_CLKGEN_DP
AM7 AB32 H13 A3 B31 AM35
AM4
VSS52
VSS53
VSS132
VSS133 AB31 H10
VSS212
VSS213
VSS285
A30
RSVD21
RSVD22
RSVD55
CLK_XDP_CLKGEN_DN
AM3 VSS54 VSS134 AB30 H9 VSS214 C29 RSVD23
AM2 VSS55 VSS135 AB29 H8 VSS215
AM1 VSS56 VSS136 AB28 H7 VSS216
AL34 VSS57 VSS137 AB27 H6 VSS217 J20 RSVD24
AL31 VSS58 VSS138 AB26 H5 VSS218 B18 RSVD25 RSVD56 AT2
AL28 VSS59 VSS139 Y9 H4 VSS219 9C7 OUT VCCIO_SEL A19 VCCIO_SEL RSVD57 AT1
AL25 Y8 H3 AR1
10K_5%_2_DY
VSS60 VSS140 VSS220 RSVD58
B AL22 Y6 H2 B
2
VSS61 VSS141 VSS221
R4555
AL19 VSS62 VSS142 Y5 H1 VSS222 J15 RSVD27
AL16 VSS63 VSS143 Y3 G35 VSS223
AL13 VSS64 VSS144 Y2 G32 VSS224
AL10 VSS65 VSS145 W35 G29 VSS225 KEY B1
AL7 W34 G26
1
VSS66 VSS146 VSS226
AL4 VSS67 VSS147 W33 G23 VSS227
AL2 VSS68 VSS148 W32 G20 VSS228
AK33 VSS69 VSS149 W31 G17 VSS229
AK30 VSS70 VSS150 W30 G11 VSS230
AK27 VSS71 VSS151 W29 F34 VSS231
AK25 VSS72 VSS152 W28 F31 VSS232 LOTES_ACA_ZIF_069_P01_989P
AK22 VSS73 VSS153 W27 F29 VSS233
AK19 VSS74 VSS154 W26
AK16 VSS75 VSS155 U9
AK13 VSS76 VSS156 U8
AK10 U6
AK7
VSS77
VSS78
VSS157
VSS158 U5 PEG STATIC LANE REVERSAL
AK4 U3
AJ25
VSS79
VSS80
VSS159
VSS160 U2 CFG(2) 1 : (DEFAULT) NORMAL OPERATION
0 : LANE REVERSED
LOTES_ACA_ZIF_069_P01_989P LOW EDP ENABLE
A 1 : (DEFAULT) EDP DISABLED A
CFG<2> 1 R4550 2 CFG(4) 0 : EDP ENABLED

PEG STATIC LAN REVERSAL IN
1K_1%_2
PEG DEFER TRAINING
CFG<4> 1 R4551 2
46D4 IN
LOW EDP ENABLE
1K_1%_2_DY
1 : (DEFAULT) PEG TRAIN IMMEDIATELY FOLLOWING XXRESETB DE ASSERTION
CFG(7) 0 : PEG WAIT FOR BIOS FOR TRAINING
CFG<5> 1 R4552 2
46D4 IN
PCIE PORT BIFURCATION STRAPS
PCIE PORT BIFURCATION IN CFG<6> 1
1K_1%_2_DY
R4553 2
1K_1%_2_DY
11 : (DEFAULT) X16 - DEVICE 1 FUNCTION AND 2 DISABLED INVENTEC
10 : X8, X8 - DEVICE 1 FUNCTION 1 ENABLE ; FUNCTION 2 DISABLED TITLE
CFG<7> R4554 2
PEG DEFER TRAINING 46D4 IN 1
1K_1%_2_DY
CFG[6:5] 01 : RESERVED - (DEVICE 1 FUNCTION 1 DISABLED ; FUNCTION 2 ENABLED) MODEL,PROJECT,FUNCTION
Block Diagram
00 : X8,X4,X4 - DEVICE 1 FUNCTION 1 AND 2 ENABLED DOC.NUMBER REV
STRAP PIN CHANGE by DATE
A3 CS
SHEET 46 of 70
XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4700~4949(PCH)
P3V3AL P3V3A
1 R4736 2
0_5%_2_DY
2
P1V05S
A2
1 R4737 2
P3V3_RTC
RSC_0402_DY
C4703
RTCX2
1
1 2
C 3 P3V3_RTC
D4700 18PF_50V_2
R4703
3
4
BAT54C_30V_0.2A
1
20K_1%_2 R4738 R4740 R4742
D 1 2 R4708 PCH_TDI RSC_0402_DY RSC_0402_DY RSC_0402_DY
2
X4700 47A6
A1
OUT D
1
10M_5%_2 PCH_TMS
32.768KHZ 47B6 OUT
C4701
11
47A6 OUT PCH_TDO
1
R4704
1
1UF_6.3V_2
2
1
20K_1%_2
2
R4700 1 2 C4704
RTCX1 1 2
2
1K_5%_2 TP4705 R4739 R4741 R4743
1
1 18PF_50V_2 RSC_0402_DY RSC_0402_DY RSC_0402_DY
1UF_6.3V_2
1 2
2
TP30
C4702
1UF_6.3V_2
1
1
1M_5%_2
C4700
R4705
CN4700
+
U4700
2
LPC_3S_AD<0>
-
P3V3_RTC A20 C38 21E3 27C3

LOTES_AAA_BAT_063_P02_A_2P RTCX1 FWH0/LAD0
LPC_3S_AD<1> BI
A38 21E3 27C3
FWH1/LAD1 BI
2
P3V3S
2
LPC_3S_AD<2>
1
C20 B37 21E3 27C3

RTCX2 FWH2/LAD2
LPC_3S_AD<3> BI
C37 21E3 27C3
R4707
FWH3/LAD3 BI
RTC
1
LPC
D20 RTCRST#
330K_5%_3 FWH4/LFRAME# D36 LPC_3S_FRAME# OUT 21E3 27C3
G22 SRTCRST#
E36 R4744
2
R4706 LDRQ0#
K22 K36 10K_5%_2
0_5%_2_DY INTRUDER# LDRQ1#/GPIO23
1 2
2
C17 INTVRMEN SERIRQ V5 PCI_3S_SERIRQ BI 21E3 27B7
C C
INTVRMEN-INTEGRATE (SUS 1.05V VRM ENABLE STRAPPING
1:ENABLE INTERNAL VRS AM3 SATA_HDD_RX_DN
SATA0RXN IN 29D5
0:ENABLE EXTERNAL VRS HDA_3S_BITCLK 1 R4709 2 HDA_3S_BITCLK_R N34 AM1 SATA_HDD_RX_DP
24A2 BI HDA_BCLK SATA0RXP IN 29D5
SATA 6G
33_5%_2 SATA0TXN AP7 SATA_HDD_TX_DN OUT 29D5
HDA_3S_SYNC 1 R4711 2 HDA_3S_SYNC_R L34 AP5 SATA_HDD_TX_DP
24B2 BI HDA_SYNC SATA0TXP OUT 29D5
33_5%_2
STRAPPING
24B1 OUT PCSPKR_PCH_3 T10 SPKR SATA1RXN AM10
SATA1RXP AM8
R4712
PCSPKR_PCH_3(NO REBOOT) 24B2 OUT HDA_3S_RST# 1 2 HDA_3S_RST#_R K34 HDA_RST# SATA1TXN AP11
1 : NO REBOOT ENABLED 33_5%_2 SATA1TXP AP10
0 : (DEFAULT) NO REBOOT DISABLED
24A2 IN HDA_3S_SDIN0 E34 AD7 SATA_MINICARD_RX_DN IN 28C7
IHDA
HDA_SDIN0 SATA2RXN
SATA2RXP AD5 SATA_MINICARD_RX_DP IN 28C7
G34 HDA_SDIN1 SATA2TXN AH5 SATA_MINICARD_TX_DN OUT 28C7
AH4 SATA_MINICARD_TX_DP OUT 28C7
STRAP C34 HDA_SDIN2
SATA2TXP
FLASH OVERRIDE SATA3RXN AB8

FLASH_OVERRIDE 1 R4715 2 A34 AB10
FLASH DESCRIPTOR SECURITY OVERIDE 21D3 IN HDA_SDIN3 SATA3RXP
47B8 1K_5%_2 SATA3TXN AF3
1:ENABLE AF1
SATA3TXP
0:DISABLE : (DEFAULT INTERNAL PULL-DOWN) P3V3A R4716
OUT HDA_3S_SDOUT 1 2 A36
SATA
HDA_SDO
B 33_5%_2 STRAPPING
SATA4RXN Y7 B
Y5
21D3 FLASH_OVERRIDE 1 R4720 2 SATA4RXP
47B7
OUT C36 HDA_DOCK_EN#/GPIO33 SATA4TXN AD3
10K_5%_2_DY SATA4TXP AD1
47A7 IN PCH_GPIO13 N32 HDA_DOCK_RST#/GPIO13
SATA5RXN Y3 SATA_ODD_RX_DN IN 29A7
R4718 Y1 SATA_ODD_RX_DP
1 2 SATA5RXP IN 29A7
HDA_3S_SYNC_R 1 R4714 2 AB3 SATA_ODD_TX_DN
OUT SATA5TXN OUT 29A7
1 TP4720 PCH_TCK J3 AB1 SATA_ODD_TX_DP
JTAG
1K_5%_2 RSC_0402_DY OUT JTAG_TCK SATA5TXP OUT 29A7
TP30
47D3 OUT 1 TP4721 PCH_TMS H7 JTAG_TMS SATAICOMPO Y11 P1V05S
HDA_3S_SYNC_R(PLL ODVR VOLTAGE) TP30 R4747
1 : VCC VRM = 1.6V 47D3 OUT 1 TP4722 PCH_TDI K5 JTAG_TDI SATAICOMPI Y10 P1V05S_SATARCOMPO 1 2
0 : VCC VRM = 1.8V(DEFAULT) TP30 37.4_1%_2
47D3 OUT 1 TP4723 PCH_TDO H1 JTAG_TDO
TP30 SATA3RCOMPO AB12
P1V05S P3V3S
AB13 P1V05S_SATA3RCOMPO 1 R4748 2
SATA3COMPI
P3V3A 49.9_1%_2
1
R4713 21D6 21C7 EC_SPI_CLK T3 1 R4749
AH1 2
1 2 PCH_GPIO13 OUT SPI_CLK SATA3RBIAS
R4751 R4750 R4752
IN 47B6
750_1%_2
SPI
21D6 21C8 OUT EC_SPI_CS0# Y14 SPI_CS0# 10K_5%_2 10K_5%_2 10K_5%_2

10K_5%_2_DY
A EC_SPI_CS1# T1 A
2
21C8 OUT SPI_CS1#
SATALED# P3
21C7 21C6 OUT EC_SPI_SI V4 SPI_MOSI SATA0GP/GPIO21 V14
21C8 21C6 OUT EC_SPI_SO U3 SPI_MISO SATA1GP/GPIO19 P1

STRAPPING
2
ITL_BD82PPSM_QPJ4_FCBGA_989P
R4734
RSC_0402_DY
INVENTEC
1
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4700~4949(PCH) SMB_ALERT# OUT 48B2
U4700 P3V3A P3V3A

22B1 IN PCIE_LAN_RX_DN BG34 PERN1
PCIE_LAN_RX_DP BJ34 E12 1 R4795 2
22B1 IN C4724 PERP1 SMBALERT#/GPIO11
22C2 OUT PCIE_LAN_TX_DN 1 2 C4725 PCIE_LAN_TX_C_DN AV32 PETN1 10K_5%_2 SML1ALERT# R4796 2
1
SMBUS
PCIE_LAN_TX_DP 1 2 PCIE_LAN_TX_C_DP AU32 H14 PCH_3A_SMCLK 48D3 IN
22C2 OUT PETP1 SMBCLK BI 48A8
10K_5%_2
0.1UF_16V_2
PCIE_WLAN_RX_DN 0.1UF_16V_2 BE34 C9 PCH_3A_SMDATA 1 R4797 2
27B7 IN PERN2 SMBDATA BI 48A8
27B7 IN PCIE_WLAN_RX_DP C4726 BF34 PERP2
PCIE_WLAN_TX_DN 1 2 PCIE_WLAN_TX_C_DN BB32 2.2K_5%_2
27B7 OUT C4727 PETN2
27B7 OUT PCIE_WLAN_TX_DP 1 2 PCIE_WLAN_TX_C_DP AY32 PETP2 1 R4798 2
0.1UF_16V_2 SML0ALERT#/GPIO60 A12 DRAMRST_CNTRL_PCH OUT 41A8
0.1UF_16V_2 BG36 2.2K_5%_2
PERN3
BJ36 PERP3 SML0CLK C8 PCH_3A_ALERT_CLK OUT 27B3 48D2 48D3 27B3 IN PCH_3A_ALERT_CLK 1 R4799 2
AV34 PETN3
D AU34 G12 PCH_3A_ALERT_DAT 27B3 48D2
2.2K_5%_2
PETP3 SML0DATA OUT PCH_3A_ALERT_DAT R4800 D
48D3 27B3 1 2
IN
PCI-E*
BF36 PERN4
BE36 2.2K_5%_2
PERP4
AY34 PETN4 SML1ALERT#/PCHHOT#/GPIO74 C13 SML1ALERT# IN 48D2
P3V3A SML1_CLK P3V3A
2
48D7 R4775 BB34 48D3
22C5 OUT CLKREQ_LAN# 1 2 48D8 R4773
PETP4 BI
48C7 10K_5%_2_DY
22C5
48C7
OUT CLKREQ_LAN# 1 2 SML1CLK/GPIO58 E14 SML1_CLK OUT 48D2
Q4702
BG37
S
PERN5
48D7 10K_5%_2 BH37 M16 SML1_DATA
R4776 2 P3V3S OUT 48C2
OUT CLKREQ_WLAN#
PERP5 SML1DATA/GPIO75
27C7 1 G 1
48B7 AY36 PETN5
10K_5%_2_DY 48D8 R4772
D
27C7
48B7
OUT CLKREQ_WLAN# 1 2 BB36 PETP5
EC_SMB3_CLK SSM3K7002FU_DY
10K_5%_2 BI
3
BJ38 PERN6
BG38 PERP6
AU36 PETN6 CL_CLK1 M7
CLOCK TERMINATION FOR FICM AV36 PETP6
SML1_DATA
2
48D3 BI
STUFF FOR INTEGRATED CLK
Controller
BG40 PERN7 CL_DATA1 T11 Q4703
Link
BJ40
S
PERP7
R4777 AY40
48B3 IN CLKIN_DMI_PCH_DN 1 2 PETN7 G 1
BB40 PETP7 CL_RST1# P10 P3V3A
10K_5%_2 R4753
D
BE38 PERN8
48C3 OUT CLKREQ_GPU# 1 2
BI EC_SMB3_DATA SSM3K7002FU_DY
R4778
3
C 48B3 CLKIN_DMI_PCH_DP 1 2
BC38 PERP8 10K_5%_2 C
IN AW38 PETN8
10K_5%_2 AY38 PETP8
R4779 M10 CLKREQ_GPU#

CLKIN_BUF_DOT96_DN 1 2 PEG_A_CLKRQ#/GPIO47 OUT 48C3
48B3 IN CLK_PCIE_LAN_DN Y40
22C2 OUT CLKOUT_PCIE0N
10K_5%_2 CLK_PCIE_LAN_DP Y39
22C2 OUT CLKOUT_PCIE0P
48D8 CLKOUT_PEG_A_N AB37 CLK_PEG_REF_DN OUT 57B6

R4780 CLKREQ_LAN# J2 AB38 CLK_PEG_REF_DP
CLKIN_BUF_DOT96_DP 1 2 22C5 IN PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P OUT 57B6
48B3 IN 48D7 XTAL25_OUT OUT 48A3
10K_5%_2
1
27C7 OUT CLK_PCIE_WLAN_DN AB49 CLKOUT_PCIE1N CLKOUT_DMI_N AV22 CLK_DMI_PCH_DN OUT 41D2
R4781 CLK_PCIE_WLAN_DP AB47 AU22 CLK_DMI_PCH_DP
CLKIN_PCH14 1 2 27C7 OUT CLKOUT_PCIE1P CLKOUT_DMI_P OUT 41D2
48A3 IN R4801
10K_5%_2 48D8 1M_5%_2
27C7 IN CLKREQ_WLAN# M1 PCIECLKRQ1#/GPIO18
48D7 CLKOUT_DP_N AM12
X4701
2
R4782 AM13
48B3 IN CLKIN_SATA1_DP 1 2 P3V3A TP24
1
CLKOUT_DP_P
1 2 XTAL25_IN OUT 48A3
TP4706 AA48 CLKOUT_PCIE2N
10K_5%_2
CLOCKS
TP4707 TP24
1 AA47 CLKOUT_PCIE2P 25MHZ
CLKIN_DMI_PCH_DN
1
R4803 BF18 48C8
R4783 1 2
CLKIN_DMI_N
CLKIN_DMI_PCH_DP IN
V10 BE18 48C8
48B3 IN CLKIN_SATA1_DN 1 2 PCIECLKRQ2#/GPIO20 CLKIN_DMI_P IN
10K_5%_2_DY C4728 C4729
10K_5%_2 R4837 33PF_50V_2 27PF_50V_2
B TP24 1 Y37 CLKOUT_PCIE3N CLKIN_GND1_N BJ30 1 2 B
TP4703 TP24 1 Y36 BG30
2
CLKOUT_PCIE3P CLKIN_GND1_P
TP4704
R4789 10K_5%_2
1 2 A8 PCIECLKRQ3#/GPIO25
10K_5%_2_DY CLKIN_DOT_96N G24 CLKIN_BUF_DOT96_DN IN 48C8
CLKIN_DOT_96P E24 CLKIN_BUF_DOT96_DP IN 48C8
Y43 CLKOUT_PCIE4N
Y45 CLKOUT_PCIE4P
R4790 CLKIN_SATA_N AK7 CLKIN_SATA1_DN IN 48B8
1 2 L12 PCIECLKRQ4#/GPIO26 CLKIN_SATA_P AK5 CLKIN_SATA1_DP IN 48B8
P3V3S P3V3A SMB_ALERT# 1 B500 2
10K_5%_2_DY 48D3 IN
P5V0S PASSWORD_0805
V45 CLKOUT_PCIE5N REFCLK14IN K45 CLKIN_PCH14 IN 48B8
V46 CLKOUT_PCIE5P
1
2.2K_5%_2 R4791
R4784 R4785 1 2 L14 PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK H45 CLKIN_PCI_FB IN 51A7
R4787
2.2K_5%_2 10K_5%_2_DY
2.2K_5%_2
R4786
2.2K_5%_2 AB42 CLKOUT_PEG_B_N XTAL25_IN V47 XTAL25_IN OUT 48B1
2
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49 XTAL25_OUT OUT 48C1

39C8 R4792
PCH_3S_SMCLK
2
20A7
38C8
BI 1 2 E6 PEG_B_CLKRQ#/GPIO56
P1V05S
Q4700
10K_5%_2_DY R4802
S
XCLK_RCOMP Y47 1 2
A G 1 V40 CLKOUT_PCIE6N 90.9_1%_2
A
V42
D
CLKOUT_PCIE6P
PCH_3A_SMCLK R4793 CLOSE TO PCH
48D3 BI SSM3K7002BFU 1 2 T13 PCIECLKRQ6#/GPIO45
3
10K_5%_2_DY TP24
FLEX CLOCKS
V38 K43 1
PCH_3A_SMDATA CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64
3
48D3 BI V37 TP4700

CLKOUT_PCIE7P TP24
Q4701 F47 1
R4794 CLKOUTFLEX1/GPIO65
TP4701
D
1 2 K12 PCIECLKRQ7#/GPIO46
G 1 TP24
INVENTEC
10K_5%_2_DY CLKOUTFLEX2/GPIO66 H47 1
AK14 TP4702
S
CLKOUT_ITPXDP_N
39C8 AK13 K49
20A7 BI PCH_3S_SMDATA SSM3K7002BFU
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67
38C8
2
TITLE
ITL_BD82PPSM_QPJ4_FCBGA_989P MODEL,PROJECT,FUNCTION
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DSWVRMEN - DEEP S4/S5 WELL ON-DIE VOLTAGE REGULATOR ENABLE

U4700
HIGH-ENABLED(DEFAULT)
42D7 DMI_RX0_DN BC24 BJ14 FDI_TX0_DN 42C7 LOW-DISABLED
IN DMI_RX1_DN BE20
DMI0RXN FDI_RXN0
AY14 FDI_TX1_DN IN
D 42D7 IN DMI1RXN FDI_RXN1 IN 42C7
42D7 DMI_RX2_DN BG18 BE14 FDI_TX2_DN 42C7 D
IN DMI_RX3_DN BG20
DMI2RXN FDI_RXN2
BH13 FDI_TX3_DN IN
42D7 IN DMI3RXN FDI_RXN3 IN 42C7
BC12 FDI_TX4_DN 42C7 P3V3_RTC
DMI_RX0_DP BE24
FDI_RXN4
BJ12 FDI_TX5_DN IN
42D7 IN DMI0RXP FDI_RXN5 IN 42C7
42D7 DMI_RX1_DP BC20 BG10 FDI_TX6_DN 42C7
IN DMI_RX2_DP BJ18
DMI1RXP FDI_RXN6
BG9 FDI_TX7_DN IN
42C7 IN DMI2RXP FDI_RXN7 IN 42C7
DMI_RX3_DP
1
42C7 BJ20
IN DMI3RXP
BG14 FDI_TX0_DP
FDI_RXP0 IN 42C7
DMI_TX0_DN AW24 BB14 FDI_TX1_DP STRAPPING
DMI
42D7 OUT DMI0TXN FDI_RXP1 IN 42C7 R4829
FDI
42D7 DMI_TX1_DN AW20 BF14 FDI_TX2_DP 42C7 330K_5%_2
OUT DMI_TX2_DN BB18
DMI1TXN FDI_RXP2
BG13 FDI_TX3_DP IN
42D7 OUT DMI2TXN FDI_RXP3 IN 42C7
P1V05S DMI_TX3_DN AV18 BE12 FDI_TX4_DP
2
42D7 OUT DMI3TXN FDI_RXP4 IN 42C7
BG12 FDI_TX5_DP 42C7
DMI_TX0_DP AY24
FDI_RXP5
BJ10 FDI_TX6_DP IN
42D7 OUT DMI0TXP FDI_RXP6 IN 42C7
DMI_TX1_DP FDI_TX7_DP
1
42D7 AY20 BH9 42B7

OUT DMI1TXP FDI_RXP7 IN
1
42D7 DMI_TX2_DP AY18
R4812 OUT DMI_TX3_DP AU18
DMI2TXP
42D7 OUT DMI3TXP
AW16 FDI_INT R4830
49.9_1%_2 FDI_INT OUT 42B7
330K_5%_2_DY
BJ24 AV12 FDI_FSYNC0
2
DMI_ZCOMP FDI_FSYNC0 OUT 42B7
2
BG25 BC10 FDI_FSYNC1 42B7
DMI_IRCOMP FDI_FSYNC1 OUT
R4814
C 1 2 BH21 AV14 FDI_LSYNC0 42B7
C
DMI2RBIAS FDI_LSYNC0 OUT
750_1%_2 BB10 FDI_LSYNC1 42B7
P3V3S
FDI_LSYNC1 OUT
P3V3A
1
DSWVRMEN A18
1
R4832
R4815 STRAPPING
R4816 R4831
10K_5%_2 SUSACK# 1 2 C12 E22 1 2 RSMRST# 1K_5%_2_DY
IN SUSACK# DPWROK IN 21D1 21D3 49B7
SHORT_0402
0_5%_2_DY
2
2
SYS_RESET# K3 B9 PCIE_WAKE#
System Power Management

41C1 IN SYS_RESET# WAKE# IN 22B5 27C7 49A5
P3V3_LDO
40B4 11C7 11A4 CORE_PG P12 N3 PCI_3S_CLKRUN# 21E3 49A5
IN SYS_PWROK CLKRUN#/GPIO32 IN
1
PCH_PWROK L22 G8
49A6 21B6 IN PWROK SUS_STAT#/GPIO61
R4883
10K_5%_2_DY
L10 N14 EC_32KHZ 21B6 P3V3_LDO
APWROK SUSCLK/GPIO62 OUT
B B
2
P3V3A SLP_S5_3R
OUT
PM_DRAM_PWRGD B13 D10 SLP_S5#_3R
3
41C7 OUT DRAMPWROK SLP_S5#/GPIO63 OUT 14D2 21D3
Q4713
1
1
R4817
D
49C2
21D1 RSMRST# C21 H41 2 1 G R4834
21D3
IN RSMRST# SLP_S4#
R4820 0_5%_2_DY 10K_5%_2
S
10K_5%_2_DY SUS_PWR_ACK
K16 F4 SLP_S3#_IC_3R
2
49A5 OUT SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# SSM3K7002FU_DY SLP_S3_3R 15B8
3 2
D4706
2
2
OUT 15A4
15B4
NC
EC_PWRSW# 3 1 E20 G10 16A7

21D6 IN PWRBTN# INT. PU 20K SLP_A# Q4714
D
1 G
ACPRESENT H20 G16 SLP_SUS#
2
BAT54_30V_0.2A 49A5 21D6 IN ACPRESENT/GPIO31 INT. PD 20K SLP_SUS# OUT
S
D4707
NC
SSM3K7002BFU
LOW_BAT#_3 3 1 E10 AP14 H_PM_SYNC
2
21D6 IN BATLOW#/GPIO72 INT. PU 20K PMSYNCH BI 41C5
P3V3A
BAT54_30V_0.2A 49A5 IN PM_RI# A10 RI# SLP_LAN#/GPIO29 K14 PCH_GPIO29 IN 49A5
P3V3A
5
U4704
R4822 P3V3A 1
A A
+
1 2
4 SLP_S3#_3R 13A2 13D2 14A6 14B8 14D2 21D6
ACPRESENT 1 2 2
OUT 45D3
2
49A6 21D6 IN R4824 10K_5%_2
8.2K_5%_2
-
PCH_PWROK SUS_PWR_ACK 1 2 TC7SZ08FU R4710
49B7 21B6 IN 49B7 IN R4825 10K_5%_2
3
1
PM_RI# 1 2 100K_5%_2
49A6 IN R4826 10K_5%_2
R4823
1
49B3 27C7 22B5 PCIE_WAKE# R4827 1 2 10K_5%_2
10K_5%_2 IN
49A3 IN PCH_GPIO29 R4821 1 2 10K_5%_2
INVENTEC
2
P3V3S
TITLE
PCI_3S_CLKRUN# 8.2K_5%_2 Block Diagram
49B3 21E3 IN R48281 2
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3S
1
D R4855
100K_5%_2
D
2
U4700
1
21E7 OUT PCH_LCM_BKLTEN J47 L_BKLTEN SDVO_TVCLKINN AP43

R4856 R4857 34D7 OUT PCH_LCM_VDDEN M45 L_VDD_EN SDVO_TVCLKINP AP45
2.2K_5%_2 2.2K_5%_2
34B5 OUT PCH_INV_PWM_3 P45 L_BKLTCTL SDVO_STALLN AM42
SDVO_STALLP AM40
2
34C5 OUT PCH_LVDS_DDCCLK T40 L_DDC_CLK

34C5 OUT PCH_LVDS_DDCDATA K47 L_DDC_DATA SDVO_INTN AP39
SDVO_INTP AP40
T45 L_CTRL_CLK
P39 L_CTRL_DATA
WHEN 1- LVDS IS DETECTED
R4858
PCH_LVDS_DDCDATA - LVDS DETECT 1 2 AF37 LVD_IBG SDVO_CTRLCLK P38
AF36 LVD_VBG SDVO_CTRLDATA M39
2.37K_1%_2
HIGH-LVDS ENABLED AE48
LVDS
LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
LOW-LVDS DISABLED (DEFAULT) DDPB_AUXP AT47
DDPB_HPD AT40
C 34B8 PCH_LVDS_TXCL_DN AK39 C
OUT PCH_LVDS_TXCL_DP
LVDSA_CLK#
34B8 AK40 AV42
OUT LVDSA_CLK DDPB_0N
DDPB_0P AV40
34B8 PCH_LVDS_TXDL0_DN AN48 AV45
OUT PCH_LVDS_TXDL1_DN
LVDSA_DATA#0 DDPB_1N
34B8 AM47 AV46
OUT PCH_LVDS_TXDL2_DN
LVDSA_DATA#1 DDPB_1P
34B8 AK47 AU48
OUT LVDSA_DATA#2 DDPB_2N
Digital Display Interface

AJ48 LVDSA_DATA#3 DDPB_2P AU47
DDPB_3N AV47
34B8 OUT PCH_LVDS_TXDL0_DP AN47 LVDSA_DATA0 DDPB_3P AV49
34B8 OUT PCH_LVDS_TXDL1_DP AM49 LVDSA_DATA1
34B8 OUT PCH_LVDS_TXDL2_DP AK49 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46 PCH_HDMI_DDCCLK BI 36D8
DDPC_CTRLDATA P42 PCH_HDMI_DDCDATA BI 36D8
AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
AH45 AT38 PCH_HPDET 36B5
LVDSB_DATA#0 DDPC_HPD IN
AH47 LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47 PCH_HDMI_TX2_DN OUT 36A5
AF45 LVDSB_DATA#3 DDPC_0P AY49 PCH_HDMI_TX2_DP OUT 36A5
DDPC_1N AY43 PCH_HDMI_TX1_DN OUT 36A5
B AH43 LVDSB_DATA0 DDPC_1P AY45 PCH_HDMI_TX1_DP OUT 36A5 B
AH49 LVDSB_DATA1 DDPC_2N BA47 PCH_HDMI_TX0_DN OUT 36A5
AF47 LVDSB_DATA2 DDPC_2P BA48 PCH_HDMI_TX0_DP OUT 36A5
AF43 LVDSB_DATA3 DDPC_3N BB47 PCH_HDMI_TXC_DN OUT 36A5
DDPC_3P BB49 PCH_HDMI_TXC_DP OUT 36A5
35D8 OUT PCH_CRTB N48 CRT_BLUE DDPD_CTRLCLK M43
CRT
35D8 OUT PCH_CRTG P49 CRT_GREEN DDPD_CTRLDATA M36
35D8 PCH_CRTR T49
OUT CRT_RED
R4859 AT45
DDPD_AUXN
1 2
OUT PCH_CRT_DDCCLK T39 CRT_DDC_CLK DDPD_AUXP AT43
35A2 OUT PCH_CRT_DDCDATA M40 CRT_DDC_DATA DDPD_HPD BH41
150_1%_2
R4860 BB43
DDPD_0N
1 2
OUT PCH_CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
35B2 OUT PCH_CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44
150_1%_2 BE44
DDPD_1P
R4861 DDPD_2N BF42
1 2 T43 DAC_IREF DDPD_2P BE42
T42 CRT_IRTN DDPD_3N BJ42
150_1%_2 DDPD_3P BG42
1
A R4862 ITL_BD82PPSM_QPJ4_FCBGA_989P A
1K_1%_2
2
CLOSE TO PCH
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4700~4949(PCH) U4700

RSVD1 AY7
RSVD2 AV7
BG26 TP1 RSVD3 AU3
BJ26 TP2 RSVD4 BG4
BH25 TP3
BJ16 TP4 RSVD5 AT10
BG16 TP5 RSVD6 BC8
GPIO51 GPIO19 BOOT BIOS
AH38 TP6
BBS_BIT0 AH37 TP7 RSVD7 AU2

BBS_BIT1 DESTINATION AK43 AT4
TP8 RSVD8
AK45 AT3
0 1 RESERVED(NAND) C18
TP9
TP10
RSVD9
RSVD10 AT1
N30 AY3
1 0 ------ H3
TP11
TP12
RSVD11
RSVD12 AT5
AH12 AV3
1 1 SPI (DEFAULT) TP13 RSVD13
NVRAM
D AM4 TP14 RSVD14 AV1
0 0 LPC
AM5 TP15 RSVD15 BB1 D
RSVD
Y13 TP16 RSVD16 BA3
K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3
AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8
RSVD21 BD4
P3V3S RSVD22 BF6
B21 TP21 RSVD23 AV5

R4874 1 2 8.2K_5%_2 PCI_3S_INTA# BI 51B6 M20 TP22
AY16 TP23
1 2 PCI_3S_INTB# ROUTE WITH 90 OHMS IMPEDANCE BG46 AV10
R4875 8.2K_5%_2 BI 51B6 TP24 RSVD24
TOTAL LENGTH NO LONGER THAN 11 INCHES
R4876 1 2 8.2K_5%_2 PCI_3S_INTC# BI 51B6 RSVD25 AT8
R4877 1 2 8.2K_5%_2 PCI_3S_INTD# BI 51B6 32C6 BI USB3_PCH_RX1_DN BE28 USB3RN1 RSVD26 AY5
33C4 BI USB3_PCH_RX2_DN BC30 USB3RN2 RSVD27 BA2
R4878 1 2 8.2K_5%_2 RUNSCI0#_3 IN 21E3 52D6 BE32 USB3RN3
BJ32 USB3RN4 RSVD28 AT12 NOTE:
32C6 BI USB3_PCH_RX1_DP BC28 BF3
33C4 USB3_PCH_RX2_DP BE30
USB3RP1 RSVD29
USB2.0/3.0 COMBO-USB2.0 PORT 0,1 MAPPEDUSB3.0 PORT 1,2
DGPU_HOLD_RST# IN BI USB3RP2
R4880 1 2 10K_5%_2 51B6 57A6 BF32 USB3RP3
C BG32 C24 USB_P0_DN 32B8
C
PCI_3S_REQ2# USB3_PCH_TX1_DN
USB3RP4 USBP0N
USB_P0_DP BI 32C8 32B8 P0.P1 RESERVER FOR USB3.0
R4881 1 2 10K_5%_2 51B6 32B7 AV26 DEBUG PORT A24
IN BI USB3_PCH_TX2_DN
USB3TN1 USBP0P
USB_P1_DN BI
33B5 BI BB26 USB3TN2 USBP1N C25
BI 33C5 32C8
R4882 1 2 10K_5%_2 DGPU_PWR_EN# IN 16A3 51B6 AU28 USB3TN3 USBP1P B25 USB_P1_DP BI 33C5
AY30 USB3TN4 USBP2N C26 USB_P2_DN BI 30C5
32B7 BI USB3_PCH_TX1_DP AU26 USB3TP1 USBP2P A26 USB_P2_DP BI 30C5
33B5 BI USB3_PCH_TX2_DP AY26 USB3TP2 USBP3N K28
R4838 1 2 10K_5%_2 SATA_ODD_DA# IN 29A5 51B6 AV28 USB3TP3 USBP3P H28
AW30 USB3TP4 USBP4N E28
R4956 1 2 10K_5%_2 PCI_3S_PIRQG# IN 51B6 USBP4P D28
USBP5N C28
R4879 1 2 10K_5%_2 PCI_3S_PIRQH# IN 51B6 USBP5P A28
USBP6N C29
R4957 1 2 10K_5%_2 PCI_3S_PIRQE# 51B6

BBS STRAPING USBP6P B29
IN 51D7 BI PCI_3S_INTA# K40 PIRQA# USBP7N N28
BBS_BIT1 51C7 BI PCI_3S_INTB# K38 PIRQB# USBP7P M28
51C7 BI PCI_3S_INTC# H38 L30 USB_CR_DN BI 26A8
PIRQC# USBP8N
CARD READER
PCI
51C7 BI PCI_3S_INTD# G38 PIRQD# USBP8P K30 USB_CR_DP BI 26A8
USB
STP_A16OVR G30 USB_WLAN_DN BI 27B3
USBP9N
WLAN
2
51C7 OUT DGPU_HOLD_RST# C46 REQ1#/GPIO50 USBP9P E30 USB_WLAN_DP BI 27B3

51C7 57A6
OUT PCI_3S_REQ2# C44 C30 USB_CAM_DN BI 34B3
R4885 R4886
16A3 DGPU_PWR_EN# E40
REQ2#/GPIO52 USBP10N
A30 USB_CAM_DP 34B3
WEBCAM
51C7
OUT REQ3#/GPIO54 USBP10P
USB_3G_DN BI
B 1K_5%_2_DY 1K_5%_2_DY USBP11N L32
BI 28C3
3G B
D47 GNT1#/GPIO51 USBP11P K32 USB_3G_DP BI 28C3
1
E42 GNT2#/GPIO53 USBP12N G32

F46 GNT3#/GPIO55 USBP12P E32
USED AS GPIO ONLY. USBP13N C32
INT. PU 20K
LOW=A16 SWAP OVERRIDE USBP13P A32
51B7 BI PCI_3S_PIRQE# G42 PIRQE#/GPIO2
STP_A16OVR SATA_ODD_DA# G40
51C7 29A5 BI PIRQF#/GPIO3 R4835
TOP-BLOCK SWAP OVERRIDE 51C7 BI PCI_3S_PIRQG# C42 PIRQG#/GPIO4 USBRBIAS# C33 1 2
51B7 BI PCI_3S_PIRQH# D44 PIRQH#/GPIO5
HIGH=DEFAULT
P3V3A 22.6_1%_3
USBRBIAS B33
1 R4887 2 P3V3A_PME# K10 CLOSE TO PCH
PME# INT. PU 20K
PLT_RST# 10K_5%_2_DY C6 A14 MACHINE_ID0

41C7 36B2 BI PLTRST# OC0#/GPIO59 IN 51A3 51A5
OC1#/GPIO40 K20 MACHINE_ID1 IN 51A3 51A5
OC2#/GPIO41 B17 MACHINE_ID2 IN 51A3 51A5
P3V3A 21E3 OUT CLK_KBPCI R4889 1 2 22_5%_2 CLK_KBPCI_R H49 CLKOUT_PCI0 OC3#/GPIO42 C16 MACHINE_ID3 IN 51A3 51A5
48A3 OUT CLKIN_PCI_FB R4890 1 2 22_5%_2 CLK_PCI_FB_R H43 CLKOUT_PCI1 OC4#/GPIO43 L16 MACHINE_ID4
MACHINE_ID5 IN 51A3 51A5
J48 A16 51A3 51A5
TP24 CLKOUT_PCI2 OC5#/GPIO9
MACHINE_ID6 IN
1 K42 D14
5
CLKOUT_PCI3 OC6#/GPIO10 IN 51A3 51A5

TP4717
OUT CLK_PCI_DEBUG R4891 MACHINE_ID1_DB
U4705 27C7 1 2 22_5%_2 H40 C14 51A3 51A5
CLK_PCI_DEBUG_R
CLKOUT_PCI4 OC7#/GPIO14 IN
1
+
BUF_PLT_RST# 4 C4800
28C3 27C7 27C3 21E3 BI 1 2 ITL_BD82PPSM_QPJ4_FCBGA_989P
57A6 TO BE USED AS GPIO
A 2 A
2
MCAHINE ID 0: USB ID0 CSC0402_DY

R4888 TC7SZ08FU
MACHINE ID 1: POWER EXPRESS (YES:1 NO:0)
3
100K_5%_2 P3V3A MACHINE_ID0 1 2

51A2 OUT R4900 10K_5%_2_DY
MACHINE ID 2: UMA:1 / DIS.:0 51A5
1
MACHINE_ID0 51A2 OUT MACHINE_ID1 R4901 1 2 10K_5%_2_DY

MACHINE ID 3: MAINSTREAM:1 / ENTRY:0 51A3 51A2 R4892 1 2 10K_5%_2
OUT MACHINE_ID1
51A5
MACHINE_ID2
51A3 51A2 R4893 1 2 10K_5%_2 51A2 R4902 1 2 10K_5%_2_DY
MACHINE ID 4: HDMI:1 / NO HDMI:0 OUT MACHINE_ID2 51A5
OUT
51A3 51A2 R4894 1 2 10K_5%_2
OUT MACHINE_ID3 51A2 OUT MACHINE_ID3 R4903 1 2 10K_5%_2_DY
MACHINE ID 5: SLEEP&CHARGE&DOLBY:(YES1 / NO 0) R4895 1 2 10K_5%_2
OUT
INVENTEC
51A5
51A3 51A2 OUT MACHINE_ID4 R4896 1 2 10K_5%_2 51A2 OUT MACHINE_ID4 R4904 1 2 10K_5%_2_DY
MACHINE ID 6: USB ID1 MACHINE_ID5 1 2 51A5
51A3 51A2 OUT R4897 10K_5%_2 MACHINE_ID5 1 2
MACHINE_ID6 1 2 51A2 OUT R4905 10K_5%_2_DY
MACHINE ID 1_DB : 35W CPU ONLY :1 / 35W&45W CPU:0 OUT R4898 10K_5%_2 51A5
51A3 51A2 OUT MACHINE_ID1_DB R4899 1 2 10K_5%_2_DY 51A2 OUT MACHINE_ID6 R4906 1 2 10K_5%_2_DY TITLE
51A5
51A5 51A2 OUT MACHINE_ID1_DB R4907 1 2 10K_5%_2 MODEL,PROJECT,FUNCTION
USB3.0 X2 / 2.0 X1 USB3.0 X1 / 2.0 X2 USB2.0 X3 Block Diagram
NOTE:10K_5%(60130B1030ZT) DOC.NUMBER REV
USB ID0 1 1 0 CODE
NOTE:10K_5%(60130B1030ZT) SIZE
A3 CS
1310xxxxx-0-0 X01
USB ID1 1 0 1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3A
R4928 1 2 10K_5%_2 PCH_GPIO27 OUT 52C6

R4908 1 2 1K_5%_2_DY PCH_GPIO15 OUT 52C6
R4909 1 2 10K_5%_2 PCH_GPIO8 52D6 P3V3S
OUT
R4910 1 2 10K_5%_2_DY PCH_GPIO12 OUT 52C6
1 2 10K_5%_2_DY PCH_GPIO24 1 R4721 2
R4911 OUT 52C6
D 33K_5%_2_DY
D
P3V3S U4700 P3V3S
MSATA_DET SATA_ODD_PWREN
28C6 T7 C40 29B8
IN BMBUSY#/GPIO0 TACH4/GPIO68 OUT
R4927 1 2 10K_5%_2 PCH_GPIO6 OUT 52D6 28C2 IN 3G_ON# A42 TACH1/GPIO1 TACH5/GPIO69 B41 R4724 1 2 10K_5%_2
R4916 1 2 10K_5%_2 PCH_GPIO22 OUT 52C6 52C7 PCH_GPIO6

52D7 H36 C41 R4725 1 2 10K_5%_2_DY
PCH_GPIO38 IN TACH2/GPIO6 TACH6/GPIO70
R4917 1 2 10K_5%_2 52B6
OUT RUNSCI0#_3
51C7 21E3 E38 A40 R4726 1 2 10K_5%_2_DY
R4915 1 2 10K_5%_2 PCH_GPIO16 OUT 52C6 IN TACH3/GPIO7 TACH7/GPIO71
R4919 1 2 10K_5%_2 SATA_ODD_PRSNT# OUT 29A5 52B6 52D7 OUT PCH_GPIO8 C10 GPIO8 INT. PU 20K
INT. PU 20K
R4920 1 2 10K_5%_2 PCH_GPIO39 OUT 52B6 PCH_GPIO12

52D7 C4
PCH_GPIO48 OUT LAN_PHY_PWR_CTRL/GPIO12
R4921 1 2 10K_5%_2 52B6
OUT PCH_GPIO15 INT. PD 20K
52D7 G2 P4 EC_3S_A20GATE 21E2
OUT GPIO15
STRAPPING
A20GATE IN
AU16 PCH_PECI 1 R4940 2 H_PECI
PECI OUT 21A6 41D5
52D7 OUT PCH_GPIO16 U2 SATA4GP/GPIO16 0_5%_2_DY
CPU/MISC
R4727 1 2 PCH_GPIO22 P5 KBRST#
GPIO
10K_5%_2_DY OUT 52C6 52D7 RCIN# IN 21D2
INT. PU 20K
13C8 13B2 IN DGPU_PWRGD D40 TACH0/GPIO17 PROCPWRGD AY11 H_CPUPWRGD

OUT 41C5
52D7 52C7 OUT PCH_GPIO22 T5 SCLOCK/GPIO22 THRMTRIP# AY10 THRMTRIP#_R

C C
P1V05S P1V05S
52D7 OUT PCH_GPIO24 E8 GPIO24 INIT3_3V# T14
PCH_GPIO27
1
52D7 E16
IN GPIO27 INT.PD 20K
1
STRAPPINGDF_TVS AY1
P3V3S 52A7 PLL_ODVR_EN STRAPPING
P8 R4942 R4944
OUT GPIO28 INT. PU 20K
TS_VSS1 AH8 56_5%_2 56_5%_2
R4929 1 2 10K_5%_2 K1 STP_PCI#/GPIO34
AK11
2
TS_VSS2 R4941 R4943
2
R4930 1 2 10K_5%_2_DY K4 GPIO35 1 2 1 2 PM_THRMTRIP# IN 40A4
TS_VSS3 AH10 41D5
0_5%_2_DY
R4932 1 2 10K_5%_2 V8 SATA2GP/GPIO36 390_5%_2
INT. PD 20K TS_VSS4 AK10
PCH_GPIO37STRAPPING M5 BOTH THESE SHOULD BE CLOSE TO PCH
52B7 OUT SATA3GP/GPIO37
NC_1 P37
52D7 OUT PCH_GPIO38 N2 SLOAD/GPIO38 NV_CLE OUT 41D6
PCH_GPIO39STRAPPING M3 FOLLOW EDS1.0
52C7 OUT SDATAOUT0/GPIO39
OUT PCH_GPIO48
STRAPPING
52C7 V13 SDATAOUT1/GPIO48 VSS_NCTF_15 BG2
52D7 29A5 OUT SATA_ODD_PRSNT# V3 SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16 BG48

B B
27C7 27B7 OUT BTIFON# D6 GPIO57 VSS_NCTF_17 BH3
FDI_OVRVLTG(GPIO37) VSS_NCTF_18 BH47
LOW- TX,RXTERMINATED TO SAME VOLTAGE A4 VSS_NCTF_1 VSS_NCTF_19 BJ4

(DC COUPLING MODE) DEFAULT A44 BJ44
VSS_NCTF_2 VSS_NCTF_20
P3V3S A45 VSS_NCTF_3 VSS_NCTF_21 BJ45
NCTF
R4934 1 2 10K_5%_2 PCH_GPIO37 52B6 A46 BJ46
OUT VSS_NCTF_4 VSS_NCTF_22
R4935 1 2 100K_5%_2_DY
A5 VSS_NCTF_5 VSS_NCTF_23 BJ5
A6 VSS_NCTF_6 VSS_NCTF_24 BJ6
B3 VSS_NCTF_7 VSS_NCTF_25 C2
B47 VSS_NCTF_8 VSS_NCTF_26 C48
BD1 VSS_NCTF_9 VSS_NCTF_27 D1

PLL_ODVR_EN(PLL ON DIE VR ENABLE)(GPIO28)
BD49 VSS_NCTF_10 VSS_NCTF_28 D49
A HIGH-ENABLED (DEFAULT) A
LOW-DISABLED BE1 VSS_NCTF_11 VSS_NCTF_29 E1
P3V3A BE49 VSS_NCTF_12 VSS_NCTF_30 E49
BF1 VSS_NCTF_13 VSS_NCTF_31 F1

1 R4950 2 PLL_ODVR_EN
IN 52C6 BF49 F49
VSS_NCTF_14 VSS_NCTF_32
10K_5%_2
R4936 ITL_BD82PPSM_QPJ4_FCBGA_989P
1 2
10K_5%_2_DY INVENTEC
STRAP TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V05S P3V3S
1.3A U4700 L4700
AA23 U48 15MIL P3V3S_VCCADAC 1 2
VCCCORE[1]
POWER VCCADAC
1
1
1
AC23 VCCCORE[2] FBM_11_160808_121T
P3V3S C4784
CRT
AD21 VCCCORE[3] C4783
1
AD23 U47 C4782
VCC CORE
VCCCORE[4] VSSADAC
1
C4772 C4773 C4774 C4775 AF21 VCCCORE[5] 0.1UF_16V_2
0_5%_2
AF23 22UF_6.3V_5 0.01UF_50V_2
VCCCORE[6]
R4931
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2
2
D 10UF_6.3V_3 AG21
2
VCCCORE[7]
AG23 VCCCORE[8] R4933 D
2
AG24 VCCCORE[9] VCCALVDS AK36 15MIL 1 2
2
AG26 VCCCORE[10]
AG27 VCCCORE[11] VSSALVDS AK37 0_5%_2_DY P1V8S
AG29 VCCCORE[12]
AJ23
LVDS
L4701
AJ26
VCCCORE[13]
VCCCORE[14] VCCTX_LVDS[1] AM37 15MIL P1V8S_VCCTX_LVDS 1 2
0_5%_2_DY
1
1
AJ27 VCCCORE[15]
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 C4785 C4786 C4787 FBM_11_160808_121T
R4937
AJ31 VCCCORE[17]
P1V05S VCCTX_LVDS[3] AP36
0.01UF_50V_2 0.01UF_50V_2 22UF_6.3V_5
AP37
2
20MIL AN19
VCCTX_LVDS[4]
P1V05S VCCIO[28]
R4945
P1V05S 1 2 P1V05S_VCCAPLLEXP BJ22 P3V3S
HVCMOS
VCCAPLLEXP
15MIL
0_5%_2_DY V33
3A AN16 VCCIO[15]
VCC3_3[6]
C4788
1 2
AN17 VCCIO[16]
VCC3_3[7] V34
1
1
C 0.1UF_16V_2 C
C4777 C4778 C4779 C4780
C4776
AN21 VCCIO[17]
10UF_6.3V_3 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 P1V5S_VCCAFDI_VRM
AN26 VCCIO[18]
2
VCCVRM[3] AT16 15MIL

AN27 P1V05S
VCCIO
VCCIO[19]
AP21
DMI
VCCIO[20]
VCCDMI[1] AT20 15MIL
AP23 VCCIO[21] P1V05S C4789
1 2
AP24 VCCIO[22]
VCCCLKDMI AB36 15MIL 1UF_6.3V_2
P3V3S AP26 VCCIO[23]
C4790
1 2
AT24 VCCIO[24]
1UF_6.3V_2_DY P1V8S
1
AN33 VCCIO[25]
VCCDFTERM[1] AG16 15MIL
C4781 AN34 VCCIO[26]
B B
1
0.1UF_16V_2 15MIL BH29 VCC3_3[3] VCCDFTERM[2] AG17 C4791
2
P1V5S_VCCAFDI_VRM
NAND / SPI
AJ16 0.1UF_16V_2
VCCDFTERM[3] P3V3AL P3V3A
2
15MIL AP16 VCCVRM[2]
P1V05S VCCDFTERM[4] AJ17
2
R4946
1 2 P1V05S_VCCAFDIPLL BG6 R4947
VccAFDIPLL R4948
P1V05S
FDI
0_5%_2_DY 0_5%_2
0_5%_2_DY
P1V05S 20MIL AP17 VCCIO[27]
1
VCCSPI V1 15MIL
1
15MIL AU20 VCCDMI[2]
C4792
1UF_6.3V_2
2
A A
P1V5S_VCCAFDI_VRM P1V5S
R4949
1 2
40MIL 0_5%_3
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V05S P1V05S
P3V3A R4865 2 P1V05S_VCCACLK AD49
U4700
3A REFERENCE 4700~4949(PCH)
1 N26
P3V3S 15MIL VCCACLK
POWER VCCIO[29]
1
0_5%_2_DY
C4803 R4866 VCCIO[30] P26
2 1 1 2 T16 C4829
VCCDSW3_3
SHORT_0402 VCCIO[31] P28 1UF_6.3V_2
1
0.1UF_16V_2
C4804
2 1 V12 T27
2
C4801 C4802 DCPSUSBYP VCCIO[32]
P3V3A
2
0.1UF_16V_2 10UF_6.3V_3 0.1UF_16V_2_DY T29
VCCIO[33] P3V3A
20MIL T38 VCC3_3[5] D4708
NC
2
2
P1V05S 10MIL 3 BAT54_30V_0.2A
1
VCCSUS3_3[7] T23
P1V05S 1 R4867 2 P1V05S_VCCAPLLDMI2 BH23 VCCAPLLDMI2
C4830 P5V0A
USB
0_5%_2_DY VCCSUS3_3[8] T24
1 2
20MIL AL29 VCCIO[14]
VCCSUS3_3[9] V23 0.1UF_16V_2
D R4869 1 2 10_5%_5
C4805
1 2 AL24 DCPSUS[3] VCCSUS3_3[10] V24 P3V3A D
P1V05S 1UF_6.3V_2_DY
VCCSUS3_3[6] P24 10MIL
Clock and Miscellaneous

C4833 1 2 0.1UF_16V_2
C4831
1.1A AA19 VCCASW[1]
1 2 P1V05S
AA21 VCCASW[2] VCCIO[34] T26 20MIL 0.1UF_16V_2
2
C4806 C4807 AA24 VCCASW[3] V5REF_SUS M26 V5REF_SUS 10MIL P3V3S
NC
22UF_6.3V_5 22UF_6.3V_5 AA26 D4709 3 1 BAT54_30V_0.2A
VCCASW[4] C4832
DCPSUS[4] AN23 2 1 P3V3A
2
AA27 VCCASW[5]
P5V0S
P1V05S VCCSUS3_3[1] AN24 10MIL 1UF_6.3V_2_DY
AA29 VCCASW[6] R4870 1 2 10_5%_5
AA31 VCCASW[7]
C4834
10MIL
1
1
AC26 VCCASW[8] V5REF P34 V5REF 1 2
C4808 C4809 C4810
AC27 VCCASW[9] P3V3A 1UF_6.3V_2
PCI/GPIO/LPC
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 VCCSUS3_3[2] N20
C AC29 VCCASW[10]
10MIL C
2
2 VCCSUS3_3[3] N22
AC31 VCCASW[11] C4835
VCCSUS3_3[4] P20 1 2
AD29 VCCASW[12]
P1V05S VCCSUS3_3[5] P22 1UF_6.3V_2
AD31 VCCASW[13] P3V3S
L4706
1 2 P1V05S_VCCADPLLA W21 VCCASW[14] VCC3_3[1] AA16 20MIL
1
FBM_11_160808_121T W23 VCCASW[15] VCC3_3[8] W16 C4836 1 2 0.1UF_16V_2 P3V3S

C4812 C4813 C4814
W24 VCCASW[16] VCC3_3[4] T34
22UF_6.3V_5_DY 1UF_6.3V_2 10UF_6.3V_3 C4837 1 2 0.1UF_16V_2
W26 VCCASW[17]
1
2
C4811 W29 VCCASW[18] P3V3S

0.1UF_16V_2 W31 VCCASW[19]
VCC3_3[2] AJ2 20MIL
2
L4707 W33
1 2 P1V05S_VCCADPLLB VCCASW[20]
C4838 1 2 0.1UF_16V_2
VCCIO[5] AF13
FBM_11_160808_121T
1
B P1V05S B
P1V5S_VCCAFDI_VRM N16 DCPRTC
C4842 C4843 C4815 C4816 C4817
VCCIO[12] AH13 20MIL
0.1UF_16V_2 0.1UF_16V_2 C4839
22UF_6.3V_5_DY 1UF_6.3V_2 10UF_6.3V_3 15MIL Y49
SATA
VCCVRM[4] VCCIO[13] AH14 1 2
2
1UF_6.3V_2
VCCIO[6] AF14 P1V05S

15MIL BD47 VCCADPLLA L4708
VCCAPLLSATA AK1 P1V05S_VCCAPLLSATA 1 2 P1V5S_VCCAFDI_VRM
15MIL BF47 VCCADPLLB
P1V05S 0603_DY
VCCVRM[1] AF11 10MIL
20MIL AF17 VCCIO[7]
C4818 1UF_6.3V_2 AF33 VCCDIFFCLKN[1]
P1V05S
2 1 15MIL AF34 VCCDIFFCLKN[2] VCCIO[2] AC16
AG34 VCCDIFFCLKN[3]
C4819 1UF_6.3V_2
2 1 VCCIO[3] AC17 20MIL
C4840
15MIL AG33 VCCSSC VCCIO[4] AD17 1 2
C4820 1UF_6.3V_2
1UF_6.3V_2
2 1
C4821 0.1UF_16V_2 V16 DCPSST
2 1
MISC
A T17 T21 A
C4822 DCPSUS[1] VCCASW[22] P1V05S
P1V05S 1 2 V19 DCPSUS[2]
1UF_6.3V_2_DY
VCCASW[23] V21 20MIL
RTC CPU
10MIL BJ8 V_PROC_IO

1
VCCASW[21] T19
P3V3_RTC P3V3A
C4823 C4824 C4825
INVENTEC
HDA
4.7UF_6.3V_3 0.1UF_16V_2 0.1UF_16V_2 A22 VCCRTC VCCSUSHDA P32 10MIL

1
1
2
C4841
C4826 C4827 C4828 ITL_BD82PPSM_QPJ4_FCBGA_989P
TITLE
0.1UF_16V_2 1UF_6.3V_2 0.1UF_16V_2 0.1UF_16V_2 MODEL,PROJECT,FUNCTION
Block Diagram
2
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4700~4949(PCH) U4700

AY4 VSS[159] VSS[259] H46
AY42 VSS[160] VSS[260] K18
U4700 AY46 K26
VSS[161] VSS[261]
H5 VSS[0]
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
AA17 VSS[1] VSS[80] AK38
B15 VSS[164] VSS[264] K7
B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
B27 VSS[167] VSS[267] L20
B31 VSS[168] VSS[268] L26
AB11 VSS[6] VSS[85] AL16
B35 VSS[169] VSS[269] L28
B39 VSS[170] VSS[270] L36
B7 VSS[171] VSS[271] L48
F45 VSS[172] VSS[272] M12
BB12 VSS[173] VSS[273] P16
D AB5 VSS[11] VSS[90] AL23
BB16 VSS[174] VSS[274] M18
BB20 VSS[175] VSS[275] M22 D
AC19 VSS[13] VSS[92] AL27
BB22 VSS[176] VSS[276] M24
BB24 VSS[177] VSS[277] M30
BB28 VSS[178] VSS[278] M32
BB30 VSS[179] VSS[279] M34
BB38 VSS[180] VSS[280] M38
AC34 VSS[18] VSS[97] AM11
BB4 VSS[181] VSS[281] M4
AC48 VSS[19] VSS[98] AM14
BB46 VSS[182] VSS[282] M42
AD10 VSS[20] VSS[99] AM36
BC14 VSS[183] VSS[283] M46
AD11 VSS[21] VSS[100] AM39
BC18 VSS[184] VSS[284] M8
AD12 VSS[22] VSS[101] AM43
BC2 VSS[185] VSS[285] N18
AD13 VSS[23] VSS[102] AM45
BC22 VSS[186] VSS[286] P30
AD19 VSS[24] VSS[103] AM46
BC26 VSS[187] VSS[287] N47
AD24 VSS[25] VSS[104] AM7
BC32 VSS[188] VSS[288] P11
AD26 VSS[26] VSS[105] AN2
BC34 VSS[189] VSS[289] P18
AD27 VSS[27] VSS[106] AN29
BC36 VSS[190] VSS[290] T33
AD33 VSS[28] VSS[107] AN3
BC40 VSS[191] VSS[291] P40
AD34 VSS[29] VSS[108] AN31
BC42 VSS[192] VSS[292] P43
AD36 VSS[30] VSS[109] AP12
BC48 VSS[193] VSS[293] P47
AD37 VSS[31] VSS[110] AP19
BD46 VSS[194] VSS[294] P7
AD38 VSS[32] VSS[111] AP28
BD5 VSS[195] VSS[295] R2
AD39 VSS[33] VSS[112] AP30
BE22 VSS[196] VSS[296] R48
AD4 VSS[34] VSS[113] AP32
C AD40 VSS[35] VSS[114] AP38
BE26 VSS[197] VSS[297] T12 C
BE40 VSS[198] VSS[298] T31
BF10 VSS[199] VSS[299] T37
AD43 VSS[37] VSS[116] AP42
BF12 VSS[200] VSS[300] T4
AD45 VSS[38] VSS[117] AP46
BF16 VSS[201] VSS[301] W34
BF20 VSS[202] VSS[302] T46
AD8 VSS[40] VSS[119] AR2
BF22 VSS[203] VSS[303] T47
AE2 VSS[41] VSS[120] AR48
BF24 VSS[204] VSS[304] T8
AE3 VSS[42] VSS[121] AT11
BF26 VSS[205] VSS[305] V11
AF10 VSS[43] VSS[122] AT13
BF28 VSS[206] VSS[306] V17
AF12 VSS[44] VSS[123] AT18
BD3 VSS[207] VSS[307] V26
AD14 VSS[45] VSS[124] AT22
BF30 VSS[208] VSS[308] V27
AD16 VSS[46] VSS[125] AT26
BF38 VSS[209] VSS[309] V29
AF16 VSS[47] VSS[126] AT28
BF40 VSS[210] VSS[310] V31
AF19 VSS[48] VSS[127] AT30
BF8 VSS[211] VSS[311] V36
AF24 VSS[49] VSS[128] AT32
BG17 VSS[212] VSS[312] V39
AF26 VSS[50] VSS[129] AT34
BG21 VSS[213] VSS[313] V43
AF27 VSS[51] VSS[130] AT39
BG33 VSS[214] VSS[314] V7
AF29 VSS[52] VSS[131] AT42
BG44 VSS[215] VSS[315] W17
AF31 VSS[53] VSS[132] AT46
BG8 VSS[216] VSS[316] W19
AF38 VSS[54] VSS[133] AT7
BH11 VSS[217] VSS[317] W2
AF4 VSS[55] VSS[134] AU24
BH15 VSS[218] VSS[318] W27
AF42 VSS[56] VSS[135] AU30
BH17 VSS[219] VSS[319] W48
B AF46 VSS[57] VSS[136] AV16
BH19 VSS[220] VSS[320] Y12 B
AF5 VSS[58] VSS[137] AV20
H10 VSS[221] VSS[321] Y38
BH27 VSS[222] VSS[322] Y4
BH31 VSS[223] VSS[323] Y42
AG19 VSS[61] VSS[140] AV38
BH33 VSS[224] VSS[324] Y46
AG2 VSS[62] VSS[141] AV4
BH35 VSS[225] VSS[325] Y8
AG31 VSS[63] VSS[142] AV43
BH39 VSS[226] VSS[328] BG29
AG48 VSS[64] VSS[143] AV8
BH43 VSS[227] VSS[329] N24
AH11 VSS[65] VSS[144] AW14
BH7 VSS[228] VSS[330] AJ3
AH3 VSS[66] VSS[145] AW18
D3 VSS[229] VSS[331] AD47
D12 VSS[230] VSS[333] B43
AH39 VSS[68] VSS[147] AW22
D16 VSS[231] VSS[334] BE10
AH40 VSS[69] VSS[148] AW26
D18 VSS[232] VSS[335] BG41
AH42 VSS[70] VSS[149] AW28
D22 VSS[233] VSS[337] G14
AH46 VSS[71] VSS[150] AW32
D24 VSS[234] VSS[338] H16
D26 VSS[235] VSS[340] T36
AJ19 VSS[73] VSS[152] AW36
D30 VSS[236] VSS[342] BG22
AJ21 VSS[74] VSS[153] AW40
D32 VSS[237] VSS[343] BG24
AJ24 VSS[75] VSS[154] AW48
D34 VSS[238] VSS[344] C22
AJ33 VSS[76] VSS[155] AV11
D38 VSS[239] VSS[345] AP13
AJ34 VSS[77] VSS[156] AY12
D42 VSS[240] VSS[346] M14
AK12 VSS[78] VSS[157] AY22
D8 VSS[241] VSS[347] AP3
AK3 VSS[79] VSS[158] AY28
E18 VSS[242] VSS[348] AP1
E26 VSS[243] VSS[349] BE16
A ITL_BD82PPSM_QPJ4_FCBGA_989P G18 VSS[244] VSS[350] BC16 A
G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
INVENTEC
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257] TITLE
F3 VSS[258] MODEL,PROJECT,FUNCTION
Block Diagram
ITL_BD82PPSM_QPJ4_FCBGA_989P DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3S_DGPU
MEM_ID3 MEM_ID2 MEM_ID1 MEM_ID0
10K_5%_2_DY GPIO0
R5016 1 2
OUT 56D5
0 0 0 0 HYNIX1GDFR*4 512MB
10K_5%_2_DY GPIO1
R5010 1 2
OUT 56D5
0 0 0 1 HYNIX2GBFR*4 1GB
10K_5%_2_DY
R5011 1
R5028 1 2
2
RSC_0402_DY
GPIO2
GPIO5
OUT 56D5
56D5
U5001 THAMES (6019B0917601) 0 0 1 0 HYNIX2GDFR*41GB
OUT 0 0 1 1 RESERVE
1 2 RSC_0402_DY GPIO9
R5037 OUT 56D5
0 1 0 0 HYNIX1GDFR*8 1GB
1 2 10K_5%_2 GPIO11 AU24 VGA_HDMI_TXC_DP
R5014 OUT GPIO11:MEMORY APERTURE SIZE 256M TXCAP_DPA3P
OUT 36A5
VGA_HDMI_TXC_DN 0 1 0 1 HYNIX2GBFR*8 2GB
F R5030 1 2 10K_5%_2 VGA_CRT_HSYNC 35B2 56D3
TXCAM_DPA3N AV23
OUT 36A5 F
OUT 0 1 1 0 HYNIX2GDFR*82GB
R5031 1 2 10K_5%_2 VGA_CRT_VSYNC 35B2 56D3 AT25 VGA_HDMI_TX0_DP 36A5
OUT P1V8S_DGPU MUTI GFX
TX0P_DPA2P
AR24 VGA_HDMI_TX0_DN OUT 0 1 1 1 RESERVE
2 1 10K_5%_2_DY GPIO22 TX0M_DPA2N
OUT 36A5
R5027 OUT 56C5 DPA
1 0 0 0 AMDC11*4 512MB
R5056 1 2 10K_5%_2 PWRCNTL_0 13C6 56D5 AU26 VGA_HDMI_TX1_DP 36A5
OUT TX1P_DPA1P
AV25 VGA_HDMI_TX1_DN OUT 1 0 0 1 AMDA11*4 1GB
2 10K_5%_2 OUT 36A5
10K_5%_2_DY
TX1M_DPA1N
R5017 1 PWRCNTL_1 13C6 56C5
OUT
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
1 0 1 0 AMDB11*4 1GB
AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27 VGA_HDMI_TX2_DP OUT 36A5
R5006 2
2
AU8 AR26 VGA_HDMI_TX2_DN 1 0 1 1 RESERVE
DVPCNTL_MVP_1 TX2M_DPA0N
OUT 36A5
R5007
R5008
R5009
AP8 DVPCNTL_0 1 1 0 0 AMDC11*8 1HB
AW8 DVPCNTL_1 TXCBP_DPB3P AR30
AR3 AT29 1 1 0 1 AMDA11*8 2GB
DVPCNTL_2 TXCBM_DPB3N
PIN BASE STRAPS AR1 DVPCLK 1 1 1 0 AMDB11*8 2GB
1
MEM_ID0 AU1 DVPDATA_0 TX3P_DPB2P AV31
MEM_ID1 AU3 AU30 1 1 1 1 RESERVE
DVPDATA_1 TX3M_DPB2N
GPIO_0 TRANSMITTER POWER SAVING ENABLE 0 : 50% TX OUTPUT SWING (DEFAULT) MEM_ID2 AW3 DVPDATA_2
DPB
1 : FULL TX OUTPUT SWING MEM_ID3 AP6 DVPDATA_3 TX4P_DPB1P AR32
AW5 DVPDATA_4 TX4M_DPB1N AT31
AU5 DVPDATA_5
GPIO_1 PCIE TRANSMITTER DE-EMPHASIS 0 : DE-EMPHASIS DISABLED (DEFAULT) AR6 DVPDATA_6 TX5P_DPB0P AT33
1 : DE-EMPHASIS ENABLED AW6 DVPDATA_7 TX5M_DPB0N AU32
AU6 DVPDATA_8
GPIO_2 GEN1/GEN2 ENABLE 0 : GEN1 (DEFAULT) AT7 DVPDATA_9 TXCCP_DPC3P AU14

1 : GEN2 AV7 DVPDATA_10 TXCCM_DPC3N AV13
AN7 DVPDATA_11
GPIO_8 MUST BE LOW DURING RESET LEFT UNCONNECTED AV9 DVPDATA_12 TX0P_DPC2P AT15
AT9 AR14
GPIO_21 AR10
DVPDATA_13 TX0M_DPC2N
DVPDATA_14
DPC
E AW10 DVPDATA_15 TX1P_DPC1P AU16 E
GPIO_9 VGA DISABLE 0 : ENABLE (DEFAULT) AU10 DVPDATA_16 TX1M_DPC1N AV15
1 : DISABLE AP10 DVPDATA_17
AV11 DVPDATA_18 TX2P_DPC0P AT17
AT11 DVPDATA_19 TX2M_DPC0N AR16
AR12 DVPDATA_20
GPIO_[11:13] MEMORY APERTURE SIZE GPIO_13 GPIO_12 GPIO_11 MEMORY APERTURE SIZE AW12 DVPDATA_21 TXCDP_DPD3P AU20 PLACE CLOSE TO ASIC
AU12 DVPDATA_22 TXCDM_DPD3N AT19
0 0 0 128M AP12 R5072
DVPDATA_23
56D3 35D8 VGA_CRTR 1 2 150_1%_2
AT21 IN
0 0 1 256M AJ21
TX3P_DPD2P
AR20 R5073
SWAPLOCKA TX3M_DPD2N
56D3 35D8 VGA_CRTG 1 2 150_1%_2
0 1 0 64M AK21 SWAPLOCKB IN
DPD AU22 R5074
0 1 1 TX4P_DPD1P
VGA_CRTB 1 2 150_1%_2
32M TX4M_DPD1N AV21 56D3 35D8 IN
I2C AT23
TX5P_DPD0P
GPIO_22 ENABLE EXTERNAL BIOS ROM DEVICE 0 : DISABLE (DEFAULT) TX5M_DPD0N AR22
1 : ENABLE 34C5 BI VGA_LVDS_DDCCLK AK26 SCL
34C5 BI VGA_LVDS_DDCDATA AJ26 SDA
HSYNC[1] AUDIO[1:0] 00 : NO AUDIO FUNCTION AD39 VGA_CRTR

R
OUT 35D8 56E2
VSYNC[0] 01 : AUDIO FOR DP ONLY
GENERAL PURPOSE I/O
RB AD37
GPIO0 AH20
IN GPIO_0
VGA_CRTG
10 : AUDIO FOR DP AND HDMI IF DONGLE IS DETECTED IN GPIO1 AH18 GPIO_1 G AE36
OUT 35D8 56E2
56F7 GPIO2 AN16 AD35
11 : AUDIO FOR BOTH DP AND HDMI IN GPU_SID AH23
GPIO_2 GB
56C7 BI GPIO_3_SMBDATA
56D7 BI GPU_SIC AJ23 GPIO_4_SMBCLK B AF37 VGA_CRTB OUT 35D8 56E2
D 56F7 GPIO5 AH17 AE38 P1V8S_DGPU D
IN AJ17
GPIO_5_AC_BATT
DAC1
BB
GPIO_6
21E7 OUT VGA_LCM_BKLTEN AK17 GPIO_7_BLON HSYNC AC36 VGA_CRT_HSYNC
OUT 35B2 56F7
AJ13 AC38 VGA_CRT_VSYNC L5000
GPIO_8_ROMSO VSYNC
OUT 35B2 56F7 I=70MA TRACE WIDTH>=15MIL P1V8S_AVDD 2 1
P3V3S_DGPU 56F7 GPIO9 AH15
40B1 40A8 15D8 OUT THRM_SHUTDWN# IN GPIO_9_ROMSI
1
AJ16 GPIO_10_ROMSCK R5000
GPIO11 AK16 AB34 1 2 FBM_11_160808_121T
56F7 IN GPIO_11 RSET
3
2 R5094 1
AL16 499_1%_2 C5001 C5000 C5005

10K_5%_2
GPIO_12
P3V3S_DGPU Q5000 AM16 GPIO_13 AVDD AD34 0.1UF_16V_2 1UF_6.3V_2 10UF_6.3V_3

1
D
AM14 GPIO_14_HPD2 AVSSQ AE34
SSM3K7002BFU_DY G 1
OUT PWRCNTL_0 AM13
2
GPIO_15_PWRCNTL_0
G
AK14 AC33
S
GPIO_16 VDD1DI
AG30 GPIO_17_THERMAL_INT VSS1DI AC34
37C6 21D3 21D2 5A7 EC_SMB2_CLK 3 2 GPU_SIC 56D5
BI D S
BI 10K_5%_2 AN14
10K_5%_2
10K_5%_2
GPIO_18_HPD3
1
2
2
Q5001 AM17 GPIO_19_CTF
P1V8S_DGPU
R5061
R5063
R5015
SSM3K7002BFU 13C6 PWRCNTL_1 AL13 AC30

56F7
OUT AJ14
GPIO_20_PWRCNTL_1 R2/NC
AC31 I=100MA TRACE WIDTH>=15MIL
GPIO_21_BB_EN R2B/NC L5001
P3V3S_DGPU 56F7 GPIO22 AK13 P1V8S_VDD1DI 2 1
IN AN13
GPIO_22_ROMCSB
AD30
GPIO_23_CLKREQB G2/NC FBM_11_160808_121T
1
2
1
1 TP14 AM23 JTAG_TRSTB G2B/NC AD31

TP30
2 R5095 1
1 TP15 AN23
10K_5%_2
JTAG_TDI
TP30 1 TP11 AK23 AF30 C5003 C5002 C5004
JTAG_TCK B2/NC
1
1 TP16 TP30 AL24 AF31 0.1UF_16V_2 1UF_6.3V_2 10UF_6.3V_3

JTAG_TMS B2B/NC
TP301
1
TP12 AM24 JTAG_TDO

2
G
2
TP30 AJ19 GENERICA
R5060 AK19 GENERICB C/NC AC32
37C3 21D3 21D2 5A7 EC_SMB2_DATA 3 2 GPU_SID 56D5 R5005
BI D S
BI 10K_5%_2 AJ20 GENERICC Y/NC AD32
10K_5%_2_DY
C Q5002 AK20 GENERICD COMP/NC AF32 C
SSM3K7002BFU AJ24
2
GENERICE_HPD4
1
DAC2
AH26 GENERICF_HPD5
AH24 GENERICG_HPD6 H2SYNC/GENLK_CLK AD29
P1V8S_DGPU V2SYNC/GENLK_VSYNC AC29
2
36B5 IN VGA_HPDET AK24 HPD1

P1V8S_DGPU VDD2DI/NC AG31
R5004 AG32
L5004 VSS2DI/NC
1 2 P1V8S_DPLL_PVDD I=75MA TRACE WIDTH>=15MIL
499_1%_2
P0V6S_VREFG
0.1UF_16V_2
1UF_6.3V_2
1
0.1UF_16V_2
21
FBM_11_160808_121T A2VDD/NC AG33

C5011
C5012
C5010
R5003 AD33
C5013 A2VDDQ/NC
249_1%_2 AH13 VREFG
10UF_6.3V_3 A2VSSQ/TSVSSQ AF33
2
2
1
R2SET/NC AA29
PVPCIE AM32 DPLL_PVDD
L5005 AN32 DPLL_PVSS
1 2 PVPCIE_DPLL_VDDC I=125MA TRACE WIDTH>=15MIL
1
DDC/AUX AM26 VGA_HDMI_DDCCLK

DDC1CLK
BI 36D8
AN31 PLL/CLOCK AN26 VGA_HDMI_DDCDATA
FBM_11_160808_121T DPLL_VDDC DDC1DATA
BI 36D8
C5014 C5015
C5016
0.1UF_16V_2 AM27
1UF_6.3V_2 AUX1P
10UF_6.3V_3 AV33 XTALIN AUX1N AL27
2
B 1 R4 2
AU34 XTALOUT B
DDC2CLK AM19
1M_5%_2 AL19
DDC2DATA
X5000
AW34 XO_IN
1 2
AUX2P AN20
27PF_50V_2
27PF_50V_2
1
AW35 XO_IN2 AUX2N AM20

27MHZ
C5211
C5212
DDCCLK_AUX3P AL30
DDCDATA_AUX3N AM30
2
DDCCLK_AUX4P AL29
AF29 DPLUS DDCDATA_AUX4N AM29
AG29 THERMAL
DMINUS
DDCCLK_AUX5P AN21
DDCDATA_AUX5N AM21
TP5000 1 AK32 TS_FDO
TP30 DDC6CLK AJ30 VGA_CRT_DDCCLK BI 35A2

AL31 TS_A/NC DDC6DATA AJ31 VGA_CRT_DDCDATA BI 35B2
P1V8S_DGPU
L5006 DDCCLK_AUX7P AK30
1 2 P1V8S_TSVDD I=20MA TRACE WIDTH>=15MIL AJ32 AK29
TSVDD DDCDATA_AUX7N
AJ33 TSVSS
1
FBM_11_160808_121T
C5017 C5018
C5019 AMD_216_0833002_FCBGA_962P
1UF_6.3V_2 0.1UF_16V_2
10UF_6.3V_3
2
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5001
42B1 PEG_C_TX0_DP AA38 Y33 PEG_RX0_DP C5022 1 2 0.22UF_6.3V_2 PEG_C_RX0_DP 42C4

BI PEG_C_TX0_DN
PCIE_RX0P PCIE_TX0P
PEG_RX0_DN
BI
42D1 BI Y37 PCIE_RX0N PCIE_TX0N Y32 C5023 1 2 0.22UF_6.3V_2 PEG_C_RX0_DN
BI 42C4
42B1 PEG_C_TX1_DP Y35 W33 PEG_RX1_DP C5024 1 2 0.22UF_6.3V_2 PEG_C_RX1_DP 42C4

BI PEG_C_TX1_DN
PCIE_RX1P PCIE_TX1P
PEG_RX1_DN
BI
42D1 BI W36 PCIE_RX1N PCIE_TX1N W32 C5025 1 2 0.22UF_6.3V_2 PEG_C_RX1_DN
BI 42C4
42B1 PEG_C_TX2_DP W38 U33 PEG_RX2_DP C5026 1 2 0.22UF_6.3V_2 PEG_C_RX2_DP 42C4

BI PEG_C_TX2_DN
PCIE_RX2P PCIE_TX2P
PEG_RX2_DN
BI
42D1 BI V37 PCIE_RX2N PCIE_TX2N U32 C5027 1 2 0.22UF_6.3V_2 PEG_C_RX2_DN
BI 42D4
D
D
42B1 PEG_C_TX3_DP V35 U30 PEG_RX3_DP C5028 1 2 0.22UF_6.3V_2 PEG_C_RX3_DP 42C4
BI PEG_C_TX3_DN
PCIE_RX3P PCIE_TX3P
PEG_RX3_DN
BI
42C1 BI U36 PCIE_RX3N PCIE_TX3N U29 C5029 1 2 0.22UF_6.3V_2 PEG_C_RX3_DN
BI 42D4
42B1 PEG_C_TX4_DP U38 T33 PEG_RX4_DP C5030 1 2 0.22UF_6.3V_2 PEG_C_RX4_DP 42C4

BI PEG_C_TX4_DN
PCIE_RX4P PCIE_TX4P
PEG_RX4_DN
BI
42C1 BI T37 PCIE_RX4N PCIE_TX4N T32 C5031 1 2 0.22UF_6.3V_2 PEG_C_RX4_DN
BI 42D4
42B1 PEG_C_TX5_DP T35 T30 PEG_RX5_DP C5032 1 2 0.22UF_6.3V_2 PEG_C_RX5_DP 42C4

BI PEG_C_TX5_DN
PCIE_RX5P PCIE_TX5P
PEG_RX5_DN
BI
42C1 BI R36 PCIE_RX5N PCIE_TX5N T29 C5033 1 2 0.22UF_6.3V_2 PEG_C_RX5_DN
BI 42D4
42B1 PEG_C_TX6_DP R38 P33 PEG_RX6_DP C5034 1 2 0.22UF_6.3V_2 PEG_C_RX6_DP 42C4

BI PEG_C_TX6_DN
PCIE_RX6P PCIE_TX6P
PEG_RX6_DN
BI
42C1 BI P37 PCIE_RX6N PCIE_TX6N P32 C5035 1 2 0.22UF_6.3V_2 PEG_C_RX6_DN
BI 42D4
42B1 PEG_C_TX7_DP P35 P30 PEG_RX7_DP C5036 1 2 0.22UF_6.3V_2 PEG_C_RX7_DP 42C4

BI PEG_C_TX7_DN
PCIE_RX7P PCIE_TX7P
PEG_RX7_DN
BI
42C1 BI N36 PCIE_RX7N PCIE_TX7N P29 C5037 1 2 0.22UF_6.3V_2 PEG_C_RX7_DN
BI 42D4
42B1 PEG_C_TX8_DP N38 N33 PEG_RX8_DP C5038 1 2 0.22UF_6.3V_2 PEG_C_RX8_DP 42C4

BI PEG_C_TX8_DN
PCIE_RX8P PCIE_TX8P
PEG_RX8_DN
BI
C 42C1 BI M37 PCIE_RX8N PCIE_TX8N N32 C5039 1 2 0.22UF_6.3V_2 PEG_C_RX8_DN
BI 42D4 C
PCI EXPRESS INTERFACE

42B1 PEG_C_TX9_DP M35 N30 PEG_RX9_DP C5040 1 2 0.22UF_6.3V_2 PEG_C_RX9_DP 42C4
BI PEG_C_TX9_DN
PCIE_RX9P PCIE_TX9P
PEG_RX9_DN
BI
42C1 BI L36 PCIE_RX9N PCIE_TX9N N29 C5041 1 2 0.22UF_6.3V_2 PEG_C_RX9_DN
BI 42D4
42A1 PEG_C_TX10_DP L38 L33 PEG_RX10_DP C5042 1 2 0.22UF_6.3V_2 PEG_C_RX10_DP 42C4

BI PEG_C_TX10_DN
PCIE_RX10P PCIE_TX10P
PEG_RX10_DN
BI
42C1 BI K37 PCIE_RX10N PCIE_TX10N L32 C5043 1 2 0.22UF_6.3V_2 PEG_C_RX10_DN
BI 42D4
42A1 PEG_C_TX11_DP K35 L30 PEG_RX11_DP C5044 1 2 0.22UF_6.3V_2 PEG_C_RX11_DP 42C4

BI PEG_C_TX11_DN
PEG_RX11_DN
BI
42C1 BI J36 PCIE_RX11N PCIE_TX11N L29 C5045 1 2 0.22UF_6.3V_2 PEG_C_RX11_DN
BI 42D4
42A1 PEG_C_TX12_DP J38 K33 PEG_RX12_DP C5046 1 2 0.22UF_6.3V_2 PEG_C_RX12_DP 42C4

BI PEG_C_TX12_DN
PEG_RX12_DN
BI
42C1 BI H37 PCIE_RX12N PCIE_TX12N K32 C5047 1 2 0.22UF_6.3V_2 PEG_C_RX12_DN
BI 42D4
U5001
42A1 PEG_C_TX13_DP H35 J33 PEG_RX13_DP C5048 1 2 0.22UF_6.3V_2 PEG_C_RX13_DP 42C4

BI PEG_C_TX13_DN
PEG_RX13_DN
BI
LVDS CONTROL AK27 VGA_INV_PWM_3 42C1 BI G36 PCIE_RX13N PCIE_TX13N J32 C5049 1 2 0.22UF_6.3V_2 PEG_C_RX13_DN
BI 42D4
VARY_BL OUT 34B5
DIGON AJ27 VGA_LCM_VDDEN OUT 34D7
B 42A1 PEG_C_TX14_DP G38 K30 PEG_RX14_DP C5050 1 2 0.22UF_6.3V_2 PEG_C_RX14_DP 42C4
B
BI PCIE_RX14P PCIE_TX14P BI
2
R5071 42B1 PEG_C_TX14_DN F37 K29 PEG_RX14_DN C5051 1 2 0.22UF_6.3V_2 PEG_C_RX14_DN 42D4
BI PCIE_RX14N PCIE_TX14N BI
AK35
TXCLK_UP_DPF3P
42A1 PEG_C_TX15_DP F35 H33 PEG_RX15_DP C5052 1 2 0.22UF_6.3V_2 PEG_C_RX15_DP 42C4
TXCLK_UN_DPF3N AL36 BI PEG_C_TX15_DN
PEG_RX15_DN
BI
10K_5%_2 42B1 BI E37 PCIE_RX15N PCIE_TX15N H32 C5053 1 2 0.22UF_6.3V_2 PEG_C_RX15_DN
BI 42D4
1
TXOUT_U0P_DPF2P AJ38
TXOUT_U0N_DPF2N AK37
CLOCK
TXOUT_U1P_DPF1P AH35
48C3 CLK_PEG_REF_DP AB35
TXOUT_U1N_DPF1N AJ36 BI CLK_PEG_REF_DN
PCIE_REFCLKP
48C3 AA36
BI PCIE_REFCLKN
PVPCIE
TXOUT_U2P_DPF0P AG38
TXOUT_U2N_DPF0N AH37 CALIBRATION
PCIE_CALRP Y30 GPU_PCIE_CALRP R5035 1 2 1.27K_1%_2
TXOUT_U3P AF35
AG36
TXOUT_U3N
1 R5039 2 AH16 PWRGOOD PCIE_CALRN Y29 GPU_PCIE_CALRN R5034 1 2 2K_1%_2
1K_5%_2
LVTMDP
R5013 0_5%_2_DY AA30 PERSTB
1 2
TXCLK_LP_DPE3P AP34 VGA_LVDS_TXCL_DP BI 34A8
AR34 VGA_LVDS_TXCL_DN 34A8
TXCLK_LN_DPE3N BI
A P3V3S_DGPU AMD_216_0833002_FCBGA_962P A
TXOUT_L0P_DPE2P AW37 VGA_LVDS_TXDL0_DP BI 34A8
TXOUT_L0N_DPE2N AU35 VGA_LVDS_TXDL0_DN BI 34A8
5
TXOUT_L1P_DPE1P AR37 VGA_LVDS_TXDL1_DP BI 34A8 U5005

AU39 VGA_LVDS_TXDL1_DN BUF_PLT_RST# 1
+
TXOUT_L1N_DPE1N BI 34A8 27C3 21E3 IN

51A8 28C3 27C7 4 DGPU_PERST
TXOUT_L2P_DPE0P AP35 VGA_LVDS_TXDL2_DP BI 34A8 51C7 51B6 IN DGPU_HOLD_RST# 2
AR35 VGA_LVDS_TXDL2_DN BI 34A8
-
TXOUT_L2N_DPE0N
TC7SZ08FU
AN36
INVENTEC
3
TXOUT_L3P
TXOUT_L3N AP37
TITLE
Block Diagram
AMD_216_0833002_FCBGA_962P
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5001 U5001
DDR2 DDR2 DDR2 DDR2
GDDR3/GDDR5 GDDR5/GDDR3 GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 DDR3 DDR3
65D4
62D5 62D1 DQA<63..0> 0 DQA<0> C37 G24 MAA<0> 0 MAA<12..0> DQB<63..0> 0 DQB<0> C5 P8 MAB<0> 0 MAB<12..0> 64D4
63D5 63D1
BI DQA<1>
DQA0_0/DQA_0 MAA0_0/MAA_0
MAA<1>
OUT BI DQB<1>
DQB0_0/DQB_0 MAB0_0/MAB_0
MAB<1>
OUT 64D7
1 C35 DQA0_1/DQA_1 MAA0_1/MAA_1 J23 1 1 C3 DQB0_1/DQB_1 MAB0_1/MAB_1 T9 1
DQA<2> MAA<2> DQB<2> MAB<2> 65D8
2 A35 DQA0_2/DQA_2 MAA0_2/MAA_2 H24 2 2 E3 DQB0_2/DQB_2 MAB0_2/MAB_2 P9 2
3 DQA<3> E34 DQA0_3/DQA_3 MAA0_3/MAA_3 J24 MAA<3> 3 3 DQB<3> E1 DQB0_3/DQB_3 MAB0_3/MAB_3 N7 MAB<3> 3
DQA<4> MAA<4> DQB<4> MAB<4>
MEMORY INTERFACE A
4 G32 DQA0_4/DQA_4 MAA0_4/MAA_4 H26 4 4 F1 DQB0_4/DQB_4 MAB0_4/MAB_4 N8 4
DQA<5> MAA<5> DQB<5> MAB<5>
MEMORY INTERFACE B
5 D33 DQA0_5/DQA_5 MAA0_5/MAA_5 J26 5 5 F3 DQB0_5/DQB_5 MAB0_5/MAB_5 N9 5
6 DQA<6> F32 DQA0_6/DQA_6 MAA0_6/MAA_6 H21 MAA<6> 6 6 DQB<6> F5 DQB0_6/DQB_6 MAB0_6/MAB_6 U9 MAB<6> 6
7 DQA<7> E32 DQA0_7/DQA_7 MAA0_7/MAA_7 G21 MAA<7> 7 7 DQB<7> G4 DQB0_7/DQB_7 MAB0_7/MAB_7 U8 MAB<7> 7
8 DQA<8> D31 DQA0_8/DQA_8 MAA1_0/MAA_8 H19 MAA<8> 8 8 DQB<8> H5 DQB0_8/DQB_8 MAB1_0/MAB_8 Y9 MAB<8> 8
9 DQA<9> F30 DQA0_9/DQA_9 MAA1_1/MAA_9 H20 MAA<9> 9 9 DQB<9> H6 DQB0_9/DQB_9 MAB1_1/MAB_9 W9 MAB<9> 9
D 10 DQA<10> C30 DQA0_10/DQA_10 MAA1_2/MAA_10 L13 MAA<10> 10 10 DQB<10> J4 DQB0_10/DQB_10 MAB1_2/MAB_10 AC8 MAB<10> 10
11 DQA<11> A30 DQA0_11/DQA_11 MAA1_3/MAA_11 G16 MAA<11> 11 11 DQB<11> K6 DQB0_11/DQB_11 MAB1_3/MAB_11 AC9 MAB<11> 11 D
12 DQA<12> F28 DQA0_12/DQA_12 MAA1_4/MAA_12 J16 MAA<12> 12 12 DQB<12> K5 DQB0_12/DQB_12 MAB1_4/MAB_12 AA7 MAB<12> 12
13 DQA<13> C28 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 H16 MAA_BA<2> OUT 62D4 62D7 63D4 63D8 13 DQB<13> L4 DQB0_13/DQB_13 MAB1_5/BA2 AA8 MAB_BA<2> OUT 64D4 64D7 65D4
14 DQA<14> A28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 J17 MAA_BA<0> OUT 62D4 62D7 63D4 63D8 14 DQB<14> M6 DQB0_14/DQB_14 MAB1_6/BA0 Y8 MAB_BA<0> OUT
65D8 64D4 64D7
15 DQA<15> E28 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 H17 MAA_BA<1> OUT 62D4 62D7 63D4 63D8 15 DQB<15> M1 DQB0_15/DQB_15 MAB1_7/BA1 AA9 MAB_BA<1> OUT 64D4 65D4 65D8
16 DQA<16> D27 DQA0_16/DQA_16 16 DQB<16> M3 DQB0_16/DQB_16 64D7 65D4 65D8
17 DQA<17> F26 A32 DQMA<0> 62C7 17 DQB<17> M5 H3 DQMB<0> 64C7
DQA<18>
DQA0_17/DQA_17 WCKA0_0/DQMA_0
DQMA<1>
BI DQB<18>
DQB0_17/DQB_17 WCKB0_0/DQMB_0
DQMB<1>
BI
18 C26 C32 62C7 18 N4 H1 64C4
DQA<19>
DQA0_18/DQA_18 WCKA0B_0/DQMA_1
DQMA<2>
BI DQB<19>
DQB0_18/DQB_18 WCKB0B_0/DQMB_1
DQMB<2>
BI
19 A26 D23 62C4 19 P6 T3 64C4
DQA<20>
DQMA<3>
BI DQB<20>
DQMB<3>
BI
20 F24 E22 62C4 20 P5 T5 64C7
DQA<21>
DQMA<4>
BI DQB<21>
DQMB<4>
BI
21 C24 C14 63C4 21 R4 AE4 65C4
DQA<22>
DQMA<5>
BI DQB<22>
DQMB<5>
BI
22 A24 A14 63C4 22 T6 AF5 65C4
DQA<23>
DQMA<6>
BI DQB<23>
DQMB<6>
BI
23 E24 E10 63C8 23 T1 AK6 65C8
DQA<24>
DQMA<7>
BI DQB<24>
DQMB<7>
BI
24 C22 D9 63C8 24 U4 AK5 65C8
DQA<25>
DQA0_24/DQA_24 WCKA1B_1/DQMA_7 BI DQB<25>
DQB0_24/DQB_24 WCKB1B_1/DQMB_7 BI
25 A22 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 25 V6 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3
26 DQA<26> F22 C34 DQSA0_DP 62C7 26 DQB<26> V1 F6 DQSB0_DP 64C7
DQA<27>
DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0
DQSA1_DP
BI DQB<27>
DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 BI
27 D21 D29 62C7 27 V3 K3 DQSB1_DP 64C4
DQA<28>
DQSA2_DP
BI DQB<28>
28 A20 D25 62C4 28 Y6 P3 DQSB2_DP 64C4
DQA<29>
DQSA3_DP
BI DQB<29>
29 F20 E20 62C4 29 Y1 V5 DQSB3_DP 64C7
DQA<30>
DQSA4_DP
BI DQB<30>
30 D19 E16 63C4 30 Y3 AB5 DQSB4_DP 65C4
DQA<31>
DQSA5_DP
BI DQB<31>
31 E18 E12 63C4 31 Y5 AH1 DQSB5_DP 65C4
DQA<32>
DQSA6_DP
BI DQB<32>
32 C18 J10 63C8 32 AA4 AJ9 DQSB6_DP 65C8
DQA<33>
DQSA7_DP
BI DQB<33>
33 A18 D7 63C8 33 AB6 AM5 DQSB7_DP 65C8
C DQA<34>
DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 BI DQB<34>
DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 BI C
34 F18 DQA1_2/DQA_34 34 AB1 DQB1_2/DQB_34
35 DQA<35> D17 A34 DQSA0_DN 62C7 35 DQB<35> AB3 G7 DQSB0_DN 64C7
DQA<36>
DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0
DQSA1_DN
BI DQB<36>
DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 BI
36 A16 E30 62C7 36 AD6 K1 DQSB1_DN 64C4
DQA<37>
DQSA2_DN
BI DQB<37>
37 F16 E26 62C4 37 AD1 P1 DQSB2_DN 64C4
DQA<38>
DQSA3_DN
BI DQB<38>
38 D15 C20 62C4 38 AD3 W4 DQSB3_DN 64C7
DQA<39>
DQSA4_DN
BI DQB<39>
39 E14 C16 63C4 39 AD5 AC4 DQSB4_DN 65C4
DQA<40>
DQSA5_DN
BI DQB<40>
40 F14 C12 63C4 40 AF1 AH3 DQSB5_DN 65C4
DQA<41>
DQSA6_DN
BI DQB<41>
41 D13 J11 63C8 41 AF3 AJ8 DQSB6_DN 65C8
DQA<42>
DQSA7_DN
BI DQB<42>
42 F12 F8 63C8 42 AF6 AM3 DQSB7_DN 65C8
DQA<43>
DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 BI DQB<43>
43 A12 DQA1_11/DQA_43 43 AG4 DQB1_11/DQB_43
P1V5S_DGPU 44 DQA<44> D11 J21 ODTA0 62C4 62C7 44 DQB<44> AH5 T7 ODTB0 64C4 64C7
DQA<45>
DQA1_12/DQA_44 ADBIA0/ODTA0
ODTA1
BI DQB<45>
DQB1_12/DQB_44 ADBIB0/ODTB0
ODTB1
BI
45 F10 G19 63C4 63C8 45 AH6 W7 65C4 65C8
DQA<46>
DQA1_13/DQA_45 ADBIA1/ODTA1 BI DQB<46>
DQB1_13/DQB_45 ADBIB1/ODTB1 BI
46 A10 DQA1_14/DQA_46 46 AJ4 DQB1_14/DQB_46
47 DQA<47> C10 H27 CLKA0_DP 62B3 62D4 62D7 47 DQB<47> AK3 L9 CLKB0_DP 64B3 64D4 64D7
DQA<48>
DQA1_15/DQA_47 CLKA0
CLKA0_DN
OUT DQB<48>
DQB1_15/DQB_47 CLKB0
CLKB0_DN
OUT
1
48 G13 G27 62B5 62C4 P1V5S_DGPU 48 AF8 L8 64B5 64C4 64C7

DQA1_16/DQA_48 CLKA0B OUT DQB1_16/DQB_48 CLKB0B OUT
40.2_1%_2
49 DQA<49> H13 DQA1_17/DQA_49

62C7 49 DQB<49> AF9 DQB1_17/DQB_49
DQA<50> CLKA1_DP DQB<50> CLKB1_DP
R5052
1
50 J13 J14 50 AG8 AD8
100_1%_2 40.2_1%_2
DQA1_18/DQA_50 CLKA1 OUT 63B4 63D4 63D8 DQB1_18/DQB_50 CLKB1 OUT 65B4 65D4 65D8
51 DQA<51> H11 H14 CLKA1_DN 63B5 63C8 63D4 51 DQB<51> AG7 AD7 CLKB1_DN 65B5 65C8 65D4
DQA<52>
DQA1_19/DQA_51 CLKA1B OUT DQB<52>
DQB1_19/DQB_51 CLKB1B OUT
G10 AK9
R5001
52 DQA1_20/DQA_52 52 DQB1_20/DQB_52
53 DQA<53> G8 K23 RASA0# 53 DQB<53> AL7 T10 RASB0#
2
DQA1_21/DQA_53 RASA0B OUT 62C4 62C7 DQB1_21/DQB_53 RASB0B OUT 64C4 64C7
54 DQA<54> K9 K19 RASA1# 63C4 63C8 54 DQB<54> AM8 Y10 RASB1# 65C4 65C8
DQA1_22/DQA_54 RASA1B OUT DQB1_22/DQB_54 RASB1B OUT
0.1UF_16V_2
DQA<55> DQB<55>
1
55 K10 55 AM7
12
DQA1_23/DQA_55 DQB1_23/DQB_55
0.1UF_16V_2
P1V5S_DGPU
100_1%_2
B DQA<56> CASA0# DQB<56> CASB0# B

C5204
1
56 G9 K20 62C4 62C7 56 AK1 W10 64C4 64C7
DQA<57>
DQA1_24/DQA_56 CASA0B
CASA1#
OUT DQB<57>
DQB1_24/DQB_56 CASB0B
CASB1#
OUT
R5045
C5201
57 A8 K17 63C4 63C8 57 AL4 AA10 65C4 65C8
DQA<58>
DQA1_25/DQA_57 CASA1B OUT DQB<58>
DQB1_25/DQB_57 CASB1B OUT
R5002
58 C8 DQA1_26/DQA_58 58 AM6 DQB1_26/DQB_58
59 DQA<59> E8 K24 CSA0#_0 62C4 62C7 59 DQB<59> AM1 P10 CSB0#_0 64C4 64C7
DQA1_27/DQA_59 CSA0B_0 OUT DQB1_27/DQB_59 CSB0B_0 OUT
1
40.2_1%_2
60 DQA<60> A6 K27 60 DQB<60> AN4 L10

2
DQA1_28/DQA_60 CSA0B_1 P1V5S_DGPU DQB1_28/DQB_60 CSB0B_1

61 DQA<61> C6 61 DQB<61> AP3
2
DQA1_29/DQA_61 DQB1_29/DQB_61
R5053
DQA<62> CSA1#_0 DQB<62> CSB1#_0
1
62 E6 M13 62 AP1 AD10
100_1%_2 40.2_1%_2
DQA1_30/DQA_62 CSA1B_0 OUT 63C4 63C8 DQB1_30/DQB_62 CSB1B_0 OUT 65C4 65C8
63 DQA<63> A5 DQA1_31/DQA_63 CSA1B_1 K16 63 DQB<63> AP5 DQB1_31/DQB_63 CSB1B_1 AC10
R5020
2
P1V05_REFDA_GPU L18 K21 CKEA0 62C4 62C7 U10 CKEB0 64C4 64C7
P1V05_REFSA_GPU
MVREFDA CKEA0
CKEA1
OUT P1V05_REFDB_GPU
CKEB0
CKEB1
OUT
L20 J20 63C4 63C8 Y12 AA11 65C4 65C8
P1V5S_DGPU
MVREFSA CKEA1 OUT P1V05_REFSB_GPU
MVREFDB CKEB1 OUT
AA12
12
MVREFSB
0.1UF_16V_2
0.1UF_16V_2
WEA0# WEB0#
1
1
R5033 1 2 243_1%_2 L27 MEM_CALRN0 WEA0B K26
OUT 62C4 62C7 WEB0B N10
OUT 64C4 64C7
WEA1# WEB1#
1
C5205
C5202
R5022 1 2 RSC_0402_DY N12 L15 63C4 63C8 P3V3S_DGPU AB11 65C4 65C8
100_1%_2
MEM_CALRN1 WEA1B OUT WEB1B OUT

R5058 1 2 243_1%_2 AG12 MEM_CALRN2
R5021
R5023
GDDR5
GDDR5
R5012 TP13
R5048 1 2 RSC_0402_DY M12 H23 MAA<13> 62D4 62D8 1 2 1 AD28 T8 MAB<13> 64D4 64D7 65D4 65D8
MEM_CALRP1 MAA0_8 OUT 63D4 63D8
TESTEN MAB0_8 OUT
R5047 1 2 243_1%_2 M27 J19 5.11K_1%_2_DY W8
2
2
MEM_CALRP0 MAA1_8 TP30 MAB1_8
R5050 1 2 243_1%_2 AH12 AK10
2
MEM_CALRP2 CLKTESTA
2 R5024 1
AL10 AH11 1R5029 2 1R5032 2 VM_RESET
CLKTESTB DRAM_RST OUT
1K_5%_2
THAMES
120PF_50V_2
10_5%_2 51_5%_2
1
5.1K_1%_2
R5022 OPEN
C5200
2 R5025
R5048 OPEN
A SEYMOUR A
AMD_216_0833002_FCBGA_962P
2
R5022 STUFF AMD_216_0833002_FCBGA_962P
R5048 STUFF
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
F F
U5001
P1V5S_DGPU MEM I/O
PCIE P1V8S_DGPU
1.8V_504MA L5013
AC7 VDDR1#1 PCIE_VDDR#1 AA31 P1V8S_PCIE_VDDR 1 2
10UF_6.3V_3
0.01UF_50V_2
AD11 AA32
0.1UF_16V_2
VDDR1#2 PCIE_VDDR#2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
AF7 AA33 BLM18PG600SN1D
VDDR1#3 PCIE_VDDR#3
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5110
C5111
C5112
C5113
C5114
C5115
1UF_6.3V_2
1
1
AG10 VDDR1#4 PCIE_VDDR#4 AA34
C5077
C5078
C5079
C5080
C5081
C5082
C5083
C5084
C5085
C5086
AJ7 VDDR1#5 PCIE_VDDR#5 V28
AK8 VDDR1#6 PCIE_VDDR#6 W29
AL9 VDDR1#7 PCIE_VDDR#7 W30
2
G11 VDDR1#8 PCIE_VDDR#8 Y31
2
G14 VDDR1#9 PCIE_VDDR/PCIE_PVDD AB37 PVPCIE
G17 VDDR1#10
G20 VDDR1#11 PCIE_VDDC#1 G30
10UF_6.3V_3
G23 G31
0.1UF_16V_2
0.1UF_16V_2
VDDR1#12 PCIE_VDDC#2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
G26 VDDR1#13 PCIE_VDDC#3 H29
C5119
C5120
C5121
C5122
C5123
C5124
C5125
C5126
E G29 VDDR1#14 PCIE_VDDC#4 H30 E
H10 J29
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
1
J7 VDDR1#16 PCIE_VDDC#6 J30
C5087
C5088
C5089
C5090
C5091
C5092
J9 VDDR1#17 PCIE_VDDC#7 L28
2
K11 VDDR1#18 PCIE_VDDC#8 M28
K13 VDDR1#19 PCIE_VDDC#9 N28
K8 VDDR1#20 PCIE_VDDC#10 R28
L12 T28
2
L16 VDDR1#22 PCIE_VDDC#12 U28
L21 VDDR1#23
PVCORE_DGPU
L23 VDDR1#24
L26 VDDR1#25 VDDC#1 AA15
L7 CORE AA17
VDDR1#26 VDDC#2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
M11 VDDR1#27 VDDC#3 AA20
C5129
C5130
C5132
C5133
C5134
C5135
C5136
N11 VDDR1#28 VDDC#4 AA22
P1V8S_DGPU P7 VDDR1#29 VDDC#5 AA24
1.8V_110MA R11 VDDR1#30 VDDC#6 AA27
L5009 U11 AB16
VDDR1#31 VDDC#7
1 2 10UF_6.3V_3 P1V8S_VDDCT
U7 AB18
2
0.1UF_16V_2
VDDR1#32 VDDC#8
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
Y11 VDDR1#33 VDDC#9 AB21
C5093
C5094
C5095
C5096
C5097
FBM_11_160808_121T Y7 AB23
VDDR1#34 VDDC#10
VDDC#11 AB26
VDDC#12 AB28
VDDC#13 AC17
2
2
VDDC#14 AC20
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
LEVEL VDDC#15 AC22
TRANSLATION
C5143
C5144
C5145
C5146
VDDC#16 AC24
D AF26 VDD_CT#1 VDDC#17 AC27 D
P3V3S_DGPU AF27 VDD_CT#2 VDDC#18 AD18
AG26 VDD_CT#3 VDDC#19 AD21
AG27 AD23
2
10UF_6.3V_3
VDD_CT#4 VDDC#20
POWER
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
VDDC#21 AD26
C5098
C5099
C5100
C5101
VDDC#22 AF17
I/O AF20
VDDC#23
AF23 VDDR3#1 VDDC#24 AF22
AF24 VDDR3#2 VDDC#25 AG16
AG23 AG18
2
2 VDDR3#3 VDDC#26
P1V8S_DGPU AG24 VDDR3#4 VDDC#27 AG21
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
VDDC#28 AH22
C5147
C5148
C5150
C5151
C5152
C5153
C5154
L5010 VDDC#29 AH27
1 2 P1V8S_VDDR4 AF13 VDDR4#4 VDDC#30 AH28
AF15 VDDR4#5 VDDC#31 M26 PVCORE_DGPU
FBM_11_160808_121T AG13 N24
0.1UF_16V_2
0.1UF_16V_2
VDDR4#7 VDDC#32
1UF_6.3V_2
1UF_6.3V_2
1
2
AG15 VDDR4#8 VDDC/BIF_VDDC#33 N27
C5106
C5102
C5103
C5108
VDDC#34 R18
VDDC#35 R21
AD12 VDDR4#1 VDDC#36 R23
AF11 VDDR4#2 VDDC#37 R26
2
AF12 VDDR4#3 VDDC#38 T17
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
AG11 VDDR4#6 VDDC#39 T20
1
P1V8S_DGPU VDDC#40 T22
C5159
C5160
C5161
C5163
C5164
C5165
L5014 T24
VDDC#41
1 2 P1V8S_MPV
VDDC/BIF_VDDC#42 T27
P1V8S_DGPU VDDC#43 U16
FBM_11_160808_121T
0.1UF_16V_2
10UF_6.3V_3
1UF_6.3V_2
1
C M20 NC_VDDRHA VDDC#44 U18 C
2
C5104
C5105
C5107
M21 NC_VSSRHA VDDC#45 U21

L5015 P1V8S_SPV18 U23
VDDC#46
1 2
VDDC#47 U26
V12 NC_VDDRHB VDDC#48 V17
FBM_11_160808_121T U12 V20
2
NC_VSSRHB VDDC#49
10UF_6.3V_3
V22
0.1UF_16V_2
VDDC#50
1UF_6.3V_2
1
VDDC#51 V24
C5206
C5207
C5208
V27
10UF_6.3V_3
VDDC#52
1UF_6.3V_2
1UF_6.3V_2
1
1
VDDC#53 Y16
PLL
C5265
C5266
C5166
VDDC#54 Y18
VDDC#55 Y21
2
VDDC#56 Y23
H7 MPV18#1 VDDC#57 Y26
H8 Y28
2
MPV18#2 VDDC#58
PVCORE_DGPU
PVPCIE
AM10 SPV18
L5016 VDDCI#1 AA13
PVPCIE_SPV10
1 2 AN9 SPV10 VDDCI#2 AB13
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
VDDCI#3 AC12
C5188
C5189
C5190
C5191
C5192
C5193
C5195
C5197
FBM_11_160808_121T AN10 SPVSS VDDCI#4 AC15
10UF_6.3V_3
AD13
0.1UF_16V_2
VDDCI#5
1UF_6.3V_2
1
VDDCI#6 AD16
C5209
C5210
C5213
VDDCI#7 M15
M16
2
VDDCI#8
VOLTAGE VDDCI#9 M18
B SENESE VDDCI#10 M23 B
2
VDDCI#11 N13
AF28 FB_VDDC VDDCI#12 N15
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
VDDCI#13 N17
1
VDDCI#14 N20
C5167
C5168
C5169
AG28 FB_VDDCI VDDCI#15 N22
ISOLATED VDDCI#16 R12
CORE I/O VDDCI#17 R13
AH29 FB_GND VDDCI#18 R16
2
VDDCI#19 T12
VDDCI#20 T15
VDDCI#21 V15
VDDCI#22 Y13
AMD_216_0833002_FCBGA_962P
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5001
P1V8S_DGPU DP C/D POWER DP A/B POWER
P1V8S_DGPU
L5019 L5017
1 2 DPCD_VDD18 AP20 DPCD/DPC_VDD18#1 DPAB/DPA_VDD18#1 AN24 DPAB_VDD18 1 2
10UF_6.3V_3
AP21 AP24
0.1UF_16V_2
10UF_6.3V_3
1UF_6.3V_2
DPCD/DPC_VDD18#2 DPAB/DPA_VDD18#2
1
0.1UF_16V_2
BLM18PG600SN1D BLM18PG600SN1D
1UF_6.3V_2
1
C5220
C5221
C5222
C5226
C5227
C5228
D AP13 DPCD/DPC_VDD10#1 DPAB/DPA_VDD10#1 AP31
AT13 DPCD/DPC_VDD10#2 DPAB/DPA_VDD10#2 AP32 D
2
2
2
AN17 DP/DPC_VSSR#1 DP/DPA_VSSR#1 AN27
AP16 DP/DPC_VSSR#2 DP/DPA_VSSR#2 AP27
AP17 DP/DPC_VSSR#3 DP/DPA_VSSR#3 AP28
AW14 DP/DPC_VSSR#4 DP/DPA_VSSR#4 AW24
AW16 DP/DPC_VSSR#5 DP/DPA_VSSR#5 AW26
60C6 60B3 IN DPCD_VDD18 AP22 DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1 AP25 DPAB_VDD18 IN 60B3 60C3
AP23 DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2 AP26 PVPCIE
PVPCIE
L5020 L5018
1 2 DPCD_VDD10 AP14 DPCD/DPD_VDD10#1 DPAB/DPB_VDD10#1 AN33 DPAB_VDD10 1 2
10UF_6.3V_3
10UF_6.3V_3
AP15 AP33
0.1UF_16V_2
0.1UF_16V_2
1UF_6.3V_2
1UF_6.3V_2
DPCD/DPD_VDD10#2 DPAB/DPB_VDD10#2
1
BLM18PG600SN1D BLM18PG600SN1D
C5229
C5230
C5231
C5223
C5224
C5225
AN19 DP/DPD_VSSR#1 DP/DPB_VSSR#1 AN29
C AP18 DP/DPD_VSSR#2 DP/DPB_VSSR#2 AP29 C
2
AP19 DP/DPD_VSSR#3 DP/DPB_VSSR#3 AP30
AW20 DP/DPD_VSSR#4 DP/DPB_VSSR#4 AW30
AW22 DP/DPD_VSSR#5 DP/DPB_VSSR#5 AW32
R5041 R5040
1 2 AW18 DPCD_CALR DPAB_CALR AW28 1 2
P1V8S_DGPU 150_1%_2 150_1%_2
L5021 DP E/F POWER DP PLL POWER

1 2 DPEF_VDD18 AH34 DPEF/DPE_VDD18#1 DPAB_VDD18/DPA_PVDD AU28 DPAB_VDD18 IN 60C3
AJ34 AV27
10UF_6.3V_3
DPEF/DPE_VDD18#2 DP_VSSR/DPA_PVSS
0.1UF_16V_2
BLM18PG600SN1D
1UF_6.3V_2
1
1
C5232
C5233
C5234
AL33 DPEF/DPE_VDD10#1 DPAB_VDD18/DPB_PVDD AV29

AM33 DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS AR28
2
AN34 DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD AU18 DPCD_VDD18 IN 60C6

AP39 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS AV17
B AR39 DP/DPE_VSSR#3
B
AU37 DP/DPE_VSSR#4
DPCD_VDD18/DPD_PVDD AV19
DP_VSSR/DPD_PVSS AR18
60B6 60B3 IN DPEF_VDD18 AF34 DPEF/DPF_VDD18#1

AG34 DPEF/DPF_VDD18#2
PVPCIE DPEF_VDD18/DPE_PVDD AM37 DPEF_VDD18 IN 60B6
DP_VSSR/DPE_PVSS AN38
L5022
1 2 DPEF_VDD10 AK33 DPEF/DPF_VDD10#1
10UF_6.3V_3
AK34
0.1UF_16V_2
1UF_6.3V_2
DPEF/DPF_VDD10#2
1
BLM18PG600SN1D AL38
DPEF_VDD18/DPF_PVDD
C5235
C5236
C5237
DP_VSSR/DPF_PVSS AM35
AF39 DP/DPF_VSSR#1
AH39 DP/DPF_VSSR#2
2
AK39 DP/DPF_VSSR#3
AL34 DP/DPF_VSSR#4
AM34 DP/DPF_VSSR#5
R5042
A 1 2 AM39 DPEF_CALR
A
150_1%_2
AMD_216_0833002_FCBGA_962P
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
F F
U5001
AB39 PCIE_VSS#1 GND#1 A3

E39 PCIE_VSS#2 GND#2 A37
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18
G33 PCIE_VSS#5 GND#5 AA2
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
J31 PCIE_VSS#10 GND#10 AA6
J34 PCIE_VSS#11 GND#11 AB12
K31 PCIE_VSS#12 GND#12 AB15
L31 PCIE_VSS#15 GND#15 AB22
L34 PCIE_VSS#16 GND#16 AB24
E M34 PCIE_VSS#17 GND#17 AB27 E
M39 PCIE_VSS#18 GND#18 AC11
N31 PCIE_VSS#19 GND#19 AC13
N34 PCIE_VSS#20 GND#20 AC16
P31 PCIE_VSS#21 GND#21 AC18
R34 PCIE_VSS#24 GND#24 AC23
T31 PCIE_VSS#25 GND#25 AC26
U31 PCIE_VSS#28 GND#28 AD15
U34 PCIE_VSS#29 GND#29 AD17
V34 PCIE_VSS#30 GND#30 AD20
V39 PCIE_VSS#31 GND#31 AD22
W31 PCIE_VSS#32 GND#32 AD24
W34 PCIE_VSS#33 GND#33 AD27
Y34 PCIE_VSS#34 GND#34 AD9
Y39 PCIE_VSS#35 GND#35 AE2
GND#36 AE6
GND#37 AF10
GND#38 AF16
GND#39 AF18
GND GND#40
GND#41
AF21
AG17
F15 GND#100 GND#42 AG2
F17 GND#101 GND#43 AG20
D F19 GND#102 GND#44 AG22 D
F25 GND#105 GND#47 AH21
F27 GND#106 GND#48 AJ10
F29 GND#107 GND#49 AJ11
F31 GND#108 GND#50 AJ2
F33 GND#109 GND#51 AJ28
F7 GND#110 GND#52 AJ6
F9 GND#111 GND#53 AK11
G2 GND#112 GND#54 AK31
G6 GND#113 GND#55 AK7
H9 GND#114 GND#56 AL11
J2 GND#115 GND#57 AL14
J27 GND#116 GND#58 AL17
K14 AL21 PX_EN
K7
GND#119 GND/PX_EN#61
AL23
IN
GND#120 GND#62
L11 GND#121 GND#63 AL26
L17 GND#122 GND#64 AL32
L2 GND#123 GND#65 AL6
L22 GND#124 GND#66 AL8
L24 GND#125 GND#67 AM11
L6 GND#126 GND#68 AM31
M17 GND#127 GND#69 AM9
M22 GND#128 GND#70 AN11
C M24 GND#129 GND#71 AN2 C
N16 GND#130 GND#72 AN30
N18 GND#131 GND#73 AN6
N2 GND#132 GND#74 AN8
N21 GND#133 GND#75 AP11
N23 GND#134 GND#76 AP7
N26 GND#135 GND#77 AP9
N6 GND#136 GND#78 AR5
R15 GND#137 GND#79 B11
R17 GND#138 GND#80 B13
R2 GND#139 GND#81 B15
R20 GND#140 GND#82 B17
R22 GND#141 GND#83 B19
R24 GND#142 GND#84 B21
R27 GND#143 GND#85 B23
R6 GND#144 GND#86 B25
T11 GND#145 GND#87 B27
T13 GND#146 GND#88 B29
T16 GND#147 GND#89 B31
T18 GND#148 GND#90 B33
T21 GND#149 GND#91 B7
T23 GND#150 GND#92 B9
T26 GND#151 GND#93 C1
U15 GND#153 GND#94 C39
U17 GND#154 GND#95 E35
U2 GND#155 GND#96 E5
U20 GND#156 GND#97 F11
B U22 GND#157 GND#98 F13 B
U24 GND#158
U27 GND#159
U6 GND#160
V11 GND#161
V16 GND#163
V18 GND#164
V21 GND#165
V23 GND#166
V26 GND#167
W2 GND#168
W6 GND#169
Y15 GND#170
Y17 GND#171
Y20 GND#172
Y22 GND#173 VSS_MECH#1 A39
Y24 GND#174 VSS_MECH#2 AW1
Y27 GND#175 VSS_MECH#3 AW39
U13 GND#152
V13 GND#162
AMD_216_0833002_FCBGA_962P
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5500 U5501
62A8 IN VRAM_VREFC_A<0> M9 VREFCA DQL0 E4 DQA<3> BI 58D8 62B4 IN VRAM_VREFC_A<2> M9 VREFCA DQL0 E4 DQA<26> BI 58D8
62A7 IN VRAM_VREFD_A<3> H2 VREFDQ DQL1 F8 DQA<0> BI 58D8 62B2 IN VRAM_VREFD_A<1> H2 VREFDQ DQL1 F8 DQA<31> BI 58D8
DQL2 F3 DQA<4> BI 58D8 DQL2 F3 DQA<29> BI 58D8
63D8 63D4 62D4 58D4 58A5 BI MAA<13..0> 0 MAA<0> N4 A0 DQL3 F9 DQA<2> BI 58D8 63D8 63D4 62D8 58D4 58A5 BI MAA<13..0> 0 MAA<0> N4 A0 DQL3 F9 DQA<25> BI 58D8
1 MAA<1> P8 A1 DQL4 H4 DQA<6> BI 58D8 1 MAA<1> P8 A1 DQL4 H4 DQA<24> BI 58D8
3 MAA<3> N3 A3 DQL6 G3 DQA<5> BI 58D8 3 MAA<3> N3 A3 DQL6 G3 DQA<27> BI 58D8
5 MAA<5> P3 A5 5 MAA<5> P3 A5
6 MAA<6> R9 A6 6 MAA<6> R9 A6
7 MAA<7> R3 A7 DQU0 D8 DQA<12> BI 58D8 7 MAA<7> R3 A7 DQU0 D8 DQA<19> BI 58D8
8 MAA<8> T9 A8 DQU1 C4 DQA<13> BI 58D8 8 MAA<8> T9 A8 DQU1 C4 DQA<18> BI 58D8
9 MAA<9> R4 A9 DQU2 C9 DQA<9> BI 58D8 9 MAA<9> R4 A9 DQU2 C9 DQA<21> BI 58D8
10 MAA<10> L8 A10_AP DQU3 C3 DQA<15> BI 58D8 10 MAA<10> L8 A10_AP DQU3 C3 DQA<16> BI 58D8
11 MAA<11> R8 A11 DQU4 A8 DQA<10> BI 58D8 11 MAA<11> R8 A11 DQU4 A8 DQA<23> BI 58D8
12 MAA<12> N8 A12 DQU5 A3 DQA<14> BI 58D8 12 MAA<12> N8 A12 DQU5 A3 DQA<17> BI 58D8
D 13 MAA<13> T4 B9 DQA<8> 58D8 13 MAA<13> T4 B9 DQA<22> 58D8
T8
A13 DQU6
A4 DQA<11> BI T8
A13 DQU6
A4 DQA<20> BI D
A14 DQU7 BI 58D8 A14 DQU7 BI 58D8
M8 A15_BA3
P1V5S_DGPU M8 A15_BA3
P1V5S_DGPU
63D8 63D4 62D4 58D5 BI MAA_BA<0> M3 BA0 VDD#B3 B3 63D8 63D4 62D7 58D5 BI MAA_BA<0> M3 BA0 VDD#B3 B3
63D8 63D4 62D4 58D5 BI MAA_BA<1> N9 BA1 VDD#D10 D10 63D8 63D4 62D7 58D5 BI MAA_BA<1> N9 BA1 VDD#D10 D10
63D8 63D4 62D4 58D5 BI MAA_BA<2> M4 BA2 VDD#G8 G8 63D8 63D4 62D7 58D5 BI MAA_BA<2> M4 BA2 VDD#G8 G8
VDD#K3 K3 VDD#K3 K3
VDD#K9 K9 VDD#K9 K9
VDD#N2 N2 VDD#N2 N2
62D4 62B3 58B5 IN CLKA0_DP J8 CK VDD#N10 N10 62D7 62B3 58B5 IN CLKA0_DP J8 CK VDD#N10 N10
62C4 62B5 58B5 IN CLKA0_DN K8 CK VDD#R2 R2 62C7 62B5 58B5 IN CLKA0_DN K8 CK VDD#R2 R2
62C4 58B5 IN CKEA0 K10 CKE_CKE0 VDD#R10 R10 P1V5S_DGPU 62C7 58B5 IN CKEA0 K10 CKE_CKE0 VDD#R10 R10 P1V5S_DGPU
62C4 58C5 IN ODTA0 K2 ODT VDDQ#A2 A2 62C7 58C5 IN ODTA0 K2 ODT VDDQ#A2 A2
62C4 58B5 IN CSA0#_0 L3 CS VDDQ#A9 A9 62C7 58B5 IN CSA0#_0 L3 CS VDDQ#A9 A9
62C4 58B5 IN RASA0# J4 RAS VDDQ#C2 C2 62C7 58B5 IN RASA0# J4 RAS VDDQ#C2 C2
62C4 58B5 IN CASA0# K4 CAS VDDQ#C10 C10 62C7 58B5 IN CASA0# K4 CAS VDDQ#C10 C10
62C4 58A5 IN WEA0# L4 WE VDDQ#D3 D3 62C7 58A5 IN WEA0# L4 WE VDDQ#D3 D3
VDDQ#E10 E10 VDDQ#E10 E10
58C5 BI DQSA0_DP F4 DQSL VDDQ#F2 F2 58C5 BI DQSA3_DP F4 DQSL VDDQ#F2 F2
58C5 BI DQSA1_DP C8 DQSU VDDQ#H3 H3 58C5 BI DQSA2_DP C8 DQSU VDDQ#H3 H3
VDDQ#H10 H10 VDDQ#H10 H10
C 58D5 BI
DQMA<0> E8 DML 58D5 BI
DQMA<3> E8 DML C
58D5 BI
DQMA<1> D4 DMU VSS#A10 A10 58D5 BI
DQMA<2> D4 DMU VSS#A10 A10
VSS#B4 B4 VSS#B4 B4
VSS#E2 E2 VSS#E2 E2
58C5 BI DQSA0_DN G4 DQSL VSS#G9 G9 58C5 BI DQSA3_DN G4 DQSL VSS#G9 G9
58C5 BI DQSA1_DN B8 DQSU VSS#J3 J3 58C5 BI DQSA2_DN B8 DQSU VSS#J3 J3
VSS#J9 J9 VSS#J9 J9
VSS#M2 M2 VSS#M2 M2
VSS#M10 M10 VSS#M10 M10
65C8 65C4 64C7 64C4 63C8 63C4 62C4 58A1 IN VM_RESET T3 RESET VSS#P2 P2 65C8 65C4 64C7 64C4 63C8 63C4 62C7 58A1 IN VM_RESET T3 RESET VSS#P2 P2
R5509 VSS#P10 P10 R5508 VSS#P10 P10
1 2 L9 ZQ_ZQ0 VSS#T2 T2 THAMES: 40OHM 1 2 L9 ZQ_ZQ0 VSS#T2 T2
T10 T10
243_1%_2
VSS#T10
SEYMOUR: 56OHM 243_1%_2
VSS#T10
VSSQ#B2 B2 (60130B5600ZT) VSSQ#B2 B2

B10 R5540 R5541 B10
VSSQ#B10
D2 62C4 58B5 IN CLKA0_DN 1 2 1 2 CLKA0_DP
IN 58B5 62D4
VSSQ#B10
D2
VSSQ#D2 62C7 62D7 VSSQ#D2
VSSQ#D9 D9 40.2_1%_2 40.2_1%_2 VSSQ#D9 D9
J2 NC_ODT VSSQ#E3 E3 J2 NC_ODT VSSQ#E3 E3
1
L2 E9 L2 E9
0.01UF_50V_2
NC_CSI VSSQ#E9 NC_CSI VSSQ#E9
C5516
J10 NC_CE1 VSSQ#F10 F10 J10 NC_CE1 VSSQ#F10 F10
L10 NC_ZQ1 VSSQ#G2 G2 L10 NC_ZQ1 VSSQ#G2 G2
VSSQ#G10 G10 VSSQ#G10 G10
B B
2
A1 NC NC T1 A1 NC NC T1
SAM_K4B1G1646D_HCF7_FBGA_100P P1V5S_DGPU SAM_K4B1G1646D_HCF7_FBGA_100P P1V5S_DGPU
4.99K_1%_2 4.99K_1%_2
4.99K_1%_24.99K_1%_2
2
2
R5504
R5506
P1V5S_DGPU
P1V5S_DGPU
2
VRAM_VREFC_A<2> VRAM_VREFD_A<1>
4.99K_1%_2 4.99K_1%_2
2
4.99K_1%_2
R5500
62D4 62D4
2 1
21
IN IN
0.1uF_16V_2
0.1uF_16V_2
R5502
1
C5502
C5503
R5507
R5505
VRAM_VREFC_A<0>
1
VRAM_VREFD_A<3>
1
62D7 IN
0.1uF_16V_2
62D7 IN
4.99K_1%_2
1
2
0.1uF_16V_2
1
1
C5500
R5501
1
R5503
C5501
2
1
2
A A
P1V5S_DGPU
P1V5S_DGPU
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
2.2UF_6.3V_2
1
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
C5528
C5529
C5530
C5531
C5532
C5520
C5521
C5522
C5523
C5524
C5525
C5526 C5527 C5533 C5534
10UF_6.3V_3 10UF_6.3V_3
10UF_6.3V_3 10UF_6.3V_3
INVENTEC
2
2
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5503
U5502 VRAM_VREFC_A<6> M9 E4DQA<35>
63A8 IN VRAM_VREFC_A<4> M9 VREFCA DQL0 E4DQA<54>
BI 58D8
63A4 IN VRAM_VREFD_A<5> H2
VREFCA DQL0
F8 DQA<38>
BI 58D8
63A6 IN VRAM_VREFD_A<7> H2 VREFDQ DQL1 F8 DQA<51>
BI 58D8
63A3 IN VREFDQ DQL1
F3 DQA<33>
BI 58D8
F3 DQA<53> DQL2 BI 58D8
MAA<13..0> 0 MAA<0> N4
DQL2
F9 DQA<49>
BI 58D8
63D8 62D8 62D4 58D4 58A5 BI MAA<13..0> 0 MAA<0> N4 A0 DQL3 F9 DQA<39>
BI 58D8
63D4 62D8 62D4 58D4 58A5 BI A0 DQL3 BI 58D8 1 MAA<1> P8 H4DQA<32>
1 MAA<1> P8 H4DQA<52> A1 DQL4 BI 58D8
A1 DQL4 BI 58D8 2 MAA<2> P4 H9DQA<37>
2 MAA<2> P4 H9DQA<50> A2 DQL5 BI 58D8
A2 DQL5 BI 58D8
3 MAA<3> N3 G3DQA<34>
3 MAA<3> N3 G3DQA<55> A3 DQL6 BI 58D8
A3 DQL6 BI 58D8
4 MAA<4> P9 H8DQA<36>
4 MAA<4> P9 H8DQA<48> 58D8
A4 DQL7 BI 58D8
MAA<5> P3
A4 DQL7 BI 5 MAA<5> P3 A5
5 A5 MAA<6> R9
MAA<6> R9 6 A6
6 A6 MAA<7> R3 D8DQA<44>
MAA<7> R3 D8DQA<62> 7 A7 DQU0 BI 58D8
7 A7 DQU0 BI 58D8 MAA<8> T9 C4DQA<43>
MAA<8> T9 C4DQA<60> 8 A8 DQU1 BI 58D8
8 A8 DQU1 BI 58D8 MAA<9> R4 C9DQA<47>
MAA<9> R4 C9DQA<58> 9 A9 DQU2 BI 58D8
9 A9 DQU2 BI 58D8 MAA<10> L8 C3DQA<42>
MAA<10> L8 C3DQA<61> 10 A10_AP DQU3 BI 58D8
10 A10_AP DQU3 BI 58D8 MAA<11> R8 A8DQA<46>
MAA<11> R8 A8DQA<59> 11 A11 DQU4 BI 58D8
11 A11 DQU4 BI 58D8 MAA<12> N8 A3DQA<40>
12
12 MAA<12> N8 A3DQA<57> A12 DQU5 BI 58D8
D A12 DQU5 BI 58D8 13 MAA<13> T4 B9DQA<45>
13 MAA<13> T4 B9DQA<56> A13 DQU6 BI 58D8
A13 DQU6 BI 58D8 T8 A4DQA<41> D
T8 A4DQA<63> 58D8
A14 DQU7 BI 58D8
M8
A14 DQU7 BI P1V5S_DGPU M8 A15_BA3 P1V5S_DGPU
A15_BA3
MAA_BA<0> M3 B3 63D8 62D7 62D4 58D5 BI MAA_BA<0> M3 BA0 VDD#B3 B3

63D4 62D7 62D4 58D5 BI MAA_BA<1> N9
BA0 VDD#B3
D10 63D8 62D7 62D4 58D5 BI MAA_BA<1> N9 BA1 VDD#D10 D10
63D4 62D7 62D4 58D5 BI MAA_BA<2> M4
BA1 VDD#D10
G8 63D8 62D7 62D4 58D5 BI MAA_BA<2> M4 BA2 VDD#G8 G8
63D4 62D7 62D4 58D5 BI BA2 VDD#G8 K3
K3 VDD#K3
VDD#K3 K9
K9 VDD#K9
VDD#K9 N2
N2 VDD#N2
CLKA1_DP J8
VDD#N2
N10 63D8 63B4 58B5 IN CLKA1_DP J8 CK VDD#N10 N10
63D4 63B4 58B5 IN CLKA1_DN K8
CK VDD#N10
R2 63C8 63B5 58B5 IN CLKA1_DN K8 CK VDD#R2 R2
63D4 63B5 58B5 IN CKEA1 K10
CK VDD#R2
R10 P1V5S_DGPU 63C8 58B5 IN CKEA1 K10 CKE_CKE0 VDD#R10 R10 P1V5S_DGPU
63C4 58B5 IN CKE_CKE0 VDD#R10
ODTA1 K2 A2 63C8 58B5 IN ODTA1 K2 ODT VDDQ#A2 A2

63C4 58B5 IN CSA1#_0 L3
ODT VDDQ#A2
A9 63C8 58B5 IN CSA1#_0 L3 CS VDDQ#A9 A9
63C4 58B5 IN RASA1# J4
CS VDDQ#A9
C2 63C8 58B5 IN RASA1# J4 RAS VDDQ#C2 C2
63C4 58B5 IN CASA1# K4
RAS VDDQ#C2
C10 63C8 58B5 IN CASA1# K4 CAS VDDQ#C10 C10
63C4 58B5 IN WEA1# L4
CAS VDDQ#C10
D3 63C8 58A5 IN WEA1# L4 WE VDDQ#D3 D3
63C4 58A5 IN WE VDDQ#D3 E10
E10 VDDQ#E10
DQSA6_DP F4
VDDQ#E10
F2 58C5 BI DQSA4_DP F4 DQSL VDDQ#F2 F2
58C5 BI DQSA7_DP C8
DQSL VDDQ#F2
H3 58C5 BI DQSA5_DP C8 DQSU VDDQ#H3 H3
58C5 BI DQSU VDDQ#H3 H10
H10 VDDQ#H10
DQMA<6> E8
VDDQ#H10
58D5 BI
DQMA<4> E8 DML
C 58C5 BI DML DQMA<5> D4 A10 C
58C5 BI
DQMA<7> D4 DMU VSS#A10 A10 58C5 BI DMU VSS#A10
B4
B4 VSS#B4
VSS#B4 E2
E2 VSS#E2
DQSA6_DN G4
VSS#E2
G9 58C5 BI DQSA4_DN G4 DQSL VSS#G9 G9
58C5 BI DQSA7_DN B8
DQSL VSS#G9
J3 58C5 BI DQSA5_DN B8 DQSU VSS#J3 J3
58C5 BI DQSU VSS#J3 J9
J9 VSS#J9
VSS#J9 M2
M2 VSS#M2
VSS#M2 M10
M10 VSS#M10
VM_RESET T3
VSS#M10
P2 65C8 65C4 64C7 64C4 63C8 62C7 62C4 58A1 IN VM_RESET T3 RESET VSS#P2 P2
64C7 64C4 63C4 62C7 62C4 58A1 IN RESET VSS#P2 P10
R5518
65C8 65C4 R5519 VSS#P10 P10 THAMES: 40 OHM 1 2 L9
VSS#P10
T2
1 2 L9 ZQ_ZQ0 VSS#T2 T2 SEYMOUR: 56 OHM ZQ_ZQ0 VSS#T2
VSS#T10 T10
VSS#T10 T10 (60130B5600ZT) 243_1%_2
243_1%_2 B2
VSSQ#B2 B2 63C8 58B5 IN CLKA1_DN 1 R5542 2 1 R5543 2CLKA1_DP IN 58B5 63D4
VSSQ#B2
B10
B10 63D4 63D8 VSSQ#B10
VSSQ#B10 D2
D2 40.2_1%_2 40.2_1%_2 VSSQ#D2
VSSQ#D2 D9
D9 VSSQ#D9
0.01UF_50V_2
VSSQ#D9 J2 E3
J2 E3 NC_ODT VSSQ#E3
1
NC_ODT VSSQ#E3 L2 E9
L2 E9 NC_CSI VSSQ#E9
C5517
NC_CSI VSSQ#E9 J10 F10
J10 F10 NC_CE1 VSSQ#F10
NC_CE1 VSSQ#F10 L10 G2
L10 G2 NC_ZQ1 VSSQ#G2
NC_ZQ1 VSSQ#G2 G10
G10 VSSQ#G10
VSSQ#G10
B B
2
A1 NC NC T1
A1 NC NC T1
A11 NC NC T11
A11 NC NC T11
SAM_K4B1G1646D_HCF7_FBGA_100P
P1V5S_DGPU P1V5S_DGPU
4.99K_1%_24.99K_1%_2
4.99K_1%_24.99K_1%_2
2
2
4.99K_1%_2 4.99K_1%_2
4.99K_1%_2 4.99K_1%_2
R5514
R5516
2
2
R5510
R5512
VRAM_VREFC_A<6> VRAM_VREFD_A<5>
VRAM_VREFC_A<4> VRAM_VREFD_A<7> 63D4 63D4
21
21
IN IN
0.1uF_16V_2
0.1uF_16V_2
1
1
1
2 1
63D8 IN 63D8 IN
C5506
R5515
C5507
R5517
0.1uF_16V_2
1
0.1uF_16V_2
1
C5505
R5513
C5504
R5511
2
1
1
P1V5S_DGPU
2
1
2
P1V5S_DGPU
A A
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
C5543
C5544
C5545
C5546
C5547
2.2UF_6.3V_2
C5548 C5549
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
C5535
C5536
C5537
C5538
C5539
C5540
10UF_6.3V_3 10UF_6.3V_3
C5541 C5542
2
2
10UF_6.3V_3 10UF_6.3V_3
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5504 U5505
64A8 IN VRAM_VREFC_B<0> M9 VREFCA DQL0 E4DQB<26>
BI 58D4 64B4 IN VRAM_VREFC_B<2> M9 VREFCA DQL0 E4DQB<10>
BI 58D4
64A7 IN VRAM_VREFD_B<3> H2 VREFDQ DQL1 F8 DQB<24>
BI 58D4 64B2 IN VRAM_VREFD_B<1> H2 VREFDQ DQL1 F8 DQB<12>
BI 58D4
F3 DQB<29> 58D4 F3 DQB<9> 58D4
MAB<13..0> MAB<0> N4
DQL2
F9 DQB<31>
BI MAB<13..0> MAB<0> N4
DQL2
F9 DQB<14>
BI
65D8 65D4 64D4 58D1 58A1 0 58D4 65D8 65D4 64D7 58D1 58A1 0 58D4
BI MAB<1> P8
A0 DQL3
H4DQB<28>
BI BI MAB<1> P8
A0 DQL3
H4DQB<13>
BI
1 58D4 1 58D4
MAB<2> P4
A1 DQL4
H9DQB<25>
BI MAB<2> P4
A1 DQL4
H9DQB<11>
BI
2 58D4 2 58D4
MAB<3> N3
A2 DQL5
G3DQB<30>
BI MAB<3> N3
A2 DQL5
G3DQB<8>
BI
3 A3 DQL6 BI 58D4 3 A3 DQL6 BI 58D4
4 MAB<4> P9 H8DQB<27> 58D4 4 MAB<4> P9 H8DQB<15> 58D4
MAB<5> P3
A4 DQL7 BI MAB<5> P3
A4 DQL7 BI
5 A5 5 A5
6 MAB<6> R9 A6 6 MAB<6> R9 A6
7 MAB<7> R3 D8DQB<6> 58D4 7 MAB<7> R3 D8DQB<20> 58D4
MAB<8> T9
A7 DQU0
C4DQB<3>
BI MAB<8> T9
A7 DQU0
C4DQB<19>
BI
8 A8 DQU1 BI 58D4 8 A8 DQU1 BI 58D4
9 MAB<9> R4 C9DQB<2> 58D4 9 MAB<9> R4 C9DQB<23> 58D4
MAB<10> L8
A9 DQU2
C3DQB<7>
BI MAB<10> L8
A9 DQU2
C3DQB<16>
BI
10 A10_AP DQU3 BI 58D4 10 A10_AP DQU3 BI 58D4
11 MAB<11> R8 A8DQB<1> 58D4 11 MAB<11> R8 A8DQB<21> 58D4
MAB<12> N8
A11 DQU4
A3DQB<4>
BI MAB<12> N8
A11 DQU4
A3DQB<17>
BI
12 58D4 12 58D4
D MAB<13> T4
A12 DQU5
B9DQB<0>
BI MAB<13> T4
A12 DQU5
B9DQB<22>
BI
13 58D4 13 58D4
T8
A13 DQU6
A4DQB<5>
BI T8
A13 DQU6
A4DQB<18>
BI D
A14 DQU7 BI 58D4 A14 DQU7 BI
M8 A15_BA3
P1V5S_DGPU M8 A15_BA3
P1V5S_DGPU
65D8 65D4 64D4 58D1 BI MAB_BA<0> M3 BA0 VDD#B3 B3 65D8 65D4 64D7 58D1 BI MAB_BA<0> M3 BA0 VDD#B3 B3
65D8 65D4 64D4 58D1 BI MAB_BA<1> N9 BA1 VDD#D10 D10 65D8 65D4 64D7 58D1 BI MAB_BA<1> N9 BA1 VDD#D10 D10
65D8 65D4 64D4 58D1 BI MAB_BA<2> M4 BA2 VDD#G8 G8 65D8 65D4 64D7 58D1 BI MAB_BA<2> M4 BA2 VDD#G8 G8
VDD#K3 K3 VDD#K3 K3
VDD#K9 K9 VDD#K9 K9
VDD#N2 N2 VDD#N2 N2
64D4 64B3 58B1 IN CLKB0_DP J8 CK VDD#N10 N10 64D7 64B3 58B1 IN CLKB0_DP J8 CK VDD#N10 N10
64C4 64B5 58B1 IN CLKB0_DN K8 CK VDD#R2 R2 64C7 64B5 58B1 IN CLKB0_DN K8 CK VDD#R2 R2
64C4 58B1 IN CKEB0 K10 CKE_CKE0 VDD#R10 R10 P1V5S_DGPU 64C7 58B1 IN CKEB0 K10 CKE_CKE0 VDD#R10 R10 P1V5S_DGPU
64C4 58C1 IN ODTB0 K2 ODT VDDQ#A2 A2 64C7 58C1 IN ODTB0 K2 ODT VDDQ#A2 A2
64C4 58B1 IN CSB0#_0 L3 CS VDDQ#A9 A9 64C7 58B1 IN CSB0#_0 L3 CS VDDQ#A9 A9
64C4 58B1 IN RASB0# J4 RAS VDDQ#C2 C2 64C7 58B1 IN RASB0# J4 RAS VDDQ#C2 C2
64C4 58B1 IN CASB0# K4 CAS VDDQ#C10 C10 64C7 58B1 IN CASB0# K4 CAS VDDQ#C10 C10
64C4 58A1 IN WEB0# L4 WE VDDQ#D3 D3 64C7 58A1 IN WEB0# L4 WE VDDQ#D3 D3
VDDQ#E10 E10 VDDQ#E10 E10
58C1 BI DQSB3_DP F4 DQSL VDDQ#F2 F2 58C1 BI DQSB1_DP F4 DQSL VDDQ#F2 F2
58C1 BI DQSB0_DP C8 DQSU VDDQ#H3 H3 58C1 BI DQSB2_DP C8 DQSU VDDQ#H3 H3
VDDQ#H10 H10 VDDQ#H10 H10
C 58D1 BI
DQMB<3> E8 DML 58D1 BI
DQMB<1> E8 DML C
58D1 BI
DQMB<0> D4 DMU VSS#A10 A10 58D1 BI
DQMB<2> D4 DMU VSS#A10 A10
VSS#B4 B4 VSS#B4 B4
VSS#E2 E2 VSS#E2 E2
58C1 BI DQSB3_DN G4 DQSL VSS#G9 G9 58C1 BI DQSB1_DN G4 DQSL VSS#G9 G9
58C1 BI DQSB0_DN B8 DQSU VSS#J3 J3 58C1 BI DQSB2_DN B8 DQSU VSS#J3 J3
VSS#J9 J9 VSS#J9 J9
VSS#M2 M2 VSS#M2 M2
VSS#M10 M10 VSS#M10 M10
65C8 65C4 64C4 63C8 63C4 62C7 62C4 58A1 IN VM_RESET T3 RESET VSS#P2 P2 65C8 65C4 64C7 63C8 63C4 62C7 62C4 58A1 IN VM_RESET T3 RESET VSS#P2 P2
R5529 VSS#P10 P10 R5528 VSS#P10 P10
1 2 L9 ZQ_ZQ0 VSS#T2 T2 1 2 L9 ZQ_ZQ0 VSS#T2 T2
T10 T10
243_1%_2
VSS#T10
THAMES: 40 OHM 243_1%_2
VSS#T10
VSSQ#B2 B2 SEYMOUR: 56 OHM VSSQ#B2 B2

VSSQ#D2 D2 VSSQ#D2 D2
VSSQ#D9 D9 64C4 58B1 IN CLKB0_DN 1 R5544 2 1 R5545 2 CLKB0_DP
IN 58B1 64D4 VSSQ#D9 D9
J2 NC_ODT VSSQ#E3 E3 64C7 64D7 J2 NC_ODT VSSQ#E3 E3
L2 E9 40.2_1%_2 40.2_1%_2 L2 E9
NC_CSI VSSQ#E9 NC_CSI VSSQ#E9
J10 F10 J10 F10
0.01UF_50V_2
NC_CE1 VSSQ#F10 NC_CE1 VSSQ#F10
L10 G2 L10 G2
1
NC_ZQ1 VSSQ#G2 NC_ZQ1 VSSQ#G2
G10 G10
C5518
VSSQ#G10 VSSQ#G10
B B
2
SAM_K4B1G1646D_HCF7_FBGA_100P P1V5S_DGPU SAM_K4B1G1646D_HCF7_FBGA_100P P1V5S_DGPU
4.99K_1%_2 4.99K_1%_2
4.99K_1%_24.99K_1%_2
2
2
R5524
R5526
P1V5S_DGPU
P1V5S_DGPU
2
VRAM_VREFC_B<2> VRAM_VREFD_B<1>
4.99K_1%_2 4.99K_1%_2
2
4.99K_1%_2
R5520
64D4 64D4
2 1
21
IN IN
0.1uF_16V_2
0.1uF_16V_2
R5522
1
C5510
C5511
R5527
R5525
VRAM_VREFC_B<0>
1
VRAM_VREFD_B<3>
1
64D7 IN
0.1uF_16V_2
64D7 IN
4.99K_1%_2
1
2
0.1uF_16V_2
1
1
C5508
R5521
1
R5523
C5509
2
1
2
A A
P1V5S_DGPU
P1V5S_DGPU
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
2.2UF_6.3V_2
1
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
C5558
C5559
C5560
C5561
C5562
C5550
C5551
C5552
C5553
C5554
C5555
C5556 C5557 C5563 C5564
10UF_6.3V_3 10UF_6.3V_3
10UF_6.3V_3 10UF_6.3V_3
INVENTEC
2
2
2
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5507
U5506 VRAM_VREFC_B<6> M9 E4 DQB<39>
65A8 IN VRAM_VREFC_B<4> M9 VREFCA DQL0 E4 DQB<55>
BI 58D4
65A4 IN VRAM_VREFD_B<5> H2
VREFCA DQL0
F8 DQB<37>
BI 58D4
65A6 IN VRAM_VREFD_B<7> H2 VREFDQ DQL1 F8 DQB<54>
BI 58D4
65A3 IN VREFDQ DQL1
F3 DQB<36>
BI 58D4
F3 DQB<51> DQL2 BI 58D4
MAB<13..0> 0 MAB<0> N4
DQL2
F9 DQB<52>
BI 58D4
65D8 64D7 64D4 58D1 58A1 BI MAB<13..0> 0 MAB<0> N4 A0 DQL3 F9 DQB<38>
BI 58D4
65D4 64D7 64D4 58D1 58A1 BI A0 DQL3 BI 58D4 1 MAB<1> P8 H4 DQB<35>
1 MAB<1> P8 H4 DQB<48> A1 DQL4 BI 58D4
A1 DQL4 BI 58D4 2 MAB<2> P4 H9 DQB<32>
2 MAB<2> P4 H9 DQB<53> A2 DQL5 BI 58D4
A2 DQL5 BI 58D4 MAB<3> N3 G3 DQB<33>
MAB<3> N3 G3 DQB<49> 3 A3 DQL6 BI 58D4
3 A3 DQL6 BI 58D4 MAB<4> P9 H8 DQB<34>
MAB<4> P9 H8 DQB<50> 4 A4 DQL7 BI 58D4
4 A4 DQL7 BI 58D4 MAB<5> P3
MAB<5> P3 5 A5
5 A5 MAB<6> R9
MAB<6> R9 6 A6
6 A6 MAB<7> R3 D8 DQB<41>
MAB<7> R3 D8 DQB<59> 7 A7 DQU0 BI 58D4
7 A7 DQU0 BI 58D4 MAB<8> T9 C4 DQB<44>
MAB<8> T9 C4 DQB<63> 8 A8 DQU1 BI 58D4
8 A8 DQU1 BI 58D4 MAB<9> R4 C9 DQB<42>
MAB<9> R4 C9 DQB<62> 9 A9 DQU2 BI 58D4
9 A9 DQU2 BI 58D4 MAB<10> L8 C3 DQB<45>
MAB<10> L8 C3 DQB<58> 10 A10_AP DQU3 BI 58D4
10 A10_AP DQU3 BI 58D4 MAB<11> R8 A8 DQB<40>
MAB<11> R8 A8 DQB<60> 11 A11 DQU4 BI 58D4
11 A11 DQU4 BI 58D4 MAB<12> N8 A3 DQB<47>
12 58D4
12 MAB<12> N8 A12 DQU5 A3 DQB<56>
BI 58D4 MAB<13> T4
A12 DQU5
B9 DQB<43>
BI
D 13 MAB<13> T4 B9 DQB<61> 58D4
13 A13 DQU6 BI 58D4
T8
A13 DQU6
A4 DQB<57>
BI T8 A14 DQU7 A4 DQB<46>
BI 58D4 D
A14 DQU7 BI 58D4 M8 P1V5S_DGPU
M8 A15_BA3
P1V5S_DGPU A15_BA3
MAB_BA<0> M3 B3 65D8 64D7 64D4 58D1 BI MAB_BA<0> M3 BA0 VDD#B3 B3

65D4 64D7 64D4 58D1 BI MAB_BA<1> N9
BA0 VDD#B3
D10 65D8 64D7 64D4 58D1 BI MAB_BA<1> N9 BA1 VDD#D10 D10
65D4 64D7 64D4 58D1 BI MAB_BA<2> M4
BA1 VDD#D10
G8 65D8 64D7 64D4 58D1 BI MAB_BA<2> M4 BA2 VDD#G8 G8
65D4 64D7 64D4 58D1 BI BA2 VDD#G8 K3
K3 VDD#K3
VDD#K3 K9
K9 VDD#K9
VDD#K9 N2
N2 VDD#N2
CLKB1_DP J8
VDD#N2
N10 65D8 65B4 58B1 IN CLKB1_DP J8 CK VDD#N10 N10
65D4 65B4 58B1 IN CLKB1_DN K8
CK VDD#N10
R2 65C8 65B5 58B1 IN CLKB1_DN K8 CK VDD#R2 R2
65D4 65B5 58B1 IN CKEB1 K10
CK VDD#R2
R10 P1V5S_DGPU 65C8 58B1 IN CKEB1 K10 CKE_CKE0 VDD#R10 R10 P1V5S_DGPU
65C4 58B1 IN CKE_CKE0 VDD#R10
ODTB1 K2 A2 65C8 58B1 IN ODTB1 K2 ODT VDDQ#A2 A2

65C4 58B1 IN CSB1#_0 L3
ODT VDDQ#A2
A9 65C8 58B1 IN CSB1#_0 L3 CS VDDQ#A9 A9
65C4 58B1 IN RASB1# J4
CS VDDQ#A9
C2 65C8 58B1 IN RASB1# J4 RAS VDDQ#C2 C2
65C4 58B1 IN CASB1# K4
RAS VDDQ#C2
C10 65C8 58B1 IN CASB1# K4 CAS VDDQ#C10 C10
65C4 58B1 IN WEB1# L4
CAS VDDQ#C10
D3 65C8 58A1 IN WEB1# L4 WE VDDQ#D3 D3
65C4 58A1 IN WE VDDQ#D3 E10
E10 VDDQ#E10
DQSB6_DP F4
VDDQ#E10
F2 58C1 BI DQSB4_DP F4 DQSL VDDQ#F2 F2
58C1 BI DQSB7_DP C8
DQSL VDDQ#F2
H3 58C1 BI DQSB5_DP C8 DQSU VDDQ#H3 H3
58C1 BI DQSU VDDQ#H3 H10
H10 VDDQ#H10
DQMB<6> E8
VDDQ#H10
58D1 BI
DQMB<4> E8 DML
C 58C1 BI DML DQMB<5> D4 A10 C
58C1 BI
DQMB<7> D4 DMU VSS#A10 A10 58C1 BI DMU VSS#A10
B4
B4 VSS#B4
VSS#B4 E2
E2 VSS#E2
DQSB6_DN G4
VSS#E2
G9 58C1 BI DQSB4_DN G4 DQSL VSS#G9 G9
58C1 BI DQSB7_DN B8
DQSL VSS#G9
J3 58C1 BI DQSB5_DN B8 DQSU VSS#J3 J3
58C1 BI DQSU VSS#J3 J9
J9 VSS#J9
VSS#J9 M2
M2 VSS#M2
VSS#M2 M10
M10 VSS#M10
VM_RESET T3
VSS#M10
P2 65C8 64C7 64C4 63C8 63C4 62C7 62C4 58A1 IN VM_RESET T3 RESET VSS#P2 P2
64C4 63C8 63C4 62C7 62C4 58A1 IN RESET VSS#P2 P10
65C4 64C7 P10 R5538 VSS#P10
R5539 VSS#P10
1 2 L9 T2
1 2 L9 ZQ_ZQ0 VSS#T2 T2 THAMES: 40 OHM ZQ_ZQ0 VSS#T2
VSS#T10 T10
T10
243_1%_2
VSS#T10
SEYMOUR: 56 OHM 243_1%_2
VSSQ#B10 B10
B10
VSSQ#B10
D2 65C8 58B1 IN CLKB1_DN 1 R5546 2 1 R5547 2CLKB1_DP IN 58B1 65D4 VSSQ#D2 D2
VSSQ#D2 65D4 65D8 D9
D9 VSSQ#D9
VSSQ#D9 40.2_1%_2 40.2_1%_2 J2 E3
J2 E3 NC_ODT VSSQ#E3
NC_ODT VSSQ#E3 L2 E9
L2 E9 NC_CSI VSSQ#E9
1
0.01UF_50V_2
NC_CSI VSSQ#E9 J10 F10
J10 F10 NC_CE1 VSSQ#F10
C5519
NC_CE1 VSSQ#F10 L10 G2
L10 G2 NC_ZQ1 VSSQ#G2
NC_ZQ1 VSSQ#G2 G10
G10 VSSQ#G10
VSSQ#G10
B B
A1 NC NC T1
A1 T1
2
NC NC A11 T11
A11 T11 NC NC
NC NC
4.99K_1%_24.99K_1%_2
4.99K_1%_24.99K_1%_2
2
2
4.99K_1%_2 4.99K_1%_2
4.99K_1%_2 4.99K_1%_2
R5534
R5536
2
2
R5530
R5532
VRAM_VREFC_B<6> VRAM_VREFD_B<5>
VRAM_VREFC_B<4> VRAM_VREFD_B<7> 65D4 65D4
21
21
IN IN
0.1UF_16V_2
0.1UF_16V_2
1
1
1
2 1
65D8 IN 65D8 IN
C5514
R5535
C5515
R5537
0.1UF_16V_2
1
0.1UF_16V_2
2
1
C5513
R5533
R5531
C5512
2
1
1
P1V5S_DGPU
2
1
1
2
P1V5S_DGPU
A A
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
C5573
C5574
C5575
C5576
C5577
2.2UF_6.3V_2
C5578 C5579
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
C5565
C5566
C5567
C5568
C5569
C5570
10UF_6.3V_3 10UF_6.3V_3
C5571 C5572
2
2
10UF_6.3V_3 10UF_6.3V_3
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
USB BOARD
D
D
P5V0A_USB3_DB
1
C9100
22UF_6.3V_5
2
DGND_USB3_DB
CN9100
L9100 1 VCC G1 G1
66B5 BI USB_P2_DN_DB 4 3
USB_L_P2_DN_DB 2 DATA- G2 G2
66B5 BI USB_P2_DP_DB 1 2
USB_L_P2_DP_DB 3 DATA+ G3 G3
4 GND G4 G4
C WCM_2012_900T C
SUYIN_020173GR004M555ZL_4P
DGND_USB3_DB
DGND_USB3_DB
P5V0A_USB3_DB
SMDPAD_1P_40X1201 PAD9100
USB_P2_DN_DB SMDPAD_1P_40X1201 PAD9101

B 66C6 BI B
USB_P2_DP_DB SMDPAD_1P_40X1201 PAD9102
66C6 BI
SMDPAD_1P_40X1201 PAD9103
DGND_USB3_DB
1 S9100
SCREW240_800_1P
1 S9101
SCREW300_1000_1P
FIX9100 FIX9101
A A
1
1
DGND_USB3_DB FIX_MASK FIX_MASK
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TOUCH PAD BOARD 4 PIN

TOUCHPAD TO MODULE CONN TOUCHPAD TO MB CONN
D
D
P5V0S_TPB
R9201 2 P5V0S_TPB
67D7 67D4 67B7 BI TP_IM_CLK_5 1 0_5%_2
TP_IM_DAT_5 1 R9202 2 SMDPAD1_28X118 1
67D7 67D4 67B7 BI 0_5%_2_DY PAD9201
R9203 2 67D7 67B7 TP_IM_CLK_5 SMDPAD1_28X118 1
67D7 67D4 67B7 BI TP_IM_DAT_5 1 0_5%_2 BI SMDPAD1_28X118 PAD9202
CN9201 67D7 67B7 TP_IM_DAT_5 1
TP_IM_CLK_5 R9204 2 1
BI SMDPAD1_28X118 PAD9203
67D7 67D4 67B7 1 0_5%_2_DY 1
BI 2
1
PAD9204
LEFT_TP 1 R9205 2 2
67C7 67A2 IN 0_5%_2 3 3
1 R9206 2 4
0_5%_2_DY 4
67A2 IN RIGHT_TP 5 5
1 R9207 2 6 G1
0_5%_2 6 G1
R9208 2 G2 G2
67C7 67A2 IN LEFT_TP 1 0_5%_2_DY
ACES_50592_0060N_001_6P DGND_TP
DGND_TP
DGND_TP
C C
4PIN IMR/METAL TEXTURE

R9201 V
R9202 V
R9203 V
R9204 V
R9205 V
R9206 V
R9207 V
R9208 V
B B
R9213 V V
R9214 V V P5V0S_TPB
R9213
67D7 67D4 TP_IM_CLK_5 2 1 47K_5%_2
BI
67D7 67D4 TP_IM_DAT_5 2 1 47K_5%_2
BI
R9214
SW9201
4 A B 1
5 2 RIGHT_TP OUT 67C7
6 C D 3
FIX9201
FIX9202
FIX9203
FIX9204
FIX9205
FIX9206
MISAKI_NTC017_DA1G_E160T_6P
SW9202
4 1
1
A B
FIX_MASK FIX_MASK FIX_MASK FIX_MASK FIX_MASK FIX_MASK 5 2 LEFT_TP OUT 67C7
6 C D 3
A A
1
2
1 S9201
D9201
SCREW230_800_1P
S9202
3
1 DGND_TP
SCREW230_500_1P
1 S9203
DGND_TP
INVENTEC
SCREW230_800_1P TITLE
Block Diagram
DOC.NUMBER REV
DGND_TP
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 9000~9999(SMALL BOARD)
D
D
POWER BUTTON
SW9000
4 1 D9000 1 PAD9000
A B SMDPAD_1P_40X120
1
2
1
5 2
6 C D 3 C9000
MISAKI_NTC017_DA1G_E160T_6P 1000PF_50V_2_DY PAD9001

1
SMDPAD_1P_40X120
2
DGND_PWRSW_DB PHP_PESD5V2S2UT_SOT23_3P
C C
B B
FIX9003 FIX9004 FIX9005

1
1
FIX_MASK FIX_MASK FIX_MASK
1 S9000
SCREW220_800_1P
1 S9001
SCREW220_800_1P
A A
DGND_PWRSW_DB
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
PVBAT P1V5 P3V3S P5V0S P5V0S_AUDIO_AVDD D
C7501 C7506 C7508

1 2 1 2 1 2
0.1UF_16V_2_DY 0.1UF_16V_2 0.1UF_16V_2_DY

C7502 C7507
1 2 1 2
0.1UF_16V_2_DY 0.1UF_16V_2_DY
C7503
1 2
0.1UF_16V_2_DY
C7504 PVCORE P1V5S_DGPU P5V0A P5V0S_AUDIO_AVDD
1 2
C7509
0.1UF_16V_2_DY 1 2
C7511
C7505 1 2
1 2
0.1UF_16V_2_DY
0.1UF_16V_2_DY
0.1UF_16V_2_DY
C7512
C 1 2 C
P5V0A P3V3S
0.1UF_16V_2_DY
P1V5S_DGPU PVCORE_DGPU
C7516
1 2
C7518
P3V3S 0.1UF_16V_2 1 2
0.1UF_16V_2
C7515
1 2
P5V0A P1V5S_DGPU
0.1UF_16V_2
C7517
1 2
0.1UF_16V_2
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TOUCH PAD BOARD 8 PIN

TOUCHPAD TO MODULE CONN TOUCHPAD TO MB CONN
D
D
P3V3S_TPM
P5V0S_DB P3V3S_TPM
CN9303
G2 G2
8 8 SMDPAD1_28X118 1
70D4 70B7 TP_IM_DAT_8 PAD9301
BI 7 7
70D7 70B7 BI TP_IM_CLK_8 SMDPAD1_28X118 1
70D4 70B7 TP_IM_CLK_8 PAD9302
BI 6 6
70D7 70B7 BI TP_IM_DAT_8 SMDPAD1_28X118 1
5 5 SMDPAD1_28X118 1 PAD9303
70B2 RIGHT_TP_8 PAD9304
IN 4 4 SMDPAD1_28X118 1
70B2 LEFT_TP_8 PAD9305
IN 3 3
70C7 BI TP_PCH_3S_SMCLK_8 SMDPAD1_28X118 1
70C4 TP_PCH_3S_SMCLK_8 PAD9306
BI 2 2
70C7 BI TP_PCH_3S_SMDATA_8 SMDPAD1_28X118 1
70C4 TP_PCH_3S_SMDATA_8 PAD9307
BI 1 1 SMDPAD1_28X118 1
PAD9308
G1 G1
ACES_50503_0084N_001_8P
DGND_DB
DGND_DB
C C
DGND_DB
SW9301
4 A B 1
5 2 RIGHT_TP_8 OUT 70C7
6 C D 3
B MISAKI_NTC017_DA1G_E160T_6P B
SW9302
4 A B 1
5 2 LEFT_TP_8 OUT 70C7
6 C D 3
P3V3S_TPM
1
2
R9313 D9301
70D7 70D4 TP_IM_CLK_8 2 1 47K_5%_2 DGND_DB
BI
70D7 70D4 TP_IM_DAT_8 2 1 47K_5%_2
BI
R9314 PHP_PESD5V2S2UT_SOT23_3P_DY
3
DGND_DB
FIX9301
FIX9302
FIX9303
FIX9304
FIX9305
FIX9306
1
FIX_MASK FIX_MASK FIX_MASK FIX_MASK FIX_MASK FIX_MASK

A A
1 S9301
SCREW230_800_1P
1 S9302
SCREW230_500_1P
S9303
INVENTEC
1 TITLE
SCREW230_800_1P MODEL,PROJECT,FUNCTION
Block Diagram
DGND_DB
DOC.NUMBER REV
A3 CS
8 7 6 5 4 3 2 1

Inventec drawing and specification document block diagram

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8 7 6 5 4 3 2 1

THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC

F HSF Property:ROHS or Halogen-Free F

PAGE PAGE PAGE

9. POWER VCCIO 34. LCM CONN 60. VGA 5

PCIE USB2.0 USB_8: CARD READER

A ENE-P2809A EC WINDBOND SPI SPI FLASH 4MB A

THERMAL SENSOR NPCE885LA0DX WINB_W25Q32BVSSIG

BATTERY CHARGER &

ADAPTOR +VBAT +V5A_+-5% +V5S

FUSE BQ24725RGRR TPS51123 NMOS

CHANGING POINTS~~ NMOS

AVG CURRENT ~~TEST RESULT(MAX CURRENT) OCP 13.2A R=115K MODEL,PROJECT,FUNCTION

FUSE6000 CN6000 L7600 PVADPTR

NMOS_4D3S NMOS_4D3S NMOS_4D3S

4.3K_5%_2 4.3K_5%_2 BAT54C_30V_0.2A

470PF_50V_2 4.7UF_25V_5 4.7UF_25V_5 CSC0805_DY

R6114 7 VO2 VO1 24

R6100 RSC_0603_DY VRP3V3A_LDO RSC_0603_DY

14C6 OUT TI_TPS51123RGER_QFN_24P

14B7 EN_VCCP PVBAT

VSS_SENSE_VCCIO 0_5%_2_DY VRP1V0_VCCP_LG

SA_PG 14A6 21B6

R6711 R6628 44C2 11A3 VR_SVID_CLK 18 43

44C2 11A3 BI VDIO TI_TPS51650RSLR_QFN_48P CDL2

17.8K_1%_2 100K_5%_NTC 28.7K_1%_2

R6713 0_5%_2 L6620

21D3 EN_PVCORE R6731

R6630 GSKIP# 12B7

11D7 11D6 11D4 11C8 11B7 11A4 IN

11B7 OUT AXG_PG 44C2 11C7 BI VR_SVID_DATA MODEL,PROJECT,FUNCTION

1 2 1 2 R6707 R6708 R6709

11B5 GPWM2 3 6 L6720

G0 G1 VOUT VOUT VOUT RESISTOR VALUE

VCCIO VCCSA DGPU P1V8S

45D3 47K_5%_2 C7040

21B6 14A6 10A5 SA_PG SA_PG

VCCP_PG VCCP_PG D7040

P15V0A P3V3AL P3V3A

16C7 16A6 IN DGPU_PWR_EN_3R 1 G

DGPU_PWR_EN_15R 16B7 16D7

16C4 16A1 13D2 13B2 DGPU_PWR_EN 1R7035 2 1 G SLP_S3_3R1 2

REFERENCE 0~49(PCB SCREW)

BOUNDARY SCAN TEST POINT

TP30 TP30 TP30

PCB CPU GPU WLAN

REFERENCE 50-99(HALL SENSOR)

DC IN / BATTERY CHARGE LED

REFERENCE 200~249(POWER CONN)

CN280 P5V0S 21D3 OUT PWR_SWIN#_3 1 1 G 3

21E8 5B7 IN BI 27C3 47C3

37B1 36B2 HDMI_HPD_EC 107

7 1 R314 2 3.3K_5%_2 1UF_6.3V_2

EC_SPI_CLK 21C7 21D6

47A6 IN /CS VCC

EC_SPI_SO 2 71 R319 2 3.3K_5%_2_DY

47A6 EC_SPI_CLK 21C7 21D6

41D6 11C7 OUT CPU_PROCHOT#

14A6 10A5 SA_PG 64 51 2

19A7 OUT GPIO32/D_PWM KBSOUT7/GPIOB7

SIZE CODE DOC.NUMBER REV

48C7 48D7 48D8