CHAPTER-1

1. INTRODUCTION

A UART is an integrated circuit that plays the most important role in serial communication. A
UART is a circuit that sends parallel data through serial lines. UARTs are used in association
with the serial communication EIA standard RS- 232. The main function of a UART is
parallel-serial conversion during transmission and serial-parallel conversion during
reception (for example the communication between a DSP and a PC). In contrast, parallel
communication needs a multi-bit address bus and is convenient only for short distance
transmission. Universal Asynchronous Receiver Transmitter (UART) is a kind of serial
communication protocol; mostly used for short-distance, low speed, low-cost data exchange
between computer and peripherals. UARTs are used for asynchronous serial data communication
by converting data from parallel to serial at transmitter with some extra overhead bits using shift
register and vice versa at receiver. Serial communication reduces the distortion of a signal,
therefore makes data transfer between two systems separated in great distance possible. It is
generally connected between a processor and a peripheral, to the processor the UART appears as
an 8-bit read/write parallel port. The UART implemented with VERILOG language can be
integrated into the FPGA to achieve compact, stable and reliable data transmission.

1
 CHAPTER-2

2. BASIC CONCEPT OF UART:

A UART (Universal Asynchronous Receiver/Transmitter) is the microchip with programming

that controls a computer's interface to its attached serial devices. Specifically, it provides the
computer with the RS-232C Data Terminal Equipment (DTE) interface so that it can "talk" to
and exchange data with modems and other serial devices.

UART is a device that has the capability to both receive and transmit serial data. UART
exchanges text data in an American Standard Code for Information Interchange (ASCII) format
in which each alphabetical character is encoded by 7 bits and transmitted as 8 data bits. For
transmission the UART protocol wraps this 8 bit sub word with a start bit in the least significant
bit (LSB) and a stop bit in the most significant bit (MSB) resulting in a 10 bit word format.

Start Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Stop

A number of factors allow serial to be clocked at a greater rate:

Clock skew between different channels is not an issue (for unclocked serial links)
A serial connection requires fewer interconnecting cables (e.g. wires/fibers) and hence
occupies less space. The extra space allows for better isolation of the channel from its
surroundings
Crosstalk is less of an issue, because there are fewer conductors in proximity.

In many cases, serial is a better option because it is cheaper to implement. Many ICs have serial
interfaces, as opposed to parallel ones, so that they have fewer pins and are therefore cheaper. In
telecommunications and computer science, serial communications is the process of sending data
one bit at one time, sequentially, over a communications channel or computer bus. This is in
contrast to parallel communications, where all the bits of each symbol are sent together. Serial
communications is used for all long-haul communications and most computer networks, where
the cost of cable and synchronization difficulties makes parallel communications impractical.

2
Serial computer buses are becoming more common as improved technology enables them to
transfer data at higher speeds.

UART transmitter controls transmission by fetching a data word in parallel format and directing
the UART to transmit it in a serial format. Likewise, the Receiver must detect transmission,
receive the data in serial format, strip of the start and stop bits, and store the data word in a
parallel format. Since the UART is asynchronous in working, the receiver does not know when
the data will come, so receiver generate local clock in order to synchronize to transmitter
whenever start bit is received. Asynchronous transmission allows data to be transmitted without
the sender having to send a clock signal to the receiver.
The transmitter and receiver agree on timing parameters in advance and special bits are added to
each word which is used to synchronize the sending and receiving units. When a word is given to
the UART for Asynchronous transmission, a bit called the Start Bit is added to the beginning
of each word that is to be transmitted. The Star Bit is used to alert the receiver that a word of data
is about to be sent, and to force the clock in the receiver into synchronization with the clock in
the transmitter. After the Start Bit, the individual bits of the word of data are sent, with the Least
Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for exactly the
same amount of time as all of the other bits, and the receiver looks at the wire at approximately
halfway through the period assigned to each bit to determine if the bit is a 1 or a 0. For example,
if it takes two seconds to send each bit, the receiver will examine the signal to determine if it is a
1 or a 0 after one second has passed, then it will wait two seconds and then examine the value of
the next bit, and so on.

2.1. BASIC MODULES OF UART:

The UART serial communication module is divided into 5 sub-modules:

1. Baud Rate Generator

2. Transmitting Subsystem
3. Receiving Sub-system
4. Transmitter FIFO
5. Receiver FIFO.

1. BAUD RATE GENERATOR:

3
Baud is a measurement of transmission speed in asynchronous communication. Traditionally, a
Baud Rate represents the number of bits that are actually being sent over the media, not the
amount of data that is actually moved from one DTE device to the other. The Baud count
includes the overhead bits Start, Stop and Parity that are generated by the sending UART and
removed by the receiving UART. This means that seven-bit words of data actually take 10 bits to
be completely transmitted. Therefore, a modem capable of moving 300 bits per second from one
place to another can normally only move 30 7-bit words if Parity is used and one Start and Stop
bit are present.

Fig no: 2.1 baud rate counter

The formula for converting bytes per second into a baud rate and vice versa was simple
until error correcting modems came along. These modems receive the serial stream of bits
from the UART in the host computer (even when internal modems are used the data is still
frequently serialized) and converts the bits back into bytes. These bytes are then combined into
packets and sent over the phone line using a Synchronous transmission method. This means that
the Stop, Start, and Parity bits added by the UART in the DTE (the computer) were removed by
the modem before transmission by the sending modem.
When these bytes are received by the remote modem, the remote modem adds Start, Stop and
Parity bits to the words, converts them to a serial format and then sends them to the receiving
UART in the remote computer, who then strips the Start, Stop and Parity bits. The reason all
these extra conversions are done is so that the two modems can perform error correction, which
means that the receiving modem is able to ask the sending modem to resend a block of data that
was not received with the correct checksum. This checking is handled by the modems, and the
DTE devices are usually unaware that the process is occurring. By striping the Start, Stop and
Parity bits, the additional bits of data that the two modems must share between themselves to
perform error-correction are mostly concealed from the effective transmission rate seen by the

4
sending and receiving DTE equipment. For example, if a modem sends ten 7-bit words to
another modem without including the Start, Stop and Parity bits, the sending modem will be able
to add 30 bits of its own information that the receiving modem can use to do error-correction
without impacting the transmission speed of the real data. The use of the term Baud is further
confused by modems that perform compression.

Fig no: 2.2 baud rate generator

A single 8-bit word passed over the telephone line might represent a dozen words that were
transmitted to the sending modem. The receiving modem will expand the data back to its original
content and pass that data to the receiving DTE. Modern modems also include buffers that allow
the rate that bits move across the phone line (DCE to DCE) to be a different speed than the speed
that the bits move between the DTE and DCE on both ends of the conversation. Normally the
speed between the DTE and DCE is higher than the DCE to DCE speed because of the use of
compression by the modems. Because the number of bits needed to describe a byte varied during
the trip between the two machines plus the differing bits-per-seconds speeds that are used present
on the DTE-DCE and DCE-DCE links, the usage of the term Baud to describe the overall
communication speed causes problems and can misrepresent the true transmission speed. So Bits
Per Second (bps) is the correct term to use to describe the transmission rate seen at the DCE to
DCE interface and Baud or Bits Per Second are acceptable terms to use when a connection is
made between two systems with a wired connection, or if a modem is in use that is not
performing error-correction or compression. Modern high speed modems (2400, 9600, 14,400,
and 19,200bps) in reality still operate at or below 2400 baud, or more accurately, 2400 Symbols
per second. High speed modem are able to encode more bits of data into each Symbol using a

5
technique called Constellation Stuffing, which is why the effective bits per second rate of the
modem is higher, but the modem continues to operate within the limited audio bandwidth that
the telephone system provides. Modems operating at 28,800 and higher speeds have variable
Symbol rates, but the technique is the same.

Transmitter FIFO and Receiver FIFO

The FIFO buffer provides more buffering space and also reduces the probability of data
overruns. The main function of FIFO buffer is to send and receive data, and reduce the
communication time between the serial port and the CPU.. Various signals defined to perform the
operation of FIFO. A data-overrun error occurs when a new data word arrives and the FIFO is
full. We can adjust the desired number of words in FIFO to accommodate the processing need of
the main system.

2. TRANSMITTER:
Transmitting Subsystem:

The main function of transmitter logic is to read data from the transmitter FIFO, convert parallel
data into serial data and send to peripherals. It is implemented using a shift register that shifts out
data bits at a specific rate. The rate can be controlled by ticks generated by the baud rate
generator module; the frequency of the ticks is 16 times slower than that of the UART receiver.
The symbol logic for transmitter.. Here, the baud rate of transmitter is a same as UART receiver.
A bit is shifted out every 16 enable ticks .

Symbol logic structure of UART Transmitter & Receiving Sub-System This circuit is
implemented to receive the data word using oversampling procedure. The oversampling scheme
basically performs the function of a clock signal. Instead of using the rising edge to indicate
when the input signal is valid, it utilizes sampling ticks to estimate the middle point of each bit.
While the receiver has no information about the exact onset time of the start bit, the estimation
can be off by at most 1/16. The ASMD chart using finite state and symbol logic.

6
 Fig no: 2.3 Transmitter using finite state machine
3. RECEIVER:
Receiving Sub-system

This circuit is implemented to receive the data word using oversampling procedure. The
oversampling scheme basically performs the function of a clock signal. Instead of using the
rising edge to indicate when the input signal is valid, it utilizes sampling ticks to estimate the
middle point of each bit. While the receiver has no information about the exact onset time of the
start bit, the estimation can be off by at most 1/16

Fig no:.2.4 Receiver using finite state machine

7
 CHAPTER-3

3. DESIGN METHODOLOGY

UART transmitter logic receive parallel signal and converted into serial data, the UART receiver
logic receive serial signal and converted into parallel signal and FIFO are used to avoid the loss
of data.

3.1 Synchronous Serial Transmission

Synchronous serial transmission requires that the sender and receiver share a clock with one
another, or that the sender provide a strobe or other timing signal so that the receiver knows
when to read the next bit of the data. In most forms of serial Synchronous communication, if
there is no data available at a given instant to transmit, a fill character must be sent instead so
that data is always being transmitted. Synchronous communication is usually more efficient
because only data bits are transmitted between sender and receiver, and synchronous
communication can be more costly if extra wiring and circuits are required to share a clock
signal between the sender and receiver. A form of Synchronous transmission is used with printers
and fixed disk devices in that the data is sent on one set of wires while a clock or strobe is sent
on a different wire. Printers and fixed disk devices are not normally serial devices because most
fixed disk interface standards send an entire word of data for each clock or strobe signal by using
a separate wire for each bit of the word. In the PC industry, these are known as Parallel devices.
The standard serial communications hardware in the PC does not support Synchronous
operations. This mode is described here for comparison purposes only.

Fig no: 3.1 Serial data transmission

8
3.2 Asynchronous Serial Transmission:

An asynchronous transmission protocol in which a start signal is sent prior to each byte,
character or code word and a stop signal is sent after each code word. The start signal serves to
prepare the receiving mechanism for the reception and registration of a symbol and the stop
signal serves to bring the receiving mechanism to rest in preparation for the reception of the next
symbol. A common kind of start-stop transmission is ASCII over RS-232, for example for use in
teletype writer operation.

Fig no: 6

In the diagram, a start bit is sent, followed by eight data bits, no parity bit and one stop bit, for a
10-bit character frame. The number of data and formatting bits, and the transmission speed, must
be pre-agreed by the communicating parties. After the stop bit, the line may remain idle
indefinitely, or another character may immediately be started.

9
 CHAPTER- 4
4. INTERFACE

4.1 DCE-DTE:

The Data Terminal Equipment (DTE) and the Data Carrier Equipment (DCE). Usually, the DTE
device is the terminal (or computer), and the DCE is a modem. Across the phone line at the other
end of a conversation, the receiving modem is also a DCE device and the computer that is
connected to that modem is a DTE device. The DCE device receives signals on the pins that the
DTE device transmits on, and vice versa. When two devices that are both DTE or both DCE
must be connected together without a modem or a similar media translator between them, a
NULL modem must be used. The NULL modem electrically re-arranges the cabling so that the
transmitter output is connected to the receiver input on the other device, and vice versa. Similar
translations are performed on all of the control signals so that each device will see what it thinks
are DCE (or DTE) signals from the other device. The numbers of signals generated by the DTE
and DCE devices are not symmetrical. The DTE device generates fewer signals for the DCE
device than the DTE device receives from the DCE.

DTE-A DTE stands for data terminal equipment is an end instrument that convert user
information into signals or reconverts the receive signal. It is a functional unit of station that
serves as data source or data sink and provides for communication control function according
to the link protocol. A male connector is used in DTE and has pin out configuration.
DCE-A DCE stands for data communication equipments. It sits between the DTE and data
transmission circuit for example modem. A DCE device uses a female connector which has
holes on the surface to hold male connector. A minimum of three signals are required for
communication between a DTE and a DCE devices. These signals are a transmission line, a
reception line and ground. These two devices communicate with each other by handshaking.
It allows a DTE and a DCE device system to acknowledge each other before sending the
data.

4.2 INTERFACING

4.2.1 RS232 PORT

10
RS-232 was first introduced in 1962 by the Radio Sector of the EIA.The original DTEs were
electromechanical teletypewriters, and the original DCEs were modems. When electronic
terminals began to be used, they were often designed to be interchangeable with teletypewriters,
and so supported RS-232. Since the requirements of devices such as computers, printers, test
instruments, POS terminals and so on were not considered by the standard, designers
implementing an RS-232 compatible interface on their equipment often interpreted the
requirements idiosyncratically.

Fig no: 4.1 RS 232

Common problems were non-standard pin assignment of circuits on connectors, and incorrect or
missing control signals. The lack of adherence to the standards produced a thriving industry of
breakout boxes, patch boxes, test equipment, books, and other aids for the connection of
disparate equipment. A common deviation from the standard was to drive the signals at a reduced
voltage. Some manufacturers therefore built transmitters that supplied +5 V and -5 V and labeled
them as "RS-232 compatible". Later personal computers (and other devices) started to make use
of the standard so that they could connect to existing equipment. For many years, an RS-232-
compatible port was a standard feature for serial communications, such as modem connections,
on many computers. It remained in widespread use into the late 1990s. In personal computer
peripherals, it has largely been supplanted by other interface standards, such as USB. RS-232 is
still used to connect older designs of peripherals, industrial equipment (such
as PLCs),console ports and special purpose equipment.
The standard has been renamed several times during its history as the sponsoring organization
changed its name, and has been variously known as EIA RS-232, EIA 232, and most recently as

11
TIA 232. The standard continued to be revised and updated by the Electronic Industries
Alliance and since 1988 by the Telecommunications Industry Association (TIA).Revision C was
issued in a document dated August 1969. Revision D was issued in 1986. The current revision
is TIA-232-F Interface Between Data Terminal Equipment and Data Circuit-Terminating
Equipment Employing Serial Binary Data Interchange, issued in 1997. Changes since Revision C
have been in timing and details intended to improve harmonization with the CCITT standard
V.24, but equipment built to the current standard will interoperate with older versions.

Fig no: 4.2 RS 232 interface

Related ITU-T standards include V.24 (circuit identification) and V.28 (signal voltage and timing
characteristics).

In revison D of EIA-232, the D-subminiature connector was formally included as part of the
standard (it was only referenced in the appendix of RS 232 C). The voltage range was extended
to +/- 25 volts, and the circuit capacitance limit was expressly stated as 2500 pF. Revision E of
EIA 232 introduced a new, smaller, standard D-shell 26-pin "Alt A" connector, and made other
changes to improve compatibility with CCITT standards V.24, V.28 and ISO 2110.

12
4.2.2 EIA

The original RS prefix became EIA (Electronics Industries Association) and later EIA/TIA after
EIA merged with TIA (Telecommunications Industries Association). The EIA-232 spec provides
also for synchronous (sync) communication but the hardware to support sync is almost always
missing on PC's. The RS designation is obsolete but is still in use.

The serial port is more than just a physical connector on the back of a computer or terminal. It
includes the associated electronics which must produce signals conforming to the EIA-232
specification. The standard connector has 25 pins, most of which are unused. An alternative
connector has only 9 pins. One pin is used to send out data bytes and another to receive data
bytes. Another pin is a common signal ground. The other "useful" pins are used mainly for
signaling purposes with a steady negative voltage meaning "off" and a steady positive voltage
meaning "on".

13
 CHAPTER-5
5. UART

A UART (Universal Asynchronous Receiver/Transmitter) is the microchip with programming

that controls a computer's interface to its attached serial devices. Specifically, it provides the
computer with the RS-232C Data Terminal Equipment (DTE) interface so that it can "talk" to
and exchange data with modems and other serial devices.
As part of this interface, the UART also:
Converts the bytes it receives from the computer along parallel circuits into a single serial bit
stream for outbound transmission
On inbound transmission, converts the serial bit stream into the bytes that the computer
handles
Adds a parity bit (if it's been selected) on outbound transmissions and checks the parity of
incoming bytes (if selected) and discards the parity bit
Adds start and stop delineators on outbound and strips them from inbound transmissions
Handles interrupts from the keyboard and mouse (which are serial devices with special ports)
May handle other kinds of interrupt and device management that require coordinating the
computer's speed of operation with device speeds
Serial transmission is commonly used with modems and for non-networked communication
between computers, terminals and other devices.

5.1 BLOCK DIAGRAM

14
 Fig no: 5.1 Block diagram of UART

5.2 PIN DIAGRAM:

Fig no: 5.2 pin diagram of UART

5.3 EXPLANATION

15
Actually UART receives/sends data to microprocessor/microcontroller through data bus. The
remaining part of signal handling of RS-232 is done by UART for example start bit, stop bit, and
parity.
The following is the experimental set up for serial communication form. Data from PIC /
MPLAB software will be received to RS-232 Transceiver. It modifies or converts signal into
format appropriate for efficient channel of transmission. Next it will implement using Verilog
HDL. Verilog is a verilfication language and hence have rich capabilities for testing. PLI
(Programming Language Interface) which gives the added flexibility in testing and verification
for the code written in C and then to be integrated with HDL code. Hence, it will connect to
UART Peripheral connector which is physical medium through RS-232. Then it will program
into Altera DE2 board for proof of concept.

CHAPTER NO-6

6. SOFTWARE REQUIREMENTS
6.1 FPGA
The Stratix series FPGAs are the company's largest, highest bandwidth devices, with up to 1.1
million logic elements, integrated transceivers at up to 28 Gbit/s, up to 1.6 Tbit/s of serial
switching capability, up to 1,840 GMACs of signal-processing performance, and up to 7 x72
DDR3 memory interfaces at 800 MHz. Cyclone series FPGAs and SoC FPGAs are the
company's lowest cost, lowest power FPGAs, with variants offering integrated transceivers up to

16
5 Gbit/s. In between these two device families are Arria series FPGAs and SoC FPGAs, which
provide a balance of performance, power, and cost for mid-range applications such as remote
radio heads, video conferencing equipment, and wireline access equipment. Arria FPGAs have
integrated transceivers up to 10 Gbit/s. In December 2012, the company announced that they are
shipping their first 28nm SoC FPGA devices.According to Altera, fully depleted silicon on
insulator (FDSOI) chip manufacturing process is benefitial for FPGAs.

6.2 ASIC
Altera offers a design flow based on HardCopy ASICs, which transitions the FPGA design, once
finalized, to a form which is not alterable. This design flow reduces design security risks as well
as costs for higher volume production. Design engineers can prototype their designs in Stratix
series FPGAs, and then migrate these designs to HardCopy ASICs when they're ready for
volume production.
The unique design flow makes hardware/software co-design and co-verification possible. The
flow has been benchmarked to deliver systems to market 9 to 12 months faster, on average, than
with standard-cell solutions. Design engineers can employ a single RTL, set of intellectual
property (IP) cores, and Quartus II design software for both FPGA and ASIC implementations.
Altera's HardCopy Design Center manages test insertion.

6.3 VERILOG HDL

In 1970''s when IC fabrication was in the primitive stages then designers were doing the digital
design using schematics. But then the design complexity has risen exponentially. So in order to
keep up with the designing complex circuits, electronics and electrical engineers were looking
for some alternative way of defining the hardware. Thus born is the (Hardware description
Language) HDL''s. There are many HDLs now and the popular HDLs are VHDL, Verilog and
systemC.
These HDL''s are different from the usual computer languages from the way it is executed.
Computer languages like C, C++ are sequentially executed whereas HDL''s are executed
concurrently. By concurrent we refer to the way the statements are executed. Hardwares are not
executed sequentially like a c program instead many blocks of the design work in parallel, so
concurrent execution is a must. VHDL is a project of DARPA and Verilog HDL is from the

17
Gateway design Automation (GDA). Cadence acquired GDA and released the language in the
public domain and thus the popularity of the language grew rapidly. Thus many fabrication
companies around the world supported verilog libraries thus making even more popular.
There are many simulators available on the internet and the best for a student is Modelsim from
Mentor Graphics. Verilog has many advantages over VHDL, one of them being the similarity
with C language. In order to build a good command over the design we build, it is important
digital design fundamentals are proper. Once this is over then rest is learning the syntax of the
language and make a succesful design. A good reference book to verilog language can be
"Verilog HDL by Samir Palnitkar", "HDL design by Douglas J Smith", Verilog HDL by Phil
Moorby(Original verilog HDL architect with GDA) and the Language reference
manual(LRM). Verilog is a verilfication language and hence have rich capabilities for testing.
PLI(programming Language Interface) which gives the added flexibility in testing and
verification for the code written in C and then to be integrated with HDL code. Another flexible
feature is UDP which stands for User Defined Primitives.
Verilog was the first modern hardware description language to be invented. It was created by Phil
Moorby and Prabhu Goel during the winter of 1983/1984. The wording for this process was
"Automated Integrated Design Systems" (later renamed to Gateway Design Automation in 1985)
as a hardware modeling language. Gateway Design Automation was purchased by Cadence
Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the
Verilog-XL, the HDL-simulator that would become the de facto standard (of Verilog logic
simulators) for the next decade. Originally, Verilog was intended to describe and allow
simulation; only afterwards was support for synthesis added.
CHAPTER NO-7

7. CODING:
UART CODE:
timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//

18
// Create Date: 22:38:46 04/03/2015
// Design Name:
// Module Name: transmitt
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart(
reset ,
txclk ,
ld_tx_data ,
tx_data ,
tx_enable ,
tx_out ,
tx_empty ,
rxclk ,
uld_rx_data ,
rx_data ,
rx_enable ,
rx_in ,
rx_empty
);
// Port declarations

19
input reset ;
input txclk ;
input ld_tx_data ;
input [7:0] tx_data ;
input tx_enable ;
output tx_out ;
output tx_empty ;
input rxclk ;
input uld_rx_data ;
output [7:0] rx_data ;
input rx_enable ;
input rx_in ;
output rx_empty ;

// Internal Variables
reg [7:0] tx_reg ;
reg tx_empty ;
reg tx_over_run ;
reg [3:0] tx_cnt ;
reg tx_out ;
reg [7:0] rx_reg ;
reg [7:0] rx_data ;
reg [3:0] rx_sample_cnt ;
reg [3:0] rx_cnt ;
reg rx_frame_err ;
reg rx_over_run ;
reg rx_empty ;
reg rx_d1 ;
reg rx_d2 ;
reg rx_busy ;

20
// UART RX Logic
always @ (posedge rxclk or posedge reset)
if (reset) begin
rx_reg <= 0;
rx_data <= 0;
rx_sample_cnt <= 0;
rx_cnt <= 0;
rx_frame_err <= 0;
rx_over_run <= 0;
rx_empty <= 1;
rx_d1 <= 1;
rx_d2 <= 1;
rx_busy <= 0;
end else begin
// Synchronize the asynch signal
rx_d1 <= rx_in;
rx_d2 <= rx_d1;
// Uload the rx data
if (uld_rx_data) begin
rx_data <= rx_reg;
rx_empty <= 1;
end
// Receive data only when rx is enabled
if (rx_enable) begin
// Check if just received start of frame
if (!rx_busy && !rx_d2) begin
rx_busy <= 1;
rx_sample_cnt <= 1;
rx_cnt <= 0;
end
// Start of frame detected, Proceed with rest of data

21
 if (rx_busy) begin
rx_sample_cnt <= rx_sample_cnt + 1;
// Logic to sample at middle of data
if (rx_sample_cnt == 7) begin
if ((rx_d2 == 1) && (rx_cnt == 0)) begin
rx_busy <= 0;
end else begin
rx_cnt <= rx_cnt + 1;
// Start storing the rx data
if (rx_cnt > 0 && rx_cnt < 9) begin
rx_reg[rx_cnt - 1] <= rx_d2;
end
if (rx_cnt == 9) begin
rx_busy <= 0;
// Check if End of frame received correctly
if (rx_d2 == 0) begin
rx_frame_err <= 1;
end else begin
rx_empty <= 0;
rx_frame_err <= 0;
// Check if last rx data was not unloaded,
rx_over_run <= (rx_empty) ? 0 : 1;
end
end
end
end
end
end
if (!rx_enable) begin
rx_busy <= 0;
end

22
end

// UART TX Logic
always @ (posedge txclk or posedge reset)
if (reset) begin
tx_reg <= 0;
tx_empty <= 1;
tx_over_run <= 0;
tx_out <= 1;
tx_cnt <= 0;
end else begin
if (ld_tx_data) begin
if (!tx_empty) begin
tx_over_run <= 0;
end else begin
tx_reg <= tx_data;
tx_empty <= 0;
end
end
if (tx_enable && !tx_empty) begin
tx_cnt <= tx_cnt + 1;
if (tx_cnt == 0) begin
tx_out <= 0;
end
if (tx_cnt > 0 && tx_cnt < 9) begin
tx_out <= tx_reg[tx_cnt -1];
end
if (tx_cnt == 9) begin
tx_out <= 1;
tx_cnt <= 0;
tx_empty <= 1;

23
 end
end
if (!tx_enable) begin
tx_cnt <= 0;
end
end

endmodule

TEST BENCH CODE:

module uart_tb(data,rxen,txem,rxem,txen,reset,rxin,txout,clkL,clkH);

inout [7:0]data;

reg load;

output clkL,clkH;

reg unload;

input rxen;

input txen;

reg rxen1;

reg txen1;

input reset;

reg res;

output txem,rxem;

reg txemt1;

reg rxemt1;

output txout;

input rxin;

24
reg clkL,clkH;

wire rxen,txen;

//reg reset;

reg [7:0]sdata;

wire [2:0]sel;

//reg [2:0]sel1;

wire [7:0]datain,dataout;

uart m1(

.reset(reset) ,

.txclk(clkH) ,

.ld_tx_data(load) ,

.tx_data(datain) ,

.tx_enable(txen) ,

.tx_out(txout) ,

.tx_empty(txem) ,

.rxclk(clkL) ,

.uld_rx_data(unload) ,

.rx_data(dataout) ,

.rx_enable(rxen) ,

.rx_in(rxin) ,

.rx_empty(rxem)

);

assign rxin=txout;

assign sel[0]=load;

assign sel[1]=unload;

25
assign data=sdata;

assign rxen=rxen1;

assign txen=txen1;

assign rxemt=rxemt1;

assign txemt=txemt1;

assign reset=res;

//assign sel=sel1;

bidirectionalbuffer m2(.A(data),.B(datain),.C(dataout),.sel(sel)); // using same data lines for

loading data into tx register and reading data from rx buffer

initial begin

#20 rxen1<= 1'b0; #20 rxen1<= 1'b1; #20 rxen1<= 1'b0; #20 rxen1<= 1'b1;

#20 txen1<= 1'b1; #25 txen1<= 1'b0; #25 txen1<= 1'b0; #25 txen1<= 1'b1;

#20 txemt1<= 1'b1; #20 txemt1<= 1'b0;#20 txemt1<= 1'b1;#20 txemt1<= 1'b0;

#20 rxemt1<= 1'b0; #20 rxemt1<= 1'b1;#20 rxemt1<= 1'b0;#20 rxemt1<= 1'b0;

#20 load<= 1'b1; #45 load<= 1'b0; #20 load<= 1'b1; #25 load<= 1'b0;

#20 unload<= 1'b0; #30 unload<= 1'b1;#20 unload<= 1'b0;#20 unload<= 1'b1;

clkL<=1'b0;

clkH<=1'b0;

res<=1;

#40 res <=0;

sdata[7]= 1'b1;#20 sdata[7]= 1'b0;#20 sdata[7]= 1'b1;#20 sdata[7]= 1'b1;#20 sdata[7]= 1'b0;

sdata[6]= 1'b1;#20 sdata[6]= 1'b1;#20 sdata[6]= 1'b0;#20 sdata[6]= 1'b0;#20 sdata[6]= 1'b1;

sdata[5]= 1'b1;#20 sdata[5]= 1'b1;#20 sdata[5]= 1'b0;#20 sdata[5]= 1'b0;#20 sdata[5]= 1'b1;

sdata[4]= 1'b0;#20 sdata[4]= 1'b1;#20 sdata[4]= 1'b0;#20 sdata[4]= 1'b1;#20 sdata[4]= 1'b0;

sdata[3]= 1'b1;#20 sdata[3]= 1'b1;#20 sdata[3]= 1'b1;#20 sdata[3]= 1'b1;#20 sdata[3]= 1'b1;

26
sdata[2]= 1'b0;#20 sdata[2]= 1'b1;#20 sdata[2]= 1'b0;#20 sdata[2]= 1'b1;#20 sdata[2]= 1'b0;

sdata[1]= 1'b1;#20 sdata[1]= 1'b0;#20 sdata[1]= 1'b1;#20 sdata[1]= 1'b0;#20 sdata[1]= 1'b1;

sdata[0]= 1'b0;#20 sdata[0]= 1'b1;#20 sdata[0]= 1'b0;#20 sdata[0]= 1'b1;#20 sdata[0]= 1'b0;

end

// clock generation

always

#10 clkL<=~clkL; // clock for rx

always

#160 clkH<=~clkH; // clock for tx

endmodule

RTL CODE:

rc:/> set_attribute lib_search_path /home/user 402a/labs/library

set_attribute: sets an attribute value on objects

Usage: set_attribute [-quiet] [-lock] <string> <string> [<object>+]

[-quiet]:

keeps quiet unless there are problems

[-lock]:

attribute becomes read only once locked

<string>:

attribute name

<string>:

new value. A compound string (containing spaces) should be represented as a list (using
double-quotes or braces).

[<object>+]:

object(s) of interest

27
rc:/> set_attribute lib_search_path /home/user402a/labs/library

Setting attribute of root '/': 'lib_search_path' = /home/user402a/labs/library

rc:/> set_attribute hdl_search_path /home/user402a/labs/uart/rtl

Setting attribute of root '/': 'hdl_search_path' = /home/user402a/labs/uart/rtl

rc:/> read_hdl {uart.v}

rc:/> set_attribute library slow_normal.lib

Info : Created nominal operating condition. [LBR-412]

: Operating condition '_nominal_' was created for the PVT values (1.000000, 0.900000,
125.000000) in library 'slow_normal.lib'.

: The nominal operating condition represents either the nominal PVT values if specified in
the library source, or the default PVT values (1.0, 1.0, 1.0).

Message Summary for Library slow_normal.lib:

********************************************

Setting attribute of root '/': 'library' = slow_normal.lib

rc:/> elaborate

Info : Found library cells that are unusable for mapping. [LBR-415]

: Library: 'slow_normal.lib', Total cells: 630, Usable cells: 602, Cells unusable for mapping:
28.

List of unusable cells: 'HOLDX1 MXI2DX1 MXI2DX2 MXI2DX4 MXI2DXL

RF1R1WX1 RF2R1WX1 RFRDX1 RFRDX2 RFRDX4 ... and others.'

Info : Elaborating Design. [ELAB-1]

: Elaborating top-level block 'uart' from file '/home/user402a/labs/uart/rtl/uart.v'.

/designs/uart

rc:/> synthesize -to_mapped -effort medium

: There are 3 CSA groups in module 'uart'... Accepted.

Mapping uart to gates.

28
Global mapping target info

==========================

Cost Group 'default' target slack: Unconstrained

Global mapping status

=====================

Worst

Total Weighted

Operation Area Neg Slk Worst Path

-------------------------------------------------------------------------------

global_map 1075 0 N/A

Global incremental target info

==============================

Cost Group 'default' target slack: Unconstrained

Global incremental optimization status

======================================

Worst

Total Weighted

Operation Area Neg Slk Worst Path

-------------------------------------------------------------------------------

global_incr 1075 0 N/A

Incremental optimization status

===============================

Worst - - DRC Totals - -

Total Weighted Max Max

Operation Area Neg Slk Trans Cap

29
-------------------------------------------------------------------------------

init_iopt 1075 0 0 0

Incremental optimization status

===============================

Worst - - DRC Totals - -

Total Weighted Max Max

Operation Area Neg Slk Trans Cap

-------------------------------------------------------------------------------

init_delay 1075 0 0 0

init_drc 1075 0 0 0

init_area 1075 0 0 0

rem_inv_qb 1071 0 0 0

io_phase 1070 0 0 0

glob_area 1069 0 0 0

area_down 1065 0 0 0

Incremental optimization status

===============================

Worst - - DRC Totals - -

Total Weighted Max Max

Operation Area Neg Slk Trans Cap

-------------------------------------------------------------------------------

init_delay 1065 0 0 0

init_drc 1065 0 0 0

init_area 1065 0 0 0

Done mapping uart

30
 Synthesis succeeded.

rc:/> report area> /home/user402a/labs/uart/output/area.txt

The 'subcommand' can be one of the following:

area - prints an area report

boundary_opto - reports boundary optimization summary

cdn_loop_breaker - reports the cdn_loop_breaker instances

cell_delay_calculation - reports how the cell delay of a libcell instance is calculated

clock_gating - prints a clock-gating report

clocks - prints a clock report

congestion - reports congestion summary

datapath - prints a datapath resources report

design_rules - prints design rule violations

dft_chains - reports on DFT scan chains

dft_clock_domain_info - reports DFT clock domain information

dft_core_wrapper - reports the wrapper segments inserted for ports using the insert_dft
wrapper_cell command

dft_registers - reports on DFT status of registers

dft_setup - reports on DFT setup

dft_violations - reports DFT violations

gates - prints a gates report

hierarchy - prints a hierarchy report

instance - prints an instance report

isolation - prints isolation report

level_shifter - prints a level-shifter report

memory - prints a memory usage report

31
memory_cells - prints the memory cells in the library

messages - prints a summary of error messages that have been issued

multibit_inferencing - prints a MULTIBIT_INFERENCING report

net_cap_calculation - reports how the capacitance of the net is calculated

net_delay_calculation - reports how the net delay is calculated

net_res_calculation - reports how the resistance of the net is calculated

nets - prints a nets report

opcg_equivalents - reports the scan cell to opcg cell equivalent mappings specified using the
'set_opcg_equivalent' command

operand_isolation - prints operand isolation report

ple - reports physical layout estimation data

port - prints a port report

power - prints a power report

power_domain - prints power domain report

proto - reports prototype synthesis information

qor - prints a QOR report

scan_compressibility - reports the scan compressibility of a design by processing its actual

compression results generated using the analyze_scan_compressibility command

sequential - prints a sequential instance report

slew_calculation - reports how the slew on the driver pin of a libcell instance is calculated

state_retention - prints state retention report

summary - prints an area, timing, and design rules report

test_power - estimates the average scan power in shift and capture modes during test

timing - prints a timing report

units - reports units

utilization - reports how floorplan utilization is calculated

32
yield - prints a yield report

rc:/> report area > /home/user402a/labs/uart/output/area.txt

rc:/> report timing > /home/user402a/labs/uart/output/timing.txt

rc:/> report power > /home/user402a/labs/uart/output/power.txt

CHAPTER NO-8
RESULTS:
8.1 SIMULATION

33
 Fig no: 6.1 Simulation of UART

8.2 RTL:

34
Fig no 6.2: RTL of UART

CONCLUSION

35
This project has introduced the technique of Universal Asynchronous Receiver/ Transmitter and
has demonstrated its great potential for use in a wide range of communication. A main focus has
been the assessment of the data transmission system. In recent years there has been interesting
the technique, and driven by the demand for low cost, simple and portable technology forth
settings, the availability of low cost and small semiconductor components, and the advancement
of computer analysis techniques. I can conclude from this project that I am trying my best to
achieve my objective. First, I success todesign a serial asynchronous receiver and transmitter
communication with standard I/O serial devices. Then, I also success to achieve my second
objective, that is design a UART that can be prototyping Altera DE2, then testing and debugging
the prototype in system. At the same time, I also cananalyze the features of UART technology
and make comparison with other existing UART technology. In addition, I also implement the
asynchronous receiver-transmitter in Altera DE2 board to achieve fast prototyping and design
verification. Lastly, I already know how to use and capable using UART in Verilog HDL.Here, I
already achieve our entire objective. This design uses Verilog HDL as design language to achieve
the modules of UART. Using this software, Alteras series chip to complete simulation and test,
the result may be stable and reliable. The design has great flexibility, high integration with some
reference value. Especially in the field of electronic design, where technology has recently
become increasingly mature, this design shows great significance. This project describes the
architecture of UART that support various data word length, parity selection and baud rates for
serial transmission of data. Working principle of this UART has been tested using simulator,
which can be implemented on Altera DE2.
Unfortunately, this project is not successfully developed. The Altera DE2 Board is still not been
fully interface with the Universal Asynchronous Receiver / Transmitter. Sometimes the resistor
tolerance also gives effect to the circuit. When supply the voltage, make sure it will enhance the
circuit to run, not to ruin the circuit. That is why the datasheet of every component is very
important to know the voltage and current limit.

REFERRENCES

36
[1] S. Mackay, E. Wright, D. Reynders, J. Park, Practical Industrial Data Networks:Design,
Installation and Troubleshooting, Newnes, 2004ISBN 07506 5807X,
[2] Wilson, Michael R. (January 2000). "TIA/EIA-422-B Overview". Application Note 1031.
National Semiconductor. Retrieved 28 July 2011
[3] Joseph Cavanagh, Digital Design and Verilog HDL Fundamentals, Published 17th June
2008 by CRC Press
[4] D. Michael Miller; Mitchell A. Thornton (2008). Multiple Valued Logic: Concepts and
Representations. Synthesis lectures on digital circuits and systems. Morgan & Claypool
Publishers. ISBN 978-1-59829-190-2.
[5] JanickBergerdon, "Writing Test benches: Functional Verification of HDL Models", 2000.
[6] I. M. Braverman, The Cutaneous Microcirculation, J Investig Dermatol Symp Proc.
,vol.5, pp.3-9,2000
[7] J. D. Briers, Laser Doppler and time-varying speckle: reconciliation, J. Opt. Soc. Am. A
13 (1996), 345-50
[8] Lecture Note Digital Design S1P 2013, Sir Suhaimi Bahisham bin Yusof, Universiti
Kuala Lumpur British Malaysian Institute.
[9 ]http://www.altera.com.my/education/univ/materials/boards/de2/unv-de2-board.html
[19] http://www.verilogcourseteam.com/vlsiproject3

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