Smart Sensor Systems

The Next Multiprocessor Challenge

MPSoC2013, Otsu, Japan

Dr. Yankin Tanurhan
VP Engineering, Solutions Group
Synopsys, Inc.

16/7/2013

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Agenda

Introduction
Smart Sensor Systems
Components
Performance
Conclusions

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 Introduction

Analog sensors meet digital and software

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Introduction

Smart Sensor: adding a

(digital) CPU core to an
analog sensor

Digital processing
Digital filtering
Calibration, linearization
Digital interfaces
Sensor fusion

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 Significant Growth in Sensors
Sensor Units to Grow to 30 Billion Units in 2017

35000

30B Units

30000

25000
Other Communications
Industrial
20000
Feature Phones
Smartphones
15000 Computing
10B Units
Automotive
10000 Consumer

5000

0
2009 2010 2011 2012 2013 2014 2015 2016 2017
Source: Semico Research, 2013

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Introduction
Topics addressed in this presentation

Smart sensor systems

Analog sensor becomes intelligent sensor
Multitude of sensors (analog and digital) combined for more precise
data
Sensor fusion host off-loading

Components that are part of a smart sensor system

Performance requirements
Area, power, footprint

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 Smart Sensor Systems

Digital processing
Scalable solution
Sensor system partitioning

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Smart Sensor System

Evolution: more digital processing
Analog in Discrete Components
Digital out
Sensor Analog
Digital
Signal ADC Conversion Peripheral
Processing Filter

Analog in Discrete DSP

Sensor Signal MCU/DSC
ADC
Processing Digital out
Signal
Mixer Peripheral
Digital in Processing
Sensor Signal
Peripheral
Processing

Discrete CPU based SoC

Analog in
Signal
Sensor ADC
Processing
Digital out
Signal
Mixer Peripheral
Processing
Digital in Signal
Sensor Peripheral
Processing

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 Sensor Systems Getting More Complex

Analog in
Sensor Signal Scalable solution
ADC
Processing

Analog in
Digital out
Sensor Signal Signal
ADC Fusion Peripheral
Processing Processing

Digital in
Sensor Signal
Peripheral
Processing

Increased processing drives higher performance

processor 8-bit 32-bit

Sensor fusion with multiple analog & digital Single Multiple

sensors requires higher level of integration Sensors Sensors

Transitioning from discrete ICs to integrated Discrete Integrated

sensor control within larger, more complex SoC

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Smart Sensor System

Multiple ways to get sensor data to the application processor
Application SoC
Sensor hub,
Audio Video Graphics
Connectivity Storage CPU real-time
subsystem subsystem subsystem
tasks for
Analog input, sensor
requires ADC processing
in SoC or on off-loaded to
separate die hub; can
1 2 4 support
Analog IO Digital IO
Sensor sensor fusion
Digital IO Hub
Digital input,
calibration,
linearization &
filtering can take Analog Digital
Sensor Sensor
place in the 3
sensor Combo
Sensor Digital Digital
Sensor Sensor

Multiple sensors
combined in one; can
Analog Analog
support sensor fusion
Sensor Sensor

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 Integrated Sensor IP Subsystem

Sensor
Subsystem

Software (I/O drivers, host drivers, DSP functions)

AHB Master Direct Memory Embedded Filtering

Debug Timers
Port SRAM Accelerators
AHB Slave
Pipeline
Embedded Interpolation
JTAG ROM/SRAM Accelerators
Execute Commit
IFQ
I2 C Vector
Slave Accelerators
Interrupt
Host Controller
Interface ARC EM4 Fast Math
Accelerators

Sensor Hardware
Capture
and Actuator ADC IF SPI I2 C GPIO APB IF
Timer Accelerators
Connectivity

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Components

Closely coupled memories

Tightly coupled IO functions
DSP extensions/Hardware accelerators
Software view

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 Typical CPU based Sensor System
bus-based design

Sensor System
Host Chip
Sensor
ADC

COMMUNICATIONS IF
Sensor IF AHB
Chip
Typical
CPU Application

on chip bus
RAM, ROM,
NVM AHB Processor

Actuator AHB
DAC

Actuator IF AHB
Chip

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Typical CPU based Sensor System

bus-based design using ARC EM processor

Sensor System
Host Chip
Sensor
ADC

COMMUNICATIONS IF

Sensor IF AHB
Chip
ARC
EM Application
on chip bus

RAM, ROM,
NVM AHB Processor

Actuator AHB
DAC

Actuator IF AHB
Chip

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 Typical CPU based Sensor System
optimization: use closely-coupled memories

Sensor System
Host Chip
Sensor
ADC

COMMUNICATIONS IF
Sensor IF AHB
Chip
ARC
EM Application

on chip bus
NVM AHB Processor
I-CCM + D-CCM

Actuator
DAC

Actuator IF AHB AHB

Chip

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Optimized CPU based Sensor System

ARC EM Processor with IO and DSP extensions
I/O Functionality tightly coupled to DSP Functions tightly coupled to
CPU by extension registers CPU by extension instructions

Sensor System
Host Chip
Sensor
ADC

Extension
COMMUNICATIONS IF

Chip Instructions +
Registers

ARC
NVM
AHB
EM
Application
Processor
I-CCM + D-CCM
Actuator
DAC

Chip

Synopsys 2013 16 Confidential

 IO functionality
Overview of sensor interfaces
Function Range Interface
Motion Accelerometers Analog/PWM/SPI/I2C
Gyroscopes Analog/SPI/I2C
Sensor IF
Magnetic and Hall Angle Analog/SPI/I2C
ADC if
Rotational speed Analog[current/voltage]
I2C
Hall effect Analog[current]/SPC/PWM/SENT SPI
Proximity Proximity I2C/SPI PWM
Optical Ambient Analog[current]/I2C/PWM
Distance Analog[voltage]
CCD image Serial Digital + GPIO
CMOS image Parallel Digital + GPIO/SPI/I2C
Host IF
I2C
Pressure Compensated Analog[voltage]
SPI
Uncompensated Analog[voltage]
UART
Integrated Analog[voltage] (on-chip) bus
Temperature Analog output Analog[voltage]/Switch[on/off/interrupt]
Digital output I2C/SMBus/SPI/1-wire/PWM/switch[on/off]/QSPI/SST
Silicon Analog[resistance]

Source: Silica, Sparkfun

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IO functionality
Tightly integrated IO

IO peripheral AHB

ARC Tightly integrated

EM
IO registers in Start from existing bus based
Memory Map I-CCM + D-CCM IO peripheral
Eliminate interface to on-chip
IO integrated
in CPU core bus
Replace load/store instructions
to IO peripheral by register
Extension
IO peripheral Registers move instructions
ARC
IO registers EM
extension of CPU
I-CCM + D-CCM
register file

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 HW support for DSP Functions
Accelerate application code

Reduce memory footprint DSP functions

HW accelerator instruction(s) Math
replaces multiple SW statements Complex Math
or functions
Filtering
FIR, IIR, correlation,
Reduces cycle count Matrix/vector
more performance, Interpolation
or less power
Extension
HW acc.
Registers
Some silicon area increase DSP
ARC
EM
Accelerator integrated
Selection of HW accelerators in processor pipeline I-CCM + D-CCM
tailored to (sensor) application

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Software

Sensor Application

SW
Signal Event
Peripheral processing Processing
Drivers
(OS)
DSP
Library

Peripherals HW
(tightly coupled + bus based) accelerators

HW

CPU core

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 Performance

Area benefits
Cycle count and memory footprint benefits
System power benefits
Embedded Non-Volatile Memories

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Significant Area & Power Benefits

180%

160%
161% Typical Sensor Implementation
Area (normalized to integrated subsystem)

156%
140%
143% 40- 60% Larger
120%
Typical Sensor Implementation
100%
100% 100% 100% Smaller & significantly more
80% power efficient
60%
Synopsys Integrated Sensor
40% Subsystem
20%
Smaller and significantly more
power efficient
0%
Intelligent sensor Combo sensor Sensor hub

DW Sensor Subsystem Typical Sensor Implementation

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Functions Implemented in HW or SW for
Area & Power Trade-offs
Software Only Functions Hardware Functions
FIR Filtering
Cos, Sin Sqrt Multiply/Accumulate (MAC) 6x reduction in
Conjugate Accumulate/Multiply (ACM) cycle count
DOT Sine/Cosine (SIN/COS)
Magnitude Square Root (SQRT)
Square Root
MaqSquared Absolute Value (ABS)
14x reduction in
Multiply Add (ADD)
cycle count
Convolute Subtract (SUB)
Correlate Multiply (MULT)
LMS, FIR, IIR Negate (NEGATE) CRC Check
Add, multiply, transpose Shift (SHIFT) 25x reduction in
Linear, Bilinear Scale (SCALE) cycle count

Fewer Cycles Equals Lower Power, Higher Performance

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HW accelerator
Cyclic Redundancy Check
Host communication check
CRC polygon :1+x1+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32;
Metrics @ 180nm Software Cycle count CRC accelerator
Optimized (hardware)
Footprint ROM Bytes 1420 12

Cycles # 76 3

Accelerator Gates 0 475

Memory footprint Gates 3140 25

Total area Gates 3140 500

Cycle count reduced by factor 25

Area reduces (!) by 2640 ND2 equivalent gates (85%)
CRC Code footprint reduces from 104 instructions to 3 instructions only

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 HW accelerator
Square root
Y= X

Metrics @ 180nm Software Hardware Hardware Hardware

48bit input Cycle count accelerator accelerator accelerator
24bit output optimized (cycle count opt) (pipelined opt) (area opt)

Footprint ROM Bytes 272 4 4 4

Cyclesa # 353*n n 6+n 24*n

Accelerator Gates 0 3740 5490 1075

Memory footprint Gates 600 10 10 10

Total area Gates 600 3750b 5500 1085

Cycle count reduced by factor 14

Area increases only 485 ND2 equivalent gates
SQRT Code footprint reduces from 136 instructions to 1 instructions only

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HW accelerator
Finite Impulse Response
N-taps asymmetric FIR filter:
FIR[i] = (SUM k in [0..N): C[k] * X[i-k])
Metrics @ 180nm Software Cycle count MAC accelerator
# taps =30 Optimized (hardware)
Footprint ROM Bytes 254 146

Cycles # 2673 430

Accelerator Gates 0 1520

Memory footprint Gates 560 300

Area Gates 560 1820

Cycle count reduces by factor 6

Area increases only 1260 ND2 equivalent gates
FIR Code footprint reduces from 86 instructions to 58 instructions only

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 Power Benefits
Sensor fusion application
9-D sensor fusion
Combo sensor based design
Design optimized using:
tightly coupled IO functions
addition of fusion specific HW accelerators

Metrics @ 90nm Bus-based design Optimized design

CPU + IO + Accelerators
Cycles [#] 100% 10%

Dynamic Power [uW/MHz] 100% 107%

Standard cell Area Gates 100% 121%

Overall power reduction of 9.3x

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Conclusions

Components
Performance
measurements

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 Conclusions
Components for Smart Sensor System

Identified Smart Sensor System variants

Intelligent sensor and Combo sensor (focus of presentation)
Sensor hub

Addressed components that are part of a Smart Sensor System

Optimized CPU based solution
IO peripheral (tightly coupled) + driver SW
HW accelerators for DSP functions (tightly coupled) + DSP SW

Mix of tightly coupled IO and bus-bused IO peripherals possible (esp.

when area is not high priority)

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Conclusions
Performance

Performance improvements by
Tightly coupled IO peripherals
Tightly coupled HW accelerators

Footprint
Silicon area, Software memory footprint (reducing ROM size)

Power
Lower CPU core frequency

Predictability
Direct access to tightly coupled IO and HW accelerators

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 Conclusions
Measurements

All measurement and studies are based on Synopsys product portfolio

ARC EM core
Tool suite for customizing ARC EM core
development of tightly coupled EIA extensions/instructions
Complete SW development tool suite
EM Starter Kit development system

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Thank You

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