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Features Description
256K x 16 advanced high-speed CMOS Static RAM The IDT71V416 is a 4,194,304-bit high-speed Static RAM organized
JEDEC Center Power / GND pinout for reduced noise. as 256K x 16. It is fabricated using high-performance, high-reliability
Equal access and cycle times CMOS technology. This state-of-the-art technology, combined with inno-
Commercial and Industrial: 10/12/15ns vative circuit design techniques, provides a cost-effective solution for high-
One Chip Select plus one Output Enable pin speed memory needs.
Bidirectional data inputs and outputs directly The IDT71V416 has an output enable pin which operates as fast as
LVTTL-compatible 5ns, with address access times as fast as 10ns. All bidirectional inputs and
Low power consumption via chip deselect outputs of the IDT71V416 are LVTTL-compatible and operation is from a
Upper and Lower Byte Enable Pins single 3.3V supply. Fully static asynchronous circuitry is used, requiring
Available in 44-pin, 400 mil plastic SOJ package and a 44- The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a
pin, 400 mil TSOP Type II package and a 48 ball grid array, 44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x
9mm x 9mm package. 9mm package.
Output
OE Enable
Buffer
High
8 8
Byte I/O 15
Output
Chip Buffer
CS Select
Buffer
High
8 8
Byte I/O 8
Write
4,194,304-bit Sense Buffer
16 Amps
Memory
and
Array Write
Write Drivers Low
WE 8 Byte 8
Enable I/O 7
Buffer Output
Buffer
Low
8 Byte 8
I/O 0
Write
Buffer
BHE
Byte
Enable
Buffers
BLE
3624 drw 01
NOVEMBER 2016
1
2016 Integrated Device Technology, Inc. DSC-3624/11
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
A9 22 23 A10
Top View
3624 drw 02
Top View
SOJ Capacitance
Pin Descriptions (TA = +25C, f = 1.0MHz)
A0 - A17 Address Inputs Input Symbol Parameter(1) Conditions Max. Unit
CS Chip Select Input CIN Input Capacitance VIN = 3dV 7 pF
WE Write Enable Input CI/O I/O Capacitance VOUT = 3dV 8 pF
OE Output Enable Input 3624 tbl 02
6.42
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IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
PT Power Dissipation 1 W
IOUT DC Output Current 50 mA Recommended DC Operating
NOTE:
3624 tbl 04
Conditions
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may Symbol Parameter Min. Typ. Max. Unit
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated VDD Supply Voltage 3.0 3.3 3.6 V
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability. VSS Ground 0 0 0 V
Truth Table(1)
CS OE WE BLE BHE I/O0-I/O7 I/O8-I/O15 Function
H X X X X High-Z High-Z Deselected - Standby
L L H L H DATAOUT High-Z Low Byte Read
L L H H L High-Z DATAOUT High Byte Read
L L H L L DATAOUT DATAOUT Word Read
L X L L L DATAIN DATAIN Word Write
L X L L H DATAIN High-Z Low Byte Write
L X L H L High-Z DATAIN High Byte Write
L H H X X High-Z High-Z Outputs Disabled
L X X H H High-Z High-Z Outputs Disabled
3624 tbl 03
NOTE:
1. H = VIH, L = VIL, X = Don't care.
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IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V416
Symbol Parameter Test Conditions Min. Max. Unit
|ILI| Input Leakage Current VCC = Max., VIN = VSS to VDD ___
5 A
|ILO| Output Leakage Current VDD = Max., CS = VIH, VOUT = VSS to VDD ___
5 A
VOL Output Low Voltage IOL = 8mA, VDD = Min. ___
0.4 V
VOH Output High Voltage IOH = -4mA, VDD = Min. 2.4 ___
V
3624 tbl 07
DC Electrical Characteristics(1, 2, 3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD 0.2V)
71V416S/L10 71V416S/L12 71V416S/L15
Symbol Parameter Com'l. Ind. Com'l. Ind. Com'l. Ind. Unit
ICC Dynamic Operating Current S 200 200 180 180 170 170 mA
CS < V LC, Outputs Open, V DD = Max., f = fMAX(4)
L 180 180 170 170 160 160
ISB Dynamic Standby Power Supply Current S 70 70 60 60 50 50 mA
CS > V HC, Outputs Open, V DD = Max., f = fMAX(4)
L 50 50 45 45 40 40
ISB1 Full Standby Power Supply Current (static) S 20 20 20 20 20 20 mA
CS > V HC, Outputs Open, V DD = Max., f = 0(4)
L 10 10 10 10 10 10
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Figure 1. AC Test Load *Including jig and scope capacitance.
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7
AC Test Conditions
6
tAA, tACS
(Typical, ns) 5
4 Input Pulse Levels GND to 3.0V
3
2
Input Rise/Fall Times 1.5ns
1
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
8 20 40 60 80 100 120 140 160 180 200
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IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71V416S/L10 71V416S/L12 71V416S/L15
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 10 ____
12 ____
15 ____
ns
tAA Address Access Time ____
10 ____
12 ____
15 ns
tACS Chip Select Access Time ____
10 ____
12 ____
15 ns
(1)
tCLZ Chip Select Low to Output in Low-Z 4 ____
4 ____
4 ____
ns
(1)
tCHZ Chip Select High to Output in High-Z ____
5 ____
6 ____
7 ns
tOE Output Enable Low to Output Valid ____
5 ____
6 ____
7 ns
tOLZ(1) Output Enable Low to Output in Low-Z 0 ____
0 ____
0 ____
ns
(1)
tOHZ Output Enable High to Output in High-Z ____
5 ____
6 ____
7 ns
tOH Output Hold from Address Change 4 ____
4 ____
4 ____
ns
tBE Byte Enable Low to Output Valid ____
5 ____
6 ____
7 ns
(1)
tBLZ Byte Enable Low to Output in Low-Z 0 ____
0 ____
0 ____
ns
(1)
tBHZ Byte Enable High to Output in High-Z ____
5 ____
6 ____
7 ns
WRITE CYCLE
tWC Write Cycle Time 10 ____
12 ____
15 ____
ns
tAW Address Valid to End of Write 8 ____
8 ____
10 ____
ns
tCW Chip Select Low to End of Write 8 ____
8 ____
10 ____
ns
tBW Byte Enable Low to End of Write 8 ____
8 ____
10 ____
ns
tAS Address Set-up Time 0 ____
0 ____
0 ____
ns
tWR Address Hold from End of Write 0 ____
0 ____
0 ____
ns
tWP Write Pulse Width 8 ____
8 ____
10 ____
ns
tDW Data Valid to End of Write 5 ____
6 ____
7 ____
ns
tDH Data Hold Time 0 ____
0 ____
0 ____
ns
tOW(1) Write Enable High to Output in Low-Z 3 ____
3 ____
3 ____
ns
(1)
tWHZ Write Enable Low to Output in High-Z ____
6 ____
7 ____
7 ns
3624 tbl 10
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
tAA
tOH tOH
tRC
ADDRESS
tAA tOH
OE
(3)
tACS (2) tCHZ (3)
tCLZ
BHE, BLE
(2)
tBE tBHZ (3)
(3)
tBLZ
DATAOUT DATA OUT VALID
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NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured 200mV from steady state.
tAW
CS
(2) (5)
tCW tCHZ
tBW
BHE, BLE
(5)
tWR tBHZ
tWP
WE
tAS (5)
tWHZ (5)
tOW
(3)
DATAOUT PREVIOUS DATA VALID DATA VALID
tDH
tDW
DATAIN DATAIN VALID
3624 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as
short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured 200mV from steady state.
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IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
tAW
CS
tAS tCW (2)
tBW
BHE, BLE
tWP tWR
WE
DATAOUT
tDH
tDW
DATAIN DATAIN VALID
3624 drw 09
tAW
CS
(2)
tCW
tAS tBW
BHE, BLE
tWP tWR
WE
DATAOUT
tDW tDH
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. During this period, I/O pins are in the output state, and input signals must not be applied.
3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
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IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
Ordering Information
71V416 X XX XXX X X X
Device Power Speed Package Process/
Type Temperature
Range
G Green
10
12 Speed in nanoseconds
15
S Standard Power
L Low Power
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IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
6.42
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